A vertical pipe short circuit fault detection and identification method in an NPP circuit topology

Abstract

The application discloses a vertical pipe short-circuit fault detection and identification method in an NPP circuit topology. If the vertical pipe set-emitter voltage is lower than the target voltage in the time when the vertical pipe is turned off and the horizontal pipe is turned on, the gate driver triggers to generate a fault signal with a fixed time length of t3. When the controller detects the fault signal with the time length of t3, it determines that the vertical pipe has a short-circuit fault, and identifies the bit number of the fault vertical pipe according to the hardware interface address of the feedback fault signal. Compared with the prior art, the application can detect the vertical pipe short-circuit fault before the bus direct-through fault and identify the bit number of the fault vertical pipe, so that the pre-judgment of the bus direct-through fault can be realized, and the fault expansion can be avoided. In addition, the gate driver uses a monostable trigger to realize the continuous duration of the fault signal in the monostable time, and the controller can determine that the corresponding vertical pipe has a short-circuit fault only when the fault signal is received and the duration of the fault signal is equal to the monostable time, so that the misjudgment can be prevented.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a method for detecting and identifying short-circuit faults in riser tubes in an NPP circuit topology. Background Technology

[0002] Current protection technologies for switching devices such as IGBTs, IEGTs, and IGCTs have two major limitations: 1) Overcurrent / short-circuit detection is limited to the switching device's turn-on period; 2) Overvoltage detection is limited to the switching device's turn-off period. When a short circuit occurs in a switching device in an NPP topology due to non-electrical factors (such as thermal cycling fatigue, package damage, soldering failure, bond wire breakage, process failure, ion failure, etc.), it can only be detected through bus shoot-through faults. However, bus shoot-through faults reduce the device's lifespan and can exacerbate the fault.

[0003] Therefore, existing technologies cannot effectively detect and identify short-circuit faults in switching devices in NPP topologies before bus shoot-through faults occur, thus making it impossible to make a preliminary judgment on bus shoot-through faults. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for detecting and identifying short-circuit faults in the riser tubes of NPP circuit topology, so as to solve the problem that the existing technology cannot effectively detect and identify short-circuit faults of switching devices in NPP topology before bus shoot-through faults, and thus cannot make a pre-judgment of bus shoot-through faults.

[0005] This invention provides a method for detecting and identifying short-circuit faults in vertical tubes in NPP circuit topologies. During the time when the vertical tube is turned off and the horizontal tube is turned on, the method determines whether a short-circuit fault has occurred in the vertical tube based on the collector-emitter voltage of the vertical tube, and identifies the position number of the vertical tube when a short-circuit fault occurs.

[0006] The above-described method for detecting and identifying short-circuit faults in the vertical tube of the NPP circuit topology determines whether a short-circuit fault has occurred in the vertical tube based on the collector-emitter voltage during the time when the vertical tube is off and the horizontal tube is on, and identifies the pin number of the vertical tube when a short-circuit fault occurs. Compared with the prior art, this invention can detect vertical tube short-circuit faults and identify the pin number of the faulty vertical tube before a busbar shoot-through fault occurs, thereby enabling pre-judgment of busbar shoot-through faults and preventing the fault from escalating. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a typical NPP circuit topology diagram;

[0009] Figure 2 This is a schematic diagram of the current path and voltage distribution of a typical NPP circuit topology when the riser tube Hu1 is short-circuited;

[0010] Figure 3 This is a schematic diagram of the current path and voltage distribution of a typical NPP circuit topology when the riser tube Hu2 is short-circuited;

[0011] Figure 4 This is a schematic diagram of the current path and voltage distribution of a typical NPP circuit topology when the riser tube Hd1 is short-circuited;

[0012] Figure 5 This is a schematic diagram of the current path and voltage distribution of a typical NPP circuit topology when the vertical tube Hd2 is short-circuited;

[0013] Figure 6 This is a circuit topology diagram of a multi-switch device with NPP three-level circuit.

[0014] Figure 7 This is a flowchart illustrating a method for detecting and identifying short-circuit faults in a riser tube in an NPP circuit topology according to one embodiment of the present invention.

[0015] Figure 8 This is an NPP circuit topology in one embodiment of the present invention;

[0016] Figure 9 This is a schematic diagram of the signal flow between the controller and the gate driver in an NPP circuit topology according to one embodiment of the present invention;

[0017] Figure 10 for Figure 7 A flowchart illustrating step S10 in the process;

[0018] Figure 11 for Figure 7 A flowchart illustrating step S20 in the process;

[0019] Figure 12 This is an example diagram of a fault detection and identification signal in one embodiment of the present invention, showing a vertical tube fault occurring during the switching dynamic process of a semiconductor device.

[0020] Figure 13 This is a flowchart illustrating the method for detecting and identifying short-circuit faults in the riser tube of an NPP circuit topology in another embodiment of the present invention.

[0021] Figure 14 This is a schematic diagram of the signal flow between the controller and the gate driver in an NPP circuit topology according to one embodiment of the present invention;

[0022] Figure 15 for Figure 13 A flowchart illustrating step S110 in the process;

[0023] Figure 16 for Figure 13 A flowchart of step S120 in the process. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Figure 1 A typical NPP circuit topology is shown, such as Figure 1 As shown, a typical NPP circuit topology single-phase bridge arm circuit includes horizontal transistor b1, horizontal transistor b2, vertical transistor Hu1, vertical transistor Hu2, vertical transistor Hd1, vertical transistor Hd2, first voltage divider capacitor C1, and second voltage divider capacitor C2. Horizontal transistors b1 and b2 are connected in series to form a horizontal bridge, vertical transistors Hu1 and Hu2 are connected in series to form the upper bridge of the vertical bridge, and vertical transistors Hd1 and Hd2 are connected in series to form the lower bridge of the vertical bridge. One end of the vertical bridge is connected to the positive terminal BUS+ of the DC power supply, and the other end of the vertical bridge is connected to the negative terminal BUS- of the DC power supply. The first voltage divider capacitor C1 and the second voltage divider capacitor C2 are connected in series between the positive and negative terminals of the DC power supply. O1 is the series connection point of the upper and lower bridges and is connected to the output terminal. O2 is the series connection point of the first voltage divider capacitor C1 and the second voltage divider capacitor C2. The horizontal bridge is connected between O1 and O2. Horizontal tube b1, horizontal tube b2, vertical tube Hu1, vertical tube Hu2, vertical tube Hd1, and vertical tube Hd2 are all semiconductor devices, and each semiconductor device has an anti-parallel diode. The semiconductor devices include, but are not limited to, IGBTs, IEGTs, and IGCTs.

[0026] Figure 2 The current path and voltage distribution of a typical NPP circuit topology when the riser Hu1 is short-circuited are shown.

[0027] Figure 2As shown, "0" indicates that the switching device is off and "1" indicates that the switching device is on. When a short circuit fault occurs in the vertical tube Hu1, the fault cannot be detected during the process from turn-on to turn-off. When the horizontal tubes b1 and b2 are on, regardless of whether the current is flowing out or in, the voltage at the end of the vertical tube Hu1 is zero. The vertical tube Hu2 bears half of the bus voltage Vdc / 2. The vertical tubes Hd1 and Hd2 together bear half of the bus voltage Vdc / 2. When the vertical tubes Hd1 and Hd2 are on, the vertical tube Hu2 will fail due to bearing the full bus voltage Vdc, inducing a bus shoot-through fault.

[0028] Figure 3 The current path and voltage distribution of a typical NPP circuit topology when the riser tube Hu2 is short-circuited are shown.

[0029] Figure 3 As shown, when a short-circuit fault occurs in the vertical pipe Hu2, the fault cannot be detected during the process from turn-on to turn-off. When the horizontal pipes b1 and b2 are turned on, regardless of whether the current is flowing out or in, the voltage at the end of the vertical pipe Hu2 is zero. The vertical pipe Hu1 bears half the bus voltage Vdc / 2, and the vertical pipes Hd1 and Hd2 together bear half the bus voltage Vdc / 2. When the vertical pipes Hd1 and Hd2 are turned on, the vertical pipe Hu1 will fail due to bearing the full bus voltage Vdc, inducing a bus straight-through fault.

[0030] Figure 4 The current path and voltage distribution of a typical NPP circuit topology when the riser Hd1 is short-circuited are shown.

[0031] Figure 4 As shown, when a short-circuit fault occurs in the vertical pipe Hd1, the fault cannot be detected during the process from turn-on to turn-off. When the horizontal pipes b1 and b2 are turned on, regardless of whether the current is flowing out or in, the voltage at the end of the vertical pipe Hd1 is zero, and the vertical pipe Hd2 bears half the bus voltage Vdc / 2. The vertical pipes Hu1 and Hu2 together bear half the bus voltage Vdc / 2. When the vertical pipes Hu1 and Hu2 are turned on, the vertical pipe Hd2 will fail due to bearing the full bus voltage Vdc, inducing a bus straight-through fault.

[0032] Figure 5 The current path and voltage distribution of a typical NPP circuit topology when the riser tube Hd2 is short-circuited are shown.

[0033] Figure 5As shown, when a short-circuit fault occurs in the vertical pipe Hd2, the fault cannot be detected during the process from turn-on to turn-off. When the horizontal pipes b1 and b2 are turned on, regardless of whether the current is flowing out or in, the voltage at the end of the vertical pipe Hd2 is zero. The vertical pipe Hd1 bears half the bus voltage Vdc / 2, and the vertical pipes Hu1 and Hu2 together bear half the bus voltage Vdc / 2. When the vertical pipes Hu1 and Hu2 are turned on, the vertical pipe Hd1 will fail due to bearing the full bus voltage Vdc, inducing a bus straight-through fault.

[0034] As can be seen from the above, when a short circuit fault occurs in the vertical tubes (vertical tube Hu1, vertical tube Hu2, vertical tube Hd1, vertical tube Hd2) in a typical NPP circuit topology, it will induce a bus shoot-through fault.

[0035] Figure 6 The diagram shows a multi-switch device circuit topology for an NPP three-level circuit, in which the number of vertical transistors is greater than 4 and the number of horizontal transistors is greater than 2. (Example:) Figure 6 As shown, vertical tubes Hu1 to Tun are connected in series to form the upper bridge of the vertical bridge in the bridge arm circuit, vertical tubes Hd1 to Tdn are connected in series to form the lower bridge of the vertical bridge in the bridge arm circuit, and horizontal tubes b1 to bn are connected in series to form the horizontal bridge in the bridge arm circuit. When a short circuit fault occurs in the vertical tubes (vertical tubes Hu1 to Tun, vertical tubes Hd1 to Tdn) in the NPP three-level multi-switching device circuit topology, it will also induce a bus shoot-through fault.

[0036] In summary, when a short-circuit fault occurs in the vertical tube of an NPP circuit topology, it will induce a bus shoot-through fault. Based on this, it is possible to determine whether a short-circuit fault has occurred in the vertical tube by detecting the collector-emitter voltage during the horizontal tube turn-on process, and to pre-determine the bus shoot-through fault based on the fault determination result.

[0037] This invention provides a method for detecting and identifying short-circuit faults in riser tubes in NPP circuit topologies. Applied to NPP circuit topologies with four or more risers, the method determines whether a riser tube has a short-circuit fault based on its collector-emitter voltage during the time when the riser tube is off and the horizontal tube is on. When a riser tube experiences a short-circuit fault, its tag number is identified. This invention enables riser tube short-circuit fault detection and tag number identification before a busbar shoot-through fault occurs, thus achieving pre-judgment of busbar shoot-through faults and preventing fault escalation.

[0038] Figure 7 A flowchart illustrating a method for detecting and identifying short-circuit faults in a riser tube of an NPP circuit topology according to one embodiment of the present invention is shown. Figure 7 As shown, the method for detecting and identifying short-circuit faults in the riser tube of the NPP circuit topology in this embodiment includes steps S10 to S20:

[0039] S10: After the vertical tube is turned off for time t1, if the collector-emitter voltage of the vertical tube is detected to be lower than the preset target voltage within time t2, the gate driver triggers the generation of a fault signal with a fixed duration of t3.

[0040] S20: When the controller detects a fault signal with a duration of t3, it determines that a short circuit fault has occurred in the riser and identifies the tag number of the faulty riser based on the hardware interface address of the feedback fault signal.

[0041] The settings for t1 and t2 are to ensure that the horizontal pipe is open, that is, to guarantee that short-circuit fault detection of the vertical pipe is performed during the time when the vertical pipe is closed and the horizontal pipe is open. Among them, t1 is greater than or equal to the dead time between the vertical pipe and the horizontal pipe and less than the minimum pulse width of the horizontal pipe, and t2 starts at the end point of t1 and ends at the end point of the minimum pulse width of the horizontal pipe.

[0042] like Figure 8 As shown, in the NPP circuit topology, the gates of both the horizontal and vertical transistors are connected to gate drivers, and the gate drivers are connected to the controller.

[0043] like Figure 9 As shown, the gate driver includes a driving module, a switch state recognition module, a delay module, a collector-emitter voltage detection module, a target voltage module, a comparator module, a gate circuit module, and a monostable multivibrator; the controller includes a PWM signal module, a fault detection module, and a fault recognition module. Specifically, the driving module drives the riser transistor to turn on and off; the switch state recognition module identifies the switch state of the riser transistor; the delay module enables the gate circuit module for a duration of t2 after the riser transistor is turned off for time t1; the collector-emitter voltage detection module detects the collector-emitter voltage of the riser transistor, obtained through resistor voltage division; the target voltage module provides a target voltage, obtained through resistor voltage division, with the amplitude of the target voltage set according to the bus voltage; the comparator module compares the collector-emitter voltage of the riser transistor with the target voltage; the gate circuit module enables the monostable multivibrator and connects the delay module and the comparator module; the monostable multivibrator generates a fault signal with a fixed monostable duration of t3, allowing the controller to identify whether a short-circuit fault has occurred in the riser transistor. The PWM signal module is used to generate PWM switching signals, which are the original signals that drive semiconductor devices. The input of the fault detection module is connected to the gate driver, and the output is connected to the fault identification module and the PWM signal module. When the gate driver feeds back a fault signal, the fault detection module needs to detect the fault immediately, execute the fault handling logic, obtain the hardware interface address of the feedback fault signal, and send the fault signal and the obtained hardware interface address to the fault identification module.

[0044] like Figure 10As shown, in one embodiment, step S10, namely, after the vertical tube is turned off for time t1, if the collector-emitter voltage of the vertical tube is detected to be lower than the preset target voltage within time t2, the gate driver triggers the generation of a fault signal with a fixed duration of t3, includes steps S11 to S15:

[0045] S11: The drive module generates a drive signal based on the PWM switching signal output by the controller to turn off the vertical transistor. Specifically, based on the PWM switching signal output by the controller, the drive module generates a drive signal to turn off the vertical transistor of the upper or lower bridge in the vertical bridge.

[0046] S12: The switch status recognition module identifies the switch status of the vertical pipe according to the drive signal and outputs the switch status signal of the vertical pipe.

[0047] S13: The comparator module compares the collector-emitter voltage of the riser transistor obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module. When the collector-emitter voltage of the riser transistor is lower than the target voltage, the comparator module outputs a first enable signal. Specifically, the comparator module compares the collector-emitter voltage of the riser transistor obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module. When the collector-emitter voltage of the riser transistor is lower than the target voltage, the comparator module outputs a high level, enabling the gate circuit module; when the collector-emitter voltage of the riser transistor is greater than or equal to the target voltage, the comparator module outputs a low level, and the gate circuit module is not enabled.

[0048] S14: The delay module receives the vertical pipe switch status signal and outputs a second enable signal for a duration of t2 after the vertical pipe is turned off for time t1. Specifically, after the vertical pipe is turned off for time t1, the delay module outputs a high level for a duration of t2 to enable the gate circuit module; after time t2 ends, it outputs a negative level, and the gate circuit module is not enabled.

[0049] S15: When the gate circuit module receives both the first and second enable signals simultaneously, it enables the monostable multivibrator (MSL). The MSL generates and outputs a fault signal with a fixed duration of t3. Specifically, the gate circuit module only outputs a high level to enable the MSL when both the delay module and the comparator module are enabled. This causes the MSL to generate and output a fixed-duration fault signal of t3. The specific duration of t3 can be set as needed.

[0050] like Figure 11 As shown, in one embodiment, step S20, whereby the controller determines that a short-circuit fault has occurred in the riser when it detects a fault signal with a duration of t3, and identifies the tag number of the faulty riser based on the hardware interface address of the feedback fault signal, includes steps S21 to S22:

[0051] S21: When the fault detection module receives a fault signal from the gate driver, it obtains the hardware interface address of the fault signal and sends the fault signal and the obtained hardware interface address to the fault identification module.

[0052] S22: When the fault identification module detects that the duration of the fault signal is t3, it determines that a short circuit fault has occurred in the riser tube and identifies the faulty riser tube's tag number based on the hardware interface address. Specifically, after receiving the fault signal, the fault identification module also needs to check whether the duration of the fault signal is equal to t3. If yes, it determines that a short circuit fault has occurred in the riser tube; otherwise, it determines that the riser tube fault is another type of fault. The controller connects to the gate drivers of different semiconductor devices through different hardware interfaces, and different hardware interfaces correspond to different semiconductor devices. Therefore, the fault identification module can identify the tag number of the faulty riser tube based on the hardware interface address of the feedback fault signal.

[0053] See you again Figure 11 In a preferred embodiment, step S20 further includes the following steps:

[0054] S23: The fault identification module sends the fault type and tag number of the faulty riser to the human-machine interface. Specifically, the fault identification module sends the fault type and tag number of the faulty riser to the human-machine interface, and displays the fault type and tag number of the faulty riser through the human-machine interface, thereby realizing the pre-judgment and fault identification of bus pass-through faults in the NPP circuit topology.

[0055] In a preferred embodiment, step S21 further includes: when the fault detection module receives a fault signal fed back by the gate driver, it executes fault handling logic to control the PWM signal module to stop outputting PWM switching signals to the corresponding vertical tube.

[0056] Figure 12 This is an example diagram illustrating fault detection and identification signals for vertical tube faults occurring during the switching dynamics of semiconductor devices.

[0057] like Figure 12As shown, the vertical switch state from off to on and back to off constitutes one cycle. When the vertical switch is off, the horizontal switch is on, the collector-emitter voltage of the vertical switch is greater than the target voltage, and the gate driver short-circuit fault signal is disabled, so no short-circuit fault detection is performed under this condition. After the horizontal switch is off and a dead time delay occurs, the vertical switch is on. During this process, the collector-emitter voltage of the vertical switch is variable, determined by the change in load current. At this time, the gate driver short-circuit fault signal is disabled, so no short-circuit fault detection is performed under this condition. After the vertical switch is on, the horizontal switch will inevitably be off, and the collector-emitter voltage of the vertical switch will be approximately zero. At this time, the gate driver short-circuit fault signal is disabled, so no short-circuit fault detection is performed under this condition. The horizontal switch completes a dead time transition from on to off. After the vertical transistor is turned on, the collector-emitter voltage of the vertical transistor is uncertain, determined by the change in load current. At this time, the gate driver short-circuit fault signal is not enabled, and short-circuit fault detection is not performed under this condition. When the vertical transistor is turned off and delayed for t1 time, t1 must be greater than or equal to the dead time and less than the minimum pulse width of the horizontal transistor. At this time, the horizontal transistor must be in the on state, enabling the gate driver short-circuit fault signal. To ensure that the horizontal transistor is in the conducting state, the time is limited to t2. The time t2 is after the time t1 and within the minimum pulse width of the horizontal transistor. The collector-emitter voltage of the vertical transistor is detected. If the collector-emitter voltage of the vertical transistor is lower than the target voltage, it indicates that a short-circuit fault has occurred in the vertical transistor. The gate driver uses a monostable multivibrator to realize the fault signal lasting for t3 time. The controller receives a fault signal from the gate driver, sets the vertical tube fault location signal to 1, obtains the hardware interface address of the feedback fault signal, and when the controller detects that the duration of the fault signal is t3, it determines that the corresponding vertical tube has a short circuit fault. It then identifies the tag number of the faulty vertical tube based on the hardware interface address of the feedback fault signal. Finally, it sends the fault type and tag number of the faulty vertical tube to the human-machine interface for display, thus realizing the pre-judgment and fault identification of bus pass-through faults in the NPP circuit topology.

[0058] The riser short-circuit fault detection and identification method in the NPP circuit topology provided in this invention can detect riser short-circuit faults and identify the faulty riser number before a bus pass-through fault occurs, thereby achieving pre-judgment of bus pass-through faults and preventing fault escalation. Furthermore, the gate driver uses a monostable multivibrator to ensure the fault signal persists for the monostable time (t3). After receiving the fault signal, the controller also needs to detect the duration of the fault signal. Only when the detected fault signal duration equals the monostable time can it be determined that the corresponding riser has a short-circuit fault, thus preventing false judgments.

[0059] Figure 13 A flowchart illustrating a method for detecting and identifying short-circuit faults in a riser tube of an NPP circuit topology according to one embodiment of the present invention is shown. Figure 13As shown, the method for detecting and identifying short-circuit faults in the riser tube of the NPP circuit topology in this embodiment includes steps S110 to S120:

[0060] S110: After the vertical tube is turned off for time t1, if the collector-emitter voltage of the vertical tube is detected to be lower than the preset target voltage within time t2, the gate driver triggers the generation of a fault signal.

[0061] S120: When the controller receives a fault signal from the gate driver, it determines that a short circuit fault has occurred in the riser and identifies the bit number of the faulty riser based on the hardware interface address of the feedback fault signal.

[0062] The settings for t1 and t2 are to ensure that the horizontal pipe is open, that is, to guarantee that short-circuit fault detection of the vertical pipe is performed during the time when the vertical pipe is closed and the horizontal pipe is open. Among them, t1 is greater than or equal to the dead time between the vertical pipe and the horizontal pipe and less than the minimum pulse width of the horizontal pipe, and t2 starts at the end point of t1 and ends at the end point of the minimum pulse width of the horizontal pipe.

[0063] The method for detecting and identifying short-circuit faults in the vertical tube of the NPP circuit topology in this embodiment is applied to the NPP circuit topology. The gates of both the horizontal and vertical tubes in the NPP circuit topology are connected to gate drivers, and the gate drivers are connected to the controller.

[0064] like Figure 14 As shown, the gate driver includes a driving module, a switch state recognition module, a delay module, a collector-emitter voltage detection module, a target voltage module, a comparator module, and a gate circuit module; the controller includes a PWM signal module, a fault detection module, and a fault recognition module. The specific limitations of each module within the gate driver and controller in this embodiment can be found in [reference needed]. Figure 9 The specific limitations of the various modules within the gate driver and controller in the illustrated embodiment will not be elaborated here.

[0065] like Figure 15 As shown, in one embodiment, step S110, namely, after the vertical tube is turned off for time t1, if the collector-emitter voltage of the vertical tube is detected to be lower than a preset target voltage within time t2, the gate driver triggers a fault signal, includes steps S111 to S115:

[0066] S111: The drive module generates a drive signal based on the PWM switching signal output by the controller to turn off the vertical transistor. Specifically, based on the PWM switching signal output by the controller, the drive module generates a drive signal to turn off the vertical transistor of the upper or lower bridge in the vertical bridge.

[0067] S112: The switch status recognition module identifies the switch status of the vertical pipe according to the drive signal and outputs the switch status signal of the vertical pipe;

[0068] S113: The comparator module compares the collector-emitter voltage of the riser transistor obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module. When the collector-emitter voltage of the riser transistor is lower than the target voltage, the comparator module outputs a first enable signal. Specifically, the comparator module compares the collector-emitter voltage of the riser transistor obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module. When the collector-emitter voltage of the riser transistor is lower than the target voltage, the comparator module outputs a high level, enabling the gate circuit module; when the collector-emitter voltage of the riser transistor is greater than or equal to the target voltage, the comparator module outputs a low level, and the gate circuit module is not enabled.

[0069] S114: The delay module receives the vertical pipe switch status signal and outputs a second enable signal for a duration of t2 after the vertical pipe is turned off for time t1. Specifically, after the vertical pipe is turned off for time t1, the delay module outputs a high level for a duration of t2 to enable the gate circuit module; after time t2 ends, it outputs a negative level, and the gate circuit module is not enabled.

[0070] S115: When the gate circuit module receives the first enable signal and the second enable signal simultaneously, it enables the gate driver to generate and output a fault signal. Specifically, the gate circuit module can only trigger the generation and output of the fault signal when the delay module and the comparator module are enabled simultaneously.

[0071] like Figure 16 As shown, in one embodiment, step S120, which is when the controller receives a fault signal from the gate driver, determines that a short-circuit fault has occurred in the riser transistor, and identifies the bit number of the faulty riser transistor according to the hardware interface address of the feedback fault signal, includes steps S121 to S122:

[0072] S121: When the fault detection module receives a fault signal from the gate driver, it obtains the hardware interface address of the fault signal and sends the fault signal and the obtained hardware interface address to the fault identification module.

[0073] S122: When the fault identification module receives a fault signal, it determines that a short circuit fault has occurred in the riser tube, and identifies the tag number of the faulty riser tube according to the hardware interface address. Specifically, the fault identification module determines that a short circuit fault has occurred in the riser tube when it receives a fault signal; moreover, the controller connects to the gate drivers of different semiconductor devices through different hardware interfaces. Therefore, different hardware interfaces correspond to different semiconductor devices, and the fault identification module can identify the tag number of the faulty riser tube according to the hardware interface address of the feedback fault signal.

[0074] See you again Figure 16 In a preferred embodiment, step S120 further includes the following steps:

[0075] S123: The fault identification module sends the fault type and tag number of the faulty riser to the human-machine interface. Specifically, the fault identification module sends the fault type and tag number of the faulty riser to the human-machine interface, and displays the fault type and tag number of the faulty riser through the human-machine interface, thereby realizing the pre-judgment and fault identification of bus pass-through faults in the NPP circuit topology.

[0076] In a preferred embodiment, step S121 further includes: when the fault detection module receives a fault signal fed back by the gate driver, it executes fault handling logic to control the PWM signal module to stop outputting PWM switching signals to the corresponding vertical tube.

[0077] The method for detecting and identifying short-circuit faults in the NPP circuit topology provided in this invention can detect short-circuit faults in the vertical tubes and identify the position number of the faulty vertical tube before a busbar through-through fault occurs, thereby achieving pre-judgment of busbar through-through faults and preventing the fault from escalating.

[0078] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for detecting and identifying short-circuit faults in riser tubes in an NPP circuit topology, characterized in that, During the time when the vertical pipe is turned off and the horizontal pipe is turned on, determine whether a short circuit fault has occurred in the vertical pipe based on the collector-emitter voltage of the vertical pipe, and identify the tag number of the vertical pipe when a short circuit fault occurs.

2. The method for detecting and identifying short-circuit faults in the riser tube of the NPP circuit topology according to claim 1, characterized in that, In the NPP circuit topology, the gates of both the horizontal and vertical transistors are connected to gate drivers, and the gate drivers are connected to the controller. The process of determining whether a short-circuit fault has occurred in the vertical pipe based on the collector-emitter voltage during the time when the vertical pipe is turned off and the horizontal pipe is turned on, and identifying the position number of the vertical pipe when a short-circuit fault occurs, includes: After the vertical tube is turned off for time t1, if the collector-emitter voltage of the vertical tube is detected to be lower than the preset target voltage within time t2, the gate driver will trigger the generation of a fault signal. When the controller receives a fault signal from the gate driver, it determines that a short circuit fault has occurred in the riser and identifies the bit number of the faulty riser based on the hardware interface address of the feedback fault signal. Among them, t1 is greater than or equal to the dead time between the vertical tube and the horizontal tube and less than the minimum pulse width of the horizontal tube, and t2 starts at the end point of t1 and ends at the end point of the minimum pulse width of the horizontal tube.

3. The method for detecting and identifying short-circuit faults in the riser tube of the NPP circuit topology according to claim 2, characterized in that, The gate driver includes a driving module, a switch state recognition module, a delay module, a collector-emitter voltage detection module, a target voltage module, a comparator module, and a gate circuit module; After the vertical tube is turned off for time t1, if the collector-emitter voltage of the vertical tube is detected to be lower than the preset target voltage within time t2, the gate driver triggers a fault signal, including: The drive module generates a drive signal based on the PWM switching signal output by the controller to drive the vertical tube to turn off; The switch status recognition module identifies the switch status of the vertical pipe based on the drive signal and outputs the switch status signal of the vertical pipe; The comparator module compares the collector-emitter voltage of the riser obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module, and outputs the first enable signal when the collector-emitter voltage of the riser is lower than the target voltage; The delay module receives the vertical pipe switch status signal and outputs a second enable signal for a duration of t2 after the vertical pipe is turned off for time t1. When the gate circuit module receives the first enable signal and the second enable signal simultaneously, it enables the gate driver to generate and output a fault signal.

4. The method for detecting and identifying short-circuit faults in the riser tube of the NPP circuit topology according to claim 3, characterized in that, The controller includes a fault detection module and a fault identification module; When the controller receives a fault signal from the gate driver, it determines that a short-circuit fault has occurred in the riser transistor, and identifies the bit number of the faulty riser transistor based on the hardware interface address of the fault signal, including: When the fault detection module receives a fault signal from the gate driver, it obtains the hardware interface address of the fault signal and sends the fault signal and the obtained hardware interface address to the fault identification module. When the fault identification module receives a fault signal, it determines that a short circuit fault has occurred in the vertical pipe and identifies the tag number of the faulty vertical pipe according to the hardware interface address.

5. The method for detecting and identifying short-circuit faults in the riser tube of the NPP circuit topology according to claim 1, characterized in that, In the NPP circuit topology, the gates of both the horizontal and vertical transistors are connected to gate drivers, and the gate drivers are connected to the controller. The process of determining whether a short-circuit fault has occurred in the vertical pipe based on the collector-emitter voltage during the time when the vertical pipe is turned off and the horizontal pipe is turned on, and identifying the position number of the vertical pipe when a short-circuit fault occurs, includes: After the vertical tube is turned off for time t1, if the collector-emitter voltage of the vertical tube is detected to be lower than the preset target voltage within time t2, the gate driver triggers the generation of a fault signal with a fixed duration of t3. When the controller detects a fault signal with a duration of t3, it determines that a short circuit fault has occurred in the riser and identifies the tag number of the faulty riser based on the hardware interface address of the feedback fault signal. Among them, t1 is greater than or equal to the dead time between the vertical tube and the horizontal tube and less than the minimum pulse width of the horizontal tube, and t2 starts at the end point of t1 and ends at the end point of the minimum pulse width of the horizontal tube.

6. The method for detecting and identifying short-circuit faults in the riser of an NPP circuit topology according to claim 5, characterized in that, The gate driver includes a driving module, a switch state recognition module, a delay module, a collector-emitter voltage detection module, a target voltage module, a comparator module, a gate circuit module, and a monostable multivibrator. After the vertical tube is turned off for time t1, if the collector-emitter voltage of the vertical tube is detected to be lower than the preset target voltage within time t2, the gate driver triggers the generation of a fault signal with a fixed duration of t3, including: The drive module generates a drive signal based on the PWM switching signal output by the controller to drive the vertical tube to turn off; The switch status recognition module identifies the switch status of the vertical pipe based on the drive signal and outputs the switch status signal of the vertical pipe; The comparator module compares the collector-emitter voltage of the riser obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module, and outputs the first enable signal when the collector-emitter voltage of the riser is lower than the target voltage; The delay module receives the vertical pipe switch status signal and outputs a second enable signal for a duration of t2 after the vertical pipe is turned off for time t1. When the gate circuit module receives the first enable signal and the second enable signal simultaneously, it enables the monostable multivibrator, which then triggers the generation and output of a fault signal with a fixed duration of t3.

7. The method for detecting and identifying short-circuit faults in the riser of an NPP circuit topology according to claim 6, characterized in that, The controller includes a fault detection module and a fault identification module; When the controller detects a fault signal with a duration of t3, it determines that a short-circuit fault has occurred in the riser pipe, and identifies the tag number of the faulty riser pipe based on the hardware interface address of the feedback fault signal, including: When the fault detection module receives a fault signal from the gate driver, it obtains the hardware interface address of the fault signal and sends the fault signal and the obtained hardware interface address to the fault identification module. When the duration of the fault signal detected by the fault identification module is t3, it determines that a short circuit fault has occurred in the vertical pipe, and identifies the tag number of the faulty vertical pipe according to the hardware interface address.

8. The method for detecting and identifying short-circuit faults in the riser tube of the NPP circuit topology according to claim 4 or 7, characterized in that, The fault identification module sends the fault type and tag number of the faulty vertical pipe to the human-machine interface.

9. The method for detecting and identifying short-circuit faults in the riser of an NPP circuit topology according to claim 4 or 7, characterized in that, When the fault detection module receives a fault signal from the gate driver, it executes fault handling logic and controls the PWM signal module to stop outputting PWM switching signals to the corresponding vertical transistor.

10. The method for detecting and identifying short-circuit faults in the riser of an NPP circuit topology according to any one of claims 1-7, characterized in that, The number of vertical tubes in the NPP circuit topology is greater than or equal to 4.

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