Display device

Abstract

The application provides a display device, wherein a first gate drive circuit and a second gate drive circuit respectively transmit corresponding first gate signals to at least one row of pixel data writing transistors in a first region and a second region, and the first gate drive circuit and the second gate drive circuit respectively transmit second gate signals and third gate signals to first reset transistors and compensation transistors in the at least one row of pixels, the signals of the first nodes of the current stage and the previous two stages in the second gate drive circuit have an overlapping period, and the starting time of the pulse of the second gate signal acting on the second region is located before the overlapping period to avoid the state of passive output of the first gate line electrically connected to the second region, and the uniformity of the display picture is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] CMOS GOA (Gate-driver On Array with CMOS (Complementary Metal-Oxide-Semiconductor)) technology, compared to traditional GOA (Gate-driver On Array) technology, can achieve display devices with narrower bezels.

[0003] Currently, display devices based on the aforementioned CMOS GOA technology generally employ two types of CMOS GOA. The two CMOS GOAs at the same level generate first gate signals that act on the first transistors in pixels within different regions. Simultaneously, they also generate second gate signals and third gate signals, respectively, to act on the second and third transistors in the pixels. Since the second and third transistors require different second and third gate signals, the waveforms of the two first gate signals generated by the two CMOS GOAs at the same level differ, resulting in differences in brightness between the corresponding two regions and reducing the uniformity of the displayed image. Summary of the Invention

[0004] Embodiments of the present invention provide a display device for improving the uniformity of the displayed image of a display device employing CMOS GOA.

[0005] An embodiment of the present invention provides a display device, including a plurality of pixels, a plurality of first gate lines, a plurality of second gate lines, a plurality of third gate lines, a cascaded multi-stage first gate driving circuit, and a cascaded multi-stage second gate driving circuit;

[0006] The pixel includes an electrically connected pixel circuit and a light-emitting element, the pixel circuit including:

[0007] A driving transistor is used to generate a driving current for driving the light-emitting element to emit light based on a data signal;

[0008] A data writing transistor is electrically connected to the driving transistor and is used to transmit the data signal to the driving transistor. The gate of the data writing transistor is electrically connected to the corresponding first gate line.

[0009] A first reset transistor is electrically connected to the driving transistor and is used to transmit a first reset signal to the driving transistor. The gate of the first reset transistor is electrically connected to the corresponding second gate line.

[0010] Wherein, the first gate driving circuit is used to transmit at least one first gate signal to a plurality of data writing transistors in at least one row of pixels in a first region through at least one first gate line, and the second gate driving circuit is used to transmit at least another first gate signal to a plurality of data writing transistors in at least one row of pixels in a second region through at least another first gate line.

[0011] The first gate driving circuit is used to transmit a second gate signal to a plurality of the first reset transistors in at least one row of the corresponding pixels via a second gate line;

[0012] The second gate driving circuit is used to transmit a third gate signal to a plurality of compensation transistors in at least one row of the corresponding pixels via a third gate line;

[0013] The first gate driving circuit and the second gate driving circuit both include a first output module, the first output module comprising:

[0014] The first pull-up module is used to output a first signal to the corresponding first gate line according to the signal of the first node of the current stage as a first gate signal of the current stage.

[0015] The first pull-down module is used to output a second signal to the corresponding first gate line based on the signal of the first node of the previous i stages as a first gate signal of the current stage, where i is a positive integer;

[0016] The pulses of the signal of the first node in the current stage and the pulses of the signal of the first node in the previous i stage of the second gate driving circuit have overlapping periods, and the first gate line electrically connected to the second gate driving circuit is in a passive output state during the overlapping period.

[0017] The start time of the pulse of the second gate signal acting on the second region is located before the overlapping period corresponding to the second gate drive circuit used to generate the first gate signal acting on the second region.

[0018] Embodiments of the present invention provide a display device in which a first gate driving circuit and a second gate driving circuit respectively transmit corresponding first gate signals to at least one row of pixel data writing transistors in a first region and a second region. The first gate driving circuit and the second gate driving circuit also respectively transmit second gate signals and third gate signals to a first reset transistor and a compensation transistor in at least one row of pixels. The pulses of the signals of the first nodes of the current stage and the two preceding stages in the second gate driving circuit have overlapping time periods. The starting time of the pulse of the second gate signal acting on the second region is located before the overlapping time period to avoid the passive output state of the first gate line electrically connected to the second region. This reduces the risk of potential jump of the first gate signal acting on the pixels in the second region, making the brightness of the second region close to the brightness of the first region, and improving the uniformity of the display screen. Attached Figure Description

[0019] Figure 1 and Figure 4 This is a schematic diagram of the architecture of a display device provided in an embodiment of the present invention.

[0020] Figure 2 This is a circuit diagram of a pixel provided in an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of the area division of a display device provided in an embodiment of the present invention.

[0022] Figure 5 These are circuit diagrams of the first gate driving circuit and the second gate driving circuit provided in embodiments of the present invention.

[0023] Figure 6 The comparative example provided by this invention shows the timing diagrams of partial signals in the pixel circuits corresponding to the first region and the second region, respectively, as well as the timing diagrams of partial signals in the first gate driving circuit and the second gate driving circuit, respectively.

[0024] Figure 7 This is a timing diagram of partial signals in the pixel circuits corresponding to the first region and the second region respectively, provided by an embodiment of the present invention. It also includes timing diagrams of partial signals in the first gate driving circuit and the second gate driving circuit respectively. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention.

[0026] The embodiments of the present invention provide a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0027] In some embodiments, such as Figure 1 As shown, the display device 100 includes multiple pixels Pi, multiple first gate lines G1, multiple second gate lines G2, multiple third gate lines G3, cascaded multi-stage first gate driving circuit CMOS_T4, and cascaded multi-stage second gate driving circuit CMOS_T3; as Figure 2 As shown, the pixel Pi includes a pixel circuit 20 and a light-emitting element 30 electrically connected. The pixel circuit 20 includes: a driving transistor M1, used to generate a driving current for driving the light-emitting element 30 to emit light according to a data signal data; a data writing transistor M2, electrically connected to the driving transistor M1, used to transmit the data signal data to the driving transistor M1, the gate of the data writing transistor M2 being electrically connected to the corresponding first gate line G1; and a first reset transistor M4, electrically connected to the driving transistor M1, used to transmit a first reset signal vi_g to the driving transistor M1, the gate of the first reset transistor M4 being electrically connected to the corresponding second gate line G2.

[0028] Among them, combined Figure 1 and Figure 3 As shown, the first gate driving circuit CMOS_T4 is used to transmit at least one first gate signal pscan1 (referred to as pscan1_1) to a plurality of data write transistors M2 in at least one row of the pixels Pi in the first region A1 through at least one first gate line G1, and the second gate driving circuit CMOS_T3 is used to transmit at least another first gate signal pscan1 (referred to as pscan1_2) to a plurality of data write transistors M2 in at least one row of the pixels Pi in the second region A2 through at least another first gate line G1.

[0029] To facilitate differentiation, the signals of the same nodes in the first gate drive circuit CMOS_T4 and the second gate drive circuit CMOS_T3 of the n2th stage are represented by "_1" and "_2" respectively.

[0030] The display device 100 includes a display area AA (including at least a first area A1 and a second area A2) and a border area (not shown) located on at least one side of the display area AA. The aforementioned plurality of pixels Pi, plurality of first gate lines G1, plurality of second gate lines G2, and plurality of third gate lines G3 are located in the display area AA. The aforementioned cascaded multi-level first gate driving circuit CMOS_T4 and cascaded multi-level second gate driving circuit CMOS_T3 are located in the border area. In this embodiment, the relative positions of the first area A1 and the second area A2 in the display area AA are not limited.

[0031] For example Figure 3 As shown, the first region A1 and the second region A2 can be two regions within the display area AA that cover different columns of pixels Pi. That is, multiple pixels Pi in the first region A1 and multiple pixels Pi in the second region A2 are located in different columns. In this case, it is not limited whether the pixels Pi covered by the first region A1 and the second region A2 are located in the same row. Furthermore, as... Figure 3 As shown, multiple pixels Pi in the first region A1 and multiple pixels Pi in the second region A2 are located in the same row. That is, the position of the multiple pixels Pi covered by the first region A1 and the second region A2 in the column direction and the number of rows they contain are the same.

[0032] For example, the first region A1 and the second region A2 can also be two regions (not shown) within the display area AA that cover different rows of pixels Pi. Furthermore, the first region A1 can cover several rows of pixels Pi, and the second region A2 can cover several other rows of pixels Pi. Furthermore, the first region A1 can include multiple odd-numbered rows of pixels Pi, and the second region A2 can include multiple even-numbered rows of pixels Pi.

[0033] In this invention, only Figure 3 The relative positional relationship between the first region A1 and the second region A2 is illustrated as an example. Other relative positional relationships between the first region A1 and the second region A2 can be understood in the same way.

[0034] Specifically, in Figure 3 Based on, combined Figure 1 and Figure 3 As shown, the display device 100 includes an opening region OA located between the first region A1 and the second region A2. The first gate line G1 electrically connected to a row of pixels Pi in the first region A1 and the first gate line G1 electrically connected to the same row of pixels Pi in the second region A2 are located on both sides of the opening region OA, and are respectively electrically connected to the corresponding first gate driving circuit CMOS_T4 and the corresponding second gate driving circuit CMOS_T3.

[0035] That is, the first gate driving circuit CMOS_T4 is electrically connected to at least one row of pixels Pi in the first region A1 through at least one first gate line G1 to provide at least one first gate signal pscan1 (referred to as pscan1_1), and the corresponding second gate driving circuit CMOS_T3 is electrically connected to at least one row of pixels Pi in the second region A2 through at least another first gate line G1 to provide at least another first gate signal pscan1 (referred to as pscan1_2).

[0036] Furthermore, in combination Figure 4 and Figure 3 As shown, the display area in the display device 100 also includes a non-aperture area NOA surrounding the aperture area OA. In the non-aperture area NOA, excluding the first area A1 and the second area A2, multiple data writing transistors M2 in multiple pixels Pi in the same row are electrically connected to the corresponding first gate driving circuit CMOS_T4 and the corresponding second gate driving circuit CMOS_T3 through the same first gate line G1.

[0037] That is, in the non-opening region NOA, excluding the first region A1 and the second region A2, the first gate driving circuit CMOS_T4 and the corresponding second gate driving circuit CMOS_T3 are both electrically connected to a row of pixels Pi in the first region A1 through the same first gate line G1 to provide the same first gate signal pscan1 (which can be understood as being determined by the interaction between pscan1_1 and pscan1_2).

[0038] Therefore, it can be assumed that within the non-aperture region NOA, excluding the first region A1 and the second region A2, each row of pixels Pi can be acted upon by the same first gate signal pscan1 to affect the multiple data writing transistors M2 of that row to the same degree, thereby avoiding the phenomenon of uneven display caused by the difference in the working state of the multiple pixels Pi of that row.

[0039] Based on the above analysis, for the first region A1 and the second region A2, the portions of each row of pixels Pi located in the first region A1 and the portions located in the second region A2 are respectively affected by the two first gate signals pscan1 (pscan1_1, pscan1_2) generated by the first gate driving circuit CMOS_T4 and the corresponding second gate driving circuit CMOS_T3, which affect the multiple data writing transistors M2 of that row to different degrees. This causes the working states of the multiple pixels Pi in that row to differ, resulting in uneven display.

[0040] Specifically, such as Figure 1 and Figure 4 As shown, for the display area AA, the first gate driving circuit CMOS_T4 is used to transmit a second gate signal nscan2_t4 to a plurality of first reset transistors M4 in at least one row of the corresponding pixels Pi through a second gate line G2; the second gate driving circuit CMOS_T3 is used to transmit a third gate signal nscan1_t3 to a plurality of transistors (e.g., compensation transistors M3) in at least one row of the corresponding pixels Pi other than the driving transistor M1, the data writing transistor M2, and the first reset transistor M4 through a third gate line G3.

[0041] Specifically, in combination Figure 1 , Figure 4 and Figure 5 As shown, the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 include a first output module 40. Here, we take the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 of the nth stage (n is a positive integer) as an example. The first output module 40 includes: a first pull-up module 401, which is used to output a first signal PVGH to the corresponding first gate line G1 according to the signal P[n] of the first node P of the current stage as the first gate signal pscan1[n] of the current stage (e.g., pscan1_1_1[n], pscan1_2_1[n] below); and a first pull-down module 402, which is used to output a second signal (e.g., a part of the first clock signal CK1) to the corresponding first gate line G1 according to the signal P[n-2] of the first node P of the previous i stages (i is a positive integer, and we take i=2 as an example) as the first gate signal pscan1[n] of the current stage (e.g., pscan1_1_1[n], pscan1_2_1[n] below).

[0042] in, Figure 6 The diagram illustrates the timing of some signals in the pixel circuit 20 corresponding to the first region A1 and the second region A2 in the same row of pixels Pi, as well as the timing of some signals in the first gate drive circuit CMOS_T4 and the second gate drive circuit CMOS_T3, which act on the two regions respectively.

[0043] In some embodiments, combined with Figure 1 and Figure 3As shown, the multi-stage first gate driving circuit CMOS_T4 is located on one of the left and right sides (e.g., the left side) of the plurality of pixels Pi, and the multi-stage second gate driving circuit CMOS_T3 is located on the other of the left and right sides (e.g., the right side) of the plurality of pixels Pi. For example, it can be defined as follows: the display device 100 includes a first border area NA1 located on the left side of the display area AA and a second border area NA2 located on the right side of the display area AA; wherein, the multi-stage first gate driving circuit CMOS_T4 is located on one of the first border area NA1 and the second border area NA2, and the multi-stage second gate driving circuit CMOS_T3 is located on the other of the first border area NA1 and the second border area NA2.

[0044] Understandably, since multiple first reset transistors M4 and multiple compensation transistors M3 in the same row of pixels Pi need to be acted upon by multiple levels of first gate driving circuit CMOS_T4 and multiple levels of second gate driving circuit CMOS_T3 respectively, the number of levels of the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 are approximately the same. In order to avoid the two from accumulating on the same side of multiple pixels Pi and causing the border on that side to be too large, in this embodiment, the two are set to be distributed on the left and right sides of multiple pixels Pi respectively, or distributed on the right and left sides of multiple pixels Pi respectively, so that the maximum width of the border of the display device 100 can be smaller.

[0045] In some embodiments, combined with Figure 1 and Figure 3 As shown, the first gate driving circuit CMOS_T4 transmits two first gate signals pscan1 (i.e., pscan1_1) to a plurality of data writing transistors M2 in two rows (referred to as the first target row and the second target row) of pixels Pi in the first region A1 through two first gate lines G1; the second gate driving circuit CMOS_T3 at the same level transmits another two first gate signals pscan1 (i.e., pscan1_2) to a plurality of data writing transistors M2 in the same two rows of pixels Pi in the second region A2 through another two first gate lines G1.

[0046] This example illustrates how a pixel Pi in a certain row can be simultaneously acted upon by the second gate signal nscan2_t4[n1] generated by the first gate driving circuit CMOS_T4 at level n1 and the third gate signal nscan1_t3[n2] generated by the second gate driving circuit CMOS_T3 at level n2, as well as by two first gate signals pscan1[n3] (i.e., pscan1_1[n3] and pscan1_2[n3]) generated by the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 at the same level (e.g., level n3). n1, n2, and n3 can be all equal, partially equal, or all unequal, and all are positive integers. For example, in the comparative example, the pixel Pi in the 2x-1 row and the 2x row can be simultaneously acted upon by the first gate driving circuit CMOS_T4 at level x-5, the second gate driving circuit CMOS_T3 at level x+2, the first gate driving circuit CMOS_T4 at level x, and the second gate driving circuit CMOS_T3 at level x, where x is a positive integer greater than 5.

[0047] Among them, such as Figure 5 As shown, the first pull-up module 401 and the corresponding first pull-down module 402 are electrically connected to one of the two first gate lines G1 electrically connected to the corresponding first gate driving circuit CMOS_T4 or the corresponding second gate driving circuit CMOS_T3. The time period of the pulse of the first gate signal pscan1 acting on a row of pixels Pi in the first region A1 is the same as the time period of the pulse of the first gate signal pscan1 acting on the same row of pixels Pi in the second region A2.

[0048] Specifically, the two first gate signals pscan1_1[n3] (i.e., pscan1_1_1[n3] and pscan1_1_2[n3]) generated by the first gate driving circuit CMOS_T4 of the n3rd stage can be transmitted to the two adjacent rows of pixels Pi in the first region A1 through the two first gate lines G1 respectively. The two first gate signals pscan1_2[n3] (i.e., pscan1_2_1[n3] and pscan1_2_2[n3]) generated by the second gate driving circuit CMOS_T3 of the n3rd stage can be transmitted to the two adjacent rows of pixels Pi in the second region A2 through the two first gate lines G1 respectively.

[0049] Among them, such as Figure 6 and Figure 7As shown, the first gate signal pscan1_1_1[n3] generated by the first gate driving circuit CMOS_T4 of the n3rd stage and the first gate signal pscan1_2_1[n3] generated by the second gate driving circuit CMOS_T3 of the n3rd stage can both act on the first row of pixels Pi in two adjacent rows of pixels Pi, and correspondingly, the pulses of the two are in the same time period; similarly, the first gate signal pscan1_1_2[n3] generated by the first gate driving circuit CMOS_T4 of the n3rd stage and the first gate signal pscan1_2_2[n3] generated by the second gate driving circuit CMOS_T3 of the n3rd stage can both act on the last row of pixels Pi in two adjacent rows of pixels Pi, and correspondingly, the pulses of the two are in the same time period.

[0050] At the same time, combined Figure 1 , Figure 3 , Figures 5 to 7 As shown, the pulses of the two first gate signals pscan1 (e.g., pscan1_1_1[n3], pscan1_1_2[n3] generated by the first gate driving circuit CMOS_T4 at the n3rd level, and pscan1_2_1[n3], pscan1_2_2[n3] generated by the second gate driving circuit CMOS_T3 at the n3rd level) acting on the two rows of pixels Pi in each of the first region A1 and the second region A2 are in two different time periods, so that the two first gate signals pscan1_1 generated by the first gate driving circuit CMOS_T4 can control the data writing transistor M2 of the corresponding two rows of pixels Pi to be turned on in a time-division manner, and the two first gate signals pscan1_2 generated by the second gate driving circuit CMOS_T3 can be analyzed in the same way.

[0051] That is, in this embodiment, the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 of the same level generate at least two first gate signals pscan1 with the same phase (i.e., pscan1_1_1[n3] and pscan1_2_1[n3] with the same waveform) to act on the corresponding row of pixels Pi. Furthermore, the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 of this level can also generate two first gate signals pscan1 with the same other phase (i.e., pscan1_1_2[n3] and pscan1_2_2[n3] with the same waveform) to act on the corresponding other row of pixels Pi, so as to realize the dual-sided driving and single-level driving of the first gate signal pscan1 for two rows.

[0052] Combination Figure 5 and Figure 6As shown, both the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 further include a control module 50. The control module 50 is used to control the signal P[n] of the first node P of the current stage according to the frame start signal stv (when n=1 above) or the signal P[n-1] of the first node P of the previous r stages (where r is a positive integer less than i, and r=1 is used as an example here) (when n is greater than 1 above), and the third clock signal XCK.

[0053] It should be noted that, due to the different operating stages of the first reset transistor M4 and compensation transistor M3 in the same pixel Pi, at least one of the phase and pulse width of the pulses acting on the second gate signal nscan2_t4[n1] and the corresponding third gate signal nscan1_t3[n2] is different (here, at least the pulse width is different as an example). Therefore, the pulse widths of the two frame start signals stv corresponding to the first gate driving circuit CMOS_T4 of the n1 stage and the second gate driving circuit CMOS_T3 of the n2 stage are also at least different. The third clock signal XCK mentioned above can be understood as being used to shift the two frame start signals stv respectively. Therefore, the signals of the same nodes in the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 of the n2 stage are also at least different, such as... Figure 6 As shown, the pulse widths of signals at the same nodes in the first gate drive circuit CMOS_T4 and the second gate drive circuit CMOS_T3 of the n2th stage (e.g., the first gate drive circuit CMOS_T4 of the n1st stage and the second gate drive circuit CMOS_T3 of the n2nd stage mentioned above) are even more different.

[0054] For example, the pulse width of the first node P_1[n3-2] of the first two stages in the first gate driving circuit CMOS_T4 of the n3rd stage is different from the pulse width of the first node P_2[n3-2] of the first two stages in the second gate driving circuit CMOS_T3 of the n3rd stage. Correspondingly, the pulse widths of the first node P_1[n3] and the first node P_2[n3] of the current stage are also different.

[0055] Among them, such as Figure 6 As shown, in conjunction with the above discussion, the first gate signal pscan1_1[n3] output by the first output module 40 in the first gate drive circuit CMOS_T4 of the n3rd stage and the first gate signal pscan1_2[n3] output by the first output module 40 in the second gate drive circuit CMOS_T3 of the n3rd stage have at least different pulse widths.

[0056] Furthermore, in combination Figure 5 and Figure 6 As shown in the comparative example, it can be assumed that for either the first gate drive circuit CMOS_T4 or the second gate drive circuit CMOS_T3, the phase difference of the signals of the first nodes P in adjacent stages can be the same. However, the pulse width of the first node P signal in the former is smaller than that in the latter, resulting in the pulses of the first nodes P signals in adjacent stages not overlapping in the former, while the pulses of the first nodes P signals in adjacent stages overlap in the latter.

[0057] like Figure 6 As shown, the pulses of the signal P_1[n3] of the first node P of the current stage in the first gate drive circuit CMOS_T4 of each stage (e.g., the n3rd stage) and the pulses of the signal P_1[n3-2] of the first node P of the previous two stages do not have an overlapping period t01, while the pulses of the signal P_2[n3] of the first node P of the current stage in the second gate drive circuit CMOS_T3 of each stage (e.g., the n3rd stage) and the pulses of the signal P_2[n3-2] of the first node P of the previous two stages have an overlapping period t01. The first gate line G1 electrically connected to the second gate drive circuit CMOS_T3 is in a floating state (i.e., a passive output state) during the overlapping period t01.

[0058] Specifically, in combination Figure 5 and Figure 6As shown, the first pull-down module 402 is further configured to output the second signal to the corresponding first gate line G1 according to the first clock signal CK1 as the first gate signal pscan1[n] of the current stage, wherein the second signal includes the pulse of the first clock signal CK1. The first pull-down module 402 includes: a first pull-down control transistor T8, the gate of the first pull-down control transistor T8 being electrically connected to the first node P of the previous i stage (this invention uses i=2 as an example), one of the source and drain of the first pull-down control transistor T8 being electrically connected to the second node K of the current stage, and the phase of the signal K[n] of the second node K of the current stage being opposite to the phase of the signal P[n] of the first node P of the current stage (for example, the signal K_1[n3] of the second node K of the current stage and the signal P_1[n3] of the first node P of the current stage in the first gate drive circuit CMOS_T4 of the n3rd stage). The two signals are out of phase (the signals K_2[n3] of the second node K of the current stage and the signals P_2[n3] of the first node P of the current stage in the second gate drive circuit CMOS_T3 of the n3 stage are out of phase); the first pull-down transistor T6, the gate of the first pull-down transistor T6 is electrically connected to the other of the source and drain of the first pull-down control transistor T8, one of the source and drain of the first pull-down transistor T6 is electrically connected to the first clock line for transmitting the first clock signal CK1, and the other of the source and drain of the first pull-down transistor T6 is electrically connected to the corresponding first gate line G1.

[0059] Furthermore, the first pull-down module 402 also includes a first bootstrap capacitor C1, electrically connected between the gate of the first pull-down transistor T6 and the corresponding first gate line G1. When the first pull-down transistor T6 is turned on and the first clock signal CK1 switches to its effective pulse (e.g., a low-potential pulse), the first pull-down transistor T6 is pulled down by the coupling between itself and the first clock line, and further pulled down by the first bootstrap capacitor C1, the potential of the first gate signal pscan1[n] output by the first gate line G1 is also further pulled down.

[0060] Specifically, in combination Figure 5 and Figure 6 As shown, the first pull-up module 401 includes: a first pull-up transistor T7, the gate of the first pull-up transistor T7 is electrically connected to the first node P of the current stage, one of the source and drain of the first pull-up transistor T7 is electrically connected to a first signal line for transmitting the first signal PVGH, and the other of the source and drain of the first pull-up transistor T7 is electrically connected to the corresponding first gate line G1.

[0061] Understandable, Figure 5In the circuit shown, when the first pull-down transistor T6 and the first pull-up transistor T7 are simultaneously turned off, the corresponding first gate line G1 is in a floating state. At this time, the signal Q1[n] of the third node Q1 of the current stage and the signal P[n] of the first node P of the current stage need to be at the corresponding high potential. That is, the signal K[n] of the second node K at this time should be at the corresponding low potential. Without considering the electrical disconnection between the second node K and the fourth node M controlled by the first frequency divider module 801, it can be assumed that the signal M[n] of the fourth node M is also at the corresponding low potential. Therefore, in order to prevent the signal M[n] of the fourth node M, which is at the low potential, from being transmitted to the third node Q1, the signal P[n-2] of the first node P of the previous two stages needs to be at the corresponding high potential to control the first pull-down control transistor T8 to be turned off.

[0062] That is, both the signal P[n-2] of the first node P and the signal P[n] of the current stage's first node P are at corresponding high potentials. During the overlapping period t01 of their pulses, the corresponding first gate line G1 is in a floating state, making the corresponding first gate signal pscan1[n] susceptible to interference. Therefore, observing... Figure 6 As can be seen, in the comparative example, the first gate driving circuit CMOS_T4 of each stage (e.g., the n1th stage) is not easily interfered with because the aforementioned overlapping period t01 does not exist. However, the first gate signal pscan1_1[n1] of the second gate driving circuit CMOS_T3 of each stage (e.g., the n2th stage) is easily interfered with because the aforementioned overlapping period t01 exists.

[0063] Based on the above, combined with Figure 2 and Figure 6As shown, combined with the above discussion of pixel circuit 20, since the gate of the first reset transistor M4 in a certain row of pixels Pi is loaded with the second gate signal nscan2_t4[n1] generated by the first gate driving circuit CMOS_T4 of the corresponding level (e.g., the n1th level), and the first reset transistor M4 is electrically connected to the driving transistor M1, and the data writing transistor M2 is electrically connected to the driving transistor M1, and the gate of the data writing transistor M2 is electrically connected to the corresponding first gate line G1, it can be considered that after the second gate signal nscan2_t4[n1] controls the first reset transistor M4 to turn on (e.g., the start time t1 of the pulse of the second gate signal nscan2_t4[n1]), the first reset signal vi_g will be transmitted to the driving transistor M1, through the action of multiple coupling capacitors between the transistors. This causes a large jump in the potential of a certain end (e.g., its gate) of the driving transistor M1, resulting in a large jump in the potential of the first pixel node Q (e.g., the first pixel node Q_1 corresponding to the first gate driving circuit CMOS_T4 at the n1 level or the first pixel node Q_2 corresponding to the second gate driving circuit CMOS_T3 at the n2 level). Since only the second gate driving circuit CMOS_T3 has the aforementioned overlapping period t01, the potential of the first gate signal pscan1_2[n2] acting on the gate of the data writing transistor M2 at the corresponding level (e.g., the n2 level) is prone to jump, causing the brightness of the second region A2 it acts on to differ from the brightness of the first region A1 acted on by the first gate signal pscan1_1[n1], thus reducing the uniformity of the display screen.

[0064] in, Figure 6 , Figure 7 They also indicated respectively Figure 2 The potential timing diagram of the second pixel node A (e.g., the second pixel node A_1 corresponding to the first gate driving circuit CMOS_T4 at the n1st level or the second pixel node A_2 corresponding to the second gate driving circuit CMOS_T3 at the n2nd level) and the third pixel node B (e.g., the third pixel node B_1 corresponding to the first gate driving circuit CMOS_T4 at the n1st level or the third pixel node B_2 corresponding to the second gate driving circuit CMOS_T3 at the n2nd level).

[0065] Understandably, in order to improve the technical problems in the above comparative examples, combined with Figure 5 and Figure 7As shown, in this embodiment, the start time t1 of the pulse of the second gate signal nscan2_t4 acting on the second region A2 is set to be before the overlapping period t01 of the second gate driving circuit CMOS_T3 used to generate the first gate signal pscan1 (i.e., pscan1_2[n3]) acting on the second region A2. That is, the overlapping period t01 of the second gate driving circuit CMOS_T3 avoids the start time t1 of the pulse of the second gate signal nscan2_t4, so that the potential jump of the first pixel node Q in the corresponding pixel circuit is before the period when the first gate line G1 electrically connected to the second gate driving circuit CMOS_T3 is in a floating state. This avoids the potential jump of the first pixel node Q affecting the potential of the first gate signal pscan1_2[n3] during the floating state of the first gate line G1 of the second gate driving circuit CMOS_T3, reduces the risk of potential jump of the first gate signal pscan1_2[n3], and makes the brightness of the second region A2 close to the brightness of the first region A1, so as to improve the uniformity of the display screen.

[0066] In this embodiment, the specific method of realizing the start time t1 of the pulse of the second gate signal nscan2_t4 corresponding to the second region A2 and the corresponding overlapping time period t01 is not limited. For example, the timing of the corresponding second gate signal nscan2_t4 can be adjusted, the timing of the signal P[n] of the first node P of the current stage and the signal P[n-2] of the first node P of the previous two stages can be adjusted, or the above adjustments can be performed simultaneously.

[0067] In some embodiments, combined with Figure 1 and Figure 3 As shown, the first gate driving circuit CMOS_T4 transmits a second gate signal nscan2_t4 through a second gate line G2 to a plurality of first reset transistors M4 in both the first region A1 and the second region A2 located in the first target row and the second target row; the second gate driving circuit CMOS_T3 of the same or different level transmits a third gate signal nscan1_t3 through a third gate line G3 to a plurality of transistors (e.g., the compensation transistor M3 mentioned above) in both the first region A1 and the second region A2 located in the first target row and the second target row, excluding the driving transistor M1, the data writing transistor M2, and the first reset transistor M4.

[0068] That is, in this embodiment, the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 of different levels generate a second gate signal nscan2_t4 and a third gate signal nscan1_t3 respectively, which are applied to the corresponding two rows of pixels Pi, so as to realize the driving mode of single-sided driving of the second gate signal nscan2_t4 and the third gate signal nscan1_t3 and the driving mode of driving two rows in one stage.

[0069] For example Figures 5 to 7 As shown, the second gate signal nscan2_t4[n1] generated by the first gate driving circuit CMOS_T4 of the n1th stage can be applied to the two adjacent rows of pixels Pi, and the third gate signal nscan1_t3[n2] generated by the second gate driving circuit CMOS_T3 of the n2th stage can also be applied to the "two adjacent rows of pixels Pi".

[0070] Based on the aforementioned driving methods for the second gate signal nscan2_t4 and the third gate signal nscan1_t3, combined with Figure 1 and Figure 3 As shown, at least a portion of the pixels Pi in the first region A1 and at least a portion of the pixels Pi in the second region A2 are electrically connected to the same second gate line G2; at least a portion of the pixels Pi in the first region A1 and at least a portion of the pixels Pi in the second region A2 are electrically connected to the same third gate line G3.

[0071] Understandably, since each of the second gate signal nscan2_t4 and the third gate signal nscan1_t3 can only be generated by a single-sided first gate driving circuit CMOS_T4 and second gate driving circuit CMOS_T3, the two parts of each row of pixels Pi located in the first region A1 and the second region A2 respectively need to be electrically connected to the same second gate line G2 to receive the corresponding second gate signal nscan2_t4, and both need to be electrically connected to the same third gate line G3 to receive the corresponding third gate signal nscan1_t3. The aforementioned second gate line G2 and third gate line G3 can be set around the edge of the opening region OA, or through the wiring layer within the opening region OA, thereby electrically connecting the pixels Pi in the first region A1 and the second region A2.

[0072] In some embodiments, to achieve the above-described driving method for the first gate signal pscan1, such as... Figure 5As shown, the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 further include a second output module 60. The second output module 60 includes a second pull-up module 601, which is used to output the first signal PVGH to the other of the two first gate lines G1 electrically connected to the corresponding first gate driving circuit CMOS_T4 or the corresponding second gate driving circuit CMOS_T3 according to the signal P[n] of the first node P of the current stage, as another first gate signal pscan1[n] of the current stage (e.g., pscan1_1_2[n] and pscan1_2_2[n] mentioned above). The second pull-down module 602 is used to output a third signal (e.g., a portion of the second clock signal CK2) to the other of the two first gate lines G1 electrically connected to the corresponding first gate drive circuit CMOS_T4 or the corresponding second gate drive circuit CMOS_T3, based at least on the signal P[n-2] of the first node P of the previous i stage (taking i=2 as an example) and the second clock signal CK2, as another first gate signal pscan1 of the current stage (e.g., pscan1_1_2[n] and pscan1_2_2[n] mentioned above), wherein the third signal includes the pulse of the second clock signal CK2.

[0073] The second pull-up module 601 may include a second pull-up transistor T25, and the second pull-down module 602 may include a second pull-down transistor T24, a second pull-down control transistor T23, and a second bootstrap capacitor C2. The connection relationship of the second output module 60 can be referred to... Figure 5 Its working principle can be found in the relevant discussion of the first output module 40 above.

[0074] The pulses of the first clock signal CK1 and the second clock signal CK2 are in different time periods, so that the pulses included in the second signal and the third signal are in different time periods. This makes the pulses of the first gate signal pscan1 (e.g., pscan1_1_1[n] and pscan1_2_1[n] above) output by the first output module 40 acting on one of the two adjacent rows of pixels Pi, and the pulses of the first gate signal pscan1 (e.g., pscan1_1_2[n] and pscan1_2_2[n] above) output by the second output module 60 acting on the other of the two adjacent rows of pixels Pi, in turn control the data writing transistor M2 of the corresponding two rows of pixels Pi to be turned on in a time-division multiplexing manner.

[0075] In some embodiments, to implement the above-described driving method for the second gate signal nscan2_t4 and the third gate signal nscan1_t3, such as... Figure 5As shown, the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 further include a third output module 70. The third output module 70 in the first gate driving circuit CMOS_T4 is used to generate the second gate signal nscan2_t4[n] of the current stage based on the signal P[n] of the first node P of the current stage. The third output module 70 in the second gate driving circuit CMOS_T3 is used to generate the third gate signal nscan1_t3[n] of the current stage based on the signal P[n] of the first node P of the current stage.

[0076] Specifically, the third output module 70 may include a third pull-up transistor T9 and a third pull-down transistor T10. The gate of the third pull-up transistor T9 is electrically connected to the second node K of the current stage. The fourth signal NVGH is loaded on one of the source and drain of the third pull-up transistor T9. The gate of the third pull-down transistor T10 is also electrically connected to the second node K of the current stage. The fifth signal NVGL is loaded on one of the source and drain of the third pull-up transistor T9. Since the phase of the signal K[n] of the second node K of the current stage is opposite to the phase of the signal P[n] of the first node P of the current stage, it can also be understood that the signal P[n] of the first node P of the current stage controls the conduction status of the third pull-up transistor T9 and the third pull-down transistor T10, thereby controlling the third output module 70 to output the potential of the fourth signal NVGH or the potential of the fifth signal NVGL in real time, so as to form the current second gate signal nscan2_t4[n] or the third gate signal nscan1_t3[n].

[0077] Furthermore, such as Figure 5 As shown, the first gate driving circuit CMOS_T4 and the second gate driving circuit CMOS_T3 also include a second frequency divider module 802. The first frequency divider module 801 is used to control whether a current path is formed between the second node K and the fourth node M, thereby controlling whether the first output module 40 can output a first gate signal pscan1[n] with a corresponding gate pulse in each frame, so as to control whether the corresponding data writing transistor M2 is turned on in the frame to refresh the data signal data. Similarly, the second frequency divider module 802 is used to control whether a current path is formed between the second node K and the fifth node W, thereby controlling whether the third output module 70 can output a second gate signal nscan2_t4[n] or a third gate signal nscan1_t3[n] with a corresponding gate pulse in each frame, so as to control whether the corresponding first reset transistor M4 or compensation transistor M3 is turned on in the frame to reset the gate of the driving transistor M1 or compensate the threshold voltage of the driving transistor M1.

[0078] Furthermore, such as Figure 5 As shown, the first output module 40 also includes a first stabilization module 403, which includes a first stabilizing transistor T21 and a second stabilizing transistor T22. The gate of the first stabilizing transistor T21 is loaded with a third clock signal XCK, and the gate of the second stabilizing transistor T22 is electrically connected to the first node P. One of the source and drain of the second stabilizing transistor T22 is loaded with a first signal PVGH, so that the first stabilization module 403 stabilizes the potential of the fourth node M of the current stage according to the potential of the first node P of the current stage. Similarly, the third output module 70 also includes a third stabilizing transistor T17 and a fourth stabilizing transistor T18. The working principle of the latter can be referred to the working principle of the first stabilizing transistor T21 and the second stabilizing transistor T22.

[0079] The specific components and connection methods of the control module 50, the first frequency divider module 801, and the second frequency divider module 802 can be found in [reference needed]. Figure 5 .

[0080] In some embodiments, such as Figure 2 As shown, the pixel circuit 20 further includes: the aforementioned compensation transistor M3, which is electrically connected between the source and drain of the driving transistor M1 and the gate of the driving transistor M1, and the gate of the compensation transistor M3 is connected to the corresponding third gate line G3; wherein, the first reset transistor M4 is electrically connected to the gate of the driving transistor M1.

[0081] Among them, such as Figure 7 As shown, the start time t1 of the pulse of the second gate signal nscan2_t4[n1] acting on the pixel Pi in the same row is ahead of the start time t2 of the pulse of the third gate signal nscan1_t3[n2] acting on the pixel Pi in the same row by k1 units of duration h, where k1 is a positive integer and the unit duration h is the phase difference between the two third gate signals nscan1_t3 of the two adjacent levels (i.e., the time interval between their start times); wherein, the pulse width of the pulse of the third gate signal nscan1_t3[n2] is equal to the pulse width of the signal of the first node P_2[n3].

[0082] On the one hand, based on the above discussion of the third output module 70, it can be seen that, as Figure 5As shown, the second gate signal nscan2_t4[n] and the third gate signal nscan1_t3[n] are both generated by the corresponding third output module 70 based on the pulse of the signal P[n] of the first node P of the current stage. Therefore, the start time of the pulse of the signal P[n] of the first node P of the current stage (e.g., the nth stage) is the same as the start time of the pulse of the second gate signal nscan2_t4[n] or the third gate signal nscan1_t3[n] of the current stage, and the pulse width of the pulse of the signal P[n] of the first node P of the current stage is also the same as the pulse width of the pulse of the second gate signal nscan2_t4[n] or the third gate signal nscan1_t3[n] of the current stage.

[0083] On the other hand, in order for the pixel circuit 20 to operate according to the corresponding timing, in this embodiment, it is necessary to ensure that the start time t1 of the pulse of the second gate signal nscan2_t4[n1] acting on the same row of pixels Pi is ahead of the start time t2 of the pulse of the third gate signal nscan1_t3[n2] acting on the same row of pixels Pi by k units of duration h. Therefore, while adjusting the "overlapping period t0" to avoid the start time t1 of the pulse of the second gate signal nscan2_t4[n1], it is necessary to ensure that the start time t1 of the pulse of the second gate signal nscan2_t4[n1] is ahead of the start time t2 of the pulse of the third gate signal nscan1_t3[n2] by k units of duration h.

[0084] Here, a unit duration h can be equal to twice H, and 1H is the duration of scanning one line of pixels Pi. Specifically, 1H can be equal to 1 / [refresh rate × total number of vertical lines], the total number of vertical lines can be equal to the sum of the number of effective display lines and the number of lines during the vertical blanking period, and the total number of vertical lines can be greater than or equal to the total number of pixels Pi.

[0085] In some embodiments, the start time t1 of the pulse of the second gate signal nscan2_t4 (e.g., the second gate signal nscan2_t4[n1] generated by the first gate driving circuit CMOS_T4 of the n1th stage) acting on the second region A2 is located before the unit duration h of the second gate driving circuit CMOS_T3 (i.e., the second gate driving circuit CMOS_T3 of the n3rd stage) used to generate the first gate signal pscan1 (e.g., the first gate signal pscan1_2[n3] of the n3rd stage) acting on the second region A2 (i.e., the overlapping period of the pulse of the first node P signal P[n3] of the n3rd stage and the pulse of the first node P signal P[n3-2] of the previous two stages), k2 is a positive integer, and k1 and k2 are equal or unequal.

[0086] As discussed above, the phase difference between the signals of the two first nodes P in two adjacent stages is the same as the phase difference between the two first gate signals pscan1 in two adjacent stages. Due to the comparative example... Figure 6 The "overlapping period t01" in the above text leads the second gate signal nscan2_t4[n1] by one unit duration h. Therefore, compared to the comparative example, if the first gate signal pscan1_2[n3+2] generated by the second gate driving circuit CMOS_T3 of the latter two stages is used to drive the pixel Pi in that row, since the first gate signal pscan1 is a bilateral drive, the first gate signal pscan1_1[n3+2] generated by the second gate driving circuit CMOS_T3 of the latter two stages needs to be used to drive the pixel Pi in that row synchronously. However, for pixel Pi in this row, in order to realize the working timing of pixel circuit 20, the original second gate signal nscan2_t4[n1] also needs to be changed to borrow the second gate signal nscan2_t4[n1+2] of the next two stages. This results in the start time t1 of the pulse of the second gate signal nscan2_t4[n1+2] acting on pixel Pi in this row still being ahead of the "overlapping period t01" (i.e. the start time of the pulse of the signal P_2[n3+2] of the first node P of the next two stages) by 1 unit duration h.

[0087] Therefore, in this embodiment, the second gate signal nscan2_t4[n1] and the first gate signal pscan1_2[n3] are still used to act on the row pixel Pi, but as Figure 7 As shown, this embodiment can be understood as changing the pulse start time of the signal P_2[[n3] of the first node P in the second gate drive circuit CMOS_T3 of the n3rd stage from the original Figure 6 In the comparative example shown, the signal nscan2_t4[n1] is ahead of the second gate signal by a certain number of units of time h, and then lags behind the second gate signal nscan2_t4[n1] by a certain number of units of time h. This is to make the "overlapping period t01" lag behind the second gate signal nscan2_t4[n1] by a certain number of units of time h, so that the two no longer overlap. As a result, the floating state of the first gate line G1, which is electrically connected to the second gate drive circuit CMOS_T3, can avoid the potential transition moment of the first pixel node Q.

[0088] It should be noted that the above adjustment method will cause the pulse width of the signal P_2[[n3] of the first node P in the second gate drive circuit CMOS_T3 to be compressed. Correspondingly, since the multi-stage second gate drive circuit CMOS_T3 is cascaded, the pulse width of the signal of the first node P in all stages of the second gate drive circuit CMOS_T3 will be compressed. Correspondingly, the pulse width of the third gate signal nscan1_t3 in all stages will also be compressed to the same extent.

[0089] Therefore, compared Figure 6 Regarding the value of n2 in the comparative example shown, as Figure 7 As shown, in this embodiment, since it is necessary to maintain the start time t2 of the third gate signal nscan1_t3[n2] only lagging behind the second gate signal nscan2_t4[n1] by k units of time h, the value of n2 in this embodiment should be set smaller. This is so that when the start time t2 of the pulse of the third gate signal nscan1_t3[n2] in this embodiment is delayed due to its pulse width compression, the third gate signal nscan1_t3[n2] generated by the second gate driving circuit CMOS_T3, which is at a higher level (with a smaller value of n2), (its start time t2 can be advanced) is applied to the pixel Pi in that row.

[0090] Specifically, assuming that the start time of the pulse of the first node P signal P_2[[n3] in the comparative example precedes the second gate signal nscan2_t4[n1] by k3 units of time h, then in this embodiment, the start time of the pulse of the first node P signal P_2[[n3] and the start time of the pulse of the third gate signal nscan1_t3[n2] are both backward by k3+k2 units of time h compared to the comparative example. Assuming that the value of n2 is y less than that of the comparative example, then it is necessary to satisfy k1+k3+k2-y=k1, that is, k3+k2=y.

[0091] For example Figure 7 As shown, k1 and k2 can be equal, meaning that the start time t2 of the pulse of the third gate signal nscan1_t3[n2] and the start time of the pulse of the signal P_2[n3] of the first node P are the same, i.e., n2 = n3. This means that the pixel Pi in that row is acted upon by the third gate signal nscan1_t3 and the first gate signal pscan1_2 generated by the second gate driving circuit CMOS_T3 of the same level. In other words, the first gate line G1 and the corresponding second gate line G2 of the pixel Pi in the same row within the second region A2 are electrically connected to the first gate driving circuit CMOS_T4 of the same level.

[0092] Furthermore, in combination Figure 6 and Figure 7 As shown, k1, k2, and k3 can be equal, for example, all three can be equal to 1. In this case, y = 1, which means the pulse start time of the first node P signal P_2[[n3] in the comparative example, the pulse start time t1 of the second gate signal nscan2_t4[n1] in the comparative example and this embodiment, and the pulse start time t2 of the third gate signal nscan1_t3[n2] in this embodiment. Each of the three is separated by 1 unit time h.

[0093] In some embodiments, combined with Figure 1 , Figure 3 , Figure 5 and Figure 7 As shown, the pulse width of the second gate signal nscan2_t4 is p units of the aforementioned duration h, and the pulse width of the third gate signal nscan1_t3 is q units of the aforementioned duration h, where p and q are positive integers, and k1+q is greater than or equal to p.

[0094] As discussed above, the start time t1 of the pulse of the second gate signal nscan2_t4[n1] precedes the start time t2 of the pulse of the third gate signal nscan1_t3[n2] by k1 units of duration h. Therefore, the end time of the former and the end time of the latter are p×h and (k1+q)×h, respectively. In order for the pixel circuit 20 to work normally, the end time of the former needs to be earlier than the end time of the latter. Therefore, k1+q is greater than or equal to p.

[0095] In some embodiments, combined with Figure 1 and Figure 4 As shown, the display device 100 also includes multiple fourth gate lines G4 and cascaded multi-stage third gate driving circuits Pscan2_T. Correspondingly, as... Figure 2 As shown, the pixel circuit 20 further includes: a second reset transistor M7, electrically connected to the driving transistor M1, for transmitting a second reset signal vi_ano to the driving transistor M1, wherein the gate of the second reset transistor M7 is electrically connected to the corresponding fourth gate line G4; the third gate driving circuit Pscan2_T transmits two fourth gate signals pscan2 to the plurality of second reset transistors M7 in the corresponding at least two rows of pixels Pi through at least two of the fourth gate lines G4.

[0096] That is, the fourth gate signal pscan2 adopts a two-line driving method of single-sided driving and single-stage driving.

[0097] Furthermore, the pixel circuit 20 also includes a third reset transistor M8, electrically connected to the driving transistor M1 and the data writing transistor M2, for transmitting a third reset signal vi3 to the driving transistor M1, and the gate of the third reset transistor M8 is also electrically connected to the corresponding fourth gate line G4.

[0098] In some embodiments, combined with Figure 1 and Figure 4 As shown, the display device 100 also includes multiple fifth gate lines G5 and cascaded multi-stage fourth gate driving circuits EM_T. Correspondingly, as... Figure 2As shown, the pixel circuit 20 further includes: a light-emitting control transistor (including a first light-emitting control transistor M5 and a second light-emitting control transistor M6), electrically connected to the driving transistor M1 and the light-emitting element 30, used to control whether a current path for the driving current is formed, and the gate of the light-emitting control transistor is electrically connected to the corresponding fifth gate line G5; the fourth gate driving circuit EM_T transmits two fifth gate signals em to the plurality of light-emitting control transistors in the corresponding at least two rows of pixels Pi through at least two of the fifth gate lines G5 respectively.

[0099] That is, the fifth gate signal em adopts a two-line driving method of single-sided driving and single-stage driving.

[0100] For example, such as Figure 1 As shown, the third gate driving circuit Pscan2_T transmits two fourth gate signals pscan2 to a plurality of second reset transistors M7 in the first region A1 and the second region A2 located in the first target row and the second target row, respectively, through two fourth gate lines G4; the fourth gate driving circuit EM_T of the same or different level transmits two fifth gate signals em to a plurality of light-emitting control transistors in the first region A1 and the second region A2 located in the first target row and the second target row, respectively, through two fifth gate lines G5.

[0101] Furthermore, the pixel circuit 20 also includes a storage capacitor Cst connected between the first voltage line VDD and the gate of the driving transistor M1, which is used to store the potential of the gate of the driving transistor M1 to store the threshold voltage of the driving transistor M1; the pixel circuit 20 also includes a bootstrap capacitor Cboost connected between the gate of the data writing transistor M2 and the gate of the driving transistor M1, which is used to further raise or lower the potential of the other according to the potential of the gate of the data writing transistor M2 and the gate of the driving transistor M1. The cathode of the light-emitting element 30 can be connected to the second voltage line VSS.

[0102] In some embodiments, such as Figure 1As shown, the first target row is row 2n-1, the second target row is row 2n, and n is a positive integer greater than 5; the nth-stage first gate driving circuit CMOS_T4 is electrically connected to the pixel Pi located in row 2n-1 and the pixel Pi located in row 2n within the first region A1 through two first gate lines G1; the nth-stage second gate driving circuit CMOS_T3 is electrically connected to the pixel Pi located in row 2n-1 and the pixel Pi located in row 2n within the second region A2 through another two first gate lines G1; the n-5th-stage first gate driving circuit CMOS_T4 is electrically connected to the pixel Pi located in row 2n-1 within the first region A1 and the pixel Pi located in row 2n within the second region A2 through one second gate line G2. The pixel Pi in the 2nth row; the second gate driving circuit CMOS_T3 of the nth stage is electrically connected to the pixel Pi in the (2n-1)th row and the pixel Pi in the 2nth row in the first region A1 and the second region A2 through a third gate line G3; the third gate driving circuit Pscan2_T of the nth stage is electrically connected to the pixel Pi in the (2n-1)th row and the pixel Pi in the 2nth row in the first region A1 and the second region A2 through two fourth gate lines G4; the fourth gate driving circuit EM_T of the nth stage is electrically connected to the pixel Pi in the (2n-1)th row and the pixel Pi in the 2nth row in the first region A1 and the second region A2 through two fifth gate lines G5.

[0103] based on Figure 1 The driver architecture and driver relationships shown are combined with Figure 1 and Figure 7 As shown, the start time t1 of the pulse of the second gate signal nscan2_t4[n1] acting on the pixel Pi in the same row precedes the start time t2 of the pulse of the third gate signal nscan1_t3[n2] acting on the pixel Pi in the same row by one unit duration h; the start time t1 of the pulse of the second gate signal nscan2_t4[n1] acting on the second region A2 is one unit duration h before the overlapping period t01 corresponding to the second gate driving circuit CMOS_T3 used to generate the first gate signal pscan1_2 acting on the second region A2; the pulse width of the second gate signal nscan2_t4[n1] is two unit duration h, and the pulse width of the pulse of the third gate signal nscan1_t3[n2] and the pulse width of the signal P_2[[n3] of P are both six unit duration h.

[0104] That is, k1, k2, and k3 are all 1, p is 2, and q is 6.

[0105] The definition of the unit duration h can be found in the relevant description above.

[0106] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display device, characterized in that, It includes multiple pixels, multiple first gate lines, multiple second gate lines, multiple third gate lines, cascaded multi-stage first gate driving circuits, and cascaded multi-stage second gate driving circuits; The pixel includes an electrically connected pixel circuit and a light-emitting element, the pixel circuit including: A driving transistor is used to generate a driving current for driving the light-emitting element to emit light based on a data signal; A data writing transistor is electrically connected to the driving transistor and is used to transmit the data signal to the driving transistor. The gate of the data writing transistor is electrically connected to the corresponding first gate line. A first reset transistor is electrically connected to the driving transistor and is used to transmit a first reset signal to the driving transistor. The gate of the first reset transistor is electrically connected to the corresponding second gate line. Wherein, the first gate driving circuit is used to transmit at least one first gate signal to a plurality of data writing transistors in at least one row of pixels in a first region through at least one first gate line, and the second gate driving circuit is used to transmit at least another first gate signal to a plurality of data writing transistors in at least one row of pixels in a second region through at least another first gate line. The first gate driving circuit is used to transmit a second gate signal to a plurality of the first reset transistors in at least one row of the corresponding pixels via a second gate line; The second gate driving circuit is used to transmit a third gate signal to a plurality of compensation transistors in at least one row of the corresponding pixels via a third gate line; The first gate driving circuit and the second gate driving circuit both include a first output module, the first output module comprising: The first pull-up module is used to output a first signal to the corresponding first gate line according to the signal of the first node of the current stage as a first gate signal of the current stage. The first pull-down module is used to output a second signal to the corresponding first gate line based on the signal of the first node of the previous i stages as a first gate signal of the current stage, where i is a positive integer; The pulses of the signal of the first node in the current stage and the pulses of the signal of the first node in the previous i stage of the second gate driving circuit have overlapping periods, and the first gate line electrically connected to the second gate driving circuit is in a passive output state during the overlapping period. The start time of the pulse of the second gate signal acting on the second region is located before the overlapping period corresponding to the second gate drive circuit used to generate the first gate signal acting on the second region.

2. The display device according to claim 1, characterized in that, The plurality of pixels in the first region and the plurality of pixels in the second region are located in different columns.

3. The display device according to claim 2, characterized in that, The plurality of pixels in the first region and the plurality of pixels in the second region are located in the same row.

4. The display device according to claim 3, characterized in that, The display device includes an opening region located between the first region and the second region. The first gate line electrically connected to a row of pixels in the first region and the first gate line electrically connected to the same row of pixels in the second region are located on both sides of the opening region, and are respectively electrically connected to the first gate driving circuit and the second gate driving circuit of the corresponding level.

5. The display device according to claim 4, characterized in that, The display device further includes a non-opening area surrounding the opening area, wherein, in the non-opening area other than the first area and the second area, a plurality of data write transistors in a plurality of pixels in the same row are electrically connected to a corresponding first gate driving circuit and a corresponding second gate driving circuit via the same first gate line.

6. The display device according to any one of claims 2 to 5, characterized in that, The plurality of pixels are located in the display area of ​​the display device, and the display device includes a first border area located on the left side of the display area and a second border area located on the right side of the display area; The multi-stage first gate driving circuit is located in one of the first frame region and the second frame region, and the multi-stage second gate driving circuit is located in the other of the first frame region and the second frame region.

7. The display device according to claim 6, characterized in that, The first gate driving circuit transmits two first gate signals to a plurality of data write transistors in the first region, namely the pixel located in the first target row and the pixel located in the second target row, through two first gate lines. The second gate driving circuit at the same level transmits two more first gate signals to the pixels located in the first target row and the plurality of data write transistors in the pixels located in the second target row within the second region through two other first gate lines; The first pull-up module and the corresponding first pull-down module are electrically connected to one of the two first gate lines electrically connected to the corresponding first gate driving circuit or the corresponding second gate driving circuit. The time period of the pulse of the first gate signal acting on a row of pixels in the first region is the same as the time period of the pulse of the first gate signal acting on the same row of pixels in the second region.

8. The display device according to claim 7, characterized in that, The pixel circuit also includes: A compensation transistor is electrically connected between the source and drain of the driving transistor and the gate of the driving transistor, and the gate of the compensation transistor is connected to the corresponding third gate line. Wherein, the first reset transistor is electrically connected to the gate of the driving transistor; Wherein, the start time of the pulse of the second gate signal acting on the pixel in a row is ahead of the start time of the pulse of the third gate signal acting on the pixel in the same row by k1 units of time, where k1 is a positive integer, and the unit of time is the time interval between the start times of the signals of the two first nodes of the two adjacent levels. The pulse width of the third gate signal is equal to the pulse width of the signal of the first node.

9. The display device according to claim 8, characterized in that, The start time of the pulse of the second gate signal acting on the second region is k2 units of time before the overlapping period corresponding to the second gate drive circuit used to generate the first gate signal acting on the second region, where k2 is a positive integer.

10. The display device according to claim 9, characterized in that, The first gate line and the third gate line corresponding to the pixels in the same row within the second region are electrically connected to the same level of the second gate driving circuit.

11. The display device according to claim 8, characterized in that, The first gate driving circuit and the second gate driving circuit further include a third output module. The third output module in the first gate driving circuit is used to generate the second gate signal of the current stage according to the signal of the first node of the current stage. The third output module in the second gate driving circuit is used to generate the third gate signal of the current stage according to the signal of the first node of the current stage. The start time of the pulse of the first node signal in the current stage is the same as the start time of the pulse of the second gate signal or the third gate signal in the current stage.

12. The display device according to claim 8, characterized in that, The pulse width of the second gate signal is p units of duration, and the pulse width of the third gate signal is q units of duration, where p and q are positive integers, and k1+q is greater than or equal to p.

13. The display device according to claim 7, characterized in that, The pulses of the two first gate signals acting on the two rows of pixels in each of the first region and the second region are in different time periods; The first pull-down module is further configured to output the second signal to the corresponding first gate line according to the first clock signal, wherein the second signal includes a pulse of the first clock signal; The first gate driving circuit and the second gate driving circuit further include a second output module, the second output module comprising: The second pull-up module is used to output the first signal to the other of the two first gate lines electrically connected to the corresponding first gate drive circuit or the corresponding second gate drive circuit, based on the signal of the first node of the current stage, so as to serve as another first gate signal of the current stage. The second pull-down module is used to output a third signal as another first gate signal of the current stage to the other of the two first gate lines electrically connected to the corresponding first gate drive circuit or the corresponding second gate drive circuit, based at least on the signal of the first node of the previous i stage and the second clock signal, the third signal including a pulse of the second clock signal; The pulses of the first clock signal and the pulses of the second clock signal are in different time periods.

14. The display device according to claim 13, characterized in that, The first dropdown module includes: The first pull-down control transistor has its gate electrically connected to the first node of the previous i-th stage, and one of its source and drain is electrically connected to the second node of the current stage. The phase of the signal at the second node of the current stage is opposite to the phase of the signal at the first node of the current stage. The first pull-down transistor has its gate electrically connected to the other of the source and drain of the first pull-down control transistor, and one of the source and drain of the first pull-down transistor is electrically connected to a first clock line for transmitting the first clock signal. The other of the source and drain of the first pull-down transistor is electrically connected to the corresponding first gate line.

15. The display device according to claim 14, characterized in that, The first drop-down module also includes: The first bootstrap capacitor is electrically connected between the gate of the first pull-down transistor and the corresponding first gate line.

16. The display device according to claim 13, characterized in that, The first pull-up module includes: The first pull-up transistor has its gate electrically connected to the first node of the current stage, one of its source and drain electrically connected to a first signal line for transmitting the first signal, and the other of its source and drain electrically connected to the corresponding first gate line.

17. The display device according to claim 7, characterized in that, The first gate driving circuit transmits a second gate signal through a second gate line to a plurality of the first reset transistors in the first region and the second region, both the pixel located in the first target row and the pixel located in the second target row. The second gate driving circuit, whether at the same level or a different level, transmits a third gate signal through a third gate line to a plurality of the compensation transistors in both the first region and the second region located in the first target row and the second target row.

18. The display device according to claim 17, characterized in that, At least some of the pixels in the first region and at least some of the pixels in the second region are electrically connected to the same second gate line; At least some of the pixels in the first region and at least some of the pixels in the second region are electrically connected to the same third gate line.

19. The display device according to claim 17, characterized in that, The display device also includes multiple fourth gate lines and cascaded multi-stage third gate driving circuits; The pixel circuit also includes: The second reset transistor is electrically connected to the driving transistor and is used to transmit a second reset signal to the driving transistor. The gate of the second reset transistor is electrically connected to the corresponding fourth gate line. The third gate driving circuit transmits two fourth gate signals to a plurality of second reset transistors in at least two corresponding rows of pixels via at least two fourth gate lines.

20. The display device according to claim 19, characterized in that, The display device also includes multiple fifth gate lines and cascaded multi-stage fourth gate driving circuits; The pixel circuit also includes: A light-emitting control transistor is electrically connected to the driving transistor and the light-emitting element, and is used to control whether a current path for the driving current is formed. The gate of the light-emitting control transistor is electrically connected to the corresponding fifth gate line. The fourth gate driving circuit transmits two fifth gate signals to the plurality of light-emitting control transistors in the corresponding at least two rows of pixels through at least two fifth gate lines.

21. The display device according to claim 20, characterized in that, The third gate driving circuit transmits two fourth gate signals to a plurality of second reset transistors in the first region and the second region respectively through two fourth gate lines to the pixels located in the first target row and the pixels located in the second target row in the first region and the second region. The fourth gate driving circuit of the same or different levels transmits two fifth gate signals to a plurality of light-emitting control transistors in the first region and the second region respectively through two fifth gate lines to the pixels located in the first target row and the pixels located in the second target row.

22. The display device according to claim 20, characterized in that, The first target line is line 2n-1, the second target line is line 2n, and n is a positive integer greater than 5; The first gate driving circuit of the nth stage is electrically connected to the pixel located in the (2n-1)th row and the pixel located in the 2nth row in the first region through two first gate lines; The second gate driving circuit of the nth stage is electrically connected to the pixel located in the (2n-1)th row and the pixel located in the 2nth row in the second region through two other first gate lines; The first gate driving circuit of the n-5th stage is electrically connected to the pixel located in the 2n-1th row and the pixel located in the 2nth row in the first region and the second region through a second gate line; The second gate driving circuit of the nth stage is electrically connected to the pixel located in the (2n-1)th row and the pixel located in the 2nth row in the first region and the second region through a third gate line; The third gate driving circuit of the nth stage is electrically connected to the pixel located in the (2n-1)th row and the pixel located in the 2nth row in the first region and the second region through two fourth gate lines; The fourth gate driving circuit of the nth stage is electrically connected to the pixel located in the (2n-1)th row and the pixel located in the 2nth row in the first region and the second region through two fifth gate lines.

23. The display device according to claim 22, characterized in that, The start time of the pulse of the second gate signal acting on the pixels in the same row is one unit of time ahead of the start time of the pulse of the third gate signal acting on the pixels in the same row. The start time of the pulse of the second gate signal acting on the second region is one unit duration before the overlapping period corresponding to the second gate drive circuit used to generate the first gate signal acting on the second region; The pulse width of the second gate signal is 2 units of time, and the pulse width of the third gate signal and the pulse width of the first node signal are both 6 units of time. Wherein, the unit duration is the phase difference between the signals of the two first nodes of two adjacent levels.

24. The display device according to claim 23, characterized in that, The unit duration is equal to twice H, where H is the duration for scanning one row of pixels.

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