Pixel driving circuit and display panel

Abstract

This application belongs to the field of display driver technology, specifically relating to a pixel driving circuit and a display panel. The input terminal of the pixel driving circuit is connected to a data line. The pixel driving circuit is used to receive the current data voltage transmitted on the data line and output the current data voltage to the target pixel unit according to a preset range, so that the target pixel unit is charged by the current data voltage. This application connects two or three pixel units to the same data line through the pixel driving circuit, and distinguishes the pixel unit that is currently being charged by the voltage range of the current data voltage on the data line. This ensures that multiple pixel units connected to the same data line are not mischarged without increasing the number of scan lines. Therefore, this application solves the problem of reducing the number of source driver chips without increasing the number of scan lines.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a pixel driving circuit and a display panel. Background Technology

[0002] In the pixel driving architecture of display panels, TRD (Triple-gate) and DRD (DRD-gate) are commonly used technologies for triple-rate driving and double-rate driving, respectively. Both reduce the number of chips and thus lower the cost of the display panel by optimizing the driving speed of the source driver IC. Their core principle is to use time-division multiplexing to enable one data channel to drive two or three sub-pixels.

[0003] However, while TRD and DRD technologies reduce the number of source driver chips, they increase the number of scan lines in the display panel to three times (TRD) or two times (DRD) of the traditional architecture, resulting in problems such as high power consumption, low aperture ratio, and limited high resolution in the display panel.

[0004] Therefore, how to reduce the number of source driver chips without increasing the number of scan lines is a problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a pixel driving circuit and a display panel that solves the problem of reducing the number of source driving chips without increasing the number of scan lines.

[0006] In a first aspect, this application provides a pixel driving circuit applied to a display panel, the display panel including scan lines, data lines, a first pixel unit, a second pixel unit, and a third pixel unit; the input terminal of the pixel driving circuit is connected to the data lines, and the output terminal of the pixel driving circuit is connected to the input terminals of the first pixel unit, the second pixel unit, and / or the third pixel unit, for receiving the current data voltage transmitted on the data lines, and outputting the current data voltage to a target pixel unit according to a preset range in which the current data voltage is located, so that the current data voltage charges the target pixel unit; wherein, the target pixel unit is one of the first pixel unit, the second pixel unit, and the third pixel unit.

[0007] In a second aspect, this application provides a display panel, the display panel including N rows of scan lines and M columns of pixel columns, the pixel column including: 1 column of data lines and N rows of pixel circuits; one end of the data lines is connected to a source driver chip, and each row of pixel circuits includes a first pixel unit, a second pixel unit, a third pixel unit and the pixel driving circuit as described in claim 2. Alternatively, the pixel column includes 3 columns of data lines, N rows of pixel circuits, and the pixel driving circuit as described in claim 3; each row of pixel circuits includes a first pixel unit, a second pixel unit, and a third pixel unit, the input terminal of the pixel driving circuit is connected to the source driving chip, and the output terminal of the pixel driving circuit is connected to the 3 columns of data lines respectively. Alternatively, the pixel column includes: 1 column of data lines and N rows of pixel circuits; one end of the data lines is connected to the source driver chip, and each row of pixel circuits includes a first pixel unit, a second pixel unit and the pixel driving circuit of claim 2, or a first pixel unit, a third pixel unit and the pixel driving circuit of claim 2, and a second pixel unit, a third pixel unit and the pixel driving circuit of claim 2. Alternatively, the pixel column includes two columns of data lines, N rows of pixel circuits, and the pixel driving circuit as described in claim 3; each row of pixel circuits includes a first pixel unit and a second pixel unit, the first pixel unit and a third pixel unit, or the second pixel unit and a third pixel unit; the input terminal of the pixel driving circuit is connected to the source driving chip, and the output terminal of the pixel driving circuit is connected to the two columns of data lines respectively.

[0008] The technical solution provided in this application has at least the following beneficial effects: This application connects two or three pixel units to the same data line through a pixel driving circuit, and distinguishes the pixel unit that should be charged by the voltage range of the current data voltage on the data line. This ensures that multiple pixel units connected to the same data line will not be incorrectly charged without increasing the number of scan lines. Therefore, this application solves the problem of reducing the number of source driver chips without increasing the number of scan lines. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0010] Figure 1 The diagram shown is a schematic of a pixel circuit in a related technology.

[0011] Figure 2 The diagram shown is a schematic diagram of the structure of the first pixel driving circuit provided in the embodiment of this application.

[0012] Figure 3 The diagram shown is a schematic diagram of the structure of the second pixel driving circuit provided in the embodiment of this application.

[0013] Figure 4 The diagram shown is a structural schematic of the third pixel driving circuit provided in the embodiment of this application.

[0014] Figure 5 The diagram shown is a structural schematic of the fourth pixel driving circuit provided in the embodiment of this application.

[0015] Figure 6 The diagram shown is a schematic diagram of the first pixel driving circuit provided in an embodiment of this application.

[0016] Figure 7 The diagram shown is a schematic diagram of a second pixel driving circuit provided in an embodiment of this application.

[0017] Figure 8 The diagram shown is a structural schematic of the fifth pixel driving circuit provided in the embodiment of this application.

[0018] Figure 9 The diagram shown is a schematic diagram of a third pixel driving circuit provided in an embodiment of this application.

[0019] Figure 10 The diagram shown is a structural schematic of the first type of display panel provided in this application embodiment.

[0020] Figure 11 The diagram shown is a structural schematic of a second type of display panel provided in an embodiment of this application.

[0021] Figure 12 The diagram shown is a structural schematic of a third type of display panel provided in an embodiment of this application.

[0022] Figure 13 The diagram shown is a structural schematic of the fourth type of display panel provided in this application embodiment.

[0023] Explanation of reference numerals in the attached figures: 10. Display panel; 11. Pixel column; 100, Pixel driving circuit; 200, Scan line; 300, Data line; 400, First pixel unit; 500, Second pixel unit; 600, Third pixel unit; 110. Central control unit; 120. First control unit; 130. Second control unit; 140. Third control unit; Q0, control transistor; T0, drive transistor; C0, storage capacitor; OLED, light-emitting diode; T1, first switch transistor; T2, second switch transistor; T3, third switch transistor; T4, fourth switch transistor; T5, fifth switch transistor; U1, first comparator; U2, second comparator. Detailed Implementation

[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0025] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0026] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0027] In the pixel driving architecture of display panels such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode), TRD technology increases the driving speed of the source driver chip by three times, enabling a single driver chip to perform the tasks of three chips in traditional technology. Specifically: in traditional designs, each sub-pixel requires an independent channel for driving; while TRD allows a single channel to drive three sub-pixels simultaneously. Resolution adaptation example: taking a 1024×600 resolution panel as an example, traditional driving requires 3072 channels (corresponding to RGB three-color sub-pixels), while TRD only requires 1024 channels, achieving efficient driving through time-division multiplexing.

[0028] DRD technology doubles the driving speed of the source driver chip, enabling a single driver chip to perform the tasks of two chips in traditional technology. Specifically, in traditional designs, each sub-pixel requires an independent channel for driving; while DRD allows a single channel to drive two sub-pixels simultaneously. Resolution adaptation example: Taking a 1024×600 resolution panel as an example, traditional driving requires 3072 channels (corresponding to RGB sub-pixels), while DRD only requires 1536 channels, achieving efficient driving through time-division multiplexing.

[0029] The main advantages of TRD and DRD architectures are: 1. Reduced costs: The reduction of source driver chips (hereinafter referred to as ICs), COF and PCB components directly reduces material costs; for example, at the same resolution, the traditional 1G1D architecture requires 6 ICs, the TRD architecture only requires 2 ICs, and the DRD architecture only requires 3 ICs.

[0030] 2. Improved performance: Increased light transmittance enhances display brightness and energy efficiency, while time-sharing drive reduces signal interference and improves image quality.

[0031] The main disadvantages of TRD and DRD architectures are: 1. Limited support for high resolution: Because this technology reduces the number of source driver chips by sharing data lines, the number of scan lines in the display panel becomes 3 times (TRD) or 2 times (DRD) of the traditional architecture (i.e., 1G1D architecture). Its driving speed and the increased number of scan lines make it difficult to meet the accuracy and stability requirements of signal transmission under high pixel density. Therefore, it cannot be applied to scenarios with resolutions of 8K and above.

[0032] 2. Decreased transmittance: The increased number of scan lines encroaches on the pixel aperture area, resulting in a decrease in transmittance (for example, the aperture ratio of DRD is 15% lower than that of traditional Single Gate).

[0033] 3. High power consumption: The increased number of scan lines results in a larger RC loading (resistive-capacitive load effect), leading to high power consumption and noise interference issues on the panel.

[0034] 4. Signal crosstalk: The increased number of scan lines leads to wiring congestion and the risk of signal crosstalk.

[0035] 5. Signal delay: Multiplied scan lines can easily introduce signal delay.

[0036] 6. Poor scalability: TRD and DRD architectures require redesigning transistor control circuits and sub-pixel arrangements, which complicates the manufacturing process and leads to poor scalability and compatibility.

[0037] To address the aforementioned problems, this application provides a pixel driving circuit, specifically including the following embodiments: The pixel driving circuit provided in this application is applied to a display panel, which includes multiple scan lines, multiple data lines, and an array of first pixel units, second pixel units, and third pixel units. The display panel can be an LCD or an OLED display. When the display panel is an LCD, each pixel unit includes liquid crystal molecules; when the display panel is an OLED, each pixel unit includes a light-emitting diode. The first pixel unit, second pixel unit, and third pixel unit are respectively a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B). Since the pixel driving circuit of this application operates on the same principle in both LCD and OLED displays, OLED will be used as an example in the following explanations of the relevant principles.

[0038] In this embodiment, the input terminal of the pixel driving circuit is connected to the data line, and the output terminal of the pixel driving circuit is connected to the input terminal of the first pixel unit, the second pixel unit, and / or the third pixel unit. It is used to receive the current data voltage transmitted on the data line and output the current data voltage to the target pixel unit according to a preset range, thereby charging the target pixel unit. The target pixel unit is one of the first pixel unit, the second pixel unit, and the third pixel unit.

[0039] It should be noted that the pixel driving circuit of this embodiment includes multiple output terminals, which can be connected to the first pixel unit and the second pixel unit simultaneously, or to the first pixel unit and the third pixel unit simultaneously, or to the first pixel unit, the second pixel unit, and the third pixel unit simultaneously. The pixel driving circuit receives the current data voltage transmitted on the data line and determines the corresponding target pixel unit according to the voltage range of the current data voltage, thereby enabling the current data voltage to charge one of the first pixel unit, the second pixel unit, and the third pixel unit. In other words, this application enables two or three pixel units to share a data line through the pixel driving circuit, and the pixel driving circuit distinguishes the corresponding pixel unit by the voltage range of the data voltage on the data line, avoiding the problem of incorrect charging.

[0040] The principle behind the pixel driving circuit in this application is as follows: Normally, different colored luminescent materials have different electrical characteristics and luminous efficiency, resulting in differences in the grayscale data driving voltage (i.e., data voltage) range of RGB sub-pixels. Specifically, blue sub-pixels (B) have higher data voltage requirements, red sub-pixels (R) have lower voltage requirements, and green sub-pixels (G) have moderate voltage requirements. Taking a conventional 2T1C (dual transistor single capacitor) OLED pixel driving circuit as an example, such as... Figure 1 As shown, Figure 1 The control transistor Q0 and the driving transistor T0 are P-type transistors. The driving current output by the driving transistor T0 can drive the light-emitting diode to emit light. The specific formula for the driving current is:

[0041] in, To drive the carrier mobility of the transistor, This represents the capacitance density of the gate layer, in units of... It can be calculated using the dielectric constant and thickness of the gate oxide layer. The channel width of the driving transistor, in units of , Represents the channel length of the driving transistor, in units of ; driving transistors It is directly related to the mobility and size of the transistor; This represents the gate-source voltage driving the crystal. The threshold voltage of the driving transistor.

[0042] From the above formula, it can be seen that the driving current I OLED The size of the LED determines its brightness, while the driving current I... OLED The size is determined by the gate-source voltage V of the driving transistor. GS Adjustment is possible; the commonly used voltage range is: (1) Gate-source voltage V of the driving transistor GS =Data voltage V DATA -Drive voltage V DD ; where the V of the red sub-pixel (R) GS The value can be (-4~-2)V, and the V of the green sub-pixel (G) is... GS The value can be (-4.5~-2.5)V, and the V of the blue sub-pixel (B) can be... GS It can be (-5~-3)V.

[0043] (2) Driving voltage V DD It can be standardized to 5V, cathode voltage V SS It can be unified as 0V.

[0044] (3) It can be deduced that, in the relevant technology, the V of the red sub-pixel (R) DATA The value can be (1.0-3.0)V, and the V of the green subpixel (G) can be... DATA (0.5-2.5)V, V of the blue subpixel (B) DATA It can be (0-2.0)V.

[0045] Therefore, the core of this application lies in adjusting the data voltage range of the three sub-pixels without using a uniform driving voltage and cathode voltage, while satisfying the gate source voltage range required by each pixel unit. This makes the data voltage ranges of the first pixel unit, the second pixel unit, and the third pixel unit staggered, so that the pixel driving circuit can identify different current data voltages corresponding to different pixel units. For example, the data voltage range corresponding to the first pixel unit (red sub-pixel) in this embodiment can be (6.0~8.0)V, the data voltage range corresponding to the second pixel unit (green sub-pixel) can be (0.5~4.5)V, and the data voltage range corresponding to the third pixel unit (blue sub-pixel) can be (-5~-3)V.

[0046] Therefore, this application connects two or three pixel units to the same data line through a pixel driving circuit, and distinguishes the pixel unit that should be charged by the voltage range of the current data voltage on the data line. This ensures that multiple pixel units connected to the same data line will not be incorrectly charged without increasing the number of scan lines. Thus, this application solves the problem of reducing the number of source driver chips without increasing the number of scan lines.

[0047] Figure 2 The diagram shown is a schematic representation of the structure of the first pixel driving circuit provided in an embodiment of this application; as shown Figure 2 As shown, the pixel driving circuit 100 in this embodiment includes a general control unit 110, a first control unit 120, a second control unit 130 and a third control unit 140.

[0048] Specifically, the control terminal of the master control unit 110 is connected to the scan line 200, and the input terminal of the master control unit 110 is connected to the data line 300. When the master control unit 110 is in a conducting state under the action of the gate drive signal on the scan line 200, it outputs the current data voltage on the data line 300. The input terminal of the first control unit 120 is connected to the output terminal of the master control unit 110, and the output terminal of the first control unit 120 is connected to the input terminal of the first pixel unit 400. When the current data voltage is within a first preset range, it outputs the current data voltage to the first pixel unit 400. The input terminal of the control unit 130 is connected to the output terminal of the main control unit 110, and the output terminal of the second control unit 130 is connected to the input terminal of the second pixel unit 500. When the current data voltage is within the second preset range, the control unit 130 outputs the current data voltage to the second pixel unit 500. The input terminal of the third control unit 140 is connected to the output terminal of the main control unit 110, and the output terminal of the third control unit 140 is connected to the input terminal of the third pixel unit 600. When the current data voltage is within the third preset range, the control unit 140 outputs the current data voltage to the third pixel unit 600.

[0049] It should be noted that the first preset range, the second preset range, and the third preset range in this embodiment are staggered, meaning there is no numerical overlap. The working principle of the pixel driving circuit 100 in this embodiment is as follows: (1) When the gate drive signal is output on the scan line 200, the total control unit 110 is in the on state, receives the current data voltage output on the data line 300, and outputs the current data voltage directly as a signal.

[0050] (2) The first control unit 120 receives the current data voltage output by the main control unit 110 and determines whether the current data voltage is within the first preset range (e.g., 6.0~8.0V). If the current data voltage is not within the first preset range, the first control unit 120 does not output any signal. If the current data voltage is within the first preset range, the first control unit 120 outputs the current data voltage to the first pixel unit 400, so that the current data voltage charges the first pixel unit 400.

[0051] (3) The second control unit 130 also receives the current data voltage output by the main control unit 110 and determines whether the current data voltage is within the second preset range (e.g., 0.5~2.5V). If the current data voltage is not within the second preset range, the second control unit 130 does not output any signal. If the current data voltage is within the second preset range, the second control unit 130 outputs the current data voltage.

[0052] (4) The third control unit 140 also receives the current data voltage output by the main control unit 110 and determines whether the current data voltage is within the third preset range (e.g., -5.0~-3.0V). If the current data voltage is not within the third preset range, the third control unit 140 does not output any signal. If the current data voltage is within the third preset range, the third control unit 140 outputs the current data voltage.

[0053] Therefore, in this embodiment, the pixel driving circuit 100 connects three pixel units to the same data line 300 and the same scan line 200, so that a single data channel of the source driving chip can drive three sub-pixels at the same time, and the driving rate can be increased by three times. This can be applied to conventional TRD structures to reduce the number of scan lines 200 in conventional TRD structures.

[0054] Figure 3 The diagram shown is a schematic representation of the second pixel driving circuit provided in an embodiment of this application. Figure 4 The diagram shown is a schematic representation of the third pixel driving circuit provided in an embodiment of this application. Figure 5 The diagram shown is a structural schematic of the fourth pixel driving circuit provided in an embodiment of this application; wherein, Figure 3 , Figure 4 and Figure 5 The pixel driving circuit 100 shown is Figure 2 The difference is that it has one less output terminal (i.e., one less corresponding control unit). Figure 2 The pixel driving circuit 100 includes three output terminals, which can be connected to three different pixel units simultaneously; Figure 3 , Figure 4 and Figure 5 The pixel driving circuit 100 shown includes two output terminals, which are respectively connected to two different pixel units.

[0055] Specifically, Figure 3 The pixel driving unit in the middle includes a general control unit 110, a first control unit 120 and a second control unit 130; Figure 4 The pixel driving circuit 100 includes a general control unit 110, a first control unit 120 and a third control unit 140; Figure 5 The pixel driving circuit 100 includes a main control unit 110, a second control unit 130, and a third control unit 140. It should be noted that... Figure 3 , Figure 4 and Figure 5 The specific working principles of the main control unit 110, the first control unit 120, and the second control unit 130 are as follows: Figure 2 The same applies, so I won't go into details here.

[0056] Therefore, in this embodiment, the pixel driving circuit 100 connects two pixel units to the same data line 300 and the same scan line 200, allowing a single channel of the source driving signal to simultaneously drive two sub-pixels, thus doubling the driving speed. Figure 3 , Figure 4 and Figure 5 The pixel driving circuit 100 shown is also used in a conventional DRD structure to reduce the number of scan lines 200 in a conventional DRD structure.

[0057] Figure 6 The diagram shown is a schematic diagram of the first pixel driving circuit provided in an embodiment of this application; as shown Figure 6 As shown, the master control unit 110 includes: a first switch transistor T1, the control terminal of the first switch transistor T1 is connected to the scan line 200, the first end of the first switch transistor T1 serves as the input terminal of the master control unit 110, and the second end of the first switch transistor T1 serves as the output terminal of the master control unit 110.

[0058] It should be noted that the first switch T1 can be a P-type MOS transistor or an N-type MOS transistor. In this embodiment, the first switch T1 is an N-type MOS transistor. When a high-level gate drive signal is output on the scan line 200, the first switch T1 is turned on, thereby outputting the data voltage received through the first terminal from the second terminal.

[0059] like Figure 6 As shown, the first control unit 120 includes: a second switch T2, the control terminal of the second switch T2 is connected to the first power supply terminal VCC1, the first terminal of the second switch T2 is connected to the second terminal of the first switch T1, and the second terminal of the second switch T2 serves as the output terminal of the first control unit 120.

[0060] It should be noted that the second switch T2 can be either a P-type MOSFET or an N-type MOSFET; the first power supply terminal VCC1 can be a voltage output terminal with any output voltage value; this embodiment will be explained using a P-type MOSFET as the second switch T2 as an example. (1) The cutoff state (turn-off) of the second switch T2: when the gate-source voltage Vgs (Vg - Vs) ≥ the threshold voltage V th (V of P-type MOSFET) th When the voltage is negative (typically between -0.4V and -1V or lower), strong inversion does not occur on the N-type substrate surface below the gate. No conductive channel is formed, and a high-resistivity state exists between the source and drain, i.e., it is off.

[0061] (2)Conduction state (on) of the second switching transistor T2: When the gate-source voltage Vgs is lower than the threshold voltage Vth (i.e., Vgs < Vth), the negative voltage on the gate (relative to the source) repels the free electrons in the N-type substrate and at the same time attracts the holes in the substrate to the surface area under the gate. When Vgs is negative enough (lower than Vth) and the hole concentration is high enough, a P-type inversion layer channel is formed on the surface of the N-type substrate under the gate. This P-type channel connects the P-type source and drain, allowing holes (majority carriers) to flow from the source to the drain (the current direction is opposite), and a low-resistance state appears between the source and drain, that is, conduction.

[0062] For example, in this embodiment, the output voltage of the first power supply terminal VCC1 is 5V, and the threshold voltage Vth of the second switching transistor T2 is -1.1V. At this time, the voltage Vg of the control terminal (i.e., the gate) of the second switching transistor T2 is 5V. If the voltage of the first terminal (i.e., the source) of the second switching transistor T2 is 6 - 8V, the gate-source voltage Vgs of the second switching transistor T2 is Vg - Vs = 5 - (6 - 8) = -3 - -1, Vgs is less than Vth, and the second switching transistor T2 conducts; therefore, when the data voltage is within the first preset range, the second switching transistor T2 conducts, enabling the data voltage received through the first terminal to be output from the second terminal to the first pixel unit 400; conversely, when the voltage of the first terminal of the second switching terminal is less than 6V (i.e., when the data voltage is within the second preset range or the third preset range), Vgs is greater than Vth, the second switching transistor T2 is turned off, and no signal is output to the first pixel unit 400.

[0063] Continue as Figure 6 shown, the second control unit 130 of this embodiment includes a third switching transistor T3, a first comparator U1, and a fourth switching transistor T4; specifically, the control terminal of the third switching transistor T3 is connected to the second power supply terminal VCC2, and the first terminal of the third switching transistor T3 is connected to the second terminal of the first switching transistor T1; the first input terminal of the first comparator U1 is connected to the second terminal of the third switching transistor T3, and the second input terminal of the first comparator U1 is connected to the first reference voltage terminal VREF1; the control terminal of the fourth switching transistor T4 is connected to the output terminal of the first comparator U1, the first terminal of the fourth switching transistor T4 is connected to the second terminal of the third switching transistor T3, and the second terminal of the fourth switching transistor T4 serves as the output terminal of the second control unit 130.

[0064] It should be noted that the third switch T3 and the fourth switch T4 in this embodiment can be either P-type MOSFETs or N-type MOSFETs; this application takes the third switch T3 as a P-type MOSFET and the fourth switch T4 as an N-type MOSFET as an example. The first comparator U1 in this embodiment is an inverting voltage comparator. When the voltage at the first input terminal (inverting terminal) is greater than that at the second input terminal (non-inverting terminal), the output voltage is a negative saturation voltage (e.g., -5V); when the voltage at the first input terminal (inverting terminal) is less than that at the second input terminal (non-inverting terminal), the output voltage is a positive saturation voltage (e.g., 5V).

[0065] Here, taking the output voltage of the second power supply terminal VCC2 as 0V, the threshold voltage of the third switch T3 as 2.5V, the threshold voltage of the fourth switch T4 as 2V, and the output voltage of the first reference voltage terminal VREF1 as 5V as an example, the working principle of the second control unit 130 in this embodiment will be explained in detail: (1) When the data voltage is in the first preset range (e.g., 6.0~8.0V), the gate-source voltage (-8~-6V) of the third switch T3 is less than the threshold voltage 2.5V, so the third switch T3 is turned on; at this time, the voltage of the first input terminal (6.0~8.0V) of the first comparator U1 is greater than the voltage of the second input terminal (5V), so -5V voltage is output to the control terminal (i.e., the gate) of the fourth switch T4; at this time, the gate-source voltage (-13~-11V) of the fourth switch T4 is less than the threshold voltage 2V, so the fourth switch T4, which is an N-type MOS transistor, is turned off and no signal is output to the second pixel unit 500.

[0066] (2) When the data voltage is in the second preset range (e.g., 0.5~2.5V), the gate-source voltage (-2.5~-0.5V) of the third switch T3 is less than the threshold voltage 2.5V, so the third switch T3 is turned on; at this time, the voltage at the first input terminal (0.5~2.5V) of the first comparator U1 is less than the voltage at the second input terminal (5V), so the +5V voltage is output to the control terminal (i.e., the gate) of the fourth switch T4; at this time, the gate-source voltage (2.5~4.5V) of the fourth switch T4 is greater than the threshold voltage 2V, so the fourth switch T4, which is an N-type MOS transistor, is turned on, and the current data voltage is output to the second pixel unit 500.

[0067] (3) When the data voltage is in the third preset range (e.g. -5.0~-3.0V), the gate-source voltage (3~5V) of the third switch T3 is greater than the threshold voltage 2.5V, so the third switch T3 is turned off. At this time, the fourth switch T4 is also turned off and no signal is output to the second pixel unit 500.

[0068] Continue as Figure 6As shown, the third control unit 140 in this embodiment includes a second comparator U2 and a fifth switch T5. Specifically, the first input terminal of the second comparator U2 is connected to the second terminal of the first switch T1, and the second input terminal of the second comparator U2 is connected to the second reference voltage terminal VREF2. The control terminal of the fifth switch T5 is connected to the output terminal of the second comparator U2, the first terminal of the fifth switch T5 is connected to the first input terminal of the second comparator U2, and the second terminal of the fifth switch T5 serves as the output terminal of the third control unit 140.

[0069] It should be noted that the fifth switch T5 in this embodiment can be either a P-type MOSFET or an N-type MOSFET. Here, taking an N-type MOSFET as an example, a threshold voltage of 2V for the fifth switch T5, and an output voltage of 0V for the second power supply terminal VCC2, the working principle of the third control unit 140 in this embodiment will be explained in detail: (1) When the data voltage is within the first preset range (e.g., 6.0~8.0V), the voltage at the first input terminal of the first comparator U1 (6.0~8.0V) is greater than the voltage at the second input terminal (0V), and then outputs a -5V voltage to the control terminal (i.e., the gate) of the fifth switch transistor T5. At this time, the gate-source voltage (-13~-11V) of the fifth switch transistor T5 is less than the threshold voltage 2V, and the fifth switch transistor T5, which is an N-type MOS transistor, is turned off and does not output any signal to the third pixel unit 600.

[0070] (2) When the data voltage is in the second preset range (e.g., 0.5~2.5V), the voltage at the first input terminal of the first comparator U1 (0.5~2.5V) is greater than the voltage at the second input terminal (0V), and then outputs a -5V voltage to the control terminal (i.e., the gate) of the fifth switch T5. At this time, the gate-source voltage (-7.5~-5.5V) of the fifth switch T5 is less than the threshold voltage 2V, and the fifth switch T5, which is an N-type MOS transistor, is turned off and does not output any signal to the third pixel unit 600.

[0071] (3) When the data voltage is in the third preset range (e.g. -5.0~-3.0V), the voltage at the first input terminal of the first comparator U1 (-5.0~-3.0V) is less than the voltage at the second input terminal (0V), so the +5V voltage is output to the control terminal (i.e., the gate) of the fifth switch T5; at this time, the gate-source voltage (8~10V) of the fifth switch T5 is greater than the threshold voltage 2V, so the fifth switch T5 of the N-type MOS transistor is turned on, and the current data voltage is output to the third pixel unit 600.

[0072] when Figure 6When the pixel driving circuit 100 shown is applied in an OLED display panel 10, the first pixel unit 400, the second pixel unit 500, and the third pixel unit 600 respectively include: a storage capacitor C0, a driving transistor T0, and a light-emitting diode OLED; as shown Figure 6 As shown, the first end of the storage capacitor C0 serves as the input end of the corresponding pixel unit, the second end of the storage capacitor C0 is connected to the driving power supply, the control end of the driving transistor T0 is connected to the first end of the storage capacitor C0, the first end of the driving transistor T0 is connected to the second end of the storage capacitor C0, the anode of the light-emitting diode OLED is connected to the second end of the driving transistor T0, and the cathode of the light-emitting diode OLED is connected to the cathode power supply.

[0073] when Figure 6 When the pixel driving circuit 100 shown is applied in the LCD display panel 10, the first pixel unit 400, the second pixel unit 500 and the third pixel unit 600 include liquid crystal capacitors, and the pixel electrodes of the liquid crystal capacitors serve as the input terminals of the corresponding pixel units.

[0074] In one application scenario Figure 6 The first driving voltage terminal VDD1 outputs 10V, the second driving voltage terminal VDD2 outputs 5V, and the third driving voltage terminal VDD3 outputs 0V; the first cathode voltage terminal VSS1 outputs 5V, the second cathode voltage terminal VSS2 outputs 0V, and the third cathode voltage terminal VSS3 outputs -5V.

[0075] In another application scenario, Figure 6 The first driving voltage terminal VDD1 outputs 10V, the second driving voltage terminal VDD2 outputs 8V, and the third driving voltage terminal VDD3 outputs 5V; the first cathode voltage terminal VSS1 outputs 5V, the second cathode voltage terminal VSS2 outputs 0V or 3V, and the third cathode voltage terminal VSS3 outputs 0V.

[0076] Figure 7 The diagram shown is a schematic diagram of a second pixel driving circuit provided in an embodiment of this application; Figure 7 exist Figure 6 Add a diode D1 to the existing structure; specifically as follows: Figure 7As shown, the second control unit 130 also includes a diode D1. The anode of diode D1 is connected to the second terminal of the fourth switch T4, and the cathode of diode D1 is connected to the input terminal of the second pixel unit 500. It should be noted that when the fourth switch T4 is an N-type MOS transistor, the first terminal of the fourth switch T4 is the drain, and the second terminal is the source. To prevent the pixel capacitor discharge current in the second pixel unit 500 from flowing from the second terminal to the first terminal and affecting the voltage of the fourth switch T4, this embodiment adds a unidirectional diode between the fourth switch T4 and the second pixel unit 500. Similarly, a diode can also be added between the second switch T2 and the first pixel unit 400, and between the fifth switch T5 and the third pixel unit 600; these will not be elaborated further here.

[0077] It is worth noting that the values ​​of the output voltages, such as the first driving voltage terminal VDD1, the second driving voltage terminal VDD2, the third driving voltage terminal VDD3, the first power supply terminal VCC1, the second power supply terminal VCC2, the first reference voltage terminal VREF1, the second reference voltage terminal VREF2, the first preset range, the second preset range, the third preset range, the first cathode voltage terminal VSS1, the second cathode voltage terminal VSS2, and the third cathode voltage terminal VSS3, are only illustrative examples. They may fluctuate due to the influence of the driving transistor T0, the type, size, and process of the light-emitting unit, and even with future material and process development. They may also be adaptively adjusted according to different application scenarios. The core of this application is to stagger the data voltage ranges of the three pixel units to ensure that pixel units connected to the same data line 300 do not experience the problem of simultaneous charging errors.

[0078] Figure 8 The diagram shown is a structural schematic of the fifth pixel driving circuit provided in an embodiment of this application; as shown Figure 8 As shown, the pixel driving circuit 100 in this embodiment includes a first control unit 120, a second control unit 130, and a third control unit 140.

[0079] Specifically, the input terminal of the first control unit 120 is connected to the data line 300, and the output terminal of the first control unit 120 is connected to the input terminal of the first pixel unit 400, for outputting the current data voltage to the first pixel unit 400 when the current data voltage is within a first preset range; the input terminal of the second control unit 130 is connected to the data line 300, and the output terminal of the second control unit 130 is connected to the input terminal of the second pixel unit 500, for outputting the current data voltage to the second pixel unit 500 when the current data voltage is within a second preset range; the input terminal of the third control unit 140 is connected to the data line 300, and the output terminal of the third control unit 140 is connected to the input terminal of the third pixel unit 600, for outputting the current data voltage to the third pixel unit 600 when the current data voltage is within a third preset range.

[0080] It should be noted that, Figure 8 The pixel driving circuit 100 shown is Figure 2 The only difference is that the main control unit 110 is missing; the working principles of its first control unit 120, second control unit 130, and third control unit 140 are the same, specifically: (1) The first control unit 120 receives the current data voltage output on the data line 300 and determines whether the current data voltage is within the first preset range (e.g., 6.0~8.0V). If the current data voltage is not within the first preset range, the first control unit 120 does not output any signal. If the current data voltage is within the first preset range, the first control unit 120 outputs the current data voltage to the first pixel unit 400, so that the current data voltage charges the first pixel unit 400.

[0081] (3) The second control unit 130 also receives the current data voltage output on the data line 300 and determines whether the current data voltage is within the second preset range (e.g., 0.5~2.5V). If the current data voltage is not within the second preset range, the second control unit 130 does not output any signal. If the current data voltage is within the second preset range, the second control unit 130 outputs the current data voltage.

[0082] (4) The third control unit 140 also receives the current data voltage output on the data line 300 and determines whether the current data voltage is within the third preset range (e.g., -5.0~-3.0V). If the current data voltage is not within the third preset range, the third control unit 140 does not output any signal. If the current data voltage is within the third preset range, the third control unit 140 outputs the current data voltage.

[0083] Therefore, it can be seen that in this embodiment, the pixel driving circuit 100 connects three pixel units to the same data line 300, so that a single data signal can drive three sub-pixels at the same time, and the driving rate can be increased by three times. This can be applied to conventional TRD structures to reduce the number of scan lines 200 in conventional TRD structures.

[0084] refer to Figure 3 , Figure 4 and Figure 5 As shown, Figure 8 The pixel driving circuit 100 can also be connected only to the first pixel unit 400 and the second pixel unit 500, or only to the third pixel unit 600 and the first pixel unit 400, or only to the second pixel unit 500 and the third pixel unit 600, which will not be elaborated here.

[0085] Figure 9 The diagram shown is a schematic diagram of a third pixel driving circuit provided in an embodiment of this application. Figure 9 The specific circuit structure and working principle of the first control unit 120, the second control unit 130 and the third control unit 140 are the same as those in the above. Figure 6 The embodiments shown are exactly the same, so they will not be described again here.

[0086] when Figure 9 When the pixel driving circuit 100 shown is applied in an OLED display panel 10, the first pixel unit 400, the second pixel unit 500, and the third pixel unit 600 each include: a control transistor Q0, a storage capacitor C0, a driving transistor T0, and a light-emitting diode OLED; as shown Figure 9 As shown, the control terminal of the control transistor Q0 is connected to the scan line 200. The first terminal of the control transistor Q0 serves as the input terminal of the corresponding pixel unit. The second terminal of the control transistor Q0 is connected to the first terminal of the storage capacitor C0. The second terminal of the storage capacitor C0 is connected to the driving power supply terminal. The control terminal of the driving transistor T0 is connected to the first terminal of the storage capacitor C0. The first terminal of the driving transistor T0 is connected to the second terminal of the storage capacitor C0. The anode of the light-emitting diode OLED is connected to the second terminal of the driving transistor T0. The cathode of the light-emitting diode OLED is connected to the cathode power supply terminal.

[0087] when Figure 9 When the pixel driving circuit 100 shown is applied in the LCD display panel 10, the first pixel unit 400, the second pixel unit 500 and the third pixel unit 600 include a control transistor Q0 and a liquid crystal capacitor. The control terminal of the control transistor Q0 is connected to the scan line 200. The first terminal of the control transistor Q0 serves as the input terminal of the corresponding pixel unit, and the second terminal of the control transistor Q0 is connected to the pixel electrode of the liquid crystal capacitor.

[0088] Figure 10 The diagram shown is a structural schematic of the first type of display panel provided in this application embodiment; as follows: Figure 10 As shown, the display panel 10 includes N rows of scan lines 200 that are scanned line by line and M columns of pixel lines 11. The pixel line 11 includes: 1 column of data lines 300 and N rows of pixel circuits. One end of the data lines 300 is connected to the source driver chip. Each row of pixel circuits includes a first pixel unit 400, a second pixel unit 500, a third pixel unit 600 and the pixel driving circuit 100 of claim 2.

[0089] It should be noted that in this embodiment, the display panel 10 and the data lines 300 simultaneously charge three pixel units. The horizontal arrangement of the three pixel units is the same as that of the traditional Stripe architecture, but it is different from the vertical arrangement in the conventional Stripe architecture.

[0090] In addition, the conventional triple architecture requires three times the number of scan lines 200 of the traditional stripe architecture, while the pixel architecture of this embodiment does not require an additional scan line 200 on the traditional stripe architecture. The number of scan lines 200 is 1 / 3 of that of the conventional triple architecture, which greatly reduces the RC loading of the display panel, effectively reducing panel power consumption and noise, and breaking the dilemma that it cannot be applied in 8K and above resolution scenarios.

[0091] Figure 11 The diagram shown is a structural schematic of a second type of display panel provided in an embodiment of this application; as shown Figure 11 As shown, the display panel 10 includes N rows of scan lines 200 that scan line by line and M columns of pixel lines 11. The pixel line 11 includes 3 columns of data lines 300, N rows of pixel circuits and the pixel driving circuit 100 of claim 3. Each row of pixel circuits includes a first pixel unit 400, a second pixel unit 500 and a third pixel unit 600. The input terminal of the pixel driving circuit 100 is connected to the source driving chip, and the output terminal of the pixel driving circuit 100 is connected to the 3 columns of data lines 300 respectively.

[0092] It should be noted that in the display panel 10 provided in this embodiment, the pixel driving circuit 100 can be set in the non-display area. The pixel driving circuit 100 sends the data voltage emitted by one data channel in the source driving chip to different data lines 300 in the panel in a time-division manner, thereby achieving the purpose of reducing the number of source driving chips in the same way as the conventional triple architecture. Figure 11 and Figure 10 Compared to the display panel 10 shown, Figure 10 This not only reduces the number of source driver chips, but also correspondingly reduces the number of scan lines 200; and Figure 11The number of scan lines 200 shown in the architecture cannot be reduced, but the number of source driver chips can be reduced proportionally; additionally, Figure 11 The pixel driving circuit 100 is located in the non-display area, which does not affect the aperture ratio of the panel. Therefore, the panel mask design can be modified on the original Striple architecture, saving product development costs.

[0093] Figure 12 The diagram shown is a structural schematic of a third type of display panel provided in an embodiment of this application; as shown Figure 12 As shown, the display panel 10 includes N rows of scan lines 200 that are scanned line by line and M columns of pixel lines 11. The pixel line 11 includes: 1 column of data lines 300 and N rows of pixel circuits. One end of the data lines 300 is connected to the source driver chip. Each row of pixel circuits includes a first pixel unit 400, a second pixel unit 500 and the pixel driving circuit 100 of claim 2, or a first pixel unit 400, a third pixel unit 600 and the pixel driving circuit 100 of claim 2, and a second pixel unit 500, a third pixel unit 600 and the pixel driving circuit 100 of claim 2.

[0094] Figure 13 The diagram shown is a structural schematic of the fourth type of display panel provided in an embodiment of this application; as shown Figure 13 As shown, the display panel 10 includes N rows of scan lines 200 that are scanned line by line and M columns of pixel lines 11. The pixel lines 11 include two columns of data lines 300, N rows of pixel circuits, and the pixel driving circuit 100 of claim 3. Each row of pixel circuits includes a first pixel unit 400 and a second pixel unit 500, the first pixel unit 400 and a third pixel unit 600, or the second pixel unit 500 and the third pixel unit 600. The input terminal of the pixel driving circuit 100 is connected to the source driving chip, and the output terminal of the pixel driving circuit 100 is connected to the two columns of data lines 300 respectively.

[0095] It is worth noting that, Figure 12 architecture and Figure 10 resemblance, Figure 13 architecture and Figure 12 Similarly, their driving principles and effects are the same, so I won't go into details here.

[0096] In summary, the display panel provided in this embodiment has at least the following advantages: 1. Supports high resolution: While reducing the number of source chips, there is no need to increase the number of scan lines, avoiding the problem of increased parasitic capacitance / resistance caused by high-density gate lines, simplifying array glass design, and is especially beneficial to the stability of high-resolution panels (such as 8K).

[0097] 2. The Stripe architecture maintains the original scan line density, and the pixel aperture ratio is unaffected.

[0098] 3. No high-frequency drive is required, RC loading is small, overall power consumption is low, and noise performance is good; through timing optimization or low-power charge sharing technology, the overall power consumption of the module can be reduced, while signal transmission loss is reduced.

[0099] 4. Strong compatibility and scalability: While meeting the requirements of DRD / Triple architecture to reduce the number of source driver chips, it is compatible with traditional Tripe / DRD sub-pixel layout, can be directly adapted to existing production line equipment, reduces mass production difficulty, and supports expansion to high resolution (8K); it can also break the dilemma of not being applicable in 8K and above resolution scenarios, and will rewrite the pixel design of high resolution panels. It is a lower cost and higher transmittance upgraded version of the Striple architecture, which is more competitive in high-end display and low power consumption scenarios.

[0100] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0101] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0102] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A pixel driving circuit, applied to a display panel, the display panel comprising scan lines, data lines, a first pixel unit, a second pixel unit, and a third pixel unit; characterized in that, The input terminal of the pixel driving circuit is connected to the data line, and the output terminal of the pixel driving circuit is connected to the input terminals of all or any two of the first pixel unit, the second pixel unit, and the third pixel unit. It is used to receive the current data voltage transmitted on the data line and output the current data voltage to the target pixel unit according to a preset range, thereby charging the target pixel unit. The target pixel unit is one of the first pixel unit, the second pixel unit, and the third pixel unit. The pixel driving circuit includes: A master control unit, wherein the control terminal of the master control unit is connected to the scan line, and the input terminal of the master control unit is connected to the data line; The pixel driving circuit further includes all or any two of a first control unit, a second control unit, and a third control unit; wherein, the input terminal of the first control unit is connected to the output terminal of the main control unit, and the output terminal of the first control unit is connected to the input terminal of the first pixel unit; the input terminal of the second control unit is connected to the output terminal of the main control unit, and the output terminal of the second control unit is connected to the input terminal of the second pixel unit; the input terminal of the third control unit is connected to the output terminal of the main control unit, and the output terminal of the third control unit is connected to the input terminal of the third pixel unit.

2. The pixel driving circuit according to claim 1, characterized in that, The main control unit is used to output the current data voltage on the data line when it is in the on state under the action of the gate drive signal on the scan line; The first control unit is configured to output the current data voltage to the first pixel unit when the current data voltage is within a first preset range; The second control unit is used to output the current data voltage to the second pixel unit when the current data voltage is within a second preset range; The third control unit is used to output the current data voltage to the third pixel unit when the current data voltage is within a third preset range.

3. A pixel driving circuit, applied to a display panel, the display panel comprising scan lines, data lines, a first pixel unit, a second pixel unit, and a third pixel unit; characterized in that, The input terminal of the pixel driving circuit is connected to the data line, and the output terminal of the pixel driving circuit is connected to the input terminals of all or any two of the first pixel unit, the second pixel unit, and the third pixel unit. It is used to receive the current data voltage transmitted on the data line and output the current data voltage to the target pixel unit according to a preset range, thereby charging the target pixel unit. The target pixel unit is one of the first pixel unit, the second pixel unit, and the third pixel unit. The pixel driving circuit includes all or any two of a first control unit, a second control unit, and a third control unit; wherein, the input terminal of the first control unit is connected to the data line, and the output terminal of the first control unit is connected to the input terminal of the first pixel unit; the input terminal of the second control unit is connected to the data line, and the output terminal of the second control unit is connected to the input terminal of the second pixel unit; the input terminal of the third control unit is connected to the data line, and the output terminal of the third control unit is connected to the input terminal of the third pixel unit.

4. The pixel driving circuit according to claim 3, characterized in that, The first control unit is configured to output the current data voltage to the first pixel unit when the current data voltage is within a first preset range; The second control unit is used to output the current data voltage to the second pixel unit when the current data voltage is within a second preset range; The third control unit is used to output the current data voltage to the third pixel unit when the current data voltage is within a third preset range.

5. The pixel driving circuit according to claim 1, characterized in that, The central control unit includes: The first switching transistor has its control terminal connected to the scan line. The first terminal of the first switching transistor serves as the input terminal of the main control unit, and the second terminal of the first switching transistor serves as the output terminal of the main control unit.

6. The pixel driving circuit according to claim 1 or 3, characterized in that, The first control unit includes: The second switch has its control terminal connected to the first power supply terminal, its first terminal connected to the output terminal or data line of the main control unit, and its second terminal serving as the output terminal of the first control unit.

7. The pixel driving circuit according to claim 1 or 3, characterized in that, The second control unit includes: The third switch is connected to the control terminal of the third switch and to the second power supply terminal. The first terminal of the third switch is connected to the output terminal or data line of the main control unit. A first comparator, wherein the first input terminal of the first comparator is connected to the second terminal of the third switch, and the second input terminal of the first comparator is connected to the first reference voltage terminal; The fourth switch is connected to the output of the first comparator, and its first end is connected to the second end of the third switch. The second end of the fourth switch serves as the output of the second control unit.

8. The pixel driving circuit according to claim 1 or 3, characterized in that, The third control unit includes: The second comparator has its first input terminal connected to the output terminal or data line of the main control unit, and its second input terminal connected to the second reference voltage terminal. The fifth switch is connected to the output of the second comparator, the first end of the fifth switch is connected to the first input of the second comparator, and the second end of the fifth switch serves as the output of the third control unit.

9. The pixel driving circuit according to claim 1, characterized in that, The first pixel unit, the second pixel unit, and the third pixel unit include a liquid crystal capacitor, and the pixel electrode of the liquid crystal capacitor serves as the input terminal of the corresponding pixel unit; Alternatively, the first pixel unit, the second pixel unit, and the third pixel unit may include: a storage capacitor, a driving transistor, and a light-emitting diode (LED). The first end of the storage capacitor serves as the input terminal of the corresponding pixel unit, the second end of the storage capacitor is connected to the driving power supply terminal, the control terminal of the driving transistor is connected to the first end of the storage capacitor, the first end of the driving transistor is connected to the second end of the storage capacitor, the anode of the LED is connected to the second end of the driving transistor, and the cathode of the LED is connected to the cathode power supply terminal.

10. The pixel driving circuit according to claim 3, characterized in that, The first pixel unit, the second pixel unit, and the third pixel unit include a control transistor and a liquid crystal capacitor. The control terminal of the control transistor is connected to the scan line. The first terminal of the control transistor serves as the input terminal of the corresponding pixel unit. The second terminal of the control transistor is connected to the pixel electrode of the liquid crystal capacitor. Alternatively, the first pixel unit, the second pixel unit, and the third pixel unit may include: a control transistor, a storage capacitor, a driving transistor, and a light-emitting diode (LED). The control terminal of the control transistor is connected to a scan line. The first terminal of the control transistor serves as the input terminal of the corresponding pixel unit. The second terminal of the control transistor is connected to the first terminal of the storage capacitor. The second terminal of the storage capacitor is connected to a driving power supply terminal. The control terminal of the driving transistor is connected to the first terminal of the storage capacitor. The first terminal of the driving transistor is connected to the second terminal of the storage capacitor. The anode of the LED is connected to the second terminal of the driving transistor. The cathode of the LED is connected to a cathode power supply terminal.

11. A display panel, the display panel comprising N rows of scan lines scanned sequentially and M columns of pixels, characterized in that, The pixel column includes: 1 column of data lines and N rows of pixel circuits; one end of the data lines is connected to the source driver chip, and each row of pixel circuits includes a first pixel unit, a second pixel unit, a third pixel unit, and the pixel driving circuit as described in claim 1; wherein, the pixel driving circuit includes a first control unit, a second control unit, and a third control unit; Alternatively, the pixel column includes 3 columns of data lines, N rows of pixel circuits, and the pixel driving circuit as described in claim 3; each row of pixel circuits includes a first pixel unit, a second pixel unit, and a third pixel unit, the input terminal of the pixel driving circuit is connected to the source driving chip, and the output terminal of the pixel driving circuit is connected to the 3 columns of data lines respectively; wherein, the pixel driving circuit includes a first control unit, a second control unit, and a third control unit; Alternatively, the pixel column includes: 1 column of data lines and N rows of pixel circuits; one end of the data lines is connected to the source driver chip, and each row of pixel circuits includes any two pixel units selected from the first pixel unit, the second pixel unit, and the third pixel unit, as well as the pixel driving circuit according to claim 1; wherein, the pixel driving circuit includes any two of the first control unit, the second control unit, and the third control unit; Alternatively, the pixel column includes two columns of data lines, N rows of pixel circuits, and the pixel driving circuit as described in claim 3; each row of pixel circuits includes any two pixel units selected from a first pixel unit, a second pixel unit, and a third pixel unit; the input terminal of the pixel driving circuit is connected to the source driving chip, and the output terminal of the pixel driving circuit is connected to the two columns of data lines respectively; wherein, the pixel driving circuit includes any two of a first control unit, a second control unit, and a third control unit.

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