SiC power module sintering packaging method

Abstract

The application discloses a SiC power module sintering packaging method and relates to the technical field of power module packaging. The method comprises the following steps: sequentially performing ultrasonic cleaning, plasma activation and drying treatment on SiC chips and ceramic substrates to obtain activated ceramic substrates and SiC chips; performing spin coating of nano-silver paste on surfaces of the activated ceramic substrates and the SiC chips, and forming a nano-porous silver layer through pre-solidification and low-temperature sintering; performing segmented pressure sintering on the graphene / nano-porous silver composite layer chip and the ceramic substrate in a vacuum sintering furnace to output a SiC power module; performing epoxy resin packaging glue coating, ultraviolet light curing and annealing treatment on the SiC power module to eliminate internal stress and enhance corrosion resistance; and performing XRD and SEM detection on the SiC power module, coating a high-temperature-resistant silicone sealing layer and solidifying the high-temperature-resistant silicone sealing layer to output a finished product. Through the epoxy resin packaging glue coating and thermal-sound combined annealing technology, the application releases residual stress of a packaging interface, and improves the working life and adaptability of the SiC power module.

Description

Technical Field

[0001] This invention relates to the field of power module packaging technology, and in particular to a SiC power module sintering and packaging method. Background Technology

[0002] Silicon carbide (SiC) power modules are widely used in power electronics, aerospace, and new energy vehicles due to their high voltage withstand capability, low conduction loss, and high-temperature stability. However, traditional SiC power module packaging methods mainly rely on high-lead solder or eutectic bonding technology. These methods are prone to interfacial diffusion, thermal fatigue, and electromigration at high temperatures, leading to a decrease in the reliability of the packaging layer. Furthermore, traditional packaging processes exhibit high thermal resistance at the bonding interface, limiting the heat dissipation performance of SiC power modules and affecting their long-term stable operation. Therefore, improving the packaging quality and interface stability of SiC power modules, and reducing interfacial thermal resistance, has become an important research direction.

[0003] Currently, nano-silver sintering technology is considered an ideal alternative to traditional high-lead solders due to its low-temperature sintering, high thermal conductivity, and excellent interfacial bonding capabilities. However, existing nano-silver sintering processes still face some challenges, such as the tendency for defects to form in the nano-silver layer, limited interfacial bonding, and poor long-term thermal stability. Furthermore, the recrystallization of particles and the porosity of the sintered layer are difficult to control precisely during the sintering process, affecting packaging quality. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a SiC power module sintering and packaging method to solve the problems of insufficient interface bonding, high thermal resistance, and poor long-term thermal stability during the SiC power module packaging process.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a SiC power module sintering and packaging method, which includes sequentially performing ultrasonic cleaning, plasma activation and drying treatment on a SiC chip and a ceramic substrate to obtain an activated ceramic substrate and a SiC chip.

[0008] Nano-silver paste was spin-coated onto the surfaces of activated ceramic substrates and SiC chips, and then pre-cured and sintered at low temperature to form a nanoporous silver layer.

[0009] On the surface of a nanoporous silver layer, monolayer graphene is grown by plasma-enhanced chemical vapor deposition to obtain a graphene / nanoporous silver composite chip.

[0010] After aligning the graphene / nanoporous silver composite chip with the ceramic substrate, segmented pressure sintering is performed in a vacuum sintering furnace to output SiC power modules.

[0011] The SiC power module is coated with epoxy resin encapsulant, cured with ultraviolet light and annealed to eliminate internal stress and enhance corrosion resistance.

[0012] The SiC power module was placed in a high and low temperature cycling test chamber for thermal cycling testing.

[0013] After screening, SiC power modules are inspected by XRD and SEM, coated with a high-temperature resistant silicone sealant layer and cured to produce the finished product.

[0014] As a preferred embodiment of the SiC power module sintering and packaging method of the present invention, the pre-curing and low-temperature sintering to form a nanoporous silver layer comprises the following specific steps.

[0015] After the activated SiC chip and ceramic substrate are fixed on an automatic spin coater for spin coating, they are placed in an automatic heating device for pre-curing.

[0016] After pre-curing, the nano-silver particles are transferred to a vacuum sintering furnace for low-temperature sintering, which partially fuses the nano-silver particles to form a nanoporous silver layer.

[0017] During the sintering process, microscopic images are acquired through online high-resolution optical monitoring, and a mathematical model is established to evaluate the quality of the silver layer in real time.

[0018] As a preferred embodiment of the SiC power module sintering and packaging method of the present invention, the specific steps of growing monolayer graphene by plasma-enhanced chemical vapor deposition are as follows.

[0019] An oxygen-free environment was established under high-purity argon purging, and the substrate was heated and a bias voltage was applied to adsorb the carbon source.

[0020] Utilizing adaptive plasma density to control the graphene growth environment;

[0021] By controlling the hydrogen / methane flow ratio and nickel atom beam injection, graphene monolayers were grown uniformly to obtain graphene / nanoporous silver composite chip.

[0022] As a preferred embodiment of the SiC power module sintering and packaging method of the present invention, the specific steps of epoxy resin encapsulation coating, ultraviolet curing, and annealing are as follows.

[0023] The surface of the SiC power module is electrostatically sprayed with epoxy resin encapsulant, and the encapsulant is cured internally by multi-band ultraviolet light.

[0024] Thermo-acoustic combined annealing is used to release residual stress at the interface through temperature gradient and ultrasonic oscillation.

[0025] As a preferred embodiment of the SiC power module sintering and packaging method of the present invention, the ultrasonic cleaning, plasma activation and drying processes are performed by using ultrasonic cleaning to remove surface oil and particulate contaminants and plasma treatment.

[0026] As a preferred embodiment of the SiC power module sintering and packaging method of the present invention, the thermal cycling test refers to the test that evaluates the structural stability, electrical performance changes and fatigue life of the SiC power module under temperature stress by repeatedly cycling between extreme high and low temperature environments.

[0027] As a preferred embodiment of the SiC power module sintering and packaging method of the present invention, the thermal cycling test refers to the test that evaluates the structural stability, electrical performance changes and fatigue life of the SiC power module under temperature stress by repeatedly cycling between extreme high and low temperature environments.

[0028] As a preferred embodiment of the SiC power module sintering and packaging method of the present invention, the XRD detection is used to analyze the crystal structure and phase composition of the SiC power module, while the SEM detection is used to observe its microstructure, interface bonding and defect distribution, so as to ensure the structural integrity and reliability of the material.

[0029] In a second aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, wherein when the computer program is executed by the processor, it implements any step of the SiC power module sintering and packaging method as described in the first aspect of the present invention.

[0030] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the SiC power module sintering and packaging method as described in the first aspect of the present invention.

[0031] The beneficial effects of this invention are as follows: By optimizing the packaging process of SiC power modules, a single layer of graphene is deposited on the surface of a nanoporous silver layer, improving the interfacial bonding force and thermal conductivity; by combining plasma activation with spin coating of nano-silver paste, the nano-silver layer forms a uniform and dense porous structure during low-temperature sintering, reducing the porosity of the sintered layer; through a segmented pressure sintering process, electromagnetic assistance and ultrasonic pre-pressing are used to achieve precise control of sintering densification, reducing the generation of interfacial microcracks; and through epoxy resin encapsulant coating and thermo-acoustic combined annealing technology, residual stress at the encapsulation interface is effectively released, improving the working life and environmental adaptability of the SiC power module. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart of the SiC power module sintering and packaging method in Example 1.

[0034] Figure 2 This is a schematic diagram of the process for forming the nanoporous silver layer in Example 1.

[0035] Figure 3 This is a schematic diagram of the monolayer graphene growth process in Example 1.

[0036] Figure 4 This is a schematic diagram of the epoxy resin encapsulation and curing process in Example 1. Detailed Implementation

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0039] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0040] Example 1, referring to Figures 1-4 This embodiment provides a SiC power module sintering and packaging method, including the following steps:

[0041] S1. The SiC chip and the ceramic substrate are subjected to ultrasonic cleaning, plasma activation and drying treatment in sequence to obtain the activated ceramic substrate and the SiC chip.

[0042] Furthermore, the SiC chip and ceramic substrate are placed separately in dedicated polytetrafluoroethylene (PTFE) trays to ensure they do not come into contact with each other and prevent cross-contamination. The surfaces are pre-rinsed with ultrapure deionized water (DI water) to remove loose particles. A cleaning solution of 70% isopropanol (IPA) and 30% deionized water is prepared; this ratio removes organic contaminants while protecting the surfaces of the SiC chip and ceramic substrate. The temperature is controlled at approximately 30°C to improve cleaning efficiency.

[0043] Specifically, set the ultrasonic cleaning parameters, using a 40kHz ultrasonic cleaner, and set the output power to 200W based on the volume of the cleaning tank. The ultrasonic energy density I is calculated using the following expression:

[0044] ;

[0045] Among them, output power trough volume If the value is 2L, then the ultrasonic energy density is... .

[0046] The cleaning time is set to 15 minutes to ensure sufficient ultrasonic action time, generating a large number of uniform micro-cavitation bubbles to effectively remove surface contaminants. The pre-treated SiC chip and ceramic substrate are placed in the cleaning tank, and the ultrasonic cleaning device is turned on, maintaining uniform temperature and liquid circulation within the tank. After cleaning, the samples are thoroughly rinsed with high-purity deionized water to remove residual cleaning solution and dissolved contaminants. A surface roughness meter or contact angle meter can be used to perform preliminary testing on some samples to verify that surface contaminants are reduced and the contact angle is lowered (surface energy is increased) after cleaning. Plasma treatment further removes trace organic residues and atomic-level contaminants, while significantly increasing the surface energy of the SiC chip and ceramic substrate, thus improving the wettability of subsequent metal pastes.

[0047] After ultrasonic cleaning and rinsing, the SiC chip and ceramic substrate are placed in a pre-cleaned vacuum plasma treatment chamber, ensuring that the samples are firmly fixed and face upwards. Argon pure gas with 5% oxygen is used, which helps to further oxidize and remove organic residues without introducing an excessively thick oxide layer.

[0048] The working pressure was set to 0.2 Torr, and the RF power was 100W for excitation. The activation time was set to 5 minutes. Under plasma excitation, ions bombarded the sample surface, causing the surface atoms to rearrange and break organic bonds.

[0049] The activation effect can be verified using the Young equation, the expression of which is as follows:

[0050] ;

[0051] in, It is the solid-gas interface energy. It is the solid-liquid interface energy. For liquid surface tension, It represents the contact angle.

[0052] After activation, the measured contact angle decreased, indicating an increase in surface energy, which improves the wettability of subsequent slurries. Online spectral detection was configured to monitor the concentration of active species in the plasma in real time, ensuring process stability. After data acquisition, the RF power and activation time were adjusted according to a PID control algorithm. After the activation time was completed, the RF power was turned off, and the sample was quickly removed from the chamber to prevent environmental contamination from re-adhering to the sample surface.

[0053] After plasma activation, the newly activated SiC chip and ceramic substrate are immediately placed in a cleanroom with N2 protection to prevent impurities in the air from re-attaching.

[0054] Specifically, infrared (IR) radiation drying equipment was used for initial drying under N2 airflow protection. The samples were then transferred to a precision temperature-controlled drying oven, where a circulating fan ensured uniform temperature. PID control was applied to monitor the oven temperature in real time to ensure stability. The PID control formula was the same as above, ensuring the drying temperature error was less than ±2°C. An infrared humidity sensor was used to detect the sample surface, confirming that the residual moisture was below 5 ppm. Simultaneously, contact angle measurements confirmed that the dried surface had high surface energy (i.e., low contact angle), laying a good foundation for subsequent spin-coating of nano-silver paste. After drying, the samples were immediately placed in a clean storage box and stored in a drying cabinet to prevent the adsorption of moisture and organic matter from the environment.

[0055] The superior method features clearly defined steps, fixed parameters, and rigorous monitoring. It also employs cross-disciplinary technologies such as PID closed-loop control, online spectral detection, and infrared humidity monitoring, significantly improving cleaning and activation effects and providing a high-quality foundation for subsequent sintering and packaging. The refined process and high degree of automation ensure effective surface activation and low contamination, laying a solid foundation for high-reliability SiC power module packaging.

[0056] S2. Spin-coat nano-silver paste onto the surface of the activated ceramic substrate and SiC chip, and form a nanoporous silver layer through pre-curing and low-temperature sintering.

[0057] Furthermore, after the activated SiC chip and ceramic substrate are fixed on an automatic spin coater for spin coating, they are placed in an automatic heating device for pre-curing.

[0058] The automatic spin coater uses a single model with a preset rotation speed to ensure uniform force on the slurry during spin coating. When preparing the nano-silver slurry, high-purity nano-silver particles (approximately 20nm in diameter) are selected and mixed with acetone and an appropriate amount of organic binder (such as polyvinylpyrrolidone, PVP) in a fixed ratio. After thorough stirring, the mixture is filtered to a pore size of 0.2µm to ensure slurry homogeneity. To ensure stable slurry thickness with each coating, the spin coater is pre-calibrated for the coating amount. The spin coating program begins by uniformly distributing the slurry at a low speed, then rapidly increasing to the preset rotation speed, for example, continuously rotating for 15 seconds, to ensure the slurry forms a uniform film under centrifugal force. After spin coating, the initial thickness of the silver paste layer is measured using an online laser thickness gauge, and the data is recorded for subsequent process adjustments.

[0059] After pre-curing, the nano-silver particles are transferred to a vacuum sintering furnace for low-temperature sintering, which partially fuses the nano-silver particles to form a nanoporous silver layer.

[0060] Specifically, the spin-coated workpiece is immediately placed into an automatic heating pre-curing device, with a set temperature of 80°C and a holding time of 120 seconds to promote solvent evaporation and initial curing of the silver paste layer. During pre-curing, an infrared temperature sensor is used to monitor the sample surface temperature in real time to ensure uniform temperature and avoid local overheating or underheating. After pre-curing, the weight change of the workpiece is detected by microgravimetry to ensure that the solvent evaporation reaches more than 95%. The pre-cured workpiece is then placed in a vacuum sintering furnace, with the vacuum level, temperature, and sintering time set. At low temperatures, the temperature and the slow-release effect of residual organic matter promote the partial fusion of nano-silver particles in the solid state to form a porous structure with fine pores. During sintering, an online high-resolution optical monitoring system is used to acquire microscopic image data of the silver layer as a basis for subsequent model control.

[0061] Furthermore, during the sintering process, microscopic images are acquired through online high-resolution optical monitoring, and a mathematical model is established to evaluate the quality of the silver layer in real time.

[0062] To optimize the microstructure of the silver layer, an innovative formula integrating spin coating, pre-curing, and sintering parameters was designed to predict and control the quality index Q (ranging from 0 to 1, where 1 represents optimal low porosity and high thermal conductivity) of the final nanoporous silver layer in real time. The expression is as follows:

[0063] ;

[0064] in, This is an index for evaluating the quality of the silver layer, with a value range of 0 to 1. A larger value indicates lower porosity, better interfacial bonding, and superior thermal conductivity of the silver layer. This is the pre-curing time; in this example, it is taken as 120 seconds. This represents the actual rotational speed during the spin coating process. In the first The ideal rotational speed for achieving optimal silver layer uniformity in each stage. The diffusion inhibition coefficient during spin coating is used to control the effect of actual rotation speed deviating from the ideal value. This is a temperature sensitivity coefficient used to describe the effect of the deviation between the sintering temperature and the ideal sintering temperature on the quality of the silver layer. The actual sintering temperature is taken as 150℃ in this example. The ideal temperature for achieving the best silver layer sintering effect was determined through previous experiments, for example, 145℃. The total number of process segments represents the number of optimal spin coating control stages considered during the spin coating process, which depends on the actual process requirements. This is an index variable for the number of process segments. For integration variables The small dependent variable.

[0065] During the pre-curing time, the comprehensive quality evaluation of the silver layer is obtained by weighted integral of the exponential decay function of the ideal rotation speed deviation and the normalized function of the temperature deviation at each stage. .like A value close to 1 indicates that the entire process parameters are in an optimal state; if... A value below 0.8 indicates a parameter deviation, requiring adjustment of the spin coating speed or sintering temperature. The model employs an integral averaging method to ensure data stability and incorporates online monitoring data for real-time feedback and control.

[0066] After sintering, the workpiece is automatically removed from the vacuum furnace, and the microstructure of the silver layer is examined using scanning electron microscopy (SEM) and X-ray diffraction (XRD) to verify whether it meets the requirements of low porosity and uniform density. Based on the test results, parameters in the formula (such as...) are adjusted through feedback. , , and ideal speed and temperature This allows for process optimization for the next batch of workpieces.

[0067] S3. On the surface of the nanoporous silver layer, monolayer graphene is grown by plasma-enhanced chemical vapor deposition to obtain a graphene / nanoporous silver composite chip.

[0068] Plasma-enhanced chemical vapor deposition (PECVD) is a technique that uses plasma to excite reactive gases (such as CH4 / H2) to generate active free radicals, thereby achieving high-quality graphene growth at low temperatures. Its core lies in controlling the plasma density and energy distribution through an electromagnetic field, reducing the carbon source decomposition energy barrier, and promoting uniform nucleation and directional growth of monolayer graphene.

[0069] Furthermore, an oxygen-free environment is established under high-purity argon purging, the substrate is heated and a bias voltage is applied to adsorb carbon sources.

[0070] Preferably, establishing an oxygen-free environment under high-purity argon purging, along with heating the substrate and applying a bias voltage to adsorb the carbon source, effectively eliminates oxygen and impurities in the growth environment, improves the utilization rate of the carbon source, and prevents oxidation defects in the graphene layer. This ensures high crystallinity and integrity of the graphene while enhancing the interfacial bonding between graphene and the nanoporous silver layer, thereby improving the stability of the composite structure. Furthermore, applying a bias voltage promotes the directional adsorption and uniform distribution of the carbon source, further optimizing the graphene deposition process and providing a material basis for the preparation of high-quality, low-defect graphene / nanoporous silver composite layers.

[0071] The graphene growth environment is controlled using adaptive plasma density.

[0072] In this process, under argon protection, a carbon source is adsorbed by bias voltage and plasma is excited. Hydrogen plasma is used to etch the amorphous carbon layer, suppressing the formation of polycrystalline graphene. Simultaneously, methane dissociates into C radicals in the plasma, which preferentially adsorb onto lattice defect sites induced by nickel atom beams, achieving preferred orientation growth of monolayer graphene. Adaptive control can eliminate the graphene thickness unevenness caused by temperature gradients or uneven gas diffusion in traditional fixed-parameter processes, reducing defect density.

[0073] The plasma power, gas flow ratio (H2 / CH4), and bias parameters are dynamically adjusted through a real-time feedback system to maintain the optimal match between plasma density and activity within the reaction chamber. For example, optical emission spectroscopy (OES) is used to monitor characteristic plasma spectral lines (such as CⅡ 426.7nm), and a PID algorithm is combined to dynamically adjust the power, ensuring a balance between graphene growth rate and defect rate.

[0074] Adaptive Plasma Density Control (APDC) uses a microwave source (e.g., frequency f=2.45GHz) to excite methane plasma, monitors the plasma density in real time, and dynamically adjusts the power based on feedback. To maintain the optimal growth environment, the expression is as follows:

[0075] ;

[0076] in, The plasma density during the growth process, Where is the initial plasma density, and is the initial plasma density of the reaction. This is the plasma power adjustment coefficient, used to determine the sensitivity of plasma density to power changes. Here, represents the real-time plasma power, and represents the currently applied plasma power. Let be the desired plasma power, and be the optimized target power. This is the electron energy sensitivity coefficient, used to describe the effect of electron energy deviating from its optimal value. The current electron energy represents the energy distribution of electrons within the reaction region. The optimal electron energy is the value that ensures high-quality growth of monolayer graphene.

[0077] To ensure plasma stability during plasma-enhanced chemical vapor deposition and improve the uniformity and continuity of graphene monolayer growth, the graphene monolayer was rapidly cooled under high-purity argon protection by adjusting the hydrogen / methane flow ratio and nickel atom beam injection. This resulted in the uniform growth of graphene monolayers and the acquisition of a graphene / nanoporous silver composite chip. Real-time stability of plasma density was achieved through dynamic power adjustment and feedback control.

[0078] It should be noted that in plasma-enhanced chemical vapor deposition, plasma density is easily affected by factors such as reactant gas flow rate and pressure fluctuations, leading to uneven graphene growth. This solution actively suppresses density fluctuations through closed-loop feedback (monitoring and adjustment). Power adjustment coefficient. Precisely matching the sensitivity of power changes to density avoids local overheating or underactivation, ensuring the continuity of the graphene lattice, and current electron energy. Deviation hour, The event triggers a compensation mechanism to suppress the generation of non-stoichiometric or defective states, thereby increasing the sp² hybridization of monolayer graphene.

[0079] By quantifying control parameters through mathematical models, process repeatability and controllability were achieved. The formulas transformed the abstract plasma state into measurable physical quantities (power, electron energy), providing a theoretical basis for process optimization. Through adjustments... and This method can quickly adapt to different reaction chamber or substrate conditions, shortening the R&D cycle. It allows for control of the hydrogen / methane (H2 / CH4) flow ratio and the introduction of nickel atom beam injection, followed by rapid cooling under high-purity argon protection to achieve uniform monolayer graphene growth. The carbon source concentration and reducing environment are optimized through H2 / CH4 ratio control. Methane, as the carbon source, needs to be cracked in a hydrogen-rich environment to avoid carbon deposition. Appropriately reducing the H2 ratio can suppress side reactions (such as the complete decomposition of CH4 into C and H2), reducing amorphous carbon deposition. Excessive H2 will dilute the reactants, while insufficient H2 will lead to uncontrolled graphene layer number. Dynamically adjusting the flow ratio achieves a balance between rate and quality.

[0080] Nickel atom beam injection provides catalytically active sites and guides graphene nucleation.

[0081] Nickel is a typical catalyst that lowers the nucleation energy barrier of graphene and promotes uniform nucleation. Nickel atoms adsorb on the substrate surface, guiding the orderly arrangement of carbon atoms and reducing grain boundary density; nickel atoms combine with unsaturated bonds, passivating edge defects and improving carrier mobility. Rapid cooling locks the monolayer structure and suppresses interlayer diffusion. At high temperatures, graphene easily stacks to form multiple layers. Rapid cooling freezes the monolayer structure, and the template effect of the nickel atom beam achieves a monolayer coverage of >95%. Slow cooling can easily lead to lattice distortion, while rapid cooling preserves an atomically flat interface and enhances carrier transport efficiency. Adaptive plasma density control ensures that the graphene layer uniformly covers the nanoporous silver layer, avoiding interfacial thermal resistance caused by poor local contact.

[0082] Through optimization Matching the work function of the graphene layer with that of the silver layer improves the ohmic contact performance between graphene and silver, reducing the on-resistance of the device. The uniform graphene layer significantly improves the thermal conductivity of the module, alleviating the heat accumulation caused by high-frequency switching in SiC devices; the mechanical interlocking structure of low-defect-density graphene and nanoporous silver withstands high and low temperature cycling tests, meeting automotive-grade reliability requirements.

[0083] A superior approach combines adaptive plasma density control (APDC) with nickel-catalyzed synergistic growth, solving the challenge of uniform nucleation of monolayer graphene on complex substrates. Through "dynamic feedback control + multi-physics synergy," the entire chain of optimization, from atomic-level growth to macroscopic module performance, is achieved, demonstrating the deep integration of precision manufacturing and materials science.

[0084] S4. After aligning the graphene / nanoporous silver composite chip with the ceramic substrate, perform segmented pressure sintering in a vacuum sintering furnace to output the SiC power module.

[0085] Furthermore, segmented pressure sintering in a vacuum sintering furnace refers to segmented pressure sintering using electromagnetic assistance and ultrasonic pre-compression to optimize the densification of the nanoporous silver layer. Laser interferometry is employed to achieve high-precision alignment of the graphene / nanoporous silver composite chip and the ceramic substrate, with temporary fixation achieved through electrostatic adsorption technology, avoiding traditional mechanical alignment errors and improving interface uniformity. In the vacuum sintering chamber, the interface oxide layer is dynamically removed using an Ar / H2 atmosphere, and the surface is activated by holding at, for example, 450°C for 10 minutes, enhancing the diffusion capacity of the sintered interface.

[0086] By employing electromagnetic assistance and ultrasonic pre-compression technology for segmented pressure sintering, the densification process of nanoporous silver is optimized, achieving high-strength interfacial bonding.

[0087] The segmented pressure sintering process, for example, involves an initial low-pressure diffusion stage (T1=500°C, P1=0.5MPa, t1=15min) where low-temperature, low-pressure diffusion promotes the migration of silver nanoparticles on the surface, ensuring good interfacial bonding; a stress-relieving medium-temperature sintering stage (T2=750°C, P2=2MPa, t2=20min) employs pulsed current sintering (PCS) technology to activate interfacial diffusion between graphene and silver, reducing thermal stress accumulation; and a high-temperature densification sintering stage (T3=850°C, P3=5MPa, t3=10min) where high pressure is applied to increase density, and ultrasonic oscillation is used to eliminate micropores, ensuring interface stability.

[0088] A nonlinear cooling curve is used to control the thermal stress release of the SiC power module and prevent interface cracking.

[0089] For example, the nonlinear cooling curve 850°C→600°C: cooling at 5°C / min to reduce thermal shock; 600°C→300°C: gradually releasing residual stress at the interface at 2°C / min; 300°C→room temperature: natural cooling under nitrogen protection to improve interface reliability.

[0090] Nanoscale X-ray computed tomography was used to evaluate the microstructure of the sintering interface to ensure that there were no significant pores or cracks; the bond strength was verified by tensile shear test to ensure that the standards were met, and finally a high-stability SiC power module was output.

[0091] S5. Apply epoxy resin encapsulant to the SiC power module, cure it with ultraviolet light, and anneal it to eliminate internal stress and enhance its corrosion resistance.

[0092] Furthermore, epoxy resin encapsulant is electrostatically sprayed onto the surface of the SiC power module, and the encapsulant is internally cured using multi-band ultraviolet light. In a vacuum sintering furnace, O2+Ar plasma is used to remove contaminants from the SiC module surface, improving its compatibility. A high-voltage electrostatic field is then used to atomize the epoxy resin and spray it onto the SiC module surface, forming a uniform coating.

[0093] Multi-band ultraviolet light (UVA and UVC combination) is used to ensure full curing of the encapsulating adhesive and reduce stress gradient. Initial exposure promotes rapid cross-linking of the surface layer and avoids solvent residue. Deep curing is achieved by using high-transmittance ultraviolet light to complete the internal cross-linking of the adhesive and enhance adhesion strength.

[0094] Thermo-acoustic combined annealing is adopted to release residual stress at the interface through temperature gradient and ultrasonic oscillation.

[0095] The stepped temperature annealing process, for example, includes: Stage 1 (T1=80°C, t1=30min), a low-temperature stage that promotes colloidal flow and improves interfacial wettability; Stage 2 (T2=150°C, t2=60min), a medium-temperature stage that induces cross-linking network structure optimization and releases stress; and Stage 3 (T3=200°C, t3=20min), a high-temperature stage that improves weather resistance and enhances crack resistance.

[0096] This process promotes microstructure rearrangement, reduces stress concentration areas, and improves interface reliability. A sol-gel process is used to form a SiO2 nano-protective layer on the encapsulation layer surface, enhancing corrosion resistance. Accelerated aging tests in a humidity environment are conducted to ensure the long-term stability of the encapsulation layer, ultimately resulting in a highly reliable SiC power module.

[0097] S6. Place the SiC power module in a high and low temperature cycling test chamber for thermal cycling testing.

[0098] Furthermore, before conducting thermal cycling tests, it is essential to ensure that the SiC power module is in a standardized state to guarantee the accuracy and repeatability of the test results. Anhydrous ethanol and plasma cleaning techniques are used to remove contaminants from the module surface to prevent contamination from affecting thermal conductivity during testing. The module's on-resistance is measured using the four-probe method, and parasitic inductance and capacitance are recorded as reference values ​​using an LCR meter.

[0099] A nonlinear temperature cycling mode with gradient temperature control and isothermal holding is employed to improve thermal stress uniformity and simulate the actual working environment. Based on the working environment of the SiC power module, a cycling range of -55°C to 200°C is set to cover extreme temperature changes. A nonlinear rate curve is used to reduce stress concentration caused by thermal shock. The temperature is maintained for 15 minutes at both the highest and lowest temperatures to ensure that the material fully responds to thermal expansion and contraction.

[0100] Thermal cycling testing involves repeatedly cycling between extreme high and low temperatures to evaluate the structural stability, electrical performance changes, and fatigue life of SiC power modules under temperature stress. During thermal cycling, the temperature gradient, stress distribution, and changes in key parameters within the SiC power module are monitored in real time. Fiber optic sensors are embedded within the encapsulation layer to monitor internal thermal stress changes. During testing, a high-resolution infrared thermal imager is used to record the surface temperature distribution of the module and detect potential areas of concentrated thermal stress.

[0101] Standard test settings include, for example, 1000 cycles, and the module's lifespan is predicted in advance by monitoring electrical parameter drift. The stress distribution of the SiC solder joints is calculated using finite element simulation. After returning to room temperature, electrical parameters are measured again to confirm the presence of transient failures. Comparing the initial data with the post-test data, if the on-resistance, parasitic inductance, and capacitance change by more than 20%, the module is considered to have failed; otherwise, the test passes.

[0102] S7. After screening the SiC power modules and inspecting them by XRD and SEM, a high-temperature resistant silicone sealing layer is coated and cured to produce the finished product.

[0103] Furthermore, the SiC power module was placed in an X-ray diffractometer (XRD), and the Cu-Kα rays and scanning angle range were set to obtain the diffraction pattern of the SiC material. Using Bragg's law:

[0104] ;

[0105] in, For diffraction series, Interplanar spacing, The diffraction angle is used to calculate the lattice parameters of SiC, confirm the presence of impurity phases or defects, and ensure the integrity of the material structure. λ is the wavelength.

[0106] SiC power module samples screened by XRD were placed in a scanning electron microscope (SEM). An accelerating voltage was selected, and the surface morphology was observed using secondary electron imaging (SE). The material composition distribution was analyzed using backscattered electron imaging (BSE). The thickness of the interfacial bonding layer was measured to ensure the absence of cracks, voids, or severe defects, thereby improving the long-term stability of the device.

[0107] SiC power modules that passed XRD and SEM screening were placed in a clean, dust-free environment and coated with a high-temperature resistant silicone layer (PDMS, polydimethylsiloxane) using an automated coating machine. A controllable flow nozzle was used to ensure uniform coverage of the module surface with the silicone coating, improving the module's resistance to moisture and heat and its dielectric strength.

[0108] After coating, place it in a constant temperature oven for two-step curing.

[0109] For example, the two-step curing process involves a first-step low-temperature pre-curing at 80°C for 1 hour to promote solvent evaporation and prevent air bubble residue. The second step is a high-temperature cross-linking curing at 150°C for 2 hours, utilizing the thermal cross-linking reaction to enhance high-temperature resistance and improve interface stability. The cured SiC power module undergoes sealing layer thickness measurement and reliability verification through high and low temperature alternating tests. Finally, qualified products are selected for final product output.

[0110] The superior method, through XRD+SEM joint screening, precise silicone coating control, and thermal cross-linking curing optimization, effectively improves the sealing performance, temperature resistance, and long-term stability of SiC power modules, reduces interfacial stress, and enhances weather resistance and electrical insulation capabilities.

[0111] This embodiment also provides a computer device applicable to the SiC power module sintering and packaging method, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the SiC power module sintering and packaging method proposed in the above embodiment.

[0112] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0113] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the SiC power module sintering and packaging method proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0114] In summary, this invention optimizes the packaging process of SiC power modules by depositing a single layer of graphene on the surface of a nanoporous silver layer, thereby improving interfacial adhesion and thermal conductivity. The combination of plasma activation and spin-coating of nano-silver paste enables the nano-silver layer to form a uniform and dense porous structure during low-temperature sintering, reducing the porosity of the sintered layer. Through a segmented pressure sintering process, utilizing electromagnetic assistance and ultrasonic pre-pressing, precise control of sintering densification is achieved, reducing the generation of interfacial microcracks. Finally, epoxy resin encapsulant coating and thermo-acoustic combined annealing effectively release residual stress at the encapsulation interface, improving the working life and environmental adaptability of the SiC power module.

[0115] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A SiC power module sintering and packaging method, characterized in that: include, The SiC chip and the ceramic substrate were sequentially subjected to ultrasonic cleaning, plasma activation and drying to obtain the activated ceramic substrate and the SiC chip. Nano-silver paste was spin-coated onto the surface of activated ceramic substrates and SiC chips, and then pre-cured and sintered at low temperature to form a nanoporous silver layer. The pre-curing process involves immediately sending the spin-coated workpiece into an automatic heating pre-curing device, setting the temperature to 80°C and holding it for 120 seconds to promote solvent evaporation and pre-curing of the silver paste layer. After the pre-curing process, the workpiece is transferred to a vacuum sintering furnace for low-temperature sintering, which partially fuses the nano-silver particles to form a nanoporous silver layer. On the surface of a nanoporous silver layer, monolayer graphene is grown by plasma-enhanced chemical vapor deposition to obtain a graphene / nanoporous silver composite chip. The monolayer graphene is grown uniformly by controlling the hydrogen / methane flow ratio and nickel atom beam injection. An oxygen-free environment is established under high-purity argon purging. The substrate is heated and a bias voltage is applied to adsorb the carbon source. Under argon protection, the carbon source is adsorbed by bias voltage and plasma is excited. Hydrogen plasma is used to etch the amorphous carbon layer and inhibit the formation of polycrystalline graphene. At the same time, methane dissociates into C radicals in the plasma, which preferentially adsorb onto lattice defect sites induced by nickel atom beam. The monolayer graphene grows with preferred orientation. The plasma power, gas flow ratio (H2 / CH4), and bias voltage parameters are dynamically adjusted to maintain the optimal match between plasma density and activity in the reaction chamber. After aligning the graphene / nanoporous silver composite chip with the ceramic substrate, segmented pressure sintering is performed in a vacuum sintering furnace to output SiC power modules. The SiC power module is coated with epoxy resin encapsulant, cured with ultraviolet light and annealed to eliminate internal stress and enhance corrosion resistance. The SiC power module was placed in a high and low temperature cycling test chamber for thermal cycling testing. After screening, SiC power modules are inspected by XRD and SEM, coated with a high-temperature resistant silicone sealant layer and cured to produce the finished product.

2. The SiC power module sintering and packaging method as described in claim 1, characterized in that: The pre-curing and low-temperature sintering process forms a nanoporous silver layer. The specific steps are as follows: After the activated SiC chip and ceramic substrate are fixed on an automatic spin coater for spin coating, they are placed in an automatic heating device for pre-curing. After pre-curing, the nano-silver particles are transferred to a vacuum sintering furnace for low-temperature sintering, which partially fuses the nano-silver particles to form a nanoporous silver layer. During the sintering process, microscopic images are acquired through online high-resolution optical monitoring, and a mathematical model is established to evaluate the quality of the silver layer in real time.

3. The SiC power module sintering and packaging method as described in claim 1, characterized in that: The specific steps for growing monolayer graphene via plasma-enhanced chemical vapor deposition are as follows. An oxygen-free environment was established under high-purity argon purging, and the substrate was heated and a bias voltage was applied to adsorb the carbon source. Utilizing adaptive plasma density to control the graphene growth environment; By controlling the hydrogen / methane flow ratio and nickel atom beam injection, graphene monolayers were grown uniformly to obtain graphene / nanoporous silver composite chip.

4. The SiC power module sintering and packaging method as described in claim 1, characterized in that: The epoxy resin encapsulating adhesive coating, UV curing, and annealing treatment follow these specific steps: The surface of the SiC power module is electrostatically sprayed with epoxy resin encapsulant, and the encapsulant is cured internally by multi-band ultraviolet light. Thermo-acoustic combined annealing is used to release residual stress at the interface through temperature gradient and ultrasonic oscillation.

5. The SiC power module sintering and packaging method as described in claim 1, characterized in that: The ultrasonic cleaning, plasma activation and drying process utilizes ultrasonic cleaning to remove surface oil and particulate contaminants, and plasma treatment.

6. The SiC power module sintering and packaging method as described in claim 1, characterized in that: The segmented pressure sintering in the vacuum sintering furnace refers to segmented pressure sintering using electromagnetic assistance and ultrasonic pre-compression, which is used to optimize the densification of the nanoporous silver layer.

7. The SiC power module sintering and packaging method as described in claim 1, characterized in that: The thermal cycling test refers to the test that evaluates the structural stability, electrical performance changes and fatigue life of SiC power modules under temperature stress by repeatedly cycling between extreme high and low temperature environments.

8. The SiC power module sintering and packaging method as described in claim 1, characterized in that: The XRD detection is used to analyze the crystal structure and phase composition of the SiC power module, while the SEM detection is used to observe its microstructure, interface bonding and defect distribution.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the SiC power module sintering and packaging method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the SiC power module sintering and packaging method according to any one of claims 1 to 8.

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