Data interaction adaptive method of photovoltaic protocol converter

Abstract

The application discloses a data interaction adaptive method of a photovoltaic protocol converter and specifically relates to the technical field of grid dispatching cooperative control, and the grid interconnection point voltage instantaneous change rate is monitored and calculated in real time and compared with a threshold value; when the threshold value is exceeded, the current phase is synchronously collected and a voltage-current phase difference change direction is generated; a voltage high-frequency component is extracted, wavelet packet decomposition is used to analyze the frequency band energy distribution and a Shannon entropy value representing energy concentration is calculated; when the phase difference change direction accords with a preset grid short-circuit fault feature and the Shannon entropy value is lower than a preset entropy threshold value, a grid transient event is determined; at this time, the data buffering mechanism of the protocol converter is immediately suspended, and a real-time streaming channel is activated; an emergency control instruction issued by a grid dispatching system is directly transmitted to a photovoltaic inverter through the channel; after the voltage instantaneous change rate continuously falls below the preset threshold value for a preset time length, the data buffering mechanism of the protocol converter is restored.

Description

Technical Field

[0001] This invention relates to the field of power grid dispatching and coordinated control technology, and more specifically, to a data interaction adaptive method for a photovoltaic protocol converter. Background Technology

[0002] In photovoltaic power plant monitoring systems, protocol converters serve as crucial hubs connecting photovoltaic equipment and the power grid dispatching platform, undertaking the function of converting and transmitting multi-source heterogeneous data. To improve communication efficiency, current mainstream protocol converters generally employ a data caching mechanism—database-stored locally in batches of collected equipment status information (such as inverter output values ​​and grid connection voltage), which is then uniformly sent to the upper-level system only after a preset data packet capacity or time window has been reached. This design significantly reduces the load on the communication link, meeting the resource utilization optimization requirements of industrial control systems.

[0003] However, when short-circuit faults or voltage drops occur in the power grid, the dispatch system needs to issue emergency control commands to the photovoltaic power station in a very short time. The inherent data delay characteristics of the existing caching mechanism cause critical commands to fail to penetrate the protocol conversion layer in a timely manner, resulting in the dynamic response capability of the photovoltaic power station lagging behind the time window requirements of the power grid safety protection. This contradiction between the timeliness of data transmission and the real-time nature of the power grid transient process has become a technical bottleneck restricting the photovoltaic power station from actively supporting the safe operation of the power grid. Summary of the Invention

[0004] To overcome the aforementioned deficiencies of the prior art, the present invention provides a data interaction adaptive method for photovoltaic protocol converters to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A data interaction adaptive method for a photovoltaic protocol converter includes the following steps:

[0007] S1. Monitor the grid connection point voltage in real time, calculate the instantaneous rate of change of the grid connection point voltage and compare it with a preset threshold in real time;

[0008] S2. When the instantaneous rate of change exceeds the preset threshold, the phase of the grid connection point current is synchronously collected to generate the direction of the phase difference between the grid connection point voltage and the grid connection point current phase.

[0009] S3. Extract the high-frequency components of the grid connection point voltage, analyze the frequency band energy distribution of the high-frequency components through wavelet packet decomposition, and obtain the Shannon entropy value that characterizes the energy concentration.

[0010] S4. When the direction of phase difference change conforms to the preset characteristics of power grid short circuit fault and the Shannon entropy value is lower than the preset entropy threshold, it is determined that the current event is a power grid transient event.

[0011] S5. When the current event is a power grid transient, immediately stop the data caching mechanism of the protocol converter and activate the real-time streaming transmission channel;

[0012] S6. The emergency control commands issued by the power grid dispatch system are directly forwarded to the photovoltaic inverter through the real-time streaming transmission channel;

[0013] S7. When the instantaneous rate of change remains below the preset threshold for a preset duration, restore the data caching mechanism of the protocol converter.

[0014] Furthermore, the voltage at the grid connection point is monitored in real time, and the instantaneous rate of change of the voltage at the grid connection point is calculated and compared with a preset threshold in real time, including:

[0015] Continuously collect instantaneous voltage values ​​at the grid connection point;

[0016] The instantaneous rate of change is calculated based on the difference between adjacent sampling points of the instantaneous voltage at the grid connection point;

[0017] The instantaneous rate of change is compared with a preset threshold in real time;

[0018] When the absolute value of the instantaneous rate of change continues to exceed a preset threshold for a preset time, a flag signal for the current phase at the grid connection point is generated to trigger synchronous acquisition.

[0019] Furthermore, when the instantaneous rate of change exceeds a preset threshold, the phase of the grid connection point current is synchronously acquired to generate the direction of the phase difference between the grid connection point voltage and the grid connection point current, including:

[0020] Based on the flag signal, the voltage phase sequence and current phase sequence at the grid connection point are simultaneously acquired within the first power frequency cycle after the fault occurs.

[0021] Calculate the instantaneous phase difference between the grid connection point voltage phase and the grid connection point current phase at each sampling time;

[0022] Trend fitting is performed on the instantaneous phase difference values ​​at multiple consecutive sampling times;

[0023] The slope value of the trend fitting result is used as the direction of phase difference change.

[0024] Furthermore, the high-frequency components of the grid connection point voltage are extracted, and the frequency band energy distribution of the high-frequency components is analyzed by wavelet packet decomposition to obtain the Shannon entropy value, which characterizes the energy concentration.

[0025] The voltage waveform at the grid connection point within a preset time after the fault determination time is extracted as the signal to be analyzed.

[0026] Wavelet packet decomposition is performed on the signal to be analyzed to obtain multiple sub-frequency band signals;

[0027] Calculate the energy value of each sub-band signal;

[0028] Calculate the frequency band energy distribution based on energy values;

[0029] Input the frequency band energy distribution into the Shannon entropy formula, and output the Shannon entropy value that characterizes the energy concentration.

[0030] Furthermore, when the direction of phase difference change conforms to the preset characteristics of a power grid short-circuit fault and the Shannon entropy value is lower than a preset entropy threshold, the current event is determined to be a power grid transient event, including:

[0031] The direction of phase difference change is matched with a preset power grid short-circuit fault feature library for pattern matching.

[0032] At the same time, the Shannon entropy value is compared with the preset entropy threshold.

[0033] When the direction of phase difference change matches the preset characteristics of power grid short-circuit fault and the Shannon entropy value is less than the preset entropy threshold, a power grid transient event judgment signal is generated.

[0034] Furthermore, the power grid transient event determination signal is used to trigger the data buffering mechanism of the interrupt protocol converter.

[0035] Furthermore, when a power grid transient event occurs, the data caching mechanism of the protocol converter is immediately suspended, and the real-time streaming channel is activated, including:

[0036] Receive power grid transient event determination signals;

[0037] Stop writing newly acquired device status information to the data buffer of the protocol converter;

[0038] Clear any unsent data from the protocol converter's data buffer.

[0039] Establish a real-time streaming channel independent of the caching mechanism at the communication link layer of the protocol converter.

[0040] Furthermore, the real-time streaming channel is used to transmit emergency control commands issued by the power grid dispatching system.

[0041] Furthermore, emergency control commands issued by the power grid dispatch system are directly forwarded to the photovoltaic inverter via a real-time streaming transmission channel, including:

[0042] Receive raw data stream of emergency control commands issued by the power grid dispatching system through the real-time streaming channel;

[0043] The protocol encapsulation format of the original data stream of the emergency control command remains unchanged;

[0044] The raw data stream of emergency control commands is transmitted through the communication interface of the photovoltaic inverter.

[0045] No protocol parsing or data caching is performed during the pass-through process.

[0046] Furthermore, when the instantaneous rate of change remains below a preset threshold for a preset duration, the data caching mechanism of the protocol converter is restored, including:

[0047] Monitor the absolute value of the instantaneous rate of change of voltage at the grid connection point;

[0048] When the absolute value of the instantaneous rate of change is continuously lower than a preset threshold for a preset duration, a cache recovery instruction is generated;

[0049] Re-enable the data buffer write function of the protocol converter according to the cache recovery command;

[0050] The data caching mechanism of the recovery protocol converter performs normal caching operations on device status information.

[0051] Compared with the prior art, the present invention has the following beneficial effects:

[0052] The photovoltaic protocol converter data interaction adaptive method provided by this invention uses real-time monitoring of the instantaneous change rate of the grid connection point voltage as an initial trigger signal, and combines the phase difference change direction characteristics of the grid connection point voltage and current phases with the Shannon entropy value of the voltage high-frequency component energy distribution for collaborative judgment, which can accurately identify transient events such as grid short-circuit faults. This multi-dimensional, multi-criteria identification mechanism effectively reduces the risk of misjudgment by single feature judgment and significantly improves the accuracy and reliability of grid transient event judgment.

[0053] After accurately identifying a power grid transient event, the original data caching mechanism of the protocol converter is immediately suspended, and a dedicated real-time streaming channel is simultaneously activated. This allows emergency control commands issued by the power grid dispatch system to bypass conventional data caching and processing procedures and be directly transmitted to the photovoltaic inverter for execution with extremely low latency. Furthermore, this method possesses self-recovery capabilities. After the power grid stabilizes, it can automatically restore the protocol converter's data caching mechanism based on the duration the instantaneous voltage change rate remains below a threshold. This effectively solves the critical problem of transmission delay for emergency control commands during power grid transients, ensuring the rapid response capability of photovoltaic power plants in the event of power grid faults, improving the safe and stable operation of the power grid, and simultaneously addressing the communication efficiency optimization needs of the system under normal operating conditions. Attached Figure Description

[0054] Figure 1 This is a flowchart of a data interaction adaptive method for a photovoltaic protocol converter according to the present invention. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0056] Example: Figure 1 The present invention provides a data interaction adaptive method for a photovoltaic protocol converter, which includes the following steps:

[0057] S1. Monitor the grid connection point voltage in real time, calculate the instantaneous rate of change of the grid connection point voltage and compare it with a preset threshold in real time;

[0058] S2. When the instantaneous rate of change exceeds the preset threshold, the phase of the grid connection point current is synchronously collected to generate the direction of the phase difference between the grid connection point voltage and the grid connection point current phase.

[0059] S3. Extract the high-frequency components of the grid connection point voltage, analyze the frequency band energy distribution of the high-frequency components through wavelet packet decomposition, and obtain the Shannon entropy value that characterizes the energy concentration.

[0060] S4. When the direction of phase difference change conforms to the preset characteristics of power grid short circuit fault and the Shannon entropy value is lower than the preset entropy threshold, it is determined that the current event is a power grid transient event.

[0061] S5. When the current event is a power grid transient, immediately stop the data caching mechanism of the protocol converter and activate the real-time streaming transmission channel;

[0062] S6. The emergency control commands issued by the power grid dispatch system are directly forwarded to the photovoltaic inverter through the real-time streaming transmission channel;

[0063] S7. When the instantaneous rate of change remains below the preset threshold for a preset duration, restore the data caching mechanism of the protocol converter.

[0064] Continuous acquisition of instantaneous voltage values ​​at the grid connection point: Instantaneous measurements of the grid connection point voltage are obtained through voltage transformers at a fixed sampling frequency. The sampling frequency is set according to the transient characteristics of the power system to ensure that voltage surge events can be captured. The specific value of the sampling frequency is determined based on the Nyquist sampling theorem and must be greater than twice the highest frequency component of interest in the grid; for example, it is set to 10 kHz in a system containing 20th harmonics.

[0065] The instantaneous rate of change is calculated based on the difference between adjacent sampling points of the instantaneous voltage at the grid connection point: The instantaneous voltage values ​​at two consecutive sampling times are taken. The instantaneous voltage value at the later sampling time is subtracted from the instantaneous voltage value at the earlier sampling time. The difference is then divided by the time interval between the two sampling points to obtain the voltage change per unit time, which is taken as the instantaneous rate of change. The time interval is determined by the reciprocal of the sampling frequency; for example, a 10 kHz sampling rate corresponds to a 0.1 millisecond interval. The calculation process is executed in real time by an arithmetic logic unit, ensuring that the calculation result is updated for each sampling point.

[0066] The instantaneous rate of change is compared in real time with a preset threshold. The preset threshold is set according to the maximum voltage fluctuation rate allowed for safe operation of the power grid, and this value is obtained through power system stability simulation and historical fault data analysis. The comparison operation is implemented using a hardware comparator. When the absolute value of the instantaneous rate of change is input to the comparator, it outputs a high or low level signal in real time to indicate whether the limit has been exceeded. The threshold setting needs to take into account the measurement error of the equipment, and a margin is added to the standard value, for example, by adding a margin of 3% to 5%.

[0067] When the absolute value of the instantaneous rate of change continuously exceeds a preset threshold for a preset time, a flag signal for the current phase at the grid connection point is generated to trigger synchronous acquisition. The preset time is determined by the characteristics of the grid fault duration, and is calculated by statistically analyzing the voltage drop duration distribution of typical short-circuit faults, taking the median value of the interval with the highest probability density. For example, it is set to 2 milliseconds for medium-voltage distribution networks. Duration verification is implemented using a timer: the timer starts when the comparator first outputs an over-limit signal, and triggers the flag signal when the over-limit continues for a preset time; if the voltage drops below the threshold during this period, the timer is reset. The flag signal is a digital level signal, transmitted to the current phase acquisition module via the control bus.

[0068] The voltage transformer's measurement accuracy must meet the 0.2 accuracy standard specified by the International Electrotechnical Commission (IEC). The sampling clock and current acquisition system must be strictly synchronized, with a synchronization error of less than 1 microsecond. The division operation in the instantaneous rate of change calculation is implemented using a fixed-point arithmetic unit, and the data bit width is set according to the measurement range, for example, using a 16-bit signed integer bit width. The threshold is stored in non-volatile memory and can be modified online via host computer software. The timer uses a high-frequency crystal oscillator as the clock source, achieving a time base resolution of 100 nanoseconds to ensure the accuracy of the preset time determination. The generation logic of the flag signal is implemented by a programmable logic device, and the output interface conforms to standard serial communication electrical specifications.

[0069] The calculation process for the difference between adjacent sampling points includes data validity verification: if the difference between the current instantaneous voltage value and the previous sampling point exceeds a certain proportion of the rated voltage, such as exceeding 30% of the rated voltage, an abnormal data filtering mechanism is activated, discarding the current value and replacing it with the previous valid value. The preset time adjustment range is set to 1 millisecond to 5 milliseconds, dynamically configured by writing parameters to the register, based on the short-circuit capacity level of the grid connection point. Digital filtering is implemented during the acquisition of instantaneous voltage values, using a low-pass filter with a specific cutoff frequency, such as a fourth-order Butterworth low-pass filter with a cutoff frequency of 500 Hz, to eliminate the influence of measurement noise on the calculation of the instantaneous rate of change.

[0070] The secondary output signal of the voltage transformer is converted into a voltage range suitable for sampling by a signal conditioning circuit, for example, converting a 100V AC input into a 0-3.3V DC signal. The accuracy of the sampling timing is ensured by a phase-locked loop (PLL) circuit, with the PLL reference signal taken from the fundamental component of the grid voltage. The calculation of the instantaneous rate of change includes sign processing: a positive value is output when the voltage rises and a negative value is output when the voltage falls. The absolute value is calculated using a full-wave rectifier circuit or digital absolute value arithmetic. The threshold setting range of the hardware comparator covers the maximum transient rate of change that may occur in the grid, for example, adjustable from 0.1 per unit per second to 1 per unit per second.

[0071] The persistent over-limit detection mechanism includes anti-interference design: when the instantaneous rate of change fluctuates around the threshold, a hysteresis interval is set to avoid frequent triggering, for example, a 5% hysteresis band is set at the threshold boundary. The flag signal remains valid after generation until the system resets, ensuring reliable triggering of subsequent steps. The accuracy of the time interval between adjacent sampling points is guaranteed by a temperature-compensated crystal oscillator, maintaining a frequency stability of 50 parts per million across the entire operating temperature range. The alternative strategy for the abnormal data filtering mechanism includes a linear interpolation option: when two consecutive sampling points are determined to be abnormal, the linear interpolation result of the preceding and following valid sampling points is used to replace the abnormal value.

[0072] The design parameters of the digital filter are adjusted according to the spectral characteristics of the power grid background noise, for example, raising the cutoff frequency to 1 kHz in strong harmonic environments. The programmable logic device's program logic includes a watchdog timer to prevent program runaway and false triggering. The control bus uses differential signal transmission methods, such as the RS-485 physical layer protocol, to enhance electromagnetic interference immunity. The host computer software configuration interface provides engineering unit conversion functions for threshold preset values, such as supporting bidirectional conversion between per-unit values ​​and volts per millisecond.

[0073] The calculation results of the arithmetic logic unit are managed using a circular storage buffer, retaining the historical record of the instantaneous rate of change of the most recent 100 sampling points. The reset timer includes a timeout reset mechanism: if it remains in an over-limit state but does not reach the preset time, and the duration exceeds the maximum allowable value (e.g., 10 milliseconds), the timer is forcibly reset and a device malfunction alarm is issued. The frequency response characteristics of the voltage transformer are calibrated, with an amplitude error of less than 0.5% and a phase offset of less than 0.1 degrees in the range of 50 Hz to 2 kHz.

[0074] The division operation in the calculation of the difference between adjacent sampling points is implemented using shift addition, avoiding the use of floating-point units to reduce latency. The non-volatile memory write operation has power-loss protection, saving the most recent configuration parameters in the event of a power failure. The fourth-order Butterworth filter is implemented using a direct type II structure, with coefficients dynamically calculated based on the sampling rate. The control bus transmission protocol includes an error check field, employing cyclic redundancy check (CRC) codes to ensure reliable signal transmission. The host computer software provides a threshold optimization function, automatically recommending threshold ranges by analyzing historical fault data.

[0075] The configuration data for programmable logic devices includes multiple backups, with real-time comparison of primary and backup configuration data to ensure consistency and integrity. The frequency calibration of the high-frequency crystal oscillator employs an automatic temperature compensation algorithm, dynamically adjusting oscillation parameters based on temperature sensor data. The activation conditions for the linear interpolation substitution strategy are configurable, for example, allowing the setting of a threshold for the number of consecutive abnormal sampling points. The watchdog timer's timeout is set to twice the preset time; for example, if the preset time is 2 milliseconds, the watchdog timeout is set to 4 milliseconds. Data updates in the circular storage buffer are managed using head and tail pointers, automatically overwriting the oldest historical data after each sampling.

[0076] The synchronous acquisition process is initiated based on a flag signal: Upon receiving a flag signal generated during the real-time monitoring of the grid connection point voltage, the synchronous acquisition timing control of the grid connection point voltage phase and grid connection point current phase is immediately triggered. This flag signal is a digital pulse signal, and its rising edge marks the start point of fault determination. The start-up time delay of synchronous acquisition is controlled within microseconds to ensure that data acquisition is completed within the first power frequency cycle after the fault occurs.

[0077] Within the first power frequency cycle after a fault occurs, the phase sequence of the grid connection point voltage and the phase sequence of the grid connection point current are acquired synchronously. A phase-locked loop (PLL) technique is used to lock the sampling clock to the grid fundamental frequency, ensuring strict synchronization of voltage and current sampling. The voltage phase sequence is calculated by continuously measuring the time interval between the zero-crossing points of the instantaneous voltage values ​​at the grid connection point. The current phase sequence is obtained by processing the instantaneous current values ​​at the grid connection point using the same method. The sampling frequency is set according to the power frequency cycle; for example, in a 50 Hz system using a 10 kHz sampling rate, phase data from 200 sampling points are collected within a single power frequency cycle. The signal transmission delay of the voltage transformer and current transformer is calibrated and compensated, and the compensation value is stored in non-volatile memory.

[0078] The instantaneous phase difference between the grid-connected voltage phase and the grid-connected current phase at each sampling moment is calculated: A subtraction operation is performed on the voltage and current phase values ​​at the same sampling moment to obtain the phase difference in radians. The phase value is calculated using the arctangent function to process the orthogonal components, which are obtained by Hilbert transform or hardware quadrature sampling. For example, the instantaneous voltage value is input to the orthogonal decomposition module of a digital signal processor, and the phase angle is calculated after outputting the in-phase and quadrature components. The calculation result of the instantaneous phase difference is stored in a circular buffer, the depth of which is equal to the number of sampling points within the power frequency cycle.

[0079] Trend fitting is performed on the instantaneous phase difference values ​​at multiple consecutive sampling times: all instantaneous phase difference values ​​within the first power frequency cycle after the fault occurred are selected as the fitting dataset. Trend fitting employs least squares linear fitting, with the sampling time series as the independent variable and the instantaneous phase difference value series as the dependent variable. The least squares calculation process includes the following steps: calculating the arithmetic mean of the sampling time series, calculating the arithmetic mean of the instantaneous phase difference value series, calculating the covariance of the sampling time series and the instantaneous phase difference value series, calculating the variance of the sampling time series, and dividing the covariance by the variance to obtain the slope value. The fitting process includes an outlier filtering mechanism: if the instantaneous phase difference value at a sampling point differs from the previous point by more than 0.1 radians, the point is marked as invalid and replaced by linear interpolation.

[0080] The slope value of the trend fitting result is used as the direction of phase difference change: the unit of the slope value is set to radians per millisecond, and the numerical sign indicates the direction of change, with a positive sign indicating an increase in phase difference and a negative sign indicating a decrease in phase difference. The calculated slope value is stored in a register and used as an input parameter for subsequent power grid transient event determination. The accuracy of the slope value calculation result is guaranteed by the floating-point unit, with a mantissa width of no less than 24 bits.

[0081] The reference signal for the phase-locked loop (PLL) circuit is taken from the fundamental component of the grid connection point voltage and implemented using a digital phase detector, achieving a phase-locking accuracy of 0.01 degrees. The orthogonal decomposition module employs a finite impulse response (FIR) filter, with the filter order set according to the sampling rate; for example, a 64th-order filter is used for a 10 kHz sampling rate. The calculated instantaneous phase difference is checked for range; if it exceeds the range of ±π radians, a circumferential correction is performed, for example, subtracting 2π radians when the difference exceeds π radians. The time series in the least squares fitting uses the fault trigger moment as the zero point, with the time unit being microseconds, and is stored as a 32-bit unsigned integer.

[0082] The threshold for the outlier filtering mechanism is dynamically configurable, ranging from 0.05 radians to 0.2 radians, with a default value of 0.1 radians. Linear interpolation is performed using the values ​​of two adjacent valid sampling points. The interpolation formula is the sum of the previous point value and the difference between the previous and next points, multiplied by a time scaling factor. The slope value is output as a 32-bit floating-point number, with the sign bit separately representing direction information. The read / write pointers to the circular buffer are managed by the direct memory access controller, ensuring that data access does not consume CPU resources.

[0083] The Hilbert transform is implemented using a 90-degree phase-shifting circuit combined with a finite impulse response filter, achieving a phase shift error of less than 0.5 degrees across the entire frequency band. The digital signal processor's operation cycle is strictly synchronized with the sampling cycle, completing the phase calculation for each sampling interval. The covariance calculation process employs an iterative algorithm, updating the accumulated sum and sum of squares after each sampling to avoid delays caused by concentrated calculations after the power frequency cycle ends. The circular correction logic includes boundary condition handling: when the instantaneous phase difference is close to negative π, if the difference at the new sampling point abruptly changes to near positive π, it is corrected to a continuously changing curve.

[0084] The burst transfer length of the direct memory access controller is set to an integer multiple of the number of sampling points in the power frequency cycle, for example, 200 sampling points of data are transferred each time. The rounding mode of the floating-point unit is set to round to zero to avoid accumulated errors. The division operation in the least squares calculation is accelerated using Newton's iteration method, with the number of iterations fixed at 3 to meet real-time requirements. The determination of the trend fitting result includes a confidence test: if the root mean square value of the fitting residual exceeds a threshold, for example, exceeding 0.05 radians, the calculation result is discarded and an alternative calculation strategy is activated.

[0085] The alternative calculation strategy employs median filtering combined with differential calculation: first, a five-point median filter is applied to the instantaneous phase difference sequence; then, the change in difference between the first and last sampling points is calculated, and divided by the time interval to obtain the alternative slope value. The confidence threshold is stored in erasable memory, supporting remote modification. The time scaling factor is calculated using a hardware divider; the numerator is the time difference between the current invalid point and the previous point, and the denominator is the time difference between the previous and subsequent valid points. The residual root mean square calculation uses a square root lookup table combined with linear interpolation; the lookup table depth is 1024 points.

[0086] The timestamps for the sampling time series are generated by a high-precision timer with a clock frequency of 100 MHz and a time resolution of 10 nanoseconds. An adaptive algorithm is used to track the grid fundamental frequency; when the system frequency fluctuates between 49 Hz and 51 Hz, the phase-locked loop (PLL) automatically adjusts the sampling timing. Calibration of the quadrature components is performed during equipment commissioning: a standard phase difference signal is applied, and the filter coefficients are adjusted until the output phase error is less than 0.1 degrees. Invalid sampling point markers are stored in a separate status register, with each sampling point corresponding to a one-bit flag.

[0087] The least squares fitting process includes a data alignment mechanism: During each sampling interrupt service routine, the newly acquired instantaneous phase difference value is written to a specified location in the buffer, and the accumulator counter is updated. When the counter reaches the number of sampling points in the power frequency cycle, a direct memory access is triggered to transfer the data block to the coprocessor. After the coprocessor completes the slope calculation, it notifies the main processor to read the result via an interrupt. The time tolerance for data alignment is set to one-tenth of the sampling interval; for example, a deviation of 10 microseconds is allowed at a 10 kHz sampling rate.

[0088] The circular correction of the instantaneous phase difference employs a conditional judgment: if the jump between the current difference and the previous valid difference exceeds π radians, a correction of 2π radians is applied. The corrected difference sequence undergoes first-order difference calculation, and the difference result is used to detect instantaneous jump points. Phase error detection in the phase-locked loop uses a multiplicative phase detector, with the loop filter bandwidth set to 10 Hz and the damping coefficient set to 0.707. The generation of the quadrature sampling clock utilizes direct digital frequency synthesis technology, achieving a frequency resolution of 0.001 Hz.

[0089] The sampling buffer uses a dual-buffered storage structure: the data acquisition area for the current power frequency cycle is physically isolated from the data processing area for the previous cycle to avoid access conflicts. The slope value output register has a dual-copy redundancy design; the primary copy is used for output, and the secondary copy is used for anomaly verification. When the difference between the primary and secondary copies exceeds a set threshold, such as 5%, an invalid slope value alarm is triggered. The invalid alarm signal is output synchronously with the slope value to subsequent decision-making steps for reliability assessment.

[0090] The least squares covariance accumulator employs a 40-bit wide design to avoid overflow when accumulating 200 sampling points. The arithmetic mean of the time series is calculated by dividing the pre-stored total value by the number of sampling points; the division operation is implemented using a combination of table lookup and bit shifting. The instantaneous phase difference is stored as a fixed-point number, with the integer part consisting of 3 bits representing plus or minus π radians, and the fractional part consisting of 13 bits corresponding to a resolution of 0.0001 radians. The interrupt response latency of the digital signal processor is measured to be less than 500 nanoseconds, ensuring that each sampling point is processed completely.

[0091] The grid-connected voltage waveform within a preset time period after the fault determination time is used as the signal to be analyzed. The fault determination time is based on the rising edge of the flag signal generated from the phase difference change direction generation step. The preset time period is set according to the duration of the transient process and determined by analyzing the attenuation characteristics of high-frequency voltage oscillations in historical fault waveform data, for example, 5 milliseconds. The extraction operation is implemented through a circular storage buffer, with the buffer depth designed according to the maximum preset time period, for example, 10 milliseconds corresponds to 500 sampling points (10 kHz sampling rate). The extraction start point is the flag signal trigger time, and the end point is the start point plus the preset time period, with a time scale alignment accuracy of 100 nanoseconds.

[0092] The signal to be analyzed is decomposed into wavelet packets to obtain multiple sub-band signals. The mother wavelet for wavelet packet decomposition is selected based on the high-frequency noise characteristics of the power grid, for example, the Daubechies 4th order wavelet is used. The number of decomposition levels is determined according to the preset duration and frequency resolution requirements; for example, 3 levels of decomposition produce 8 sub-bands. The decomposition process includes the following steps: low-pass and high-pass filtering of the signal to be analyzed to obtain approximation coefficients and detail coefficients; the same operation is recursively performed on the approximation coefficients and detail coefficients until the set number of levels is reached; finally, the time-domain signal of each sub-band is obtained through a reconstruction algorithm. The filtering operation is implemented using convolution, and the convolution kernel coefficients are stored in read-only memory.

[0093] Calculate the energy value of each sub-band signal: the energy value is defined as the sum of the squares of the amplitudes of all sampled points of the sub-band signal. The calculation process is implemented in hardware using a multiply-accumulate unit. The square of one point is performed in each sampling period and accumulated to the corresponding frequency band accumulator. The energy value calculation result is stored by frequency band index in 32-bit unsigned integer format. Before the amplitude squaring operation, a data range check is performed. If the sampled value exceeds 80% of the full scale, overflow protection is activated, and the value is truncated to the maximum representable value.

[0094] The sub-band energy value is calculated as follows:

[0095]

[0096] Among them, E k x represents the energy value of the k-th sub-band; k is the sub-band number; x k(n) represents the amplitude of the nth sampling point; n is the number of the sampling point; N is the number of sampling points.

[0097] Frequency band energy distribution is calculated based on energy values: Frequency band energy distribution represents the proportion of energy in each sub-band to the total energy. The calculation process includes: summing the energy values ​​of all sub-bands to obtain the total energy; and dividing the energy value of each sub-band by the total energy to obtain the energy proportion of that band.

[0098] The formula for calculating the frequency band energy ratio is:

[0099]

[0100] Among them, EnergyRatio specificBand EnergyValue represents the energy ratio of the specific band sub-band. specificBand This represents the energy measurement value of the specificBand sub-band; TotalEnergy represents the total energy value of all sub-bands; specificBand represents the specific sub-band number currently being calculated.

[0101] The division operation uses a floating-point arithmetic unit, and the ratio value is stored as a single-precision floating-point number. The ratio calculation result is normalized and verified: the difference between the sum of all frequency band ratio values ​​and 1 is less than a certain tolerance, for example, less than 0.001.

[0102] The frequency band energy distribution is input into the Shannon entropy formula, and the output is the Shannon entropy value, which characterizes the energy concentration. The Shannon entropy formula is defined as the negative sum of the energy proportions of each frequency band multiplied by the base-2 logarithm of that proportion. The calculation process is performed in three steps: calculate the base-2 logarithm of each energy proportion; multiply the energy proportion by the corresponding logarithm; and sum the products of all frequency bands and take the negative. The logarithmic operation is implemented using a lookup table combined with linear interpolation. The lookup table covers the range from 0 to 1 with a step size of 0.001. The final entropy value is output as a single-precision floating-point number, with three significant digits retained.

[0103] The formula for calculating Shannon entropy is:

[0104]

[0105] Where ShannonEntropyResult represents the calculated Shannon entropy value; numberOfBand represents the total number of subbands; currentBand represents the current subband index (ranging from 1 to numberOfBand); EnergyRatio currentBand represents the energy ratio of the currentBand subband; log2 represents the logarithmic operation to the base 2.

[0106] The circular storage buffer uses a dual-pointer mechanism for address management: the write pointer tracks the latest sampling point in real time, while the read pointer locks the truncation interval when a flag signal is triggered. The recursion depth of wavelet packet decomposition is controlled by a configurable register, allowing for 1 to 5 levels of decomposition, with a default value of 3 levels. The accumulation result of the multiply-accumulate is cleared after each sub-band calculation to avoid cross-band interference. The overflow protection threshold can be adjusted online, ranging from 50% to 95% of full scale.

[0107] Handling strategy for normalization verification failure: If the difference between the sum of the proportional values ​​and 1 exceeds the tolerance, the total energy is recalculated and the proportional values ​​are redistributed. The logarithmic operation in the Shannon entropy calculation uses a piecewise approximation: when the proportional value is less than 0.001, the minimum value of -10 is returned directly to avoid calculating invalid values. A validity check is performed before outputting the entropy value: if all proportional values ​​are equal, the maximum entropy value is output, for example, 3.0 for 8 sub-bands; if a single band occupies 100%, 0 is output.

[0108] The mother wavelet coefficients are stored using symmetrical compression: leveraging the symmetry of the wavelet function, only half of the coefficients are stored. The reconstruction algorithm employs a tree-structured inverse filtering, performing upsampling before convolution. The bit width design of the multiply-accumulate unit considers the worst-case scenario: a preset duration of 500 sampling points, a full-scale value of 32767, and a maximum sum of squares of 500 × 32767. 2 This corresponds to a 48-bit accumulator width. Floating-point division operations use the Goldschmidt iterative algorithm, with a fixed number of iterations of 3.

[0109] Logarithmic lookup table data generation: Logarithmic values ​​for 1000 points are pre-calculated during device initialization and stored in static memory. The linear interpolation process includes: calculating the decimal part of the lookup table index based on the proportional value, and then taking a weighted average of the two preceding and following integer values. Negative sign handling in entropy calculation uses two's complement arithmetic, with a separate sign bit. The maximum entropy value for validity checks is dynamically calculated based on the number of sub-bands, using the logarithmic value of the number of sub-bands as the calculation formula.

[0110] Boundary handling of the truncation interval: When the preset duration exceeds the end of the buffer, a circular address mapping is used to access the beginning of the buffer. The wavelet packet decomposition filtering convolution implementation uses a transpose structure to reduce computational latency. When the multiply-accumulate overflow protection is triggered, an event log is recorded, including the overflow frequency band index and sampling point location. The tolerance value for normalization verification can be configured via software, ranging from 0.0001 to 0.01. The scaling factor correction uses a scaling method: each scaling value is multiplied by a correction factor until the sum equals 1.

[0111] Special value handling for logarithmic operations: When the ratio is 0, the logarithm is defined as negative infinity; in actual implementation, a preset minimum value is used instead. The range of entropy calculation results is limited to 0 to the maximum entropy value; saturation processing is performed when the value exceeds this range. The synchronization signal at the fault determination time is marked with a timestamp, and the timestamp counter is driven by a 100 MHz clock. Data updates in the circular storage buffer use a ping-pong operation: the current write buffer and the historical read buffer are physically separated.

[0112] The frequency bands in wavelet packet decomposition are arranged by increasing frequency index, with index 0 representing the lowest frequency band. The squaring operation of the multiply-accumulate operation employs a multiplier multiplexing strategy, completing one squaring calculation per clock cycle. Input and output range checks are performed for floating-point division. Intermediate variables in the Shannon entropy calculation process are stored in double precision, and the final result is converted to single precision output.

[0113] The product of the proportional and logarithmic values ​​is calculated using a hardware multiplier with a bit width of 24 bits × 24 bits. The entropy accumulator is initialized to 0 and accumulates the product value after each frequency band is calculated. The maximum entropy value for validity checking is calculated using a floating-point logarithmic arithmetic unit and is pre-calculated and stored when the configuration changes. The accuracy verification method for the output entropy value is as follows: input known distribution data, compare the output value with the theoretical value, and ensure the error is less than one-thousandth.

[0114] The start delay of the truncation operation is controlled within two sampling periods to ensure that the fault initiation point is included. The filter coefficients for wavelet packet decomposition are loaded using burst transmission mode, with the coefficient memory updated before each decomposition. The number of sampling points for energy value calculation varies with the actual truncation length and is dynamically determined by multiplying the preset duration by the sampling rate. The storage structure for the frequency band energy distribution is in array form, with the array size equal to the number of sub-bands. The number of loop iterations for Shannon entropy calculation equals the total number of sub-bands, and loop control is implemented using a state machine.

[0115] The reference time for fault determination is synchronized with the power grid frequency clock and generated using a phase-locked loop (PLL) frequency division. After the buffer read pointer is positioned, direct memory access is triggered, transmitting the captured data block to the signal processing unit. The recursive operation of wavelet packet decomposition uses a dedicated coprocessor, supporting multi-level decomposition pipelined processing. The energy calculation unit works in parallel with the decomposition unit; energy calculation begins immediately after each sub-band signal is generated. The frequency band energy distribution calculation unit receives all sub-band energy values ​​and then initiates the total energy summation operation.

[0116] The Shannon entropy calculation unit includes a proportional value input interface, a logarithmic lookup table interface, and an accumulation output interface. The entropy output register is directly connected to the input register of subsequent decision steps, with a transmission delay of less than 100 nanoseconds. The header information of the truncated data block includes a fault timestamp and the actual number of sampling points for verification in subsequent steps. The intermediate coefficients of wavelet packet decomposition are stored in a hierarchical memory, with each level of coefficients allocated an independent storage area. The energy value calculation unit includes a squaring pipeline, completing the processing of one sampling point per cycle.

[0117] The division instruction in the frequency band energy distribution calculation is supported by a proprietary floating-point instruction set. The logarithmic base conversion in the Shannon entropy formula is achieved through a base-changing formula: the natural logarithm result is multiplied by a pre-stored constant 1.442695 (i.e., 1 / ln2). The entropy accumulation process uses a Caesar window accumulator to reduce the cumulative effect of rounding errors. The output interface includes a data validity signal, which is set when the entropy calculation is complete.

[0118] The phase difference change direction is pattern matched against a pre-defined power grid short-circuit fault feature library. The phase difference change direction is derived from the 32-bit floating-point slope value output in step S2, expressed in radians per millisecond. The pre-defined power grid short-circuit fault feature library is stored in non-volatile memory and contains phase change pattern data for typical short-circuit faults. The pattern matching process performs the following operations: reads the sign and amplitude of the current slope value; compares the sign direction with that of each record in the feature library; and verifies whether the amplitude is within the preset range for the corresponding fault type. The feature library is constructed by simulating 10 standard short-circuit faults (e.g., three-phase short circuit, single-phase ground fault) in a laboratory setting, recording the phase difference change slope during the first power frequency cycle of each fault occurrence, and taking the average of 200 experiments as the baseline value. A 20% fluctuation above or below the baseline value is used as the matching range. The matching result is output as a Boolean flag, for example, outputting logic 1 when the sign matches and the amplitude is within the range.

[0119] Simultaneously, the Shannon entropy value is compared with a preset entropy threshold. The Shannon entropy value, derived from the single-precision floating-point number output in step S3, represents the concentration of energy distribution in the high-frequency components of the voltage. The preset entropy threshold is set based on the difference in Shannon entropy values ​​under normal grid operation and fault conditions, determined through the following steps: Voltage waveforms are continuously collected for 1000 power frequency cycles during fault-free grid periods, their Shannon entropy values ​​are calculated and statistically distributed, and the 5th percentile value is used as the threshold benchmark. For example, the typical threshold for a medium-voltage distribution network is 2.3. The comparison operation is implemented using a hardware comparator: the Shannon entropy value is input to port A of the comparator, and the preset entropy threshold is input to port B. When the value at port A is less than the value at port B, a high level is output. The dynamic adjustment mechanism for the entropy threshold is as follows: the latest operating data is re-collected every quarter, and the stored value is updated via the host computer software.

[0120] When the direction of phase difference change matches the preset characteristics of a power grid short-circuit fault and the Shannon entropy value is less than the preset entropy threshold, a power grid transient event judgment signal is generated. This step is a logical AND operation, with inputs being a high-level signal from the Boolean flag of pattern matching and the entropy comparison result. The implementation uses a dual-input AND gate circuit, outputting a high-level pulse only when both inputs are simultaneously valid. Signal generation timing control: the judgment is completed within 5 milliseconds after the fault judgment time, and the output pulse width is fixed at 10 microseconds. The judgment signal is output in isolation via an optocoupler to ensure anti-interference capability. Electrical characteristics of the output signal: the high level is 5V DC, and the drive current capability reaches 20mA.

[0121] The power grid transient event determination signal is used to trigger the termination of the protocol converter's data buffering mechanism: the determination signal is connected to the hardware interrupt pin of the protocol converter, triggering the following operations immediately: pausing the current data transmission process; clearing the temporary data in the data buffer to be transmitted; and resetting the data frame assembly state machine to its initial state. The recovery condition of the termination mechanism is: after a specific delay (e.g., 100 milliseconds) following the failure of the determination signal, data transmission is automatically restarted. The data buffer clearing operation uses a memory block zeroing instruction, with an execution time of less than 10 microseconds. The state machine reset includes loading the register initial values, which are stored in read-only memory.

[0122] The pre-defined power grid short-circuit fault feature database is stored in a two-dimensional array: the first dimension indexes the fault type number (e.g., 0 represents a three-phase short circuit, 1 represents a single-phase ground fault), and the second dimension stores the symbol flag (1 indicates positive, -1 indicates negative) and the upper and lower limits of the amplitude range. Amplitude range verification for pattern matching uses an interval comparator: the current slope value is simultaneously connected to both the lower limit comparator (greater than or equal to) and the upper limit comparator (less than or equal to), and the outputs of the two comparators are logically ANDed with the symbol comparison result. The entropy threshold's storage address is mapped to a specific memory page and has write protection.

[0123] Input signal synchronization processing for the dual-input AND gate circuit: The pattern matching result and entropy comparison signal are aligned by a clock edge trigger at a clock frequency of 100 MHz. Optocoupler selection parameters: insulation voltage 4000 volts, transmission delay less than 1 microsecond. The interrupt service routine for the protocol converter is stored in flash memory and contains three core instructions: loading the data buffer's starting address into the address register; loading the buffer length value into the counter; and executing a memory block clearing loop. The initial values ​​for state machine reset include: data frame header identifier, checksum initial value, and byte counter reset to zero.

[0124] The feature library maintenance interface receives feature library update data packets from the host computer via a serial communication interface. The data packet contains four fields: fault type number, symbol flag, lower amplitude limit, and upper amplitude limit. Validity verification during amplitude range updates: the lower limit must be less than the upper limit, and the upper limit must not exceed the maximum allowable rate of change of 1.5 per unit per second. Online entropy threshold calibration function: when a calibration command is manually entered, the entropy value of the current 100 power frequency cycles is automatically collected, and the 5th percentile is calculated to cover the original threshold.

[0125] The default fault type for pattern matching is three-phase short circuit, which can be switched to other fault types via a DIP switch. The reference voltage of the interval comparator is generated by a digital potentiometer, which is controlled by a value stored in the feature library. The memory block clearing loop is optimized by using a 32-bit wide data bus to clear 4 bytes of data with a single instruction, improving clearing efficiency. The state machine reset signal generation path is as follows: a decision signal triggers a monostable multivibrator, generating a 50-nanosecond wide reset pulse.

[0126] The protocol converter's data buffer address pointer hard reset mechanism: a fixed initial address value of 0000H is loaded via an address generator. The checksum register's reset value is set to 0xFFFF. The byte counter is cleared using a synchronous reset signal to avoid metastability issues. Interrupt response latency protection measures: a decision signal is connected to the processor's non-maskable interrupt pin, with a response latency of less than 500 nanoseconds. Clear operation completion confirmation signal: after the data buffer is cleared, a hardware comparator detects the all-zero state and outputs an confirmation flag.

[0127] The feature library update data packet verification mechanism includes a 16-bit cyclic redundancy check (CRC) field; data can only be written to memory after successful verification. The digital potentiometer has a 12-bit resolution, corresponding to 4096 voltage adjustment levels. The timing capacitor for the monostable multivibrator is a ceramic capacitor with a temperature stability of 30 parts per million. The initial value of the address generator is stored in the fuse bit configuration memory, which is automatically loaded upon power-on. All-zero state detection uses a 1024-bit wide OR gate tree structure; a valid flag is output when all input bits are 0.

[0128] Priority logic for fault type switching: When multiple fault characteristics match simultaneously, the fault type number with the highest priority is output (e.g., three-phase short circuit priority is 0, single-phase grounding priority is 1). Hysteresis design of the entropy comparator: A 3% hysteresis band is set near the threshold to avoid frequent switching due to noise. Schmitt triggers are configured at the optocoupler output to eliminate signal edge jitter. Direct memory access requests are paused during data buffer clearing to prevent data conflicts. After state machine reset, data transmission must wait two clock cycles before resuming.

[0129] Failure detection of the judgment signal: monitored by a pulse width counter; if the high level duration exceeds 1 millisecond, the output is forcibly pulled low. The restart delay time of the protocol converter is controlled by a programmable timer with a timer base clock of 10 kHz and a prescaler of 1000, corresponding to a 100-millisecond timing. The opcode of the memory zeroing instruction is hardwired to the processor instruction decoder for specific encoding. The entry address of the interrupt service routine is fixed at location 0xFFF0 in the interrupt vector table.

[0130] Confidence output of feature library matching results: When the deviation between the current slope value and the benchmark value is less than 10%, an additional confidence flag is output. Margin indication for entropy threshold comparison results: If the Shannon entropy value is more than 10% below the threshold, a strong judgment flag is output. Fault-safe design of AND gate circuits: Automatically locks the output low level when any input signal is abnormal. Real-time monitoring of data buffer clearing progress: Generates a progress status code every 25% of the data area cleared. Self-test process after state machine reset: Sequentially verifies the initial values ​​of each register and outputs the verification results.

[0131] Receive the power grid transient event determination signal: This signal is a 5V DC high-level pulse signal from step S4, with a fixed pulse width of 10 microseconds. The signal receiver is configured with a Schmitt trigger for edge shaping to eliminate oscillation interference during transmission. The shaped signal is then connected to the non-maskable interrupt pin of the protocol converter, with the interrupt priority set to the highest level. The interrupt trigger condition is rising edge detection, and the response delay has been measured to be less than 200 nanoseconds. Signal level validity verification: When the input voltage exceeds 3.5V, it is determined to be a valid high level; when it is below 1.5V, it is determined to be an invalid low level.

[0132] Stop writing newly acquired device status information to the data buffer of the protocol converter: Immediately execute the write enable flag reset operation in the interrupt service routine. Specifically, this is achieved by setting the output enable register of the data acquisition module to zero, which controls the write gating circuit for data flow to the buffer. Timing control for stopping write operations: Freeze the write pointer after the current data transmission cycle ends; the freezing action is completed within 2 clock cycles. Device status information includes the effective values ​​of grid connection point voltage, current, and active power. Each type of data is updated at a fixed period, for example, the effective voltage value is updated 100 times per second. Data handling after write stop: Newly acquired data is temporarily stored in a first-in-first-out queue with a queue depth of 10 data groups; the oldest data is automatically discarded when overflow occurs.

[0133] Clear unsent data from the protocol converter's data buffer: The data buffer is implemented using a dual-port static memory with a capacity of 1 megabyte. The clear operation executes block erase instructions through the direct memory access controller, starting at the buffer base address 0000H and ending at the current write pointer position minus one. The erase mode is all-zero filling, writing a 0x00 value to each memory cell. Clear progress monitoring mechanism: The status register is updated every 256 bytes erased, with the lower 8 bits of the status register indicating the completion percentage. Clear completion flag generation: A completion interrupt is triggered when the end address equals the current erase address. Exception handling: If the erase time exceeds a preset value of 50 microseconds, a backup erase circuit is activated to forcibly pull down the chip select signals of all memory cells.

[0134] A real-time streaming channel independent of the caching mechanism is established at the communication link layer of the protocol converter: the communication link layer is based on an Ethernet physical layer chip, and the real-time streaming channel is isolated through a virtual LAN identifier. Channel establishment steps: 1) Configure the priority flag of the network protocol stack, setting the service type field to the highest priority; 2) Allocate an independent media access control address suffix, for example, by overlaying 0xFF after the base address; 3) Pre-configure a dedicated routing table entry in the switching chip to directly route data packets destined for the power grid dispatch system to the physical layer transmission queue. Channel bandwidth guarantee mechanism: 30% of the total bandwidth is reserved, and traffic shaping is achieved through a token bucket algorithm. Channel heartbeat detection: A 1-byte heartbeat packet is sent every millisecond; if no response is received within 3 milliseconds, the channel is rebuilt.

[0135] The real-time streaming channel is used to transmit emergency control commands issued by the power grid dispatching system. The command transmission format adopts a simplified frame structure, with a fixed frame header of 0xAA55. The payload contains the command code (1 byte) and parameter values ​​(4 bytes). The transmission process omits the handshake step of the transmission control protocol and uses the user datagram protocol broadcast mode. Command reception verification: A hardware filtering circuit is set at the protocol converter receiver to allow only data packets whose source media access control address is the dispatching system's registered address to pass through. Command execution delay constraint: The delay from receiving the command to outputting it to the actuator does not exceed 500 microseconds. Command security verification: Each command frame is appended with a 2-byte cyclic redundancy check code; if verification fails, the frame is discarded.

[0136] The reset operation of the data buffer write enable register includes state synchronization: the reset signal is synchronized to the clock domain of the data acquisition module to avoid metastability. The first-in-first-out (FIFO) queue overflow discard strategy uses a circular buffer design, with the write pointer automatically overwriting the oldest data. The address generation for block erase instructions uses a linearly incrementing counter with a counter step frequency of 200 MHz. The virtual LAN identifier configuration range is set to 4096 to 4100, dynamically written through management information base variables. The token bucket algorithm parameters are configured as follows: bucket depth is set to 10 frames of data, and the token generation rate is fixed at 1000 frames per second.

[0137] Emergency control command code table storage and mapping: Command code 0x01 represents circuit breaker tripping, 0x02 represents capacitor bank activation, and a total of 16 commands are defined. Parameter value parsing rules: The first 2 bytes are the device address code, and the last 2 bytes are the action parameters (e.g., tripping time). The media access control address whitelist of the hardware filtering circuit is stored in content-addressable memory, with a capacity supporting 8 address registrations. The User Datagram Protocol (UDP) port number is fixed at 9999, and the destination Internet Protocol (IP) address is preset to the primary and backup addresses of the dispatch system. The Cyclic Redundancy Check (CRC) generator polynomial adopts the CRC-16-CCITT standard, with an initial value of 0xFFFF.

[0138] Position locking mechanism during write pointer freeze: The current write pointer value is captured by a latch, and the latch enable signal is synchronized with the interrupt signal. First-In-First-Out (FIFO) queue read / write pointer difference calculation: An overflow flag is triggered when the write pointer minus the read pointer exceeds the queue depth. Power guarantee for block erase operations: Backup supercapacitor power is used during the erase process to maintain power supply for at least 100 milliseconds. Virtual LAN tag insertion position: Located 4 bytes after the Ethernet frame source media access control address, the tag format conforms to the IEEE 802.1Q standard. Token bucket state update: One token is consumed for each received data frame, and the token count increases by one every millisecond.

[0139] Methods for measuring instruction execution latency: A high-precision timer is started when the instruction frame header arrives, and the timer stops after the actuator responds. Hardware acceleration for cyclic redundancy check (CRC) code calculation: A 16-bit linear feedback shift register is used, processing 1 byte of data per clock cycle. State recovery process after data buffer clearing: The write enable register is set, the write pointer is unfrozen, and the FIFO queue read / write pointers are reset. Abnormal reconstruction process of real-time streaming channel: The current VLAN configuration is released, a new media access control address is requested, and routing table entries are reloaded. Priority overriding mechanism for emergency control instructions: After the channel is established, regular telemetry data transmission is automatically paused until instruction transmission is complete.

[0140] Clock synchronization guarantee for the protocol converter: Employs the IEEE 1588 precise time protocol, with a time deviation of less than 1 microsecond from the scheduling system. Physical layer chip transmit queue management: A dual-priority queue is set up, with real-time streaming channel data packets always inserted at the head of the high-priority queue. Instruction execution feedback mechanism: After the actuator responds, it generates a 4-byte status code, which is transmitted back in real-time through the original channel. Interrupt nesting handling for clearing operations: If a new judgment signal is received during the clearing process, the current clearing is terminated and the entire process is immediately restarted. Channel heartbeat acknowledgment mechanism: After receiving a heartbeat packet, the scheduling system returns an acknowledgment packet containing a timestamp for transmission delay compensation.

[0141] Hardware-fixed data buffer base address: Locked by fuse configuration in the address decoder, cannot be modified by software. Media access control address suffix generation algorithm: Logical OR operation is performed between the base address and 0x0000FFFF. Pre-setting timing of switching chip routing table entries: Loaded via the serial peripheral interface during the protocol converter initialization phase. Electrical isolation of the actuator interface: Employs magnetic isolation technology with an insulation strength of 5000V AC. Cyclic redundancy check error counting: Triggers a channel self-test program after three consecutive failed checks. Real-time streaming channel bandwidth monitoring: Calculates actual bandwidth usage every second; generates an early warning event when bandwidth exceeds 80% of the reserved bandwidth.

[0142] The system receives raw data streams of emergency control commands issued by the power grid dispatching system through a real-time streaming channel. This real-time streaming channel is a dedicated link with virtual local area network (VLAN) identifiers 4096 to 4100 established using the S5 steps. Data reception employs the physical layer chip's direct memory access (DMI) mode. A DMI request is triggered when the target media access control address matches the registered whitelist and the VLAN tag value is within a preset range. The receive buffer is configured with a ping-pong double-buffered structure, with each buffer having a capacity of 1526 bytes (the maximum size of a standard Ethernet frame). Reception timing control: During the transmission of a complete frame from the start-of-frame delimiter to the end of the frame check sequence, the hardware automatically masks interrupt requests. Data stream verification mechanism: The frame length is checked to ensure it is within the valid range of 64 bytes to 1526 bytes; if it exceeds this range, the frame is discarded and an error log is generated.

[0143] The protocol encapsulation format of the original data stream of the emergency control command remains unchanged: the format maintains processing at the following three levels: 1) The physical layer maintains the original Manchester encoded waveform, regenerating the original timing through a clock data recovery circuit; 2) The data link layer maintains the original frame structure, including the complete bit sequence of the preamble, start-of-frame delimiter, destination MTAC address, source MTAC address, VLAN tag, and Ethernet type field; 3) Modification of the network layer and above payload content is prohibited. The implementation uses hardware-level signal relay: the serial output of the receiver's physical layer chip directly drives the differential input of the transmitter's physical layer chip, passing through only two stages of signal shaping amplifiers. The shaping amplifier gain is set to unity gain, and the bandwidth is limited to 100 MHz to suppress high-frequency noise.

[0144] The raw data stream of emergency control commands is transparently transmitted to the communication interface of the photovoltaic inverter: the transmission path is a dedicated physical channel, directly connected from the medium-independent interface of the protocol converter to the medium-independent interface of the photovoltaic inverter. Interface electrical characteristics are matched: the differential level at the transmitting end is adjusted to the 1.8V peak-to-peak value required by the photovoltaic inverter, and the common-mode voltage offset is compensated to 1.25V. Industrial-grade RJ45 connectors are used, with a contact resistance of less than 20 milliohms. Transmission start condition: the transmit driver is automatically enabled upon detection of a valid frame start delimiter. Transmission delay compensation mechanism: the inherent channel delay is measured and a compensation value (e.g., 200 nanoseconds) is pre-stored; an equal-duration prefix extension is inserted during frame transmission.

[0145] No protocol parsing or data buffering is performed during transparent transmission. Protocol parsing is prohibited in the following ways: 1) The Media Access Control (MAC) controller is prohibited from accessing the receive frame buffer; 2) The network protocol stack processing thread is prohibited from running; 3) The Transmission Control Protocol / Internet Protocol demultiplexer enable signal is disabled. Data buffering is prohibited through the following design: a point-to-point direct data bus is used between the receive and transmit buffers, with a bus width of 4 bits (corresponding to a rate of 100 megabits per second), and bus control is exclusively held by the physical layer chip. A hardware watchdog monitoring mechanism is in place: if a buffer enable signal transition is detected during transmission, the transmission channel is immediately reset.

[0146] Ping-Pong Buffer Switching Logic: The receiving completion flag of buffer A triggers three actions: 1) Switching buffer B to receive mode; 2) Starting data transmission from buffer A to the sending end; 3) Setting the status flag of buffer A to transmitting. Transmission Completion Determination: When the physical layer chip at the sending end returns a frame end signal, buffer A is released. The Manchester-encoded clock regeneration circuit adopts a phase-locked loop structure with a damping coefficient set to 0.707 and a bandwidth set to 10% of the data rate. Temperature Compensation for the Signal Shaping Amplifier: The bias voltage is dynamically adjusted based on ambient temperature sensor data, with a compensation coefficient of -0.2 mV per degree Celsius.

[0147] Differential level adjustment circuit: Employs a digitally controlled variable gain amplifier, with the gain control word stored in an electrically erasable programmable read-only memory. Common-mode voltage compensation circuit: Generates a reference voltage based on a digital-to-analog converter, with 12-bit accuracy. The industrial-grade RJ45 socket has a gold plating thickness greater than 50 microinches and a guaranteed insertion / removal life of 1000 cycles. Measurement method for transmission delay compensation value: Send a test short frame, measure the time difference from transmission enable to reception interrupt, repeat 100 times, and take the average value.

[0148] Arbitration mechanism for point-to-point direct data bus: Implemented through hardware signal interlocking. The receiving physical layer chip outputs a request to send signal, and the sending physical layer chip returns a clear send signal. Bus transmission protocol: 4 bits of data are transmitted per clock cycle, along with a data validity signal and a byte enable signal. The watchdog monitoring cycle is 50 nanoseconds, and the timeout threshold is 1 microsecond. Error log storage format: Includes a timestamp (32 bits), frame length (16 bits), and error code (8 bits), stored in a circular buffer.

[0149] Parallel processing of frame validity checks: The length checker, media access control address matcher, and virtual LAN verifier operate simultaneously. The length checker uses a 16-bit comparator with a lower limit of 64 and an upper limit of 1526. The media access control address matcher is a content-addressable memory (MAP) storing eight 64-bit address templates. The virtual LAN verifier is a 4-bit range comparator with a lower limit of 4096 and an upper limit of 4100. The phase error detector in the clock data recovery circuit uses a Hogge structure, with a sampling clock frequency of 200 MHz.

[0150] Bit error rate monitoring of the data pass-through path: Test codes are inserted between frame transmission intervals, and the receiver performs bit error statistics. A channel performance alarm is triggered when the bit error rate exceeds 10⁻⁹ per second. Electrical isolation of the pass-through channel: A pulse transformer is used, with a primary and secondary side insulation withstand voltage of 4000V AC. Transmission path length matching: The difference in trace length between the receiver and transmitter is controlled within 0.1 mm, and the delay difference is less than 1 picosecond. Impedance continuity guarantee: The characteristic impedance of the printed circuit board traces is maintained at 50 ohms, with a deviation not exceeding ±5%.

[0151] Status indicator lights control during transparent transmission: a green LED illuminates during transmission, a blue LED illuminates during reception, and a red LED flashes in case of an error. Channel self-test function: A 512-byte pseudo-random code is automatically sent upon power-up, and the receiving end performs cyclic redundancy check verification. Maintenance interface: Error statistics register is read via the joint test action group interface. Hot-swap protection: The interface circuit integrates a transient voltage suppression diode with a response time of less than 1 nanosecond. Electrostatic discharge protection meets the 8 kV contact discharge standard.

[0152] Data bus interlock signal timeout handling: When a request to transmit signal remains valid for more than 5 microseconds, the transmit physical layer chip is forcibly reset. The watchdog reset action includes: shutting down the transmit driver for 500 nanoseconds and clearing all status registers. The shielding layer of the industrial-grade RJ45 socket is grounded at a single point through a 1 megohm resistor to suppress common-mode interference. The cyclic redundancy check (CRC) calculation unit is set in parallel with the transparent transmission channel for self-testing without affecting the data transmission path.

[0153] Real-time monitoring metrics for pass-through performance: Successful pass-through frames per second, maximum frame delay, and minimum frame interval are counted. Performance data is output to the maintenance terminal via an independent serial port. Channel fault switching strategy: When three consecutive frames fail to transmit, automatic switching to the backup physical port (port number + 1) occurs. The backup port initialization time is controlled within 100 microseconds. All configuration parameters are stored using triple-modular redundancy storage units, with a single-event upset tolerance of 10^-13 error rate. The operating temperature range of the pass-through channel is -40°C to 85°C, and temperature adaptation is achieved through real-time adjustment of the bias current using on-chip sensors.

[0154] The absolute value of the instantaneous rate of change of voltage at the grid connection point is monitored. This value is derived from the absolute value of the voltage difference between adjacent sampling points calculated in step S1, divided by the sampling interval, which is fixed at 100 microseconds (corresponding to a 10 kHz sampling rate). A sliding window mechanism is used during monitoring, with a window length of 10 sampling points. The rate of change value is updated once for each new sampling point. The hardware implementation includes two parallel calculation units: Unit A calculates the absolute value of the difference between the current sampling point's voltage value and the previous point's voltage value; Unit B divides the absolute value of the difference by the sampling interval of 100 microseconds, outputting the absolute value of the instantaneous rate of change per second in per-unit values. The output value is stored in a 32-bit floating-point register, and its update cycle is strictly synchronized with the rising edge of the sampling clock. Data validity verification: When the voltage value exceeds the rated voltage range by ±20%, the output is frozen, and an invalid status bit is marked.

[0155] When the absolute value of the instantaneous rate of change is continuously lower than a preset threshold for a preset duration, a buffer recovery command is generated. The preset threshold is set to 0.01 per unit per second, determined by the 95th percentile of the rate of change distribution during the steady-state operation of the power grid. The default preset duration is 1000 milliseconds, configurable from 100 to 5000 milliseconds. The continuous judgment logic is implemented using a 16-bit decrementing counter. The initial value is equal to the preset duration / sampling interval (e.g., 1000 milliseconds / 100 microseconds = 10000). When the absolute value of the instantaneous rate of change is lower than the preset threshold, the counter decrements by 1 in each sampling period; when the absolute value of the instantaneous rate of change is higher than the preset threshold, the counter immediately resets to its initial value. When the counter decrements to 0, a buffer recovery command is triggered, which is a high-level pulse with a width of 50 microseconds. Counter overflow protection: If the initial value exceeds 65535, it automatically switches to frequency division counting mode.

[0156] The data buffer write function of the protocol converter is re-enabled based on the cache recovery instruction: the cache recovery instruction is connected to bit 0 (write enable bit) of the protocol converter's control register. Specific operation procedures: 1) On the rising edge of the instruction, the frozen state of the data acquisition module's output enable register is released (the register value is set to 1); 2) The write pointer movement function is restored, and the write pointer increments from the frozen position; 3) The transmission channel from the first-in-first-out queue to the data buffer is activated. Timing control is enabled: the operation is performed with a delay of 2 sampling cycles after the rising edge of the instruction to avoid the synchronization cycle of the data acquisition module. Data redirection mechanism: data temporarily stored in the first-in-first-out queue is transferred to the data buffer according to the first-in-first-out principle, with the transfer rate consistent with the acquisition rate. Confirmation mechanism is enabled: when the write pointer moves successfully, the operation completion status code 0x55 is returned.

[0157] The data caching mechanism of the recovery protocol converter performs normal caching operations on device status information. Normal caching operations consist of three parallel processes: 1) The effective voltage value, effective current value, and active power value are written to a designated address segment in the cache at fixed intervals (e.g., voltage values ​​are updated every 10 milliseconds); 2) The write pointer automatically cyclically overwrites the data, jumping to the base address 0x00000 when it reaches the end address 0xFFFFF of the cache; 3) The data checksum is calculated and reactivated in real time, updating once every 256 bytes written. Cache recovery flag setting: Bit 7 is set in the cache management status register; this flag is queried by subsequent data transmission modules. Recovery completion verification: The write pointer movement status is continuously monitored for 10 sampling cycles; if it increments normally throughout, a recovery success signal is output.

[0158] Dynamic adjustment strategy for preset thresholds: Automatically collects change rate data every 24 hours, recalculates the 95th percentile, and updates the stored threshold value. Temperature compensation for preset duration: Adjusts the duration value based on ambient temperature sensor readings; reduces the duration by 5% for every 10 degrees Celsius increase in temperature. Initial value calculation unit for decrementing counter: Includes a 32-bit divider; the dividend is the preset duration in milliseconds multiplied by 1000 (converted to microseconds), and the divisor is the sampling interval of 100 microseconds; the quotient is truncated. First-in-first-out queue transfer control: A dedicated direct memory access channel is provided; the channel burst transmission length is fixed at 16 bytes, and bus occupancy has the highest priority.

[0159] Data buffer address management: The write pointer uses a 32-bit circular counter, the actual buffer size is 1 megabyte, and the address range is 0x00000 to 0xFFFFF. The checksum calculation algorithm uses a 32-bit cyclic redundancy check, with a polynomial of 0x04C11DB7. Electrical characteristics of the successful recovery signal: 3.3V high level, 10mA drive capability, duration 100ms. Clearing condition for invalid status bits: Automatically cleared when the voltage value returns to within ±10% of the rated range for 1ms. Sampling clock synchronization guarantee: A phase-locked loop is used to track the power grid frequency, with a synchronization error of less than 0.1 degree phase angle.

[0160] Interlocking logic for cache recovery instructions: When the real-time streaming channel is active (step S6), cache recovery instructions are automatically disabled. Emergency clearing mechanism for the FIFO queue: If data stored in the queue remains unprocessed for more than 100 milliseconds, a forced clear is initiated. Boundary handling for write pointer loop jumps: After writing to address 0xFFFFF, the next address is automatically reset to 0x00000 and the address wraparound flag is set. Checksum update timing: Calculation is triggered when the write pointer moves to an address that is an integer multiple of 256 bytes. Temperature compensation coefficients are stored in electrically erasable programmable read-only memory, with each byte corresponding to a compensation value of 1 degree Celsius.

[0161] Data filtering for dynamic threshold updates: Only data with a change rate between 40% and 60% of the grid load rate are selected for statistical analysis. Frequency division coefficient calculation in frequency division counting mode: The quotient of the initial value divided by 65535 is used as the pre-division value, and the remainder is used as the final count value. Setting bit 0 of the control register: Completed by a write-1 instruction, which requires two consecutive writes of the 0xA5 acknowledgment code to prevent accidental operation. Data redirection rate matching: The transmission channel clock frequency is from the same source as the data acquisition clock, and the phase difference is controlled within 90 degrees. Automatic clearing of the address wraparound flag: Cleared immediately upon the next write pointer movement.

[0162] Anomaly monitoring during recovery: When five consecutive write operations fail, a write error interrupt is triggered, and the system reverts to a frozen state. Invalid status flag propagation path: A pause command is sent to the data acquisition module simultaneously with setting the status register. Real-time streaming channel status detection: This is determined by querying the transmit queue occupancy flag on the media access controller. Forced clear operation execution time: Clearing the queue of 10 data sets takes no more than 20 microseconds. Dynamic threshold update effectiveness delay: New thresholds are automatically enabled at 00:00 the following day to avoid switching during operation.

[0163] Bit definitions for the buffer management status register: Bit 0 write enable, Bit 1 read enable, Bit 7 buffer restore flag. Write error interrupt service routine: Records the error address and data type, attempts to write three times, then abandons. Sampling clock synchronization fault detection: Switches to the local crystal oscillator when synchronization is lost for 100 consecutive cycles. Temperature reading cycle: Reads the temperature sensor value every 10 seconds via the serial bus. Compensation value lookup method: Divides the temperature value by 10 and rounds down to the nearest integer as the index address, then reads the corresponding compensation coefficient. Response time for data acquisition pause command: Takes effect at the start of the next acquisition cycle, with a delay of less than 100 microseconds.

[0164] Feedback path for successful recovery signal: connected to the driver circuit of the status indicator light, and simultaneously uploaded to the power grid dispatching system. Hardware acceleration for cyclic redundancy check calculation: employs a 32-bit linear feedback shift register, processing 1 byte of data per clock cycle. Purpose of address wraparound flag: adds a special field to the data transmission protocol to identify data block boundaries. Write operation failure criterion: write response signal fails to return within 1 microsecond timeout. Data storage area for dynamic threshold updates: allocated independent storage pages, physically isolated from the running threshold. Frequency division coefficient register width: 16-bit prescaler value, 16-bit final count value. Control register write protection: locks write operation permissions during real-time streaming channel activation.

[0165] All calculations involved in the embodiments are dimensionless numerical calculations, and the preset parameters and thresholds in the calculations are set by those skilled in the art according to the actual situation.

[0166] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0167] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and inventive constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0168] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0169] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0170] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0171] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A data interaction adaptive method of a photovoltaic protocol converter, characterized in that, Includes the following steps: S1. Monitor the grid connection point voltage in real time, calculate the instantaneous rate of change of the grid connection point voltage and compare it with a preset threshold in real time; S2. When the instantaneous rate of change exceeds the preset threshold, the phase of the grid connection point current is synchronously collected to generate the direction of the phase difference between the grid connection point voltage and the grid connection point current phase. S3. Extract the high-frequency components of the grid connection point voltage, analyze the frequency band energy distribution of the high-frequency components through wavelet packet decomposition, and obtain the Shannon entropy value that characterizes the energy concentration. S4. When the direction of phase difference change conforms to the preset characteristics of power grid short circuit fault and the Shannon entropy value is lower than the preset entropy threshold, it is determined that the current event is a power grid transient event. S5. When the current event is a power grid transient, immediately stop the data caching mechanism of the protocol converter and activate the real-time streaming transmission channel; S6. The emergency control commands issued by the power grid dispatch system are directly forwarded to the photovoltaic inverter through the real-time streaming transmission channel; S7. When the instantaneous rate of change remains below the preset threshold for a preset duration, restore the data caching mechanism of the protocol converter.

2. The data interaction adaptive method for a photovoltaic protocol converter according to claim 1, characterized in that, Real-time monitoring of the grid connection point voltage, calculation of the instantaneous rate of change of the grid connection point voltage and real-time comparison with a preset threshold, including: Continuously collect instantaneous voltage values ​​at the grid connection point; The instantaneous rate of change is calculated based on the difference between adjacent sampling points of the instantaneous voltage at the grid connection point; The instantaneous rate of change is compared with a preset threshold in real time; When the absolute value of the instantaneous rate of change continues to exceed a preset threshold for a preset time, a flag signal for the current phase at the grid connection point is generated to trigger synchronous acquisition.

3. The data interaction adaptive method for a photovoltaic protocol converter according to claim 2, characterized in that, When the instantaneous rate of change exceeds a preset threshold, the phase of the grid connection point current is synchronously acquired to generate the direction of the phase difference between the grid connection point voltage and the grid connection point current phase, including: Based on the flag signal, the voltage phase sequence and current phase sequence at the grid connection point are simultaneously acquired within the first power frequency cycle after the fault occurs. Calculate the instantaneous phase difference between the grid connection point voltage phase and the grid connection point current phase at each sampling time; Trend fitting is performed on the instantaneous phase difference values ​​at multiple consecutive sampling times; The slope value of the trend fitting result is used as the direction of phase difference change.

4. The data interaction adaptive method for a photovoltaic protocol converter according to claim 1, characterized in that, High-frequency components of the grid connection point voltage are extracted, and the frequency band energy distribution of these components is analyzed through wavelet packet decomposition to obtain the Shannon entropy value, which characterizes the energy concentration. This includes: The voltage waveform at the grid connection point within a preset time after the fault determination time is extracted as the signal to be analyzed. Wavelet packet decomposition is performed on the signal to be analyzed to obtain multiple sub-frequency band signals; Calculate the energy value of each sub-band signal; Calculate the frequency band energy distribution based on energy values; Input the frequency band energy distribution into the Shannon entropy formula, and output the Shannon entropy value that characterizes the energy concentration.

5. The data interaction adaptive method for a photovoltaic protocol converter according to claim 1, characterized in that, When the direction of phase difference change conforms to the preset characteristics of a power grid short-circuit fault and the Shannon entropy value is lower than the preset entropy threshold, the current event is determined to be a power grid transient event, including: The direction of phase difference change is matched with a preset power grid short-circuit fault feature library for pattern matching. At the same time, the Shannon entropy value is compared with the preset entropy threshold. When the direction of phase difference change matches the preset characteristics of power grid short-circuit fault and the Shannon entropy value is less than the preset entropy threshold, a power grid transient event judgment signal is generated.

6. The data interaction adaptive method for a photovoltaic protocol converter according to claim 5, characterized in that, The power grid transient event determination signal is used to trigger the data buffering mechanism of the interrupt protocol converter.

7. The data interaction adaptive method for a photovoltaic protocol converter according to claim 5, characterized in that, When a power grid transient event occurs, immediately suspend the protocol converter's data caching mechanism and activate the real-time streaming channel, including: Receive power grid transient event determination signals; Stop writing newly acquired device status information to the data buffer of the protocol converter; Clear any unsent data from the protocol converter's data buffer. Establish a real-time streaming channel independent of the caching mechanism at the communication link layer of the protocol converter.

8. The data interaction adaptive method for a photovoltaic protocol converter according to claim 7, characterized in that, The real-time streaming transmission channel is used to transmit emergency control commands issued by the power grid dispatching system.

9. The data interaction adaptive method for a photovoltaic protocol converter according to claim 1, characterized in that, Emergency control commands issued by the power grid dispatch system are directly forwarded to the photovoltaic inverter via a real-time streaming transmission channel, including: Receive raw data stream of emergency control commands issued by the power grid dispatching system through the real-time streaming channel; The protocol encapsulation format of the original data stream of the emergency control command remains unchanged; The raw data stream of emergency control commands is transmitted through the communication interface of the photovoltaic inverter. No protocol parsing or data caching is performed during the pass-through process.

10. The data interaction adaptive method for a photovoltaic protocol converter according to claim 1, characterized in that, When the instantaneous rate of change remains below a preset threshold for a preset duration, the data caching mechanism of the protocol converter is restored, including: Monitor the absolute value of the instantaneous rate of change of voltage at the grid connection point; When the absolute value of the instantaneous rate of change is continuously lower than a preset threshold for a preset duration, a cache recovery instruction is generated; Re-enable the data buffer write function of the protocol converter according to the cache recovery command; The data caching mechanism of the recovery protocol converter performs normal caching operations on device status information.

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