A power transistor device and electronic equipment

Abstract

This invention provides a power transistor device and an electronic device. The device includes: a first metal electrode layer; a substrate disposed on the first metal electrode layer; an epitaxial layer disposed on the substrate, wherein alternating first and second body regions are disposed within the epitaxial layer; a third body region disposed above the first body region and containing heavily doped regions; a trench gate disposed between adjacent first and second body regions and in contact with the interface of the third body region; a planar gate located above the second body region, with its two ends respectively connected to two adjacent trench gates; an insulating dielectric layer disposed on the epitaxial layer; and a second metal electrode layer disposed on the insulating dielectric layer. The size of the injection window of the second body region and the length of the planar gate are adjustable. This device increases the area of ​​the gate oxide layer by using a planar gate, thereby increasing the capacitance between the gate and drain terminals and reducing noise and EMI problems generated during switching operation.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a power transistor device and an electronic device. Background Technology

[0002] To improve the breakdown voltage of traditional power devices, it is necessary to continuously reduce the doping concentration of the drift region while increasing the thickness of the drift region. This leads to a sharp increase in the on-resistance of the device, thereby increasing the system power consumption. Superjunction power devices, by using an alternating arrangement of N-type and P-type regions in the drift region to achieve charge balance, have greatly improved the relationship between the on-resistance and breakdown voltage of the device, and are receiving increasing attention.

[0003] Meanwhile, in the off-state, as the drain voltage increases, the N-type and P-type regions of a superjunction power device are rapidly depleted within a short time. The capacitances at the gate-drain and drain-source terminals also decrease rapidly, causing a drastic change in dv / dt at the drain, meaning the drain voltage rises rapidly in a short period. Because of these characteristics, compared to traditional planar power devices, superjunction power devices offer the advantage of higher operating frequencies in switching applications, but they also generate significant voltage and current noise.

[0004] To address the aforementioned problems, it is necessary to propose a power transistor device and electronic device that is reasonably designed and effectively solves these problems. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a power transistor device and an electronic device.

[0006] One aspect of the present invention provides a power transistor device, comprising:

[0007] First metal electrode layer;

[0008] A substrate is disposed on the first metal electrode layer;

[0009] An epitaxial layer is disposed on the substrate, wherein a plurality of first body regions and a plurality of second body regions are disposed therein, which are spaced and alternately distributed;

[0010] Multiple third body regions are disposed above the multiple first body regions, and each third body region contains a heavily doped region;

[0011] Multiple trench gates are disposed between adjacent first and second body regions and are in contact with the interface of the third body region;

[0012] Multiple planar gates are located above the second body region, and the two ends of each planar gate are respectively connected to two adjacent trench gates;

[0013] An insulating dielectric layer is disposed on the epitaxial layer and covers the first body region, the second body region, the third body region, the trench gate, and the planar gate;

[0014] A second metal electrode layer is disposed on the insulating dielectric layer;

[0015] Multiple conductive vias pass through the insulating dielectric layer and are respectively connected to the second metal electrode layer and the third body region; the heavily doped regions are in contact with the conductive vias and the trench gate interface, respectively; wherein...

[0016] The size of the injection window in the second body region and the length of the planar gate are adjustable.

[0017] Optionally, the plurality of first body regions are in a non-floating state, while the plurality of second body regions are in a floating state.

[0018] Optionally, the planar gate connects two adjacent trench gates.

[0019] Optionally, the planar gate includes a first sub-gate and a second sub-gate;

[0020] The first end of the first sub-gate is connected to an adjacent trench gate, and the first end of the second sub-gate is connected to another adjacent trench gate;

[0021] There is a preset distance between the second end of the first sub-gate and the second end of the second sub-gate.

[0022] Optionally, the injection window size of the first body region is the same as the injection window size of the second body region.

[0023] Optionally, the injection window size of the first body region is different from the injection window size of the second body region.

[0024] Optionally, the trench gate includes a trench, a gate oxide layer disposed on the inner wall of the trench, and polysilicon filling the trench.

[0025] Optionally, the substrate, the epitaxial layer, and the heavily doped region all have a first conductivity type.

[0026] Optionally, the first body region, the second body region, and the third body region all have a second conductivity type.

[0027] Another aspect of the present invention provides an electronic device comprising at least a portion of an integrated circuit formed from the power transistor devices described above.

[0028] The present invention relates to a power transistor device and an electronic device, wherein the second body region of the power transistor device is not connected to the second metal electrode layer through a conductive via, so that the second body region is in a floating potential state, thereby increasing the capacitance between the gate and drain ends of the device. Multiple planar gates are located above the second body region, and the two ends of the planar gates are respectively connected to two adjacent trench gates, increasing the area of ​​the gate oxide layer covering the gate, further increasing the capacitance between the gate and drain ends of the device, increasing the parasitic capacitance value of the device, and thus reducing the noise and EMI problems generated by the device during switching operation. The injection window size of the second body region and the length of the planar gates are adjustable, which can effectively adjust the parasitic gate-drain capacitance. This power transistor device does not require additional production costs and is easy to implement. Attached Figure Description

[0029] Figure 1 This is a top view schematic diagram of a power transistor device according to the present invention;

[0030] Figure 2 This is a schematic diagram of the structure of a power transistor device according to an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of a power transistor device according to another embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of the structure of a power transistor device according to another embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of the structure of a power transistor device according to another embodiment of the present invention;

[0034] Figure 6 This is a schematic diagram of the structure of a power transistor device according to another embodiment of the present invention;

[0035] Figure 7 This is a schematic diagram of the structure of a power transistor device according to another embodiment of the present invention. Detailed Implementation

[0036] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] The power transistor device of the present invention (e.g., a power transistor having a superjunction structure) can be formed on a semiconductor substrate, which can be divided into a cell region, a transition region, and a termination structure region in the lateral direction (parallel to the surface of the substrate). The cell region is located in the central region of the semiconductor substrate, and a MOS structure is formed within the cell region. The termination structure region is located in the peripheral region of the semiconductor substrate and surrounds the cell region. The transition region is formed between the cell region and the termination structure region. Figure 1 As shown, the dashed box marks the extent of the cell region, which is located at the center of the device and is covered by a metal electrode 10' and a polysilicon gate 8'. A transition region and a termination structure region are formed around the cell region. Multiple polysilicon strips 8a' are formed at intervals in the termination structure region, and the polysilicon strips 8a' are formed in a ring around the cell region.

[0038] like Figures 2 to 7 As shown, one aspect of the present invention provides a power transistor device, including a first metal electrode layer 1, a substrate 2, an epitaxial layer 3, a plurality of first body regions 4a, a plurality of second body regions 4b, a plurality of third body regions 5, a plurality of trench gates, a plurality of planar gates 8a, a heavily doped region 9, an insulating dielectric layer 10, a plurality of conductive vias 11, and a second metal electrode layer 12.

[0039] The first metal electrode layer 1 is a back metal electrode layer used to connect external circuits; the second metal electrode layer 12 is a front metal electrode layer used to connect the source and the gate.

[0040] The substrate 2 is disposed on the first metal electrode layer 1. The substrate 2 can serve as the basic support for the entire device.

[0041] An epitaxial layer 3 is disposed on a substrate 2, wherein a plurality of first body regions 4a and a plurality of second body regions 4b are disposed therein in an alternating manner. Specifically, as shown in the figure, the plurality of first body regions 4a and the plurality of second body regions 4b are arranged on the epitaxial layer 3 in an alternating manner of first body region 4a, second body region 4b, first body region 4a, second body region 4b, and so on.

[0042] Multiple third body regions 5 are disposed above multiple first body regions 4a, and a heavily doped region 9 is disposed within the third body region 5 for forming source contacts.

[0043] Multiple trench gates are disposed between adjacent first body region 4a and second body region 4b, and are in contact with the interface of third body region 5.

[0044] Multiple planar gates 8a are located above the second body region 4b, and the two ends of the planar gates 8a are respectively connected to two adjacent trench gates.

[0045] An insulating dielectric layer 10 is disposed on the epitaxial layer 3 and covers the first body region 4a, the second body region 4b, the third body region 5, the trench gate, and the planar gate 8a.

[0046] The second metal electrode layer 12 is disposed on the insulating dielectric layer 10.

[0047] Multiple conductive vias 11 pass through the insulating dielectric layer 10 and are respectively connected to the second metal electrode layer 12 and the third body region 5. The heavily doped region 9 is in contact with the conductive vias 11 and the trench gate interface. Specifically, the multiple conductive vias 11 extend upward from multiple corresponding third body regions 5, pass through the insulating dielectric layer 10, and reach the second metal electrode layer 12.

[0048] The size of the injection window in the second body region 4b and the length of the planar gate 8a are adjustable. Specifically, the width and depth of the second body region 4b can be adjusted to effectively regulate the parasitic gate-drain capacitance; in addition, the length of the planar gate 8a can also be adjusted to further effectively regulate the parasitic gate-drain capacitance.

[0049] Specifically, multiple third body regions 5 are disposed above multiple first body regions 4a, and multiple conductive vias 11 pass through the insulating dielectric layer 10 and are respectively connected to the second metal electrode layer 12 and the third body regions 5, so that the first body regions 4a are in a non-potential floating state; the second body region 4b is not connected to the second metal electrode layer 12 through the conductive vias 11, so that the second body region 4b is in a potential floating state. That is to say, the first body region 4a is connected to the second metal electrode layer 12, and the second body region 4b is not connected to the second metal electrode layer 12.

[0050] The power transistor device of the present invention has a second body region that is not connected to the second metal electrode layer through a conductive via, thereby placing the second body region in a floating potential state and increasing the capacitance between the gate and drain ends of the device. Multiple planar gates are located above the second body region, and each end of the planar gate is connected to two adjacent trench gates, increasing the area of ​​the gate oxide layer covering the gate and further increasing the capacitance between the gate and drain ends of the device. This increases the parasitic capacitance value of the device, thereby reducing noise and EMI problems generated during switching operation. The injection window size of the second body region and the length of the planar gates are adjustable, effectively regulating the parasitic gate-drain capacitance. This power transistor device requires no additional production costs and is easy to implement.

[0051] For example, in this embodiment, such as Figures 2 to 7 As shown, multiple first body regions 4a are in a non-floating state, and multiple second body regions 4b are in a floating state.

[0052] In this embodiment, the second body region is in a floating potential state, thereby increasing the capacitance between the gate and drain terminals of the device, and thus reducing the noise and EMI problems generated by the device during switching operation.

[0053] For example, such as Figures 2 to 7 As shown, in this embodiment, the trench gate includes a trench 6 disposed on the epitaxial layer 3, a gate oxide layer 7 disposed on the inner wall of the trench 6, and polysilicon 8 filling the trench 6.

[0054] For example, such as Figure 2 , Figure 4 and Figure 6 As shown, in one embodiment, the planar gate 8a connects two adjacent trench gates, that is, the length of the planar gate 8a is the distance between two adjacent trench gates.

[0055] In this embodiment, the area of ​​the gate oxide layer 7 is increased by connecting two adjacent trench gates through the planar gate 8a, which further improves the capacitance between the gate and drain ends of the device.

[0056] For example, such as Figure 3 , Figure 5 and Figure 7 As shown, in another embodiment, the planar gate 8a includes a first sub-gate 8a1 and a second sub-gate 8a2. A first end of the first sub-gate 8a1 is connected to one of the adjacent trench gates, and a first end of the second sub-gate 8a2 is connected to the other adjacent trench gate. A predetermined spacing exists between the second ends of the first sub-gate 8a1 and the second ends of the second sub-gate 8a2. That is, the planar gate 8a is discontinuously distributed, and the total length of the planar gate 8a is less than the distance between two adjacent trench gates.

[0057] It should be noted that the preset spacing between the second end of the first sub-gate 8a1 and the second end of the second sub-gate 8a2 can be adjusted according to actual needs, thereby adjusting the length of the entire planar gate 8a to effectively adjust the size of the parasitic gate-drain capacitance.

[0058] For example, the injection window size of the first body region 4a is the same as the injection window size of the second body region 4b. Specifically, the width of the first body region 4a can be the same as the width of the second body region 4b, and the injection depth of the first body region 4a can be the same as the injection depth of the second body region 4b.

[0059] For example, the injection window size of the first body region 4a is different from the injection window size of the second body region 4b. That is, the injection width of the first body region 4a can be different from the injection width of the second body region 4b, and the injection depth of the first body region 4a can be different from the injection depth of the second body region 4b.

[0060] In this embodiment, the size of the injection window in the second body region 4b is adjustable. That is, the injection width and injection depth of the second body region 4b are adjustable, thereby effectively adjusting the parasitic gate-drain capacitance.

[0061] For example, in this embodiment, the substrate 2, the epitaxial layer 3, and the heavily doped region 9 all have a first conductivity type. The first conductivity type can be an N-type semiconductor layer.

[0062] For example, in this embodiment, the first body region 4a, the second body region 4b, and the third body region 5 all have a second conductivity type. The second conductivity type can be a P-type semiconductor.

[0063] The specific structure of the power transistor device of the present invention will be described below through several specific embodiments.

[0064] like Figure 2 As shown, in one embodiment, the planar gate 8a is not disconnected, and the planar gate 8a connects two adjacent trench gates. The implantation width and implantation depth of the second body region 4b are the same as those of the first body region 4a.

[0065] like Figure 3 As shown, in another embodiment, the planar gate 8a is disconnected. The planar gate 8a includes a first sub-gate 8a1 and a second sub-gate 8a2, with a preset spacing between the first sub-gate 8a1 and the second sub-gate 8a2. The injection width and injection depth of the second body region 4b are the same as those of the first body region 4a.

[0066] like Figure 4 As shown, in another embodiment, the planar gate 8a is not disconnected, and the planar gate 8a connects two adjacent trench gates. The implantation depth of the second body region 4b is the same as the implantation depth of the first body region 4a, and the implantation width of the second body region 4b is smaller than the implantation width of the first body region 4a.

[0067] like Figure 5 As shown, in another embodiment, the planar gate 8a is disconnected. The planar gate 8a includes a first sub-gate 8a1 and a second sub-gate 8a2, with a preset spacing between the first sub-gate 8a1 and the second sub-gate 8a2. The implantation depth of the second body region 4b is the same as the implantation depth of the first body region 4a, and the implantation width of the second body region 4b is smaller than the implantation width of the first body region 4a.

[0068] like Figure 6 As shown, in another embodiment, the planar gate 8a is not disconnected, and the planar gate 8a connects two adjacent trench gates. The injection width of the second body region 4b is the same as the injection width of the first body region 4a, and the injection depth of the second body region 4b is different from the injection depth of the first body region 4a.

[0069] like Figure 7 As shown, in another embodiment, the planar gate 8a is disconnected. The planar gate 8a includes a first sub-gate 8a1 and a second sub-gate 8a2, with a preset spacing between the first sub-gate 8a1 and the second sub-gate 8a2. The injection width of the second body region 4b is the same as the injection width of the first body region 4a, but the injection depth of the second body region 4b is different from the injection depth of the first body region 4a.

[0070] It should be noted that the specific structure of the power transistor device is not limited to the above embodiment. The length of the planar gate 8a and the injection width and injection depth of the second body region 4b can be selected according to actual needs, and the present invention does not impose specific limitations.

[0071] Another aspect of the present invention provides an electronic device comprising at least a portion of an integrated circuit formed from the power transistor device described above. The specific structural features of the power transistor device have been described in detail above and will not be repeated here.

[0072] The power transistor device with a superjunction structure according to the present invention can be applied to various electronic devices. For example, by integrating multiple such power transistor devices and other devices (e.g., other forms of transistors, etc.), an integrated circuit (IC) can be formed, thereby constructing an electronic device. The electronic device may also include components such as a display screen that works with the integrated circuit and a wireless transceiver that works with the integrated circuit. Examples of such electronic devices include smartphones, computers, tablet computers (PCs), artificial intelligence devices, wearable devices, and power banks.

[0073] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A power transistor device, characterized in that, include: First metal electrode layer; A substrate is disposed on the first metal electrode layer; An epitaxial layer is disposed on the substrate, wherein a plurality of first body regions and a plurality of second body regions are disposed therein, which are spaced and alternately distributed; Multiple third body regions are disposed above the multiple first body regions, and each third body region contains a heavily doped region; Multiple trench gates are disposed between adjacent first and second body regions and are in contact with the interface of the third body region; Multiple planar gates are located above the second body region, and the two ends of each planar gate are respectively connected to two adjacent trench gates; An insulating dielectric layer is disposed on the epitaxial layer and covers the first body region, the second body region, the third body region, the trench gate, and the planar gate; A second metal electrode layer is disposed on the insulating dielectric layer; Multiple conductive vias pass through the insulating dielectric layer and are respectively connected to the second metal electrode layer and the third body region; the heavily doped regions are in contact with the conductive vias and the trench gate interface, respectively; wherein... The size of the injection window in the second body region and the length of the planar gate are adjustable.

2. The power transistor device according to claim 1, characterized in that, The plurality of first body regions are in a non-floating state, and the plurality of second body regions are in a floating state.

3. The power transistor device according to claim 1, characterized in that, The planar gate connects two adjacent trench gates.

4. The power transistor device according to claim 1, characterized in that, The planar gate includes a first sub-gate and a second sub-gate; The first end of the first sub-gate is connected to an adjacent trench gate, and the first end of the second sub-gate is connected to another adjacent trench gate; There is a preset distance between the second end of the first sub-gate and the second end of the second sub-gate.

5. The power transistor device according to any one of claims 1 to 4, characterized in that, The injection window size of the first body region is the same as the injection window size of the second body region.

6. The power transistor device according to any one of claims 1 to 4, characterized in that, The injection window size of the first body region is different from that of the second body region.

7. The power transistor device according to any one of claims 1 to 4, characterized in that, The trench gate includes a trench, a gate oxide layer disposed on the inner wall of the trench, and polysilicon filling the trench.

8. The power transistor device according to any one of claims 1 to 4, characterized in that, The substrate, the epitaxial layer, and the heavily doped region all have a first conductivity type.

9. The power transistor device according to any one of claims 1 to 4, characterized in that, The first body region, the second body region, and the third body region all have a second conductivity type.

10. An electronic device comprising at least a portion of an integrated circuit formed from a power transistor device as described in any one of claims 1 to 9.

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