Heterojunction cell, heterojunction cell preparation method and photovoltaic module

Abstract

The application provides a heterojunction cell, a heterojunction cell preparation method and a photovoltaic module, and relates to the technical field of solar cells. The heterojunction cell comprises a silicon substrate layer, the silicon substrate layer has a first surface and a second surface arranged oppositely, the first surface is a rough surface, the second surface is a polished surface, the rough surface and the polished surface are sequentially stacked with an intrinsic amorphous silicon layer, a doped layer and a transparent conductive layer, impurity Fe elements and Al elements exist in the rough surface and the polished surface, and the concentration ratio of Fe elements / Al elements in the rough surface is higher than that in the polished surface. In use, the surface of the polished surface is more smooth, which is beneficial to the subsequent deposition of the amorphous silicon film, impurity Fe elements and Al elements exist in the rough surface and the polished surface, the content of impurity elements in the polished surface is much lower than that in the rough surface, thereby the minority carrier lifetime is improved, and the passivation effect of the polished surface is better.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a heterojunction cell, a method for preparing a heterojunction cell, and a photovoltaic module. Background Technology

[0002] The photovoltaic industry is developing rapidly. With continuous improvements in traditional technologies and the development of new technologies, the conversion efficiency of solar cells is gradually increasing. Heterojunction solar cell technology has an iterative advantage over PERC solar cell technology. The current mainstream heterojunction solar cell manufacturing process involves texturing the original silicon wafer on both sides, followed by CVD amorphous silicon thin film deposition, TCO film deposition, and finally screen printing to form the solar cell. Although the process is simple and the cell has a high bifaciality, it is still far from achieving the theoretical conversion efficiency of heterojunction solar cells. Due to its structure, the core technology of heterojunction solar cells is CVD amorphous silicon thin film deposition. The quality of back passivation directly determines the Voc of the solar cell; a higher Voc makes it easier to improve conversion efficiency. The extremely high Voc is the biggest advantage of heterojunction solar cells compared to other solar cell technologies.

[0003] Existing heterojunction solar cells suffer from poor back passivation, resulting in poor cell conversion efficiency. Summary of the Invention

[0004] This invention provides a heterojunction solar cell, a method for preparing a heterojunction solar cell, and a photovoltaic module, which can improve the back passivation effect of the solar cell, thereby improving the conversion efficiency of the solar cell.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] An embodiment of the present invention provides a heterojunction solar cell, including a silicon substrate layer having a first surface and a second surface disposed opposite to each other, wherein the first surface is a textured surface and the second surface is a polished surface, wherein an intrinsic amorphous silicon layer, a doped layer and a transparent conductive layer are sequentially stacked on both the textured surface and the polished surface, wherein impurities Fe and Al elements are present in both the textured surface and the polished surface, and the Fe / Al element concentration in the textured surface is higher than that in the polished surface.

[0007] Optionally, the concentration of Fe in the velvet surface is 10 to 100 times higher than the concentration of Fe in the polished surface, and the concentration of Al in the velvet surface is 10 to 100 times higher than the concentration of Al in the polished surface.

[0008] Optionally, the concentration of Fe / Al elements in the velvet surface is 0.1ppb-1ppb.

[0009] Optionally, the concentration of Fe / Al elements in the polished surface is not greater than 0.1 ppb.

[0010] Optionally, the difference between the reflectivity of the velvet surface and the reflectivity of the polished surface is 7%-17%.

[0011] Optionally, the transparent conductive layer has metal grid lines on the surface away from the doped layer.

[0012] Embodiments of the present invention also provide a method for fabricating a heterojunction solar cell, the method comprising:

[0013] The silicon substrate layer is texturized on both sides.

[0014] A mask layer is prepared on the first surface of the silicon substrate;

[0015] The second surface of the silicon substrate is polished.

[0016] The silicon substrate layer is subjected to multiple gettering processes.

[0017] Optionally, the step of polishing the second surface of the silicon substrate layer further includes:

[0018] The polishing and etching thickness of the second surface is 2µm-6µm.

[0019] Optionally, the step of forming a mask layer on the first surface of the silicon substrate layer includes:

[0020] A mask layer with a thickness of 50nm-100nm was prepared on the first surface of the silicon substrate using a PECVD device.

[0021] Optionally, prior to the step of texturing the silicon substrate on both sides, the heterojunction solar cell fabrication method further includes:

[0022] The silicon substrate is polished on both sides and then subjected to gettering.

[0023] Optionally, the step of performing double-sided texturing on the silicon substrate layer includes:

[0024] The first and second surfaces of the silicon substrate are formed with a textured surface of a pyramid structure with a width of 0.05um-5um.

[0025] Embodiments of the present invention also provide a photovoltaic module, including the above-described heterojunction cell, or including a heterojunction cell prepared by the heterojunction cell preparation method.

[0026] The beneficial effects of the heterojunction solar cell, the heterojunction solar cell fabrication method, and the photovoltaic module of the present invention include, for example:

[0027] This heterojunction solar cell includes a silicon substrate layer with a first surface and a second surface disposed opposite to each other. The first surface is textured, and the second surface is polished. Both the textured and polished surfaces are sequentially stacked with an intrinsic amorphous silicon layer, a doped layer, and a transparent conductive layer. Both the textured and polished surfaces contain impurities of Fe and Al elements, with a higher Fe / Al concentration in the textured surface than in the polished surface. In use, the polished surface is smoother, which is beneficial for the subsequent deposition of the amorphous silicon thin film. The presence of Fe and Al impurities in both the textured and polished surfaces, with a significantly lower impurity content in the polished surface, improves the overall minority carrier lifetime and results in better passivation of the polished surface.

[0028] This heterojunction solar cell fabrication method includes double-sided texturing of a silicon substrate; fabrication of a mask layer on the first surface of the silicon substrate; polishing of the second surface of the silicon substrate; and multiple gettering processes on the silicon substrate. In practice, after double-sided texturing, a mask layer is fabricated on the first surface of the silicon substrate, and the second surface is polished to make it smoother, which is beneficial for subsequent deposition of amorphous silicon thin films. The smooth surface allows for more uniform film growth, thereby improving film quality and cell performance. Multiple gettering processes on both the first and second surfaces of the silicon substrate allow for more effective removal of impurities, further reducing the impurity concentration on the second surface, making it lower than that on the first surface. This improves the overall minority carrier lifetime and enhances the passivation effect of the second surface.

[0029] The photovoltaic module includes the aforementioned heterojunction cell, or a heterojunction cell prepared by the heterojunction cell preparation method. It possesses all the aforementioned beneficial effects. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a flowchart of the heterojunction solar cell fabrication method provided in this embodiment;

[0032] Figure 2 A comparison of the concentration of metal impurities on the front side of the silicon substrate before and after multiple repeated gettering processes;

[0033] Figure 3 A comparison of the concentration of metal impurities on the back side of the silicon substrate before and after multiple repeated gettering processes;

[0034] Figure 4 This is a schematic diagram of the heterojunction battery provided in this embodiment.

[0035] Icons: 10-Silicon substrate; 11-Textured surface; 12-Polished surface; 20-Intrinsic amorphous silicon layer; 30-Doped layer; 40-Transparent conductive layer; 50-Metal gate line. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0038] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0039] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0040] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0041] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0042] The photovoltaic industry is developing rapidly. With continuous improvements in traditional technologies and the development of new technologies, the conversion efficiency of solar cells is gradually increasing. Heterojunction solar cell technology has an iterative advantage over PERC solar cell technology. The current mainstream heterojunction solar cell manufacturing process involves texturing the original silicon wafer on both sides, followed by CVD amorphous silicon thin film deposition, TCO film deposition, and finally screen printing to form the solar cell. Although the process is simple and the cell has a high bifaciality, it is still far from achieving the theoretical conversion efficiency of heterojunction solar cells. Due to its structure, the core technology of heterojunction solar cells is CVD amorphous silicon thin film deposition. The quality of back passivation directly determines the Voc of the solar cell; a higher Voc makes it easier to improve conversion efficiency. The extremely high Voc is the biggest advantage of heterojunction solar cells compared to other solar cell technologies.

[0043] The heterojunction solar cells in related technologies suffer from poor back passivation, resulting in poor cell conversion efficiency.

[0044] Please refer to Figures 1-2 This embodiment provides a heterojunction cell, a method for preparing a heterojunction cell, and a photovoltaic module, which can effectively improve the technical problems mentioned above, improve the back passivation effect of the cell, and thus improve the conversion efficiency of the cell.

[0045] The method for fabricating this heterojunction solar cell includes:

[0046] S1: Polish both sides of the silicon substrate 10.

[0047] Specifically, a pre-cleaning solution is used to clean and polish both sides of the silicon substrate 10 to remove organic matter and metallic impurities from the surface of the silicon substrate 10. The pre-cleaning solution consists of 10%-18% hydrogen peroxide and 10%-15% alkaline solution. During the pre-cleaning process, the double-sided etching thickness of the silicon substrate 10 is 3µm-6µm.

[0048] In this embodiment, the concentration of hydrogen peroxide can be 10%, 12%, 15%, or 18%. The concentration of the alkaline solution can be 10%, 12%, or 15%. No specific limitation is made here.

[0049] In this embodiment, the double-sided etching thickness of the silicon substrate 10 during the pre-cleaning process can be 3µm, 5µm, or 6µm, and no specific limitation is made here.

[0050] S2: Phosphorus gettering is performed on both sides of the silicon substrate 10.

[0051] Specifically, a layer of phosphorus paste is coated on the surface of a silicon substrate 10. Then, using roller drive, the silicon substrate 10 is uniformly passed through multiple high-temperature chambers at a speed of 3-6 m / min, with temperatures ranging from 700℃ to 1000℃. At high temperatures, the phosphorus paste forms a phosphosilicate glass (PSG) layer on the surface of the silicon substrate 10, precipitating out metallic impurities within the silicon substrate 10. The concentration of phosphorus compounds in the phosphorus paste is 2%-12%. Two rollers are used, positioned opposite each other, both coated with phosphorus paste. The silicon substrate 10 is passed between the two rollers, thus achieving the coating of phosphorus paste onto its surface. The phosphorus-coated silicon substrate 10 passes through the multiple high-temperature chambers sequentially at a uniform speed, causing the phosphorus paste to form a phosphosilicate glass (PSG) layer on its surface, precipitating out metallic impurities within the silicon substrate 10 and reducing the amount of metallic impurities on its surface.

[0052] S3: Remove the phosphor silicate (PSG) glass layer.

[0053] Specifically, the silicon substrate 10 is subjected to a 10%-15% hydrofluoric acid solution to remove the phosphosilicate glass (PSG) layer, wherein the etching thickness of the silicon substrate 10 is 0.02µm-0.05µm. For example, it can be 0.02µm, 0.03µm or 0.05µm, and no specific limitation is made here.

[0054] S4: Perform double-sided texturing on the silicon substrate layer 10.

[0055] Specifically, a textured surface with a pyramid structure and a width of 0.05µm-5µm is formed on the first and second surfaces of the silicon substrate layer 10. The width of the textured surface with the pyramid structure can be 0.05µm, 1µm, 3µm or 5µm, and is not specifically limited here.

[0056] Understandably, the textured surface of the pyramid structure can reduce optical reflectivity, improve electrical performance, and enhance carrier collection efficiency.

[0057] It should be noted that, in this embodiment, the two surfaces disposed opposite to each other on the silicon substrate 10 are the first surface and the second surface, wherein the first surface is the front side and the second surface is the back side.

[0058] S5: Prepare a mask layer on the first surface of the silicon substrate 10.

[0059] Specifically, a mask layer with a thickness of 50nm-100nm is prepared on the first surface of the silicon substrate 10, i.e., the front side of the silicon substrate 10, using a PECVD device. For example, the thickness of the mask layer can be 50nm, 60nm, 80nm or 100nm, and no specific limitation is made here.

[0060] S6: Polish the second surface of the silicon substrate 10.

[0061] Specifically, the second surface of the silicon substrate 10, i.e. the back side of the silicon substrate 10, is polished using a mixture of an alkaline solution with a concentration of 1.10%-1.40% and a polishing aid additive with a concentration of 0.50%-0.80%.

[0062] It should be noted that in existing heterojunction solar cell fabrication technologies, after double-sided texturing of the silicon substrate 10, an amorphous silicon thin film is directly deposited. Because the textured surface of the silicon substrate 10 forms a pyramidal structure, meaning the surface is not smooth and is uneven, direct deposition of the amorphous silicon thin film leads to localized uneven film thickness, affecting passivation. Furthermore, the uneven surface of the silicon substrate 10 is also detrimental to the interception of long-wavelength light. Therefore, to address this technical problem, after double-sided texturing of the silicon substrate 10, the second surface of the silicon substrate 10, i.e., the back surface, is polished again. This makes the back surface of the silicon substrate 10 smooth, which is beneficial for subsequent amorphous silicon thin film deposition. The smooth surface allows for more uniform film growth, reduces defects and stress concentration in the film, thereby improving film quality and passivation, and ultimately enhancing the efficiency and stability of the solar cell.

[0063] In this embodiment, the polishing and etching thickness of the second surface is 2µm-6µm. Specifically, the polishing and etching thickness of the back side of the silicon substrate 10 can be 2µm, 3µm, 5µm or 6µm, and is not specifically limited here.

[0064] S7: Remove the mask layer from the first surface.

[0065] Specifically, the mask layer is removed by reacting a 9%-11% hydrofluoric acid solution at 18℃-30℃ for 200s-300s.

[0066] Furthermore, texturing both sides of the silicon substrate 10 followed by single-sided polishing of the back side of the silicon substrate 10 can more effectively remove impurities from the surface of the silicon substrate 10 and fix the impurities on the surface of the silicon substrate 10 in a specific position. Compared with the prior art, this reduces unnecessary impurity diffusion paths on the back side of the polished silicon substrate 10, making it easier for impurities to be absorbed during subsequent gettering. This creates a difference between the impurity concentration on the back side of the silicon substrate 10 and the impurity concentration on the front side of the silicon substrate 10, thereby increasing the efficiency improvement brought about by gettering.

[0067] S8: Perform multiple gettering operations on the silicon substrate 10.

[0068] Specifically, the silicon substrate 10 is subjected to phosphorus getter treatment using a phosphorus getter. The phosphorus getter treatment process is consistent with step S2, namely, a layer of phosphorus paste is coated on both sides of the silicon substrate 10, and the silicon substrate 10 is driven by rollers to pass through multiple high-temperature chambers at a speed of 3m / min-6m / min at a constant temperature of 700℃-1000℃. At high temperature, a PSG layer is formed on the surface of the silicon substrate 10 by the phosphorus paste, thereby condensing and precipitating out metallic impurities inside the silicon substrate 10. The concentration of phosphorus compounds in the phosphorus paste is 2%-12%.

[0069] Understandably, the specific temperatures of the multiple high-temperature chambers need to be set according to the different segregation coefficients of each metal, so that after the silicon substrate 10 passes through multiple high-temperature chambers in sequence, the aluminum, iron, zinc and copper metal impurities inside the silicon substrate 10 can be precipitated into the phosphosilicate glass layer.

[0070] It should also be noted that step S8 is repeated 2 to 5 times. That is, the front and back sides of the silicon substrate 10 are repeatedly gouged 2 to 5 times.

[0071] Furthermore, although a gettering process (step S2 in this embodiment) has been performed before the double-sided texturing of the silicon substrate 10, due to the quality of the silicon substrate 10, its internal metal impurity content is high and there are many defects. The gettering step before the double-sided texturing of the silicon substrate 10 cannot effectively solve the defect problems existing in the silicon substrate 10. Therefore, the heterojunction fabrication process provided in this embodiment performs a second and repeated gettering process on both sides of the silicon substrate 10 after the double-sided texturing to further reduce the metal impurity concentration of the silicon substrate 10.

[0072] In addition, during the phosphorus gettering process, the back side of the polished silicon substrate 10 can more precisely control the diffusion of phosphorus atoms, enabling them to better interact with impurities on the surface of the silicon substrate 10, thereby improving the gettering effect.

[0073] Please refer to Figures 2-3 , Figure 2 The diagram shows a comparison of the concentration of metal impurities on the front side of the silicon substrate 10 before and after repeated gettering processes. Figure 3 This image shows a comparison of the concentration of metal impurities on the back side of the silicon substrate 10 before and after multiple repeated gettering processes. Figure 2 and Figure 3As can be seen, after repeated gettering processes, the concentrations of metal impurities on both the front and back sides of the silicon substrate 10 decreased significantly. Furthermore, comparing the concentrations of various metal impurities on the front and back sides of the silicon substrate 10 yields Table 1, as detailed below:

[0074] Table 1

[0075]

[0076] As shown in Table 1, the Fe concentration on the back side of the silicon substrate 10 is 14.24% lower than that on the front side, and the Al concentration on the back side is 17.37% lower than that on the front side. The significant difference between the element concentrations on the back and front sides of the silicon substrate 10 allows for a more reasonable electric field distribution, improves carrier collection efficiency, enhances the overall minority carrier lifetime, and results in better passivation of the polished back side of the silicon substrate 10, thereby improving the cell conversion efficiency.

[0077] Furthermore, the lower Fe concentration on the back side of the polished silicon substrate 10 can reduce recombination and improve minority carrier lifetime, while the appropriate Fe concentration on the front side of the silicon substrate 10 helps to carry out other steps such as gettering and optimizes overall performance.

[0078] S9: Remove the phosphor silicate (PSG) glass layer.

[0079] Specifically, the silicon substrate 10 is subjected to a 10%-15% hydrofluoric acid solution to remove the phosphosilicate glass (PSG) layer, wherein the etching thickness of the silicon substrate 10 is 0.02µm-0.05µm. For example, it can be 0.02µm, 0.03µm or 0.05µm, and no specific limitation is made here.

[0080] S10: Rounding treatment is performed on the silicon substrate layer 10.

[0081] S11: Clean the silicon substrate layer 10.

[0082] S12: An intrinsic amorphous silicon layer 20 is prepared on both sides of the silicon substrate layer 10.

[0083] Specifically, an intrinsic amorphous silicon thin film is deposited on the front and back sides of the silicon substrate 10 using chemical vapor deposition technology.

[0084] S13: A P-type doped layer 30 is prepared on the front side of the silicon substrate 10, and an N-type doped layer 30 is prepared on the back side of the silicon substrate 10.

[0085] S14: A transparent conductive layer 40 is prepared on both sides of the silicon substrate 10.

[0086] Specifically, a TCO thin film is prepared on both sides of the silicon substrate 10 using physical vapor deposition. The TCO thin film can be an indium tin oxide thin film or a fluorine-doped tin oxide thin film.

[0087] S15: Screen printing.

[0088] Please refer to Figure 4 The present invention also provides a heterojunction solar cell, which is prepared by the above-described heterojunction solar cell preparation method. The heterojunction solar cell includes a silicon substrate 10, which has a first surface and a second surface disposed opposite to each other. The first surface is a textured surface 11, and the second surface is a polished surface 12. Both the textured surface 11 and the polished surface 12 are sequentially stacked with an intrinsic amorphous silicon layer 20, a doped layer 30, a transparent conductive layer 40, and metal grid lines 50. The metal grid lines 50 are disposed on the surface of the transparent conductive layer 40 away from the doped layer 30. The silicon substrate 10 has a first surface and a second surface disposed opposite to each other. The first surface is a textured surface 11 and the second surface is a polished surface 12. Both the textured surface 11 and the polished surface 12 contain impurities of Fe and Al elements. The concentration of Fe element in the textured surface 11 is 10 to 100 times higher than that in the polished surface 12, and the concentration of Al element in the textured surface 11 is 10 to 100 times higher than that in the polished surface 12. The difference in reflectivity between the textured surface 11 and the polished surface 12 is 7% to 17%.

[0089] Specifically, the concentration of Fe in the velvet surface 11 is 0.1 ppb-1 ppb, and the concentration of Al in the velvet surface 11 is 0.1 ppb-1 ppb. The concentrations of Fe and Al in the polished surface 12 are both no greater than 0.1 ppb.

[0090] In this embodiment, the doped layer 30 can be made of amorphous silicon material, such as boron-doped amorphous silicon oxide or phosphorus-doped amorphous silicon oxide. The doped layer 30 can also be made of microcrystalline silicon material. No specific limitations are imposed here.

[0091] In this embodiment, the heterojunction cell fabricated by the heterojunction cell fabrication method provided in this embodiment will ultimately form a cell structure with a textured front surface and a polished back surface 12. From an appearance perspective, the polished surface 12 has a mirror-like effect, being brighter and smoother than the unpolished surface. From an electrical performance perspective, carrier transport is improved, open-circuit voltage is increased, and fill factor is optimized. From an optical performance perspective, since the reflectivity of a mirror surface is higher than that of a rough surface, the reflectivity Ref of the polished surface 12 is significantly higher than that of the textured surface 11, with the optimal difference being 7%-17%. Polishing within this range can slightly improve the open-circuit voltage, increase the short-circuit current by more than 20mA, and increase the fill factor by more than 0.30%, while reducing the bifaciality of the cell by ≤5%, achieving the optimal balance between cell efficiency and bifaciality.

[0092] Embodiments of the present invention also provide a photovoltaic module, including the above-described heterojunction cell.

[0093] In summary, the embodiments of the present invention provide a method for fabricating a heterojunction cell, a heterojunction cell, and a photovoltaic module. The method for fabricating a heterojunction cell includes performing double-sided texturing on a silicon substrate 10; preparing a mask layer on a first surface of the silicon substrate 10; polishing a second surface of the silicon substrate 10; and performing multiple gettering operations on the silicon substrate 10. In use, after double-sided texturing of the silicon substrate 10, a mask layer is prepared on the first surface of the silicon substrate 10. The second surface of the silicon substrate 10 is polished to make it smoother, which is beneficial for the subsequent deposition of amorphous silicon thin films. The smooth surface enables more uniform film growth, thereby improving the quality of the film and the performance of the battery. Multiple gettering processes are performed on the first and second surfaces of the silicon substrate 10. Multiple gettering processes can more effectively remove impurities on the first and second surfaces of the silicon substrate 10, further reducing the impurity concentration on the second surface of the silicon substrate 10. This results in the impurity concentration on the second surface of the silicon substrate 10 being lower than that on the first surface, thereby improving the overall minority carrier lifetime and making the passivation effect of the second surface of the silicon substrate 10 better.

[0094] The heterojunction solar cell includes a transparent conductive layer 40, a doped layer 30, an intrinsic amorphous silicon layer 20, and a silicon substrate layer 10 stacked sequentially. The first surface is a textured surface 11, and the second surface is a polished surface 12. The Fe concentration in the textured surface 11 is 10 to 100 times higher than that in the polished surface 12, and the Al concentration in the textured surface 11 is 10 to 100 times higher than that in the polished surface 12. The difference in reflectivity between the textured surface 11 and the polished surface 12 is 7% to 17%. During use, the smoother surface of the polished surface 12 facilitates the subsequent deposition of amorphous silicon thin films. The Fe concentration in the textured surface 11 of the silicon substrate layer 10 is 10 to 100 times higher than that in the polished surface 12, and the Al concentration in the textured surface 11 is also 10 to 100 times higher than that in the polished surface 12. This means that the impurity element content in the polished surface 12 is much lower than that in the textured surface 11, thereby improving the overall minority carrier lifetime and resulting in better passivation of the polished surface 12. Furthermore, the difference in reflectivity between the textured surface 11 and the polished surface 12 is 7% to 17%, meaning that the reflectivity of the polished surface 12 is much higher than that of the textured surface 11, which enhances the light-trapping effect of the polished surface 12 and improves the light absorption efficiency.

[0095] This photovoltaic module includes the aforementioned heterojunction cell and possesses all the aforementioned beneficial effects.

[0096] Example 1

[0097] This embodiment provides a method for fabricating a heterojunction solar cell, including:

[0098] S1: Polish both sides of the silicon substrate 10.

[0099] S2: Phosphorus gettering is performed on both sides of the silicon substrate 10.

[0100] S3: Remove the phosphor silicate (PSG) glass layer.

[0101] S4: Perform double-sided texturing on the silicon substrate layer 10.

[0102] S5: Prepare a mask layer on the first surface of the silicon substrate 10.

[0103] S6: Polish the second surface of the silicon substrate 10.

[0104] S7: Remove the mask layer from the first surface.

[0105] S8: Perform multiple gettering operations on the silicon substrate 10.

[0106] Specifically, the silicon substrate 10 undergoes two phosphorus getter treatments using a phosphorus getter. First, a phosphorus slurry is coated on both sides of the silicon substrate 10. Then, using a roller drive, the silicon substrate 10 is passed uniformly through multiple high-temperature chambers at 700℃-1000℃. At high temperatures, the phosphorus slurry forms a PSG layer on the surface of the silicon substrate 10, which condenses and precipitates metallic impurities from within the silicon substrate 10. The concentration of phosphorus compounds in the phosphorus slurry is 6%.

[0107] S9: Remove the phosphor silicate (PSG) glass layer.

[0108] S10: Rounding treatment is performed on the silicon substrate layer 10.

[0109] S11: Clean the silicon substrate layer 10.

[0110] S12: An intrinsic amorphous silicon layer 20 is prepared on both sides of the silicon substrate layer 10.

[0111] S13: A P-type doped layer 30 is prepared on the front side of the silicon substrate 10, and an N-type doped layer 30 is prepared on the back side of the silicon substrate 10.

[0112] S14: Prepare TCO thin film layers on both sides of silicon substrate 10.

[0113] S15: Screen printing.

[0114] Example 2

[0115] Referring to Example 1, the method differs from Example 1 in that step S8 of the heterojunction solar cell fabrication method in this example includes: performing multiple gettering operations on the silicon substrate 10.

[0116] Specifically, the silicon substrate 10 is subjected to five phosphorus getter treatments using a phosphorus getter. In this process, a phosphorus slurry is coated on both sides of the silicon substrate 10. The silicon substrate 10 is then passed at a constant speed of 6 m / min through multiple high-temperature chambers with temperatures ranging from 700℃ to 1000℃. At these high temperatures, a PSG layer is formed on the surface of the silicon substrate 10, which condenses and precipitates metallic impurities from within the silicon substrate 10. The concentration of phosphorus compounds in the phosphorus slurry is 10%.

[0117] Comparative Example 1

[0118] Referring to Example 1, the difference is that this comparative example provides a heterojunction solar cell fabrication method in which, in step S8, only the silicon substrate 10 is gouged once.

[0119] Comparative Example 2

[0120] Referring to Example 1, the method differs from Example 1 in that it omits steps S8 and S9 when using a heterojunction solar cell fabrication method.

[0121] Comparative Example 3

[0122] The method is carried out with reference to Example 1. The difference between Example 1 and Example 2 is that this comparative example provides a heterojunction battery preparation method in which step S6 is omitted.

[0123] Test case

[0124] The minority carrier lifetime, short-circuit current, open-circuit voltage, conversion efficiency, and fill factor of the heterojunction solar cells prepared by the methods described in Examples 1, 2, and Comparative Examples 1-3 were tested. The results are shown in Table 2.

[0125] Table 2

[0126]

[0127] The results above show that the solar cell prepared by the method of Example 1 of the present invention has the highest minority carrier lifetime, the best conversion efficiency and fill factor.

[0128] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A heterojunction battery, characterized in that, The system includes a silicon substrate layer (10), which has a first surface and a second surface disposed opposite to each other. The first surface is a textured surface (11), and the second surface is a polished surface (12). Both the textured surface and the polished surface are sequentially stacked with an intrinsic amorphous silicon layer (20), a doped layer (30), and a transparent conductive layer (40). Both the textured surface (11) and the polished surface (12) contain impurities Fe and Al elements. The Fe / Al element concentration in the textured surface (11) is higher than that in the polished surface (12).

2. The heterojunction solar cell according to claim 1, characterized in that, The Fe concentration in the velvet surface (11) is 10 to 100 times higher than the Fe concentration in the polished surface (12), and the Al concentration in the velvet surface (11) is 10 to 100 times higher than the Al concentration in the polished surface (12).

3. The heterojunction solar cell according to claim 1, characterized in that, The Fe / Al concentration in the velvet (11) is 0.1ppb-1ppb.

4. The heterojunction solar cell according to claim 1, characterized in that, The concentration of Fe / Al elements in the polished surface (12) is no greater than 0.1 ppb.

5. The heterojunction battery according to claim 1, characterized in that, The difference between the reflectivity of the velvet surface (11) and the reflectivity of the polished surface (12) is 7%-17%.

6. The heterojunction solar cell according to claim 1, characterized in that, The transparent conductive layer (40) has metal grid lines (50) on the side surface away from the doped layer (30).

7. A method for fabricating a heterojunction solar cell, characterized in that, The method for preparing the heterojunction solar cell according to any one of claims 1-6 comprises: The silicon substrate layer (10) is textured on both sides; A mask layer is prepared on the first surface of the silicon substrate layer (10); The second surface of the silicon substrate (10) is polished; The silicon substrate (10) is subjected to multiple gettering processes.

8. The method for fabricating a heterojunction solar cell according to claim 7, characterized in that, The step of polishing the second surface of the silicon substrate (10) further includes: The polishing and etching thickness of the second surface is 2µm-6µm.

9. The method for fabricating a heterojunction solar cell according to claim 7, characterized in that, The step of preparing a mask layer on the first surface of the silicon substrate (10) includes: A mask layer with a thickness of 50 nm to 100 nm is prepared on the first surface of the silicon substrate layer (10) using a PECVD device.

10. The method for fabricating a heterojunction solar cell according to claim 7, characterized in that, Prior to the step of performing double-sided texturing on the silicon substrate layer (10), the heterojunction cell fabrication method further includes: The silicon substrate (10) is polished on both sides and then subjected to gettering.

11. The method for fabricating a heterojunction solar cell according to claim 7, characterized in that, The step of performing double-sided texturing on the silicon substrate layer (10) includes: The first and second surfaces of the silicon substrate layer (10) are formed with a textured surface of a pyramid structure with a width of 0.05um-5um.

12. A photovoltaic module, characterized in that, Includes the heterojunction battery according to any one of claims 1-6, or includes the heterojunction battery prepared by the heterojunction battery preparation method according to any one of claims 7-11.

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