Hardware wake-up for display panels

Abstract

Aspects relate to hardware wakeup for a display panel. In one aspect, a wake event is received at a system processor. The system processor wakes up from an idle state to an active state. During wake-up of the system processor, a wake-up signal is transmitted at an output of the system processor. The output is configured to be coupled to a display panel. The wake-up signal is a command to the display panel that increases a frame rate of the display panel from an idle frame rate to an active frame rate.

Description

Technical Field

[0001] Aspects of the present disclosure relate generally to display panel operation, and particularly to hardware wake-up configurations for refreshing the refresh rate of a display panel. Background Art

[0002] Display panels appear in countless portable and stationary devices. Display panels can include a light emitter (e.g., a backlight or light-emitting diode elements) and a video driver, both of which consume power. The video driver generates content based on what will be viewed on the display panel and refreshes the panel at a rate typically expressed as frames per second. The lowest-power display panels have no backlight or an intermittent backlight and slow or fixed content. This is suitable for thermostats or e-readers. The highest-power display panels are characterized by bright, fast-moving video content and are suitable for entertainment and content consumption.

[0003] For many devices that include display panels, there are idle or low-use times and high-speed, high-use times. During the slower times, the frame rate of the display can be low, such as 30 frames per second (fps) or 60fps or less. During the high-speed times, faster frame rates may be required. Video consumption is typically rendered at 24fps to 30fps. Computer monitors typically operate at 60fps. For video games, higher frame rates, such as 120fps or 240fps, are desired. For interactive systems that respond to touch or pointers, the frame rate directly affects the user's impression of the system's responsiveness. At 1fps, even typing will appear sluggish. At 60fps, screen scrolling may appear slow or jittery. When the display panel operates at a high frame rate, user interaction is significantly improved.

[0004] To save power, many portable devices will collapse the power consumption of the display panel by turning off the display panel. This eliminates the power consumed by the light emitter and video driver. When the display is still powered, power consumption is reduced by dimming the screen, reducing the refresh rate, and repeatedly rendering the same image for each frame. For command mode display panels, the display panel can operate autonomously at a specified frame rate. This eliminates part of the power consumed by the light emitter and most of the power consumed by the video driver. In mobile phones with large display panels, the power consumption of the device can be reduced by up to 4% by reducing the display panel refresh rate from 120fps to 30fps. When the user lifts the device, touches the touch screen, looks at the front camera, or reactivates the device in another way, the refresh rate returns to a more satisfactory rate, such as 60fps or 120fps. Summary of the Invention

[0005] The following content presents a summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that will be presented later.

[0006] In one example, a method includes receiving a wake-up event at a system processor; waking the system processor from an idle state to an active state; and transmitting a wake-up signal at an output of the system processor during the wake-up of the system processor. The output is configured to be coupled to a display panel. The wake-up signal is a command to the display panel to increase a frame rate of the display panel from an idle frame rate to an active frame rate.

[0007] In another example, an apparatus includes a system processor configured to receive a wake-up event. The system processor is configured to wake up from an idle state to an active state in response to the wake-up event. A wake-up connector is coupled to the system processor and is configured to couple to a display panel to transmit a wake-up signal to the display panel during wake-up of the system processor from the idle state. The wake-up signal is a command to the display panel to increase a frame rate of the display panel from an idle frame rate to an active frame rate.

[0008] In another example, a non-transitory computer-readable medium has stored therein instructions for causing a system processor coupled to a command mode display panel to perform the operations of the above method.

[0009] To accomplish the foregoing and related objectives, one or more implementations include the features fully described below and particularly pointed out in the claims. The following description and the accompanying figures set forth in detail certain illustrative aspects of one or more implementations. However, these aspects are merely indicative of a few of the various ways in which the principles of various implementations may be employed, and the described implementations are intended to encompass all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A block diagram illustrating a system on a chip according to certain aspects of the present disclosure is shown.

[0011] Figure 2 A block diagram illustrating a system coupled to a command mode display panel having a hardware wakeup connector, in accordance with certain aspects of the present disclosure, is illustrated.

[0012] Figure 3 Illustrate system wake-up timing relative to the command mode display panel frame refresh rate.

[0013] Figure 4 System wake-up timing with discrete new frame rate settings related to a command mode display panel frame refresh rate is illustrated in accordance with certain aspects of the present disclosure.

[0014] Figure 5 A functional block diagram illustrating a wake-up process according to certain aspects of the present disclosure is shown.

[0015] Figure 6 A block diagram illustrating an exemplary hardware implementation of a device with hardware wakeup for a command-mode display panel having a processor core, a display processor unit, and memory, among other components, in accordance with certain aspects of the present disclosure.

[0016] Figure 7 A flow chart illustrating a method for implementing hardware wakeup of a command mode display panel according to certain aspects of the present disclosure is illustrated. DETAILED DESCRIPTION

[0017] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details to provide a comprehensive understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0018] Aspects disclosed herein provide a hardware wake-up configuration to restore the active refresh rate of a display panel (e.g., a command-mode display panel). For many use cases, periods of idle use are followed by periods of active use. When a device switches from a reduced-power, idle, or sleep state to a fully awake or powered state, faster wake-up times (also known as reduced wake-up latency) provide a more pleasant user experience. Wake-up latency is directly affected by frame rate, as it changes at the start of a new frame. At 60 fps, it takes 16 ms before the next frame can be refreshed. At 1 fps, it takes 1000 ms to refresh a new frame. Users experience a 1000 ms delay, or even a 100 ms or 50 ms delay, as poor performance. To avoid this experience, the display panel can be limited to at least 60 fps, even during idle periods. Some panels, such as low-temperature polycrystalline oxide (LTPO) panels, can achieve extremely low frame rates, such as 1 fps. By reducing wake-up latency, this low-power performance can be more fully utilized, saving power without negatively impacting the user experience.

[0019] Some devices have an active frame rate that varies depending on the specific use of the device. For relatively static activities such as reading, typing, or browsing, a command mode display panel can operate at an active frame rate of 60fps. For active consumption activities such as rendering video, a command mode display panel can operate at an active frame rate of 120fps. For interactive activities such as scrolling or gaming, a command mode display panel can operate at an active frame rate of 240fps. As frame rates get higher, the power demand on the device also increases. By using lower and lower idle frame rates during idle time, such as 30fps, 10fps, or 1fps, the overall impact of the high power demand can be compensated.

[0020] Various aspects provide a dedicated electrical connection between the system processor and the display panel (e.g., using display panel pins) to quickly wake up the panel's refresh rate to the active refresh rate when the system processor (which may include a display processor unit (DPU), video controller, or other driver for the command mode display panel) resumes its active state. The display panel refresh rate can be increased at the next opportunity after the display panel receives a pin assertion from the system processor. This can be at the beginning of the next video synchronization cycle, i.e., when rendering of the next frame begins, which can be the same or a different image from the previous frame. When the software resumes and is ready to generate new content, the refresh rate has already been increased. This allows for a faster transition to active, high-speed operation than waiting for software to increase the refresh rate.

[0021] Wake events can come from one or more sources, depending on the nature of the device and its use case. A touchscreen interface can generate a wake event if the user taps the screen to wake the device. Wake events can also or alternatively come from a low-power digital signal processor (DSP), a video driver, or a sensor island for devices using eye-tracking sensors, accelerometers, proximity sensors, or tilt sensors. Wake events provide the basis for wake signals at the output of the system processor.

[0022] The wake-up signal can come from various sources within the system processor, such as a lower-power processor or DSP associated with the sensor or touch panel. The wake-up signal can also come from the application processor or display processing unit after waking up. The faster wake-up time allows the frame rate of the command mode display panel to be switched to a much lower idle frame rate, and to be switched to the idle frame rate more frequently. This allows the device to reduce power consumption without the disadvantages of the system latency of typical power collapse.

[0023] While various aspects and examples are described herein through the lens of certain examples, those skilled in the art will appreciate that additional implementations and use cases can be generated in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, various aspects or uses can be generated via integrated circuit chip examples and other non-modular component-based devices (e.g., end-user devices, vehicles, communications equipment, computing devices, industrial equipment, retail / shopping equipment, medical devices, AI-enabled devices, etc.). While some examples may or may not be specifically directed to use cases or applications, the applicability of the described innovations can be diverse. Implementations can range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or OEM (original equipment manufacturer) devices or systems incorporating one or more aspects of the described innovations. In some practical environments, a device incorporating the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, temperature and power sensors may use multiple components for both analog and digital purposes (e.g., hardware components including power supplies, transducers, detectors, accumulators, digital-to-analog converters, etc.). It is intended that the innovations described herein may be practiced in a wide variety of devices, chip-level components, systems, distributed arrangements, end-user devices, and the like, of various sizes, shapes, and configurations.

[0024] Figure 1 is a block diagram of a system-on-chip (SoC) suitable for use with a portable device or computer. SoC 102 has multiple components on a single integrated circuit chip, thermally coupled to a cooler 134 (e.g., a heat sink) and attached to a package (not shown). Alternatively, the SoC can be implemented as a system-in-package (SiP), where components are formed on two or more different chips coupled together within a single package. SoC 102 has a multi-core processor (which may include, for example, a CPU 104 or an application processor), a multi-core graphics processor (e.g., GPU 106), a multi-core digital signal processor (e.g., DSP 108), and a security module 110 that provides secret keys, device security, encryption, and decryption.

[0025] SoC 102 may also include a user interface 112 coupled to external components such as a touch screen, a keyboard, buttons, and the like. Figure 1The SoC shown in FIG1 also includes a mass storage device 114, an inertial reference unit 116, a camera 118, a position system 120 (such as a satellite positioning system), and a display driver 122 (e.g., a display processor unit (DPU)). The display driver 122 is coupled to a command mode display panel 136, such as a user display with a touch screen overlay. The display driver transmits new frames and control signals and commands the refresh rate of the command mode display panel 136. In some embodiments, the display driver 122 can be incorporated into the GPU 106. In addition, the SoC can include a wireless interface 124 that is coupled to analog radio frequency components and an antenna (not shown) to support wireless data and control interfaces.

[0026] Each of the components is coupled via a bus (not shown) or via CPU 104, and more or fewer components may be used to suit a particular application. As an alternative to SoC 102, as shown, any one or more of the components may be fabricated on separate chips and packaged together or separately. One or more of GPU 106, DSP 108, CPU 104, display driver 122, and mass storage device 114 or a portion of mass storage device 114 may be physically or logically combined to form a system processor as further described herein.

[0027] The device including the SoC 102 is coupled to a power source 130 such as a battery, or a main power converter coupled to the SoC 102 through a power manager 132, which may be on-chip or a discrete component. The power manager 132 regulates power to the components of the SoC 102 and controls the operating clock frequency and voltage applied to the components of the SoC 102. The power manager 132 further controls the voltage applied to the SoC and can also measure the battery charge level of the power source.

[0028] The cores of CPU 104, GPU 106, and other components such as mass storage device 114 and wireless interface 124 may include or be equipped with thermal and power sensors in the form of voltage sensors, current sensors, or both. The sensors provide information to power manager 132 for use in adjusting the frequency and voltage provided to the components. In some examples, CPU 104, GPU 106, and other clocked components may also include power manager circuitry or software for determining appropriate clocking frequencies and voltages.

[0029] The power manager 132 or CPU 104 may also control the device's active state, such as one or more idle or power-collapse states and one or more active or wake-up states. Depending on the specific state, various components of the SoC are slowed down or shut down to save power and reduce heat to the cooler 134. When a wake-up event occurs, the system resumes. The SoC may also be able to shut down certain components during certain operating modes.

[0030] Figure 2 A hardware block diagram of a portion of a system processor 202 (e.g., a SoC, SiP, or motherboard) is illustrated, wherein an application processor (AP) 204 (e.g., a CPU) and a display processor unit (DPU) 206 (e.g., a GPU, a display driver, or both) are coupled to a command mode display panel using a hardware wakeup connection. The system processor 202 includes the AP 204, which is internally coupled to the DPU 206 and other components 208. The other components 208 may include, for example, Figure 1 Any of the components mentioned, including memory, power controllers, sensors, and external interfaces. Other components 208 may also include wakeup sources such as button interfaces, touch screen controllers, cameras, inertial reference units, external interfaces, etc. Software instructions executed by AP 204 may also be a wakeup source. System processor 202 has a data bus 212 for communicating with command mode display panel 210. Data bus 212 can be any suitable data bus for carrying video frames and command and control information, such as a mobile industry processor interface, a display serial interface (MIPI DSI), an inter-integrated circuit (I2C), and a power connection.

[0031] In addition, a wakeup connector 214 is coupled from the system processor 202 to the command-mode display panel 210 to carry a wakeup signal transmitted by the system processor 202. The wakeup connector 214 can be coupled from the DPU 206, the AP 204, another component 208 (e.g., a sensor island or touch sensor), or an external source. In an example, the wakeup connector 214 is in the form of a general-purpose input / output (GPIO) connector that connects a dedicated wakeup pin 216 (e.g., a GPIO pin) of the system processor 202 to a dedicated wakeup pin 218 of the command-mode display panel 210. The dedicated wakeup pin 216 sets the signal to a high or low format, or another signal format, generated by a suitable signal source of the system processor. In an example, the wakeup signal source sets the wakeup signal at the dedicated wakeup pin 216 of the system processor to, for example, high or low, which is coupled through the wakeup connector 214 to set the corresponding dedicated wakeup pin 218 of the display panel to high or low. In another example, the wake-up signal is transmitted as a multi-bit command or control packet through the wake-up connector 214 , which is dedicated only to the wake-up signal or may also carry other command and control signals.

[0032] Although the wakeup connector 214 is shown as a single wire, the wakeup signal can be carried on a bus that provides fast, low data rate communication (e.g., I2C). A more complex bus can be used to command the command mode display panel 210 to change to a specific refresh rate for the next wakeup sequence. The system processor 202 and the command mode display panel 210 may include more components. To simplify the description, these components are not shown here. The wakeup connector 214 is independent of the data bus 212 that carries data, commands, control, and new frames to the command mode display panel 210. Therefore, the wakeup signal is independent of any frame and independent of any current or pending frame rate of the command mode display panel 210. The wakeup signal can be transmitted independently of and in parallel with any activity on the video bus.

[0033] In other examples, a wake-up event may be triggered by eye tracking at an eye sensor on a sensor island. In this example, a wake-up connector may be coupled between the eye sensor and the command-mode display panel 210. The eye sensor DSP may be configured to generate a wake-up signal after a detected gaze activity generates a wake-up event. In another example, a touchscreen integrated circuit (IC) may be coupled to the wake-up connector, such that after the firmware in the touchscreen IC detects the wake-up event, a wake-up signal may be generated and transmitted to the command-mode display panel. In another example, an accelerometer detects tilt or lift as a wake-up event. An inertial reference unit IC may be coupled to the wake-up connector, such that the firmware in the inertial reference unit IC generates the wake-up signal. In another example, multiple sensors may be connected to the same wake-up pin of the command-mode display panel, and any one of the sensors may generate the wake-up signal. In such an example, the wake-up signal is independent of the AP and the DPU.

[0034] When the device including the system processor 202 and the command mode display panel 210 is idle and there is no new content to be displayed on the command mode display panel 210, the AP and DPU can be power collapsed to a power collapsed state, an idle state, or another low power state to reduce power consumption. The command mode display panel can still be powered and perform a self-refresh of its display. Significant power savings are achieved by reducing the frame rate of the display during the power collapse period. The lower the frame rate, the greater the power savings. In some scenarios, the active frame rate is between 60 frames per second (fps) and 240 fps, while the reduced idle frame rate can be between 1 fps and 30 fps.

[0035] Figure 3300 is a diagram illustrating system wakeup timing in relation to the command mode display panel frame refresh rate. The top portion of the diagram illustrates a sequence of video synchronization cycles across a timeline. Six video synchronization cycles are shown in temporal sequence from left to right, each of which refreshes the display of a frame. There are earlier video synchronization cycles not shown on the left side, as well as later video synchronization cycles not shown on the right side. On the left side of the diagram's timeline, the device is in a power-collapsed or idle state. The command mode display panel has been set to a low frame rate and is repeatedly refreshing the same frame, frame n-1. This may be the self-refresh mode of the command mode display panel, which is active when the AP and DPU are idle. During a first video synchronization cycle 304, the command mode display panel displays the frame numbered frame n-1. During a second video synchronization cycle 306, the command mode display panel again displays the same frame, frame n-1. This same frame is displayed in a third video synchronization cycle 308 and a fourth video synchronization cycle 310.

[0036] In this example, during the second video synchronization period, a wakeup event is received at time 322. This causes the system processor (e.g., AP and DPU) to exit the power collapse state and wake up to the active state. The wakeup event can be a touch of the power key or other key, a touchscreen controller touch, an inertial reference sensor event (such as tilt or acceleration), a camera detection, a proximity sensor detection, or other events. The wakeup event can originate from a sensor island, a touchscreen controller, an inertial reference unit, and be received at the system processor. This causes the system processor to begin the process of exiting the power collapse at time 322.

[0037] The power collapse exit requires some time to execute. The duration of the power collapse exit is indicated as T1, and the span of T1 across the timeline along the horizontal axis is illustrated by arrow 330. The end of arrow 330 is indicated at time 324. With the AP and DPU now active, the system processor can begin reacting to the wakeup event by refreshing the video display with a new frame (frame n). First, after the power collapse exit at T1, the system processor generates a new frame for the command mode display panel. Generating the new frame (frame n) requires a duration of T2 and is illustrated by a second arrow 332 between times 324 and 326. Once the DPU or other video device generates the new frame, the device waits for a duration of T3, indicated by a third arrow 334 between times 326 and 328, until the start of the next video synchronization period 312, and then transmits the new frame (frame n) to the command mode display panel.

[0038] The total time from the wake-up event to the presentation of a new frame on the command mode display panel is the sum of T1, T2, and T3. In some examples, T1 may be greater than 100ms. T2 may be less than the duration of a frame at a high frame rate, for example, less than 1 / 120 second or less than 8ms. T3 depends on the frame rate and is longer at lower frame rates. At a frame rate of 1fps, T3 may be as long as 1000ms. As shown, the faster frame rate at time 326 allows the display panel to be refreshed faster. However, the slower frame rate reduces the power consumed by the display panel.

[0039] consider Figure 3 In the example shown in FIG. 3 , a wake-up event occurs at time 322 during the second video synchronization period 306. The time T1 for exiting the power collapse ends at time 324 during the third video synchronization period 308. The time T2 for generating the next frame ends at time 326 during the fourth video synchronization period 310. The time T3 for transmitting the new frame ends at time 328 (which is determined by the end of the fourth video synchronization period 310 being the current period). The device then transmits the new frame and sets a new faster fps or active frame rate at time 328. This causes the command mode display panel to display a new frame, frame n, during the fifth video synchronization period 312. In the sixth video synchronization period 314, a new frame, frame n+1, may be transmitted by the active device. The sequence of video frames may continue with the same frame or new frames at the new faster frame rate until the next power collapse.

[0040] Using a software system via the AP, DPU, or similar component, the frame rate cannot be refreshed until the device exits the power-collapse state at time 324 and also generates a frame rate command at time 326. While the device is active, a frame and a new frame rate can be generated and transmitted to the command mode display panel. The transition occurs at the end of the current frame to begin the next frame. At very low frame rates (such as 1 fps), the user will perceive the device as unresponsive because it will take more than a second for the device to respond with a new frame. In the illustrated example, more than two video synchronization cycles elapse before the device responds. To avoid this slow response, the frame rate is maintained at a higher speed, such as 24 fps, 30 fps, or 60 fps. However, more power is required to self-refresh the command mode display panel at a faster rate. During idle time, a faster frame rate does not benefit the user. This is partly because the device is not actively used and partly because the frames are the same regardless of the refresh rate.

[0041] Figure 44 is a diagram illustrating system wakeup timing 400 using hardware wakeup in relation to the command mode display panel frame refresh rate. On the left side of the diagram, the device is in a power collapsed state, an idle state, or any other suitable low-power state. The command mode display panel has been set to the idle frame rate and repeatedly refreshes the same frame. During a first video synchronization period 402, the command mode display panel shows a frame numbered frame n-1. During a second video synchronization period 404, the command mode display panel again shows the same frame, frame n-1. This same frame is shown in a third video synchronization period 406, a fourth video synchronization period, a fifth video synchronization period, and a sixth video synchronization period 410.

[0042] In this example, during the second video synchronization period, a wake-up event is received at the system processor at time 422. This causes the system processor (eg, AP and DPU) to begin a power collapse exit and return to an active state at time 424. The duration of the power collapse exit, T1, is the same as Figure 3 426 , and is controlled by the configuration of the AP and DPU, as well as the configuration of the idle state prior to time 422. The duration is indicated as T1, and the span along the horizontal axis across the timeline from time 422 to time 424 is illustrated by arrow 430. At time 424, the device is active and generates a new frame for the command mode display panel. The new frame (frame n) requires a duration of T2 to generate, and is illustrated by a second arrow 432 between times 424 and 426.

[0043] When a wake-up event occurs, there is a signal to the system processor to wake up the AP and DPU. There is also a wake-up signal to the command mode display panel. The wake-up signal can be provided by a dedicated wake-up pin of the system processor to a wake-up connector that is dedicated to the wake-up pin of the command mode display panel. The wake-up signal can also be provided to the AP and DPU in another way separate from the wake-up. The wake-up event can come from a sensor island, a touch screen controller, an inertial reference unit, or any other component that is directly or indirectly coupled to the command mode display panel. The sensor can be coupled to the command mode display panel directly or through a DSP or other controller that receives and acts on signals from the sensor. The sensor can be coupled to the system processor or be part of the system processor and operate as a part of the system processor that is not in a power collapse state.

[0044] The hardware wake-up signal causes the command mode display panel to switch to a faster frame rate at the end of the current video sync cycle (i.e., second video sync cycle 404). The current video sync cycle is the video sync cycle during which the wake-up signal is transmitted. In this example, receiving a wake-up event during second video sync cycle 404 causes the third video sync cycle 406 to be at a new, faster active frame rate. The same frame (frame n-1) is repeated in each video sync cycle until the next frame (frame n) is generated during duration T2, indicated by second arrow 432. At time 420, the frame rate is changed at the beginning of the third video sync cycle. This occurs before the power collapse exit ends at time 424 and before the next frame is generated at time 426. The specific timing of the power collapse exit and new frame generation relative to a particular video sync cycle can vary depending on the idle frame rate, the active frame rate, and the time when the wake-up event occurs. The refresh rate change from the idle frame rate to the active frame rate can be implemented by the command mode display panel in parallel with or independent of the system collapse exit, so that the system collapse exit is unaffected.

[0045] Once the DPU or other video device generates a new frame, the device waits for a duration T3, indicated by a third arrow 434 between times 426 and 428, until the start of the next video synchronization period 410, and then transmits the new frame (frame n) to the command mode display panel. The new frame is shown in the seventh video synchronization period 410, and subsequent new frames are shown on the command mode display panel in subsequent video synchronization periods 412, 414, and so on. Some of the new frames may be duplicates of frame n, depending on the specific activity of the device.

[0046] As shown for frame n-1, the command mode display panel can self-refresh the display using the same frame for each video synchronization cycle. It can also change the frame rate used for self-refresh in response to commands from the system processor, as shown for video synchronization cycle 406 and video synchronization cycle 408. Each frame represents an image as it is rendered on the display. Therefore, when the command mode display panel repeats rendering of frame n-1, it repeatedly displays the same image at the idle frame rate. The displayed image is static. It then repeatedly displays the same image at the active frame rate, starting from video synchronization cycle 406 and continuing until video synchronization cycle 408. When the system processor provides a new frame (frame n), this can result in a new image being displayed or the same image being displayed again for static image display until there is new information from the system processor to be presented on the display for dynamic image display.

[0047] The total time from the wake-up event to the presentation of a new frame (frame n) on the command mode display panel is the sum of T1, T2, and T3. Figure 3T3 is the same as T4 in the 2D / 3D since they are determined by the device configuration, the idle state conditions, and the active state configuration of the AP and DPU. Figure 3 In the example shown in Figure 2, the frame rate is much shorter because the frame rate has been increased to the active frame rate. By changing the frame rate from 1 fps or 1000 ms to 120 fps or 8.3 ms, T3 can be reduced by up to 991.3 ms during the power collapse exit duration T1 or the frame generation duration T2. ​​By changing the frame rate from the idle rate of 10 fps or 100 ms, T3 can be reduced by up to 91.3 ms.

[0048] By enhancing the software system with hardware wakeup, the frame rate can be refreshed to the active frame rate before the system processor exits the power-collapse state. While the system processor is active, frames can be generated and transmitted to the command mode display panel while the command mode display panel is already at the active frame rate. The transition occurs at the end of the current frame to start the next frame. This allows the system processor to idle at a much lower frame rate (such as 1 fps) because the frame rate will increase before the user will perceive the device as unresponsive. This allows for a better user experience with a lower power idle state.

[0049] The timelines in the illustrated examples are not necessarily drawn to scale. The idle frame rate (e.g., 404) is shown as being only approximately three times longer than the active frame rate (e.g., 406). Such a scenario is possible with an idle frame rate of 20 fps and an active frame rate of 60 fps. While the structures and methods are applicable to such scenarios, they are also applicable to scenarios where the difference between the idle and active frame rates is much larger, such as 10 fps and 120 fps, or 1 fps and 240 fps. Figure 4 The timeline shows changing the command mode display panel frame rate at the start of the next video synchronization period after receiving the wake signal. This can be during T1 or T2. This earlier change to the active refresh rate reduces duration T3. In other examples, the command mode display panel frame rate can be changed at the start of a second later video synchronization period after receiving the wake signal. This can still reduce duration T3, depending on the relative frame rates and durations T1 and T2.

[0050] Figure 5 5. The wakeup process 500 includes a system idle process 504, a system wakeup process 506, and a system active process 508. A system wakeup event 516 occurs between the system idle process 504 and the system wakeup process 506.

[0051] During the system idle process 504, at 510, the command mode display panel is in an idle fps or frame rate. This is a low frame rate for power conservation. At 512, the processor is in a power-down state (e.g., an idle state), and at 514, the command mode display panel is optionally self-refreshing. With the system processor (e.g., AP and DPU), no new content is generated during power down. The image on the display is static or unchanged. The display panel repeatedly displays the same image at the idle frame rate. However, for many display systems, the display must be refreshed to display the same image. In another idle state, the command mode display is off. In an alternative example, all of the operations described herein may be initiated when the command mode display is off during the system idle process 504.

[0052] A system wakeup event occurs at 516. The system wakeup event generates a software command to wake up software system processors (eg, AP and DPU) as well as a hardware wakeup (eg, a wakeup signal to a command mode display panel or other similar component).

[0053] The system wake-up event is provided to a system wake-up process 506. The system wake-up process includes the device exiting the power-collapsed state at 518. This is followed by generating a new frame at 520, which is then followed by transmitting the newly generated frame to the command mode display panel at 522. In parallel, there is also a process of transmitting a wake-up signal at 524 during the power-collapsed state exit 518. The wake-up signal is transmitted via a wake-up connector coupled to the command mode display panel. The wake-up signal is a command to switch the command mode display panel to the active frame rate. Using the parallel process, the command mode display panel may have already been switched at 524 and is operating at the active frame rate before the new frame is transmitted to the command mode display panel at 522.

[0054] Then, at 508, the device operates the system active process. At 528, a new frame is refreshed on the command mode display panel. During the system active process at 508, the frame can be changed to suit the usage scenario, and different active frame rates can be used to suit different usage scenarios. At a later time, the device returns to the system idle process at 504 until the next system wakeup event with hardware wakeup at 516.

[0055] Figure 6A block diagram illustrating an example of a hardware implementation of a device 600 is shown, such as a user equipment, portable device, laptop, tablet computer, computer, server, projector, entertainment device, gaming handheld device, or any other suitable device having a command mode display unit and an idle state. In this example, the command mode display panel 614 can have different refresh rates and can also self-refresh a static image in one or more states. The system processor 602 drives the command mode display panel 614 via bus 622 to display frames of a video source. According to various aspects of the present disclosure, the system processor 602 can be used to implement an element, any portion of an element, or any combination of elements. The system processor 602 may include a processor 604. Examples of processor 604 include APs and DPUs that, alone or together, may be in the form of and work with microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gating logic, discrete hardware circuits, and other suitable hardware, including processing circuitry configured to perform one or more of the functions described herein, including the functions of an application processor and a display processing unit.

[0056] In this example, the system processor 602 can be implemented using a bus architecture (generally represented by bus 622). Bus 622 can include any number of interconnecting buses and bridges, depending on the specific application of the system processor 602 and the overall design constraints. Bus 622 communicatively couples various circuits, including one or more processors (generally represented by processor 604), a computer-readable medium having instructions stored thereon (generally represented by computer-readable medium 606), and sensor island 608, which can include one or more cameras, proximity sensors, inertial reference units (IRUs), and any other sensor components. Bus 622 can also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and will not be described further.

[0057] Bus interface 610 provides an interface between bus 622 and a radio (shown as transmitter / receiver 616), as well as an interface between bus 622 and interface 618. Transmitter / receiver 616 provides a communication interface or component for communicating over one or more wireless transmission media. Interface 618 provides a communication interface or component for communicating with various other devices and equipment (e.g., other devices housed within the same device or other external devices) via an internal bus or an external transmission medium such as an Ethernet cable. Bus 622 is also coupled to user interface 612, such as a keypad, display, speaker, microphone, joystick, etc. User interface 612 is also optionally coupled to a command mode display panel for a touch screen overlay.

[0058] The processor 604 is responsible for managing the bus 622 and general processing, including executing software stored on the computer-readable medium 606. The software, when executed by the processor 604, causes the system processor 602 to perform the various functions described below for any particular device. The computer-readable medium 606 and memory 608 may also be used to store data that is manipulated by the processor 604 when executing the software.

[0059] In some aspects, the processor 604 may be part of one or more processor cores of the system processor 602 and perform operations using its processing resources by virtue of the processor core executing software stored in the computer-readable medium 606. Software should be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside on the computer-readable medium 606. The processor 604 executes software stored in the computer-readable medium 606. Figure 1 or Figure 2 The system processor performs the operations, and as Figure 5 The status of the wake-up process 500 is shown.

[0060] Computer-readable medium 606 may be a non-transitory computer-readable medium. Examples of non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic tapes), optical disks (e.g., compact discs (CDs) or digital versatile discs (DVDs)), smart cards, flash memory devices (e.g., card, stick, or key-type drives), random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), registers, removable disks, and any other suitable medium for storing software or instructions that can be accessed and read by a computer. Computer-readable medium 606 may reside in system processor 602, be external to system processor 602, or be distributed across multiple entities including system processor 602. Computer-readable medium 606 may be embodied in a computer program product. For example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize how to best implement the described functionality presented throughout this disclosure, depending on the specific application and the overall design constraints imposed on the overall device.

[0061] Device 600 may be configured to perform any one or more of the operations described herein.In some aspects of the disclosure, processor 604 as utilized in device 600 may include circuitry configured for various functions.

[0062] Processor 604 may include system wake-up circuitry 640 to wake processor 604 from an idle state in response to a wake-up event. System wake-up circuitry 640 may include one or more hardware components that provide the physical structure for performing various processes associated with waking processor 604 from an idle state to an active state. System wake-up circuitry 640 may also include functionality for transitioning the processor from an active state to an idle state. System wake-up circuitry 640 may also be configured to execute system wake-up software (instructions) 660 included on computer-readable medium 606 to implement device wake-up as described herein.

[0063] The processor 604 may include a frame generation circuit 642 configured to generate new frames for use by the command mode display panel 614 as discussed herein when the processor is in an active state. The frame generation circuit 642 may also be configured to execute frame generation software (instructions) 662 included on the computer-readable medium 606 to implement the frame generation functionality described herein.

[0064] The system processor 602 and the processor 604 may include a video communication circuit 644 configured to perform operations as discussed herein to transmit a new frame from the system processor 602 to the command mode display panel 614 following a wake-up signal provided to the command mode display panel 614 via the bus 622. The video communication circuit 644 may also be configured to execute video communication software (instructions) 664 included on the computer-readable medium 606 to implement one or more functions described herein.

[0065] In addition to bus 622 and user interface 612, the command mode display panel is also directly connected via a wakeup connector 620. The wakeup connector is shown as being connected to sensor island 608 of system processor 602, but may also be connected to processor 604 or other idle state management circuitry of system processor 602. Wakeup connector 620 is a dedicated hardware connector that carries a wakeup signal directly to command mode display panel 614 during wakeup of system processor 602. The wakeup signal is a command to command mode display panel 614 to increase the frame rate of command mode display panel 614 to the active frame rate. In response to the wakeup signal, command mode display panel 614 is configured to increase the frame rate of the command mode display panel from the idle frame rate to the active frame rate, independent of the system processor state, without requiring communication via bus 622.

[0066] The circuit architecture described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described herein may also be manufactured using various process technologies, such as complementary metal oxide semiconductor (CMOS), NMOS, PMOS, bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistor (HBT), high electron mobility transistor (HEMT), silicon on insulator (SOI), etc.

[0067] The apparatus implementing the circuits described herein may be a standalone device or may be part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs that may include a memory IC for storing data and / or instructions, (iii) a radio frequency integrated circuit (RFIC) such as an RF receiver (RFR) or RF transmitter / receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) and the like.

[0068] Figure 7 is an example of a command mode display panel (such as Figure 2FIG2 is a flowchart showing an example of a method for hardware wakeup of a display panel 210 in command mode. The method may be performed by Figure 1 or Figure 2 The system processor Figure 4 is performed in the manner shown in Figure 5 status.

[0069] The method begins at block 702 by receiving a wakeup event at a system processor. The wakeup event may be received as input from at least one of a camera, a button, or an inertial reference system, and receiving the wakeup event is in response to receiving the input.

[0070] Waking up the system processor from the idle state to the active state is performed in block 704. The system processor may be in a power collapsed state or any other type of idle or low power state.

[0071] In block 706, the method continues by transmitting a wake-up signal during waking up the system processor. The wake-up signal is transmitted at an output of the system processor, the output being configured to couple to the command mode display panel. The wake-up signal is a command to the command mode display panel to increase the frame rate of the command mode display panel from an idle frame rate to an active frame rate. In some aspects, transmitting the wake-up signal is performed by setting a level on a pin of the system processor that is coupled to a hardware connection between the system processor and the display panel. In some aspects, the display panel is a command mode display panel, and transmitting the wake-up signal includes setting a general purpose input / output pin of a command mode interface of the display panel via a hardware connection. Transmitting the wake-up signal can be performed independently of and in parallel with waking up the system processor.

[0072] In some aspects, before receiving the wake-up signal, the display panel is in an idle state having an idle frame rate. In some aspects, the display panel repeatedly displays the same image at the idle frame rate.

[0073] Generating the new frame at the system processor is performed in optional block 708. In some aspects, generating the new frame is performed by a display processor unit of the system processor, and transmitting the new frame includes transmitting the new frame from the display processor unit.

[0074] In optional block 710 , transmitting a new frame from the system processor to the command mode display panel after asserting the wake-up signal is performed.

[0075] As used herein, "or" is intended to be interpreted as inclusive unless expressly stated otherwise. For example, "a or b" may include only a, only b, or a combination of a and b. As used herein, a phrase referring to "at least one of" or "one or more of" a list of items refers to any combination of those items, including individual items. For example, "at least one of a, b, or c" is intended to encompass the following examples: only a, only b, only c, a combination of a and b, a combination of a and c, a combination of b and c, and a combination of a, b, and c.

[0076] The various illustrative components, logical components, logical blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. This interchangeability of hardware, firmware, and software has been generally described in terms of their functionality and exemplified in the various illustrative components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the overall device.

[0077] The various illustrative logical blocks, modules, and circuits described in conjunction with the illustrative aspects disclosed herein may be implemented or executed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration.

[0078] In one or more exemplary aspects, the described functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or transmitted as one or more instructions or code stored on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. A storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a computer. Furthermore, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0079] Various modifications to the specific implementations described in this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other specific implementations without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the specific implementations shown herein but are to be accorded the widest scope consistent with this disclosure, the principles, and the novel features disclosed herein.

[0080] Additionally, various features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, individual features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable subcombination. Thus, although features may be described above as functioning in a particular combination and even initially claimed as such, one or more features from a claimed combination may in some cases be deleted from the combination, and a claimed combination may involve subcombinations or variations of subcombinations.

[0081] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring such operations to be performed in the particular order shown or in a sequential order, or to perform all illustrated operations to achieve the desired result. In addition, the accompanying drawings may schematically depict one or more example processes in the form of a flow chart or flow diagram. However, other operations not depicted may be incorporated into the example processes schematically illustrated. For example, one or more additional operations may be performed before, after, simultaneously, or between any of the illustrated operations. In some environments, multitasking and parallel processing may be advantageous. In addition, the separation of the various components in the specific implementation described above should not be understood as requiring such separation in all specific implementations, but it should be understood that the program components and systems described can usually be integrated together in a single software product, or be packaged into multiple software products.

[0082] The following provides an overview of various embodiments of the disclosure.

[0083] Embodiment 1: A method, the method comprising: receiving a wake-up event at a system processor; waking the system processor from an idle state to an active state; and transmitting a wake-up signal at an output of the system processor during the waking of the system processor, the output being configured to couple to a display panel, the wake-up signal being a command to the display panel to increase a frame rate of the display panel from an idle frame rate to an active frame rate.

[0084] Embodiment 2: The method according to embodiment 1 further comprising: generating a new frame at the system processor; and transmitting the new frame from the system processor to the display panel after transmitting the wake-up signal.

[0085] Embodiment 3: The method of Embodiment 2, wherein generating the new frame is performed by a display processor unit of the system processor, and wherein transmitting the new frame comprises transmitting the new frame from the display processor unit.

[0086] Embodiment 4: The method according to any one or more of embodiments 1 to 3, wherein before receiving the wake-up signal, the display panel is in an idle state with the idle frame rate.

[0087] Embodiment 5: The method according to embodiment 4, wherein the display panel repeatedly displays the same image at the idle frame rate.

[0088] Embodiment 6: The method of any one or more of embodiments 1 to 5, further comprising receiving input from at least one of a camera, a button, or an inertial reference system, and wherein receiving the wake event is in response to receiving the input.

[0089] Embodiment 7: The method of any one or more of Embodiments 1 to 6, wherein transmitting the wake-up signal comprises setting a level on a pin of the system processor, the pin coupled to a hardware connection between the system processor and the display panel.

[0090] Embodiment 8: The method of embodiment 7, wherein the display panel comprises a command mode display panel, and wherein transmitting the wake-up signal comprises setting a general purpose input / output pin of a command mode interface of the display panel through the hardware connection.

[0091] Embodiment 9: The method of any one or more of Embodiments 1 to 8, wherein transmitting the wake-up signal is performed independently and in parallel with waking up the system processor.

[0092] Embodiment 10: The method of any one or more of Embodiments 1 to 9, wherein the idle state of the system processor is a power collapse state.

[0093] Embodiment 11: A device comprising: a system processor, the system processor being configured to receive a wake-up event, the system processor being configured to wake up from an idle state to an active state in response to the wake-up event; and a wake-up connector, the wake-up connector being coupled to the system processor and being configured to couple to a display panel to transmit a wake-up signal to the display panel during the wake-up of the system processor from the idle state, the wake-up signal being a command to the display panel to increase a frame rate of the display panel from an idle frame rate to an active frame rate.

[0094] Embodiment 12: The apparatus of Embodiment 11, wherein the system processor is further configured to generate a new frame and transmit the new frame to the display panel after transmitting the wake-up signal.

[0095] Embodiment 13: The apparatus of Embodiment 12, wherein the system processor comprises a display processor unit, wherein the display processor unit is configured to generate the new frame.

[0096] Embodiment 14: The apparatus of any one or more of Embodiments 11 to 13, wherein the system processor comprises an application processor and a display processor unit.

[0097] Embodiment 15: The apparatus of any one or more of Embodiments 11 to 14, wherein prior to increasing the frame rate, the display panel is in an idle state having the idle frame rate.

[0098] Embodiment 16: The apparatus of any one or more of Embodiments 11 to 15, wherein the system processor is configured to avoid generating new frames in the idle state.

[0099] Embodiment 17: A device according to any one or more of embodiments 11 to 16, wherein the device also includes at least one of a camera, a button, or an inertial reference system, and wherein the wake-up event is in response to input from at least one of the camera, the button, or the inertial reference system.

[0100] Embodiment 18: The apparatus of any one or more of Embodiments 11 to 17, wherein the wake-up connector is coupled to a dedicated pin of the system processor, and wherein transmitting the wake-up signal comprises setting a level on the dedicated pin of the system processor between the system processor and the display panel.

[0101] Embodiment 19: The apparatus of Embodiment 18, wherein the dedicated pin is a general purpose input / output pin.

[0102] Embodiment 20: The apparatus of any one or more of Embodiments 11 to 19, wherein the idle state of the system processor is a power collapse state.

[0103] Embodiment 21: A non-transitory computer-readable medium having stored therein instructions for causing a system processor coupled to a command mode display panel to perform operations comprising: receiving a wake-up event at the system processor; waking the system processor from an idle state to an active state; and transmitting a wake-up signal at an output of the system processor during the wake-up of the system processor, the output being configured to be coupled to the display panel, the wake-up signal being a command to the display panel to increase a frame rate of the display panel from an idle frame rate to an active frame rate.

[0104] Embodiment 22: The medium of Embodiment 21, wherein transmitting the wake-up signal comprises setting a level on a pin of the system processor, the pin coupled to a hardware connection between the system processor and the display panel.

[0105] Embodiment 23: The medium of Embodiment 21 or 22, wherein transmitting the wake-up signal is performed before generating a new frame at the system processor.

Claims

1. A method comprising: receiving a wake event at a system processor; waking up the system processor from an idle state to an active state; as well as A wake-up signal is transmitted at an output of the system processor during the wake-up of the system processor, the output being configured to be coupled to a display panel, the wake-up signal being a command to the display panel to increase a frame rate of the display panel from an idle frame rate to an active frame rate.

2. The method according to claim 1, further comprising: generating a new frame at the system processor; as well as After transmitting the wake-up signal, the new frame is transmitted from the system processor to the display panel. 3 . The method of claim 2 , wherein generating the new frame is performed by a display processor unit of the system processor, and wherein transmitting the new frame comprises transmitting the new frame from the display processor unit. The method of claim 1 , wherein before receiving the wake-up signal, the display panel is in an idle state having the idle frame rate. The method of claim 4 , wherein the display panel repeatedly displays the same image at the idle frame rate. 6 . The method of claim 1 , further comprising receiving input from at least one of a camera, a button, or an inertial reference system, and wherein receiving the wake event is in response to receiving the input. 7 . The method of claim 1 , wherein transmitting the wake-up signal comprises setting a level on a pin of the system processor, the pin coupled to a hardware connection between the system processor and the display panel. 8 . The method of claim 7 , wherein the display panel comprises a command mode display panel, and wherein transmitting the wake-up signal comprises setting a general purpose input / output pin of a command mode interface of the display panel through the hardware connection.

9. The method of claim 1, wherein transmitting the wake-up signal is performed independently of and in parallel with waking up the system processor.

10. The method of claim 1, wherein the idle state of the system processor is a power collapse state.

11. A device comprising: a system processor configured to receive a wake-up event, the system processor configured to wake up from an idle state to an active state in response to the wake-up event; and a wakeup connector coupled to the system processor and configured to be coupled to a display panel to transmit a wakeup signal to the display panel during the wakeup of the system processor from the idle state, the wakeup signal being a command to the display panel to increase a frame rate of the display panel from an idle frame rate to an active frame rate. 12 . The apparatus of claim 11 , wherein the system processor is further configured to generate a new frame and transmit the new frame to the display panel after transmitting the wake-up signal.

13. The apparatus of claim 12, wherein the system processor comprises a display processor unit, wherein the display processor unit is configured to generate the new frame. The apparatus of claim 11 , wherein the system processor comprises an application processor and a display processor unit.

15. The apparatus of claim 11, wherein before increasing the frame rate, the display panel is in an idle state having the idle frame rate.

16. The apparatus of claim 11, wherein the system processor is configured to avoid generating new frames in the idle state.

17. The apparatus of claim 11, further comprising at least one of a camera, a button, or an inertial reference system, and wherein the wake event is in response to input from at least one of the camera, the button, or the inertial reference system.

18. The apparatus of claim 11, wherein the wake-up connector is coupled to a dedicated pin of the system processor, and wherein transmitting the wake-up signal comprises setting a level on the dedicated pin of the system processor between the system processor and the display panel. The apparatus of claim 18 , wherein the dedicated pin is a general purpose input / output pin.

20. The apparatus of claim 11, wherein the idle state of the system processor is a power collapse state.

21. A non-transitory computer-readable medium having stored therein instructions for causing a system processor coupled to a command mode display panel to perform operations comprising: receiving a wake event at the system processor; waking up the system processor from an idle state to an active state; as well as A wake-up signal is transmitted at an output of the system processor during the wake-up of the system processor, the output being configured to be coupled to a display panel, the wake-up signal being a command to the display panel to increase a frame rate of the display panel from an idle frame rate to an active frame rate.

22. The medium of claim 21, wherein transmitting the wake-up signal comprises setting a level on a pin of the system processor, the pin coupled to a hardware connection between the system processor and the display panel.

23. The medium of claim 21, wherein transmitting the wake-up signal is performed before generating a new frame at the system processor.

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