Chip testability design method, electronic device and computer readable storage medium

Abstract

The application discloses a chip testability design method, an electronic device and a computer readable storage medium, relates to the field of integrated circuit design and test technology, and the chip testability design method comprises the steps of obtaining a plurality of test items of a chip, wherein the plurality of test items at least include a first test item and a second test item, the first test item is a test item for a first module group of the chip, the second test item is a test item for a second module group of the chip, and the first module group is different from the second module group; the test parameters of the first test item are configured through a JTAG port, and a first main running stage corresponding to the first test item is entered; during the running of the first main running stage, the test parameters of the second test item are configured through the JTAG port, and a second main running stage corresponding to the second test item is entered. The application can shorten the test time and reduce the test cost.

Description

Technical Field

[0001] This application relates to the fields of integrated circuit design and testing technology, and in particular to chip testability design methods, electronic devices, and computer-readable storage media. Background Technology

[0002] With the rapid development of information technology, large-scale integration (LSI) is increasingly widely used in modern society. These highly integrated circuit systems are not only characterized by their diverse functions, but also by their stringent requirements for performance, reliability, and cost-effectiveness. As an indispensable part of ensuring chip quality, design for testability (DFT) technology has seen significant development and application in recent years.

[0003] DFT technology primarily includes several methods such as SCAN (scan chain) technology, Memory Built-In Self-Test (MBIST), and Intellectual Property Core Testing (IPTEST), which work together to ensure the reliability of LSI products. SCAN technology transforms the circuit into a scannable shift register chain, achieving controllability and observability of the internal state, greatly simplifying the testing process. MBIST is specifically designed for on-chip memory, using embedded test algorithms to achieve self-testing, improving testing efficiency and reducing dependence on external test equipment. IPTEST is mainly used to verify the functional correctness of each independent IP (Intellectual Property) core in the integrated circuit, ensuring the stable operation of the overall system.

[0004] However, with the continuous expansion of chip scale and the increasing market demands for product quality standards, traditional DFT technology faces new challenges. To comprehensively cover all possible fault points within the chip, a large number of test parameters (SCAN vectors) need to be generated during the testing process. The number of these vectors grows exponentially with chip scale, directly leading to increased testing time and costs, becoming a key bottleneck restricting further improvements in integrated circuit testing efficiency. Therefore, how to shorten testing time and reduce testing costs while ensuring chip testing quality and coverage has become an urgent technical problem to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a chip testability design method, electronic device, and computer-readable storage medium, aiming to solve the technical problem of how to shorten testing time and reduce testing costs while ensuring chip testing quality and coverage.

[0006] To achieve the above objectives, this application provides a chip testability design method, comprising: Multiple test items are obtained for the chip, wherein the multiple test items include at least a first test item and a second test item, the first test item is a test item for a first module group of the chip, and the second test item is a test item for a second module group of the chip, wherein the first module group is different from the second module group; The test parameters of the first test item are configured through the JTAG port, and the first main running stage corresponding to the first test item is entered. The first main running stage is used to generate the first test result information corresponding to the first test item. During the first main body operation phase, the test parameters of the second test item are configured through the JTAG port, and the second main body operation phase corresponding to the second test item is entered. The second main body operation phase is used to generate the second test result information corresponding to the second test item.

[0007] Furthermore, to achieve the above objectives, this application also provides a chip testability design method, comprising: Obtain multiple test items for the chip, wherein the multiple test items include at least a third IP test item and a fourth IP test item, wherein the third IP test item is an IP test item for a first module of the chip, and the fourth IP test item is an IP test item for a second module of the chip, wherein the IP test type of the third IP test item is the same as the IP test type of the fourth IP test item; The test parameters of the third IP test item and the fourth IP test item are configured in parallel through signal broadcasting via the JTAG port, and the third main body operation phase corresponding to the third IP test item and the fourth main body operation phase corresponding to the fourth IP test item are entered. The third main body operation phase is used to generate the third test result information corresponding to the third IP test item, and the fourth main body operation phase is used to generate the fourth test result information corresponding to the fourth IP test item.

[0008] In addition, to achieve the above objectives, this application also provides an electronic device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the chip testability design method as described above.

[0009] In addition, to achieve the above objectives, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the chip testability design method as described above.

[0010] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the chip testability design method as described above.

[0011] Given the aforementioned background, there is still significant room for improvement in chip design-for-test technology. A method that can both guarantee test quality and efficiently shorten test time is needed, which is crucial for promoting the sustainable development of the semiconductor industry. Based on this, the applicant has devoted considerable time and effort to numerous experiments. Through these experiments, research has revealed that by cleverly utilizing the principle that the JTAG port is idle during the main operation phase of a test item (statistics show that the main operation phase is much longer than the configuration and observation time), the applicant can fully leverage the idle time of the JTAG port during the main operation phase to configure test parameters for other test items. This enables parallel testing of multiple test items' test vectors, thus rationally utilizing the idle time of the JTAG network, reducing the total execution time of all test parameters, and saving testing costs on ATE (Automatic Test Equipment) machines.

[0012] In DFT testing techniques, IP testing only utilizes the JTAG port during configuration and observation. During the main testing phase, the chip operates internally, and the JTAG port remains idle. SCAN, on the other hand, only requires the JTAG port during the configuration phase. During the main testing phase (i.e., the main operation phase), the chip's SCAN in and SCAN out paths are used. Based on this, this application provides a chip testability design method, an electronic device, and a computer-readable storage medium. The technical solution of this application involves acquiring multiple test items of the chip, wherein the multiple test items include at least a first test item and a second test item. The first test item is for a first module group of the chip, and the second test item is for a second module group of the chip. The first module group is distinct from the second module group. The test parameters of the first test item are configured through the JTAG port, and the first main operation phase corresponding to the first test item is entered. The first main operation phase is used to generate the first test result information corresponding to the first test item. During the operation of the first main operation phase, the test parameters of the second test item are configured through the JTAG port, and the second main operation phase corresponding to the second test item is entered. In this embodiment, the second main operation phase is used to generate the second test result information corresponding to the second test item. This allows the embodiment to make full use of the idle time of the JTAG port, reducing the time wasted due to the need to test each test item serially and waiting in a queue for processing. Since most of the wasted test time is the duration of the main operation phase of each test item, this embodiment cleverly utilizes the idle state of the JTAG port during the main operation phase to configure test parameters for other test items through the JTAG port. This enables parallel testing of test vectors for multiple test items, saving test costs on the ATE machine, improving the utilization rate of the ATE machine, and effectively solving the technical problem of how to shorten test time and reduce test costs while ensuring chip test quality and coverage. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0015] Figure 1A flowchart illustrating the first embodiment of the chip testability design method of this application; Figure 2 A flowchart illustrating the second embodiment of the chip testability design method of this application; Figure 3 This is a schematic diagram of the overall circuit structure of the DFT parallel measurement technology in a specific embodiment of this application; Figure 4 This is a schematic diagram of IPTEST serial test to parallel test conversion in a specific embodiment of this application; Figure 5 This is a schematic diagram of the conversion of the same IPTEST serial test to broadcast parallel test in a specific embodiment of this application; Figure 6 This is a schematic diagram illustrating the conversion of SCAN test and IPTEST serial test to parallel test in a specific embodiment of this application; Figure 7 This is a schematic diagram of the device structure of the hardware operating environment involved in the chip testability design method in the embodiments of this application.

[0016] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0017] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0018] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0019] In traditional DFT technology, all test items must be executed sequentially, and the test mode is serial testing. Each test item must wait for the previous test item to complete its main operation phase before it can start configuration. The JTAG port responsible for configuration is idle during the main operation of different test items and is not effectively utilized, resulting in a long test process and high testing costs on ATE.

[0020] To address this, the applicant devoted considerable time and effort to numerous experiments. Through these experiments, the research revealed that by cleverly utilizing the principle that the JTAG port is idle during the main operation phase of the test items (statistics showed that the duration of the main operation phase is much longer than the configuration and observation time), the applicant could fully leverage the idle time of the JTAG port during the main operation phase to configure test parameters for other test items. This would enable parallel testing of test vectors for multiple test items, thereby making reasonable use of the idle time of the JTAG network, reducing the total time for all test parameters to run, and saving testing costs on the ATE (Automatic Test Equipment) equipment.

[0021] Based on this, this application provides a solution: obtaining multiple test items of a chip, wherein the multiple test items include at least a first test item and a second test item, the first test item being a test item for a first module group of the chip, and the second test item being a test item for a second module group of the chip, the first module group being distinct from the second module group; configuring the test parameters of the first test item through a JTAG port and entering a first main running stage corresponding to the first test item, wherein the first main running stage is used to generate first test result information corresponding to the first test item; during the operation of the first main running stage, configuring the test parameters of the second test item through the JTAG port and entering a second main running stage corresponding to the second test item, wherein the second main running stage is used to generate second test result information corresponding to the second test item.

[0022] This application embodiment can make full use of the idle time of the JTAG port, reducing the time wasted due to the need to test each test item serially and waiting in a queue for processing. Since most of the wasted test time is mainly the main running phase of each test item, this embodiment cleverly utilizes the idle state of the JTAG port during the main running phase to configure test parameters for other test items through the JTAG port, thereby realizing parallel testing of test vectors for multiple test items, saving test costs on the ATE machine, improving the utilization rate of the ATE machine, and effectively solving the technical problem of how to shorten test time and reduce test costs while ensuring chip test quality and coverage.

[0023] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] This application proposes a chip testability design method according to a first embodiment.

[0025] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the chip testability design method of this application.

[0026] In this embodiment, the chip testability design method includes steps S100~S300: Step S100: Obtain multiple test items for the chip, wherein the multiple test items include at least a first test item and a second test item. The first test item is a test item for the first module group of the chip, and the second test item is a test item for the second module group of the chip. The first module group is different from the second module group. It should be noted that in the design process of large-scale integrated circuits, chips are typically divided into many modules, each of which is a relatively independent logic unit or physical region within the chip. During chip testing, all modules can be flexibly divided into several module groups as required, with each module group containing at least one module.

[0027] In this embodiment, the chip's multiple modules are divided into at least a first module group and a second module group, and the first module group and the second module group do not have any common modules. This ensures that the first module group is distinct from the second module group, so as to avoid the situation where the same module executes multiple test items simultaneously during parallel testing, which could lead to I / O (Input / Output) conflicts.

[0028] As those skilled in the art will recognize, in DFT technology, test items refer to test tasks designed for the function or structure of internal modules of a chip. These are mainly divided into IP test items and SCAN test items. IP test items are test tasks that use IPTEST technology to perform functional verification of the chip's internal IP cores, while SCAN test items are test tasks that use SCAN technology to perform structural testing of the chip's internal circuitry. Both IP test items and SCAN test items can be divided into a configuration phase, a main operation phase, and a signal observation phase. The configuration phase refers to the process of configuring test parameters. Test parameters are parameter variables that need to be pre-configured on the module under test during the test process, mainly including test vectors, clock frequency, voltage thresholds, timing constraints, and fault coverage targets. The test vector includes the input stimulus signal and the corresponding expected output response. The main operation phase refers to the process of running the test logic and outputting the test results. The test logic refers to the internal self-test logic that needs to be executed on the module under test during the test process, and the test result refers to the output response obtained by the module under test running the test logic under the configured test parameters. The signal observation phase refers to the process of observing the test results. By comparing the test results with the expected output response in the test vector, it can be determined whether the module under test has functional defects, performance deviations, or abnormal electrical characteristics.

[0029] Step S200: Configure the test parameters of the first test item through the JTAG port and enter the first main body running stage corresponding to the first test item. The first main body running stage is used to generate the first test result information corresponding to the first test item. Step S300: During the operation of the first main body operation phase, the test parameters of the second test item are configured through the JTAG port, and the second main body operation phase corresponding to the second test item is entered. The second main body operation phase is used to generate the second test result information corresponding to the second test item.

[0030] It should be noted that the JTAG (Joint Test Action Group) port is a test access port, whose functions include at least the configuration of test parameters and the reading back of test results (i.e., the observation of test results).

[0031] It should also be noted that, in this embodiment, the first main execution stage refers to the main operation stage corresponding to the first test item, the second main execution stage refers to the main operation stage corresponding to the second test item, the first test result information refers to the test result generated by the first module group after executing the first main operation stage, and the second test result information refers to the test result generated by the second module group after executing the second main operation stage.

[0032] As those skilled in the art will know, the IP test items only utilize the JTAG port for configuring test parameters and reading back test results during the configuration and signal observation phases. During the main operation phase, the JTAG port is not required for signal transmission; the test logic is run autonomously by relying solely on the internal circuitry of the chip. In contrast, the SCAN test items only require the JTAG port during the configuration phase. During the main operation phase, the chip's SCAN in / SCAN out ports are used. Therefore, the JTAG port is idle during the main operation phase corresponding to each test item.

[0033] In traditional serial testing, all test items must be executed sequentially. That is, the JTAG port can only begin configuring the test parameters for the next test item after the previous test item has completed its parameter configuration, main operation, and result observation. Since the main operation phase typically accounts for more than 80% of the total test time (e.g., long-cycle computations in functional testing or large-scale shift operations in SCAN testing), the JTAG port is idle for most of the time in traditional serial testing, resulting in lengthy overall test times, low ATE equipment utilization, and high test costs.

[0034] To address this, this embodiment identifies and utilizes the idle time window of the JTAG port during the first main operation phase, embedding the test parameter configuration of the second test item into the main operation phase of the first test item. This achieves spatiotemporal decoupling between the test parameter configuration of the second test item and the test logic operation of the first test item, thereby eliminating the waste of JTAG port idleness caused by waiting for the entire process of the previous test item to be completed before the test parameter configuration of the next test item in the traditional serial testing mode. This enables parallel testing of the loaded test vectors in the main operation phases of multiple test items, saving testing costs on the ATE equipment, improving the utilization rate of the ATE equipment, and effectively solving the technical problem of how to shorten testing time and reduce testing costs while ensuring chip testing quality and coverage.

[0035] In this embodiment, before entering the first main body operation stage corresponding to the first test item in step S200, the chip testability design method may further include step A10: Step A10: Isolate other SCAN signals and / or other IP TEST signals through the JTAG network. Isolation is used to prevent other SCAN signals and / or other IP TEST signals from affecting the test results corresponding to each test item. Among them, the other SCAN signals are SCAN signals that are unrelated to each test item, and the other IP TEST signals are IP TEST signals that are unrelated to each test item.

[0036] It should be noted that the JTAG network refers to a test access path built through the JTAG protocol, used for debugging and testing the internal or external interfaces of a chip. It allows access to the internal state of the chip and the execution of configuration, testing, and diagnostic tasks without interfering with the normal operation of the system.

[0037] It is important to note that the JTAG port is the specific hardware interface that implements the JTAG function and is used to connect external test equipment (such as ATE equipment) to the inside of the chip. The JTAG network, on the other hand, is an interconnected test environment created using the JTAG port and the JTAG protocol. That is, in design for testability, external test equipment sends commands and data through the JTAG port, which are then transmitted to the internal modules of the chip via the JTAG network.

[0038] It should also be noted that SCAN signals refer to the signals used during the SCAN test, including control signals such as SCAN in (scan input), SCAN out (scan output), and SCAN enable (scan enable). IP TEST signals refer to the signals used during the IPTEST process, involving test stimuli and responses specific to a particular IP core, used to verify the functional correctness of that IP core.

[0039] This embodiment improves the accuracy and reliability of test results by using the JTAG network to isolate other SCAN signals and / or other IP TEST signals unrelated to each test item before entering the first main body operation phase corresponding to the first test item.

[0040] It is worth mentioning that the specific isolation methods can be clamping other SCAN signals and / or other IP TEST signals, or inserting wrapper cells into other SCAN signals and / or other IP TEST signals. Those skilled in the art have already studied this extensively, and this embodiment will not elaborate on it further.

[0041] In one feasible implementation, the first test item is a first IP test item, the second test item is a second IP test item, and the chip testability design method may further include step S410 or step S420: Step S410: If the first main body running phase is completed before the second main body running phase, during the running period of the second main body running phase after the first main body running phase is completed, the generated first test result information is observed through the JTAG port. Alternatively, in step S420, if the second main running phase finishes before the first main running phase, during the period when the second main running phase has finished and the first main running phase is in progress, the generated second test result information is observed through the JTAG port.

[0042] It should be noted that the first IP test item is for the first module group of the chip, and the second IP test item is for the second module group of the chip.

[0043] In this embodiment, both the first test item and the second test item are IP test items. Therefore, in the signal observation phase corresponding to each of the first test item and the second test item, the test results need to be observed through the JTAG port.

[0044] Because IP cores are diverse, including but not limited to DDR (Double Data Rate), SerDes (Serializer / Deserializer), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express), GEPHY (Gigabit Ethernet Physical layer), POR (Power-On Reset), PVT-Sensor (Process, Voltage, and Temperature Sensor), and PLL (Phase-Locked Loop), the types of IP test items (also known as IP test types) required for functional testing of different types of IP cores also differ, and the main operating phases corresponding to each type of IP test item vary in length.

[0045] Therefore, this implementation dynamically adjusts the order in which the test results of each IP test item are observed through the JTAG port according to the completion order of the main operation phase corresponding to each IP test item, that is, according to the generation order of the test results corresponding to each IP test item. Thus, when the main operation phase corresponding to a certain IP test item finishes first and generates the corresponding test result, the idle time window of the JTAG port while other test items are still in the main operation phase is utilized to observe the test result corresponding to the first completed IP test through the JTAG port. This fully utilizes the idle time period of the JTAG port, embedding the signal observation phase of the IP test item that finishes its main operation phase first into the main operation phase of the IP test item that finishes its main operation phase later. This significantly reduces the time wasted by the IP test item that finishes its main operation phase later while waiting for the IP test item that finishes its main operation phase earlier to complete the test result observation, achieving the effect of spatiotemporal decoupling, reducing resource conflicts on the JTAG port during the signal observation phase of each IP test item, thereby improving the utilization rate of the JTAG port, significantly shortening the overall test time, and reducing the test cost of the ATE equipment.

[0046] In another feasible implementation, the first test item is the SCAN test item, the second test item is the second IPtest test item, and the chip testability design method may further include step S430: Step S430: If the second main running phase is completed before the first main running phase, during the running period of the first main running phase after the second main running phase is completed, the generated second test result information is observed through the JTAG port.

[0047] In this embodiment, the first test item is the SCAN test item, whose corresponding signal observation phase does not require observation of test results through the JTAG port. The second test item is the IP test item, which requires observation of test results through the JTAG port during the signal observation phase. Therefore, this embodiment combines the characteristics of the SCAN and IP test items, cleverly utilizing the different requirements of different types of test items for JTAG port usage at different stages. When the main operation phase of the IP test item finishes first, the signal observation phase of the IP test item is embedded into the main operation phase of the SCAN test item. This fully utilizes the idle time of the JTAG port, completes the signal observation phase of the IP test item as early as possible, reduces the idle time of JTAG port resources, improves the utilization rate of the ATE equipment, and makes the overall test process more compact and efficient. In this way, while ensuring test coverage and test quality, test costs are reduced and test efficiency is improved.

[0048] In another feasible implementation, the first test item is a first IP test item, the second test item is a SCAN test item, and the chip testability design method may further include step S440: Step S440: If the first main body running phase is completed before the second main body running phase, during the running period of the second main body running phase after the first main body running phase is completed, the generated first test result information is observed through the JTAG port.

[0049] In one example, if the second main execution phase finishes before the first main execution phase, no processing is performed during the execution of the first main execution phase after the second main execution phase has finished. Then, the generated first test result information is observed through the JTAG port when the first main execution phase has finished.

[0050] In this embodiment, the second test item is the SCAN test item, whose corresponding signal observation phase does not require observation of test results through the JTAG port. The first test item is the IP test item, which requires observation of test results through the JTAG port during the signal observation phase. Therefore, this embodiment combines the characteristics of the SCAN and IP test items, cleverly utilizing the different requirements of different types of test items for JTAG port usage at different stages. When the main operation phase of the IP test item finishes first, the signal observation phase of the IP test item is embedded into the main operation phase of the SCAN test item. This fully utilizes the idle time of the JTAG port, completes the signal observation phase of the IP test item as early as possible, reduces the idle time of JTAG port resources, improves the utilization rate of the ATE equipment, and makes the overall test process more compact and efficient. In this way, while ensuring test coverage and test quality, test costs are reduced and test efficiency is improved.

[0051] It is worth mentioning that when the chip has few test items to complete, and the test parameter configuration for all test items can be completed before the main operation phase corresponding to any test item ends, the test results of each test item can be observed sequentially according to the ending order of the main operation phase corresponding to each test item after the test parameter configuration is completed. Alternatively, the observation order of the test results of each test item can be determined in advance according to the importance and urgency of each test item, and then the test results of each test item can be observed sequentially according to the predetermined observation order in actual application.

[0052] For example, when the chip needs to complete IP test items including IP test item a for module group A, IP test item b for module group B, and IP test item c for module group C, the configuration phase corresponding to a takes 1 second, the configuration phase corresponding to b takes 2 seconds, the configuration phase corresponding to c takes 3 seconds, the main operation phase corresponding to a takes 10 seconds, the main operation phase corresponding to b takes 12 seconds, and the main operation phase corresponding to c takes 15 seconds. After completing the configuration phases of a, b, and c sequentially in 6 seconds, the main operation phase corresponding to each IP test item has not yet ended. That is, the chip needs to complete fewer test items, and the test parameter configuration of all test items can be completed before the main operation phase corresponding to any one test item ends. At this time, it can be configured according to each IP... The test results of each test item are observed sequentially based on the completion order of its main running phase. For example, if the main running phase corresponding to test item 'a' ends at 11 seconds, but the main running phases corresponding to test items 'b' and 'c' have not yet ended, the signal observation phase corresponding to test item 'a' is immediately entered through the JTAG port. This aims to end the signal observation phase corresponding to test item 'a' before the main running phases corresponding to test items 'b' end, and vice versa. Similarly, when the signal observation phase corresponding to test item 'a' ends and the main running phase corresponding to test item 'b' begins, the signal observation phase corresponding to test item 'b' is immediately entered through the JTAG port, aiming to end the signal observation phase corresponding to test item 'b' before the main running phase corresponding to test item 'c' ends. This maximizes the use of the JTAG port's idle time to complete the configuration of test parameters and the observation of test results.

[0053] In addition, when there are many tests that the chip needs to complete, and the main operation phase corresponding to a certain IP test item has been completed, but some test items have not yet been configured with test parameters, you can choose to first complete the test parameter configuration of the remaining test items through the JTAG port, and then observe the test results of the IP test items whose main operation phase has been completed through the JTAG port. Alternatively, you can choose to first observe the test results of the IP test items whose main operation phase has been completed through the JTAG port, and then go back to complete the test parameter configuration of the remaining test items through the JTAG port. This application proposes a chip testability design method according to a second embodiment.

[0054] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating the second embodiment of the chip testability design method of this application.

[0055] In the second embodiment of this application, the same or similar content as in the above embodiments can be referred to the above description, and will not be repeated hereafter.

[0056] In this embodiment, the chip testability design method may include steps S500~S600: Step S500: Obtain multiple test items of the chip, wherein the multiple test items include at least a third IP test item and a fourth IP test item. The third IP test item is an IP test item for the first module of the chip, and the fourth IP test item is an IP test item for the second module of the chip. The IP test type of the third IP test item is the same as the IP test type of the fourth IP test item. In this embodiment, the first module includes a first IP core, the second module includes a second IP core, the third IP test item is actually an IP test item for the first IP core, and the fourth IP test item is actually an IP test item for the second IP core. Since the first IP core and the second IP core are different IP cores of the same type, the IP test type of the third IP test item and the fourth IP test item are the same, the required test parameters are also the same, and they can be configured in parallel through signal broadcasting.

[0057] It is worth mentioning that, in this embodiment, the first module and the second module can be the same module or different modules.

[0058] Step S600: Configure the test parameters of the third IP test item and the fourth IP test item in parallel through the signal broadcasting method of the JTAG port, and enter the third main body operation stage corresponding to the third IP test item and the fourth main body operation stage corresponding to the fourth IP test item. The third main body operation phase is used to generate the third test result information corresponding to the third IP test item, and the fourth main body operation phase is used to generate the fourth test result information corresponding to the fourth IP test item.

[0059] As those skilled in the art will recognize, signal broadcasting refers to a technical method in testing or communication systems where the same information or instructions are simultaneously sent to multiple target devices or modules through a common channel (such as a JTAG port). In this mode, information is not transmitted one-to-one to a specific target, but rather broadcast, and all receivers connected to the common channel can receive the same information. This method can significantly improve data transmission efficiency, especially when the same operation needs to be performed on multiple similar devices or modules.

[0060] In this embodiment, since the first IP core and the second IP core are of the same type, and the third IP test item and the fourth IP test item have the same IP test type, the same test parameters can be used for configuration during the configuration phase of the third IP test item and the fourth IP test item. Furthermore, the test parameters for the third IP test item and the fourth IP test item can be configured simultaneously via JTAG port signal broadcasting, enabling parallel execution of the configuration phases for multiple test items. This avoids configuring the test parameters for each test item sequentially, significantly reducing the total time required for configuring the test parameters for each test item during the entire chip testing process, thereby significantly improving testing efficiency and reducing testing costs.

[0061] It is easy to understand that when multiple (two or more) IP cores of the same type need to execute the same IP test items, the test parameters of each IP test item can be configured in parallel through the signal broadcasting method of the JTAG port, thereby executing the configuration phase of multiple IP test items in parallel.

[0062] In this embodiment, before entering the third main body operation stage corresponding to the third IP test item and the fourth main body operation stage corresponding to the fourth IP test item in step S600, the chip testability design method may further include step B10: Step B10: Isolate other SCAN signals and / or other IP TEST signals through the JTAG network. Isolation is used to prevent other SCAN signals and / or other IP TEST signals from affecting the test results corresponding to each test item. Among them, the other SCAN signals are SCAN signals that are unrelated to each test item, and the other IP TEST signals are IP TEST signals that are unrelated to each test item.

[0063] Before entering the main operation phase corresponding to each test item, this embodiment isolates other SCAN signals and / or other IP TEST signals unrelated to each test item through the JTAG network. This ensures that the ongoing test item is not affected by other unrelated signals, thereby improving the accuracy and reliability of the test results.

[0064] In one feasible implementation, after step S600, which involves entering the third main body operation stage corresponding to the third IP test item and the fourth main body operation stage corresponding to the fourth IP test item, the chip testability design method may further include step S710: Step S710: After the third and fourth main body operation phases are completed, the generated third and fourth test result information is observed through the JTAG port.

[0065] In this embodiment, since the IP test type of the first IP test item is the same as that of the second IP test item, and the same test parameters are configured in parallel through signal broadcasting, this means that the main operation phases corresponding to each test item start almost simultaneously and have basically the same duration. Correspondingly, the main operation phases corresponding to each test item also end almost simultaneously. Therefore, there will inevitably be resource contention for the JTAG port during the signal observation phase of each test item, making it impossible to embed the signal observation phase of this test item into the main operation phase of another test item.

[0066] Therefore, this embodiment can perform serial observation of the test results of each test item through the JTAG port in a serial observation manner, or it can improve the hardware circuit structure so that the JTAG port can observe the test results of each test item in parallel, or it can compress the signal to observe the test results of each test item in parallel through the JTAG port. As for the specific hardware circuit structure improvement method and signal compression method, those skilled in the art have already studied them to some extent, and this embodiment will not elaborate on them in detail.

[0067] It is worth mentioning that, through the two embodiments described above, this application can achieve parallelism between IP test items and IP test items, parallelism between IP test items and SCAN test items, and broadcast parallelism between IP test items and IP test items of the same type among different module groups. Furthermore, by combining the solutions of the two embodiments, a solution can be obtained where IP test items in different module groups are parallel to each other, and IP test items are also parallel to SCAN test items, or even broadcast parallelism of IP test items of the same IP test type within the same module group. For example, the first IP test item in module group A is parallel to the second IP test item in module group B, and the SCAN test item in module group C. Simultaneously, within module group A, each module executes the first IP test item synchronously through broadcast parallelism. Within module group B, each module executes the second IP test item synchronously through broadcast parallelism.

[0068] To facilitate understanding of the technical concept or principle of the chip testability design method described in the above embodiments of this application, a specific embodiment is provided: Large-scale integrated circuit chips contain multiple modules, some of which may contain IP cores, such as DDR, SerDes, PCIe, USB, GEPHY, POR, PVT-Sensor, PLL, etc. IPTEST-related signals (i.e., IPTEST signals) are generally controlled by a JTAG network. The entire IPTEST process includes a configuration phase, a main operation phase, and a signal observation phase. The configuration and signal observation phases require the use of the JTAG network, while the main operation phase involves the internal logic operations of the IP core. This phase requires no configuration and only requires waiting; therefore, the JTAG network is idle during this time.

[0069] As shown in Table 1, in IPTEST, the configuration and signal observation phases require the use of a JTAG network, and these two phases account for a very small percentage of the total time in IPTEST. However, the main operation phase does not require a JTAG network, yet it takes a considerable amount of time to wait for the IP cores to complete. Table 1:

[0070] Each module in a large-scale integrated circuit chip contains SCAN logic. The control signals of the SCAN logic (i.e., SCAN signals), such as mode signals and reset signals, are also controlled by the JTAG network. The entire process of SCAN testing also includes a configuration phase, a main operation phase, and a signal observation phase. The difference is that the configuration phase of SCAN testing requires the use of the JTAG network, while the main operation phase and the signal observation phase use the SCAN in / SCAN out ports and do not require the use of the JTAG network.

[0071] As shown in Table 2, in the SCAN test, only the configuration phase requires the use of the JTAG network, and the configuration phase accounts for a very small percentage of the total time in the entire SCAN test. The main operation phase, however, does not require the JTAG network, yet it takes a considerable amount of time to wait for the SCAN logic to complete. Table 2:

[0072] Since both IPTEST and SCAN tests only utilize the JTAG network for a portion of the time, with the JTAG network idle for most of the time, testing multiple IPTEST vectors (i.e., test vectors for IP test items) in parallel on the ATE machine, or testing IPTEST vectors and SCAN vectors (i.e., test vectors for SCAN test items) in parallel, can make good use of the JTAG network's idle time, reduce the total running time of all test vectors, and save testing costs on the ATE machine.

[0073] In this specific embodiment, the specific implementation scheme can be divided into the following items: (1) Parallel testing between IPTEST and IPTEST (i.e., parallel testing of IP test items). (2) Parallel testing of the same type of IP test (i.e., IP test items of the same type of IP test are tested in parallel through signal broadcasting). (3) Parallel testing between IPTEST and SCAN tests (i.e., parallel testing of IP test items and SCAN test items).

[0074] like Figure 3 As shown, a medium-sized chip contains multiple modules, which may contain IP cores. The IPTEST signals include: clock signal, reset signal, IPTEST mode signal, JTAG interface signal, and other control signals (i.e., other IPTEST signals). In IPTEST, except for the clock signal which is generated by the PLL, the reset signal, IPTEST mode signal, and JTAG interface signal are all controlled by the JTAG network. Other control signals from the module interface also need to be isolated in IPTEST mode through the JTAG network (that is, other IP TEST signals are isolated through the JTAG network to prevent them from affecting the test results of each test item). Specific isolation methods include clamping other control signals or inserting wrapper cells for other control signals, etc.

[0075] Each module also contains SCAN logic. Figure 1 The SCAN test shown employs a multi-chain SCAN test approach. SCAN signals include: SCAN in / SCAN out signals, SCAN mode signals, reset signals, clock signals, and other control signals (i.e., other SCAN signals). Similarly, in the SCAN test, the clock signal is generated by the PLL, while the reset and SCAN mode signals are controlled by the JTAG network. Other control signals from the module interface also need to be isolated in SCAN mode via the JTAG network (i.e., other SCAN signals are isolated via the JTAG network to prevent them from affecting the test results of each test item). Specific isolation methods include clamping other control signals or inserting wrapper cells for them. Unlike the JTAG interface signals in the IP core, the SCAN in / SCAN out signals in the SCAN logic are not controlled by the JTAG network.

[0076] In parallel testing of IPTEST and IPTEST, such as Figure 4As shown, the original IPTESTs were all serial tests. This specific implementation modifies them so that the configuration phase of different IPTESTs is serial, the main operation waiting phase (i.e., the main operation phase) is parallel, and the signal observation phase is serial. Thus, when the previous IPTEST is in the main operation waiting phase, the configuration phase of the next IPTEST is embedded, and when the main operation phase of the previous IPTEST ends and the next IPTEST is still in the main operation waiting phase, the signal observation phase of the previous IPTEST is embedded. This makes full use of the time when JTAG is idle in the main operation waiting phase to achieve parallel main operation waiting phases of each IPTEST.

[0077] In other words, the test parameters of the first IP test item are configured through the JTAG port, and the system enters the first main running phase corresponding to the first IP test item; during the operation of the first main running phase, the test parameters of the second IP test item are configured through the JTAG port, and the system enters the second main running phase corresponding to the second IP test item; if the first main running phase completes before the second main running phase, the system observes the first test result information corresponding to the first IP test item through the JTAG port during the operation of the second main running phase after the first main running phase has completed; or, if the second main running phase completes before the first main running phase, the system observes the second test result information corresponding to the second IP test item through the JTAG port during the operation of the first main running phase after the second main running phase has completed.

[0078] In the same type of IPTEST broadcast parallel test, such as Figure 5 As shown, if the same type of IP is instantiated multiple times and the design complexity is acceptable, this specific embodiment can use JTAG broadcasting to conduct parallel broadcast testing of the same type of IP testets. Specifically, during the configuration phase, the test parameters are simultaneously broadcast to all IP cores of the same type via JTAG broadcasting, achieving parallel configuration of the same type of IP testets and causing all IP cores of the same type to synchronously enter the main operation waiting phase, achieving parallel main operation waiting phase of the same type of IP testets. Finally, by compressing the test results of each IP testet, the signal observation phase of the same type of IP testets is achieved in parallel, or serial observation is maintained.

[0079] In other words, the test parameters of the third IP test item and the fourth IP test item are configured in parallel through the signal broadcasting method of the JTAG port, and the third main body operation phase corresponding to the third IP test item and the fourth main body operation phase corresponding to the fourth IP test item are entered. After the execution of the third main body operation phase and the fourth main body operation phase are completed, the generated third test result information and fourth test result information are observed through the JTAG port.

[0080] In parallel testing of IPTEST and SCAN tests, such as Figure 6 As shown, the original SCAN and IPTEST tests were serial tests. This implementation modifies them as follows: First, the configuration phase of the SCAN test is completed using the JTAG port, followed by the main SCAN test phase. At this point, the JTAG port can be used for the IPTEST configuration phase. It's easy to understand that in the parallel testing of IPTEST and SCAN, the serial order of the configuration phases can be reversed. Furthermore, when multiple different IPTESTs exist, the parallel testing of IPTEST and SCAN can be performed by referring to... Figure 4 The proposed solution incorporates IPTEST and IPTEST's parallel testing.

[0081] In other words, the test parameters of the IP test item are configured through the JTAG port, and the first main running phase corresponding to the IP test item is entered; during the operation of the first main running phase, the test parameters of the SCAN test item are configured through the JTAG port, and the second main running phase corresponding to the SCAN test item is entered; if the first main running phase is completed before the second main running phase, the test result information corresponding to the generated IP test item is observed through the JTAG port during the operation of the second main running phase after the first main running phase is completed.

[0082] Alternatively, the test parameters of the SCAN test item can be configured via the JTAG port, and the first main running phase corresponding to the SCAN test item can be entered; during the operation of the first main running phase, the test parameters of the IP test item can be configured via the JTAG port, and the second main running phase corresponding to the IP test item can be entered; if the second main running phase completes before the first main running phase, the test result information corresponding to the generated IP test item can be observed via the JTAG port during the operation of the first main running phase after the second main running phase has completed.

[0083] It should be noted that the above examples are only used to help understand this application and do not constitute a limitation on the chip testability design method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0084] In addition, please refer to Figure 7 , Figure 7 This is a schematic diagram of the device structure of the hardware operating environment involved in the chip testability design method in the embodiments of this application.

[0085] This application also provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the steps of the chip testability design method in the above embodiments.

[0086] The following is for reference. Figure 7 It shows a schematic diagram of the structure of an electronic device suitable for implementing the embodiments of this application. Figure 7 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0087] like Figure 7 As shown, the electronic device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory 1002 or a program loaded from a storage device 1003 into a random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the electronic device. The processing unit 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An input / output interface 1006 is also connected to the bus. Typically, the following systems can be connected to the input / output interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. The communication device 1009 allows the electronic device to exchange data with other devices wirelessly or via wired communication. Although the diagrams show electronic devices with various systems, it should be understood that it is not required to implement or have all of the systems shown. More or fewer systems may be implemented alternatively.

[0088] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0089] The electronic device provided in this application, employing the chip testability design method in the above embodiments, can solve the technical problem of how to shorten testing time and reduce testing costs while ensuring chip testing quality and coverage. Compared with the prior art, the beneficial effects of the electronic device provided in this application are the same as those of the chip testability design method provided in the above embodiments, and other technical features in this electronic device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0090] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0091] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the above claims.

[0092] In addition, this application also provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to perform the steps of the chip testability design method in the above embodiments.

[0093] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, optical fibers, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (Radio Frequency), etc., or any suitable combination thereof.

[0094] The aforementioned computer-readable storage medium may be included in an electronic device or may exist independently without being assembled into an electronic device.

[0095] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by an electronic device, the electronic device causes the electronic device to: acquire multiple test items of the chip, wherein the multiple test items include at least a first test item and a second test item, the first test item being a test item for a first module group of the chip, and the second test item being a test item for a second module group of the chip, the first module group being distinct from the second module group; configure the test parameters of the first test item through a JTAG port and enter a first main running stage corresponding to the first test item, wherein the first main running stage is used to generate first test result information corresponding to the first test item; during the operation of the first main running stage, configure the test parameters of the second test item through a JTAG port and enter a second main running stage corresponding to the second test item, wherein the second main running stage is used to generate second test result information corresponding to the second test item.

[0096] Alternatively, the electronic device may: acquire multiple test items of the chip, wherein the multiple test items include at least a third IP test item and a fourth IP test item, the third IP test item being an IP test item for a first module of the chip, and the fourth IP test item being an IP test item for a second module of the chip, the IP test type of the third IP test item being the same as that of the fourth IP test item; configure the test parameters of the third IP test item and the fourth IP test item in parallel via signal broadcasting through the JTAG port, and enter the third main body operation stage corresponding to the third IP test item and the fourth main body operation stage corresponding to the fourth IP test item; wherein the third main body operation stage is used to generate the third test result information corresponding to the third IP test item, and the fourth main body operation stage is used to generate the fourth test result information corresponding to the fourth IP test item.

[0097] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0099] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0100] The computer-readable storage medium provided in this application stores computer-readable program instructions (i.e., a computer program) for performing the steps of the above-described chip testability design method, which can solve the technical problem of how to shorten testing time and reduce testing costs while ensuring chip testing quality and coverage. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the chip testability design method provided in the above embodiments, and will not be repeated here.

[0101] Furthermore, embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the steps of the chip testability design method as described in the above embodiments.

[0102] The computer program product provided in this application solves the technical problem of shortening testing time and reducing testing costs while ensuring chip testing quality and coverage. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the chip testability design method provided in the above embodiments, and will not be repeated here.

[0103] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A chip testability design method, comprising: Multiple test items are obtained for the chip, wherein the multiple test items include at least a first test item and a second test item, the first test item is a test item for a first module group of the chip, and the second test item is a test item for a second module group of the chip, wherein the first module group is different from the second module group; The test parameters of the first test item are configured through the JTAG port, and the first main running stage corresponding to the first test item is entered. The first main running stage is used to generate the first test result information corresponding to the first test item. During the first main body operation phase, the test parameters of the second test item are configured through the JTAG port, and the second main body operation phase corresponding to the second test item is entered. The second main body operation phase is used to generate the second test result information corresponding to the second test item.

2. The chip testability design method as described in claim 1, characterized in that, The first test item is the first IP test item, the second test item is the second IP test item, and the method further includes: If the first main body operation phase completes before the second main body operation phase, then during the period when the first main body operation phase has completed and the second main body operation phase is underway, the generated first test result information is observed through the JTAG port; or, If the second main operation phase completes before the first main operation phase, the generated second test result information is observed through the JTAG port during the period when the second main operation phase has completed and the first main operation phase is in progress.

3. The chip testability design method as described in claim 1, characterized in that, The first test item is the SCAN test item, the second test item is the second IP test item, and the method further includes: If the second main operation phase completes before the first main operation phase, the generated second test result information is observed through the JTAG port during the period when the second main operation phase has completed and the first main operation phase is in progress.

4. The chip testability design method as described in claim 1, characterized in that, The first test item is the first IPtest test item, the second test item is the SCAN test item, and the method further includes: If the first main operation phase completes before the second main operation phase, the first test result information generated is observed through the JTAG port during the period when the first main operation phase has completed and the second main operation phase is in progress.

5. The chip testability design method according to any one of claims 1 to 4, characterized in that, Before proceeding to the first main body operation phase corresponding to the first test item, the method further includes: The JTAG network is used to isolate other SCAN signals and / or other IP TEST signals to prevent other SCAN signals and / or other IP TEST signals from affecting the test results corresponding to each test item. Wherein, the other SCAN signals are SCAN signals unrelated to each of the test items, and the other IP TEST signals are IP TEST signals unrelated to each of the test items.

6. A chip testability design method, comprising: Obtain multiple test items for the chip, wherein the multiple test items include at least a third IP test item and a fourth IP test item, wherein the third IP test item is an IP test item for a first module of the chip, and the fourth IP test item is an IP test item for a second module of the chip, wherein the IP test type of the third IP test item is the same as the IP test type of the fourth IP test item; The test parameters of the third IP test item and the fourth IP test item are configured in parallel through signal broadcasting via the JTAG port, and the third main body operation phase corresponding to the third IP test item and the fourth main body operation phase corresponding to the fourth IP test item are entered. The third main body operation phase is used to generate the third test result information corresponding to the third IP test item, and the fourth main body operation phase is used to generate the fourth test result information corresponding to the fourth IP test item.

7. The chip testability design method as described in claim 6, characterized in that, After entering the third main body operation phase corresponding to the third IP test item and the fourth main body operation phase corresponding to the fourth IP test item, the method further includes: After the third and fourth main body operation phases are completed, the generated third and fourth test result information is observed through the JTAG port.

8. The chip testability design method as described in claim 6 or 7, characterized in that, Before proceeding to the third main body operation phase corresponding to the third IP test item and the fourth main body operation phase corresponding to the fourth IP test item, the method further includes: The JTAG network is used to isolate other SCAN signals and / or other IP TEST signals to prevent other SCAN signals and / or other IP TEST signals from affecting the test results corresponding to each test item. Wherein, the other SCAN signals are SCAN signals unrelated to each of the test items, and the other IP TEST signals are IP TEST signals unrelated to each of the test items.

9. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the chip testability design method as described in any one of claims 1 to 5, or 6 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the chip testability design method as described in any one of claims 1 to 5, or 6 to 8.

11. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the chip testability design method as described in any one of claims 1 to 5, or 6 to 8.

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