Common mode return loss optimization method and device, computer device, medium and program product

Abstract

The present application relates to the technical field of circuit design, and discloses a common mode return loss optimization method and device, computer equipment, medium and program product.The method comprises the following steps: obtaining a substrate simulation model;the substrate simulation model is constructed in advance based on a substrate link;the substrate link comprises substrate wiring and a fan-out area;starting the substrate simulation model, collecting the common mode impedance of the fan-out area and the common mode impedance of the substrate wiring;comparing the common mode impedance of the fan-out area with the common mode impedance of the substrate wiring, so as to adjust the accompanying ground hole design value and / or the core hole design value in the substrate simulation model;obtaining the common mode impedance of the substrate wiring, the common mode impedance of the fan-out area and the substrate common mode return loss of the adjusted substrate simulation model;if the common mode impedance of the substrate wiring, the common mode impedance of the fan-out area and the substrate common mode return loss of the adjusted substrate simulation model do not meet the preset conditions, returning to the step of starting the substrate simulation model.The above scheme is simple and easy to operate, and has good common mode return loss optimization effect.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, specifically to common-mode return loss optimization methods, apparatus, computer equipment, media, and program products. Background Technology

[0002] Common-mode loops refer to common-mode noise phenomena caused by the characteristics of current flow paths in circuit design. Common-mode return loss originates from signal echo phenomena caused by factors such as capacitive coupling or electromagnetic coupling between signal lines and ground lines during signal transmission. It is an important indicator for measuring the reflection or loss of common-mode signals during signal transmission, and is defined as the absolute value of the ratio of the power of the reflected wave to the power of the incident wave during the transmission of the common-mode signal.

[0003] In substrate circuits, common-mode return loss causes signal interference and loss, affecting signal integrity and reliability, reducing signal quality, and consequently impacting the overall performance of the substrate circuit. Therefore, a solution to optimize the common-mode return loss of substrate circuits is urgently needed. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a common-mode return loss optimization method, apparatus, computer equipment, medium and program product to solve the problem that common-mode return loss in substrate circuits leads to poor signal quality and affects circuit performance.

[0005] In a first aspect, the present invention provides a common-mode return loss optimization method, the method comprising:

[0006] Obtain a substrate simulation model; the substrate simulation model is pre-built based on the substrate traces; the substrate traces include substrate wiring and fan-out regions;

[0007] Start the substrate simulation model and collect the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces;

[0008] The common-mode impedance of the fan-out region is compared with the common-mode impedance of the substrate traces to adjust the design values ​​of the accompanying ground vias and / or the core vias in the substrate simulation model.

[0009] Obtain the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model;

[0010] If the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions, return to the step of starting the substrate simulation model.

[0011] In one optional implementation, comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model includes:

[0012] If the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, increase the number of accompanying ground vias in the substrate simulation model.

[0013] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, reduce the number of accompanying ground vias in the substrate simulation model.

[0014] In one optional implementation, the step of comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model further includes:

[0015] If the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate trace, increase the N / P spacing of the core via in the substrate simulation model;

[0016] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate trace, reduce the N / P spacing of the core via in the substrate simulation model.

[0017] In one optional implementation, the step of comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model further includes:

[0018] If the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate trace, increase the number of accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model.

[0019] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate trace, reduce the number of accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model.

[0020] In one optional implementation, the step of returning to start the substrate simulation model if the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions includes:

[0021] Calculate the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region in the adjusted substrate simulation model;

[0022] When the difference exceeds the first preset threshold and / or the common-mode return loss of the substrate exceeds the second preset threshold, return to the step of starting the substrate simulation model.

[0023] In an optional implementation, the method further includes:

[0024] Gradually adjust the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model to obtain the common-mode impedance variation curve of the substrate traces, the common-mode impedance variation curve of the fan-out region, and the common-mode return loss variation curve of the substrate simulation model.

[0025] Based on the common-mode impedance variation curves of the substrate traces, the common-mode impedance variation curves of the fan-out region, and the common-mode return loss variation curves of the substrate simulation model, the optimal values ​​for the accompanying ground via design and / or the optimal values ​​for the core via design are determined so that the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate meet the preset conditions.

[0026] Secondly, the present invention provides a common-mode return loss optimization device, the device comprising:

[0027] The model acquisition module is used to acquire a substrate simulation model; the substrate simulation model is pre-constructed based on the substrate links; the substrate links include substrate traces and fan-out regions.

[0028] The impedance acquisition module is used to start the substrate simulation model and acquire the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces.

[0029] The adjustment module is used to compare the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces in order to adjust the design values ​​of the accompanying ground vias and / or the core vias in the substrate simulation model.

[0030] The parameter acquisition module is used to acquire the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model.

[0031] The judgment module is used to return to the step of starting the substrate simulation model if the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions.

[0032] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the common-mode return loss optimization method of the first aspect or any corresponding embodiment described above.

[0033] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the common-mode return loss optimization method of the first aspect or any corresponding embodiment described above.

[0034] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the common-mode return loss optimization method of the first aspect or any corresponding embodiment described above.

[0035] The technical solution provided by this invention may include the following beneficial effects:

[0036] The common-mode return loss optimization method provided by this invention first obtains a pre-constructed substrate simulation model based on the substrate link. Then, the substrate simulation model is started to perform a simulation operation to collect the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces. With the goal of reducing the difference between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region is compared with the common-mode impedance of the substrate traces. Based on the comparison result, the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model are adjusted, and the simulation operation is performed again to obtain the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model. If the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions, the step of starting the substrate simulation model is returned, and the adjustment is readjusted until the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate meet the preset conditions. The above solution adjusts the design values ​​of the accompanying ground vias and / or core vias by comparing the difference between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces. The adjustment steps are repeated until the preset target is achieved. The solution is simple and easy to operate, and it has a good effect on optimizing common-mode return loss. Attached Figure Description

[0037] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0038] Figure 1 This is a flowchart illustrating the common-mode return loss optimization method according to an embodiment of the present invention;

[0039] Figure 2 This is a flowchart illustrating another common-mode return loss optimization method according to an embodiment of the present invention;

[0040] Figure 3 This is a flowchart illustrating another common-mode return loss optimization method according to an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the differential-mode impedance and common-mode impedance curves according to an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the borehole distribution before adjusting the number of return boreholes according to an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of the borehole distribution after adjusting the number of return boreholes according to an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram comparing the common mode return loss curves before and after adjusting the number of return ground holes according to an embodiment of the present invention;

[0045] Figure 8 This is a schematic diagram comparing the distribution of core holes before and after adjusting the N / P spacing of the signal holes according to an embodiment of the present invention;

[0046] Figure 9 This is a schematic diagram of the common mode return loss curve before adjusting the N / P spacing of the core hole according to an embodiment of the present invention;

[0047] Figure 10 This is a schematic diagram of the common mode return loss curve after adjusting the N / P spacing of the core hole according to an embodiment of the present invention;

[0048] Figure 11 This is a structural block diagram of a common-mode return loss optimization device according to an embodiment of the present invention;

[0049] Figure 12 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] Common-mode loops refer to common-mode noise phenomena caused by the characteristics of current flow paths in circuit design. Common-mode return loss originates from signal echo phenomena caused by factors such as capacitive coupling or electromagnetic coupling between signal lines and ground lines during signal transmission. It is an important indicator for measuring the reflection or loss of common-mode signals during signal transmission, and is defined as the absolute value of the ratio of the power of the reflected wave to the power of the incident wave during the transmission of the common-mode signal.

[0052] SerDes (Serializer / Deserializer) is a mainstream high-speed time-division multiplexing (TDM) and point-to-point (P2P) serial communication technology. Its core function is to convert multiple low-speed parallel signals into high-speed serial signals for transmission, and then restore the serial signals to low-speed parallel signals at the receiving end. In substrate SerDes circuits, common-mode return loss can cause signal interference and loss, affecting signal integrity and reliability, reducing signal quality, and consequently impacting the overall performance of the substrate SerDes circuit.

[0053] According to an embodiment of the present invention, a common-mode return loss optimization method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0054] This embodiment provides a common-mode return loss optimization method, which can be used in desktop computers, laptops, etc. Figure 1 This is a flowchart of the common-mode return loss optimization method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0055] Step S101: Obtain the substrate simulation model.

[0056] In this application scenario, the substrate can be a printed circuit board (PCB). The substrate simulation model is pre-built based on the substrate traces, and the appropriate simulation software can be selected to build the substrate simulation model as needed. The substrate traces include substrate traces and fan-out regions. The fan-out region is the BGA (Ball Grid Array) region. Fan-out refers to the trace routing process from the BGA pads to adjacent vias. BGA is used to create an array of solder balls on the bottom of the package substrate as the I / O (input / output) terminals of the circuit to interconnect with the printed circuit board. The fan-out region of the substrate includes impedance discontinuities such as vias and solder balls. Impedance discontinuity refers to a sudden change in impedance value in a transmission line, circuit, or signal path due to factors such as changes in physical structure (e.g., variations in conductor width, dielectric thickness, or material inhomogeneity); changes in local capacitance and inductance (e.g., variations in insulation thickness and copper wire diameter); and cable aging or defects). This phenomenon can significantly affect signal transmission, including signal reflection, energy attenuation, timing issues, and electromagnetic interference.

[0057] Step S102: Start the simulation model of the substrate and collect the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces.

[0058] A common-mode signal is a signal that acts simultaneously on two or more conductors, and that is equal in magnitude and in the same direction. Common-mode impedance refers to the impedance presented in a circuit for a common-mode signal. Common-mode impedance is a key parameter for measuring a circuit's ability to transmit common-mode signals, and it directly affects the performance of common-mode return loss. The higher the common-mode impedance, the stronger the circuit's ability to attenuate common-mode signals, resulting in lower common-mode return loss.

[0059] When optimizing common-mode return loss, it is necessary to analyze the common-mode impedance of the substrate traces and vias, solder balls, etc. in the fan-out region of the substrate, optimize the impedance discontinuities, reduce the common-mode impedance difference between the substrate traces and the fan-out region, improve the common-mode impedance continuity of the substrate link, and thus reduce common-mode return loss. The common-mode impedance of the substrate traces is mainly affected by the substrate material characteristics, trace geometry, and wiring rules.

[0060] Specifically, the substrate simulation model is started to perform simulation experiments to collect the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces.

[0061] Step S103: Compare the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the design values ​​of the accompanying ground vias and / or the core vias in the substrate simulation model.

[0062] In this embodiment, reducing the difference between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces is the core of optimizing common-mode return loss. Therefore, by comparing the difference between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces, the design values ​​of the accompanying ground vias and / or core vias in the fan-out region can be adjusted based on this difference, thereby adjusting the common-mode impedance of the fan-out region to bring it closer to the common-mode impedance of the substrate traces. An accompanying ground via is a type of grounding via, typically used at signal vias. Accompanying ground vias optimize signal integrity by increasing grounding connections, providing a signal return path and reducing electromagnetic interference. A core via is a via that penetrates the core layer of a multilayer substrate, typically used to connect electrical connections between different layers. The design values ​​for accompanying ground vias can be the number and arrangement of the vias, and the design values ​​for core vias can be the number and arrangement of the core vias. The design values ​​for accompanying ground vias and / or core vias can be adjusted directly in the substrate simulation model as needed.

[0063] Step S104: Obtain the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model.

[0064] After adjusting the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model, the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region in the substrate simulation model changed, which in turn changed the common-mode return loss of the substrate. A simulation experiment can be performed by starting the adjusted substrate simulation model to collect the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate.

[0065] Step S105: If the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions, return to the step of starting the substrate simulation model.

[0066] The preset conditions can be set according to actual needs, such as setting the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region to be within a preset range and the common-mode return loss of the substrate to be less than a preset threshold. Meeting the preset conditions indicates that the common-mode return loss optimization is successful, and the design values ​​of the accompanying ground vias and / or core vias obtained in this operation are applied to the subsequent substrate circuit design; not meeting the preset conditions indicates that the common-mode return loss optimization is unsuccessful, and the process returns to the step of starting the substrate simulation model, that is, cyclically repeating steps S102 to S105 until the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model meet the preset conditions.

[0067] The common-mode return loss optimization method provided in this embodiment first obtains a pre-constructed substrate simulation model based on the substrate link. Then, it starts the substrate simulation model to perform a simulation operation to collect the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces. With the goal of reducing the difference between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces, it compares the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces. Based on the comparison result, it adjusts the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model and then performs the simulation operation again to obtain the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model. If the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions, it returns to the step of starting the substrate simulation model and readjusts until the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate meet the preset conditions. The above solution adjusts the design values ​​of the accompanying ground vias and / or core vias by comparing the difference between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces. The adjustment steps are repeated until the preset target is achieved. The solution is simple and easy to operate, and it has a good effect on optimizing common-mode return loss.

[0068] This embodiment provides a common-mode return loss optimization method, which can be used in desktop computers, laptops, etc. Figure 2This is a flowchart of the common-mode return loss optimization method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0069] Step S201: Obtain the substrate simulation model.

[0070] The substrate simulation model is pre-built based on the substrate link, which includes substrate traces and fan-out regions.

[0071] Please see details Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0072] Step S202: Start the simulation model of the substrate and collect the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces.

[0073] Please see details Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0074] Step S203: Compare the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model.

[0075] Optionally, based on the comparison between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces, the design values ​​of the accompanying ground vias can be adjusted individually. The design values ​​of the accompanying ground vias include the number of accompanying ground vias and the spacing between them. The spacing between accompanying ground vias is the distance between two adjacent accompanying ground vias. Specifically, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, the number of accompanying ground vias in the substrate simulation model is increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number of accompanying ground vias in the substrate simulation model is decreased. Alternatively, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, the spacing of the accompanying ground vias in the substrate simulation model is increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the spacing of the accompanying ground vias in the substrate simulation model is decreased. Alternatively, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, both the number and spacing of the accompanying ground vias in the substrate simulation model are increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, both the number and spacing of the accompanying ground vias in the substrate simulation model are decreased. When adjusting the number or spacing of accompanying boreholes, an adjustment threshold can be set based on experience or historical experimental data. The adjustment can be made gradually according to the adjustment threshold each time, such as adding one accompanying borehole each time, or adding 100um each time.

[0076] Optionally, the core via design value can be adjusted individually based on the comparison between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces. Specifically, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, the N / P spacing of the core vias in the substrate simulation model is increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the N / P spacing of the core vias in the substrate simulation model is decreased. When adjusting the N / P spacing of the core vias, an adjustment threshold can be set, and the adjustment can be gradually increased according to the adjustment threshold each time, for example, by 100um each time. Here, N (negative) and P (positive) are the two poles of the differential signal. The differential signal is transmitted by two transmission lines, one is the N line and the other is the P line. Therefore, the core vias are divided into N-vias and P-vias. The N / P spacing of the core vias refers to the pitch between a pair of N-vias and P-vias, that is, the distance between the center of the N-via and the center of the P-via.

[0077] Optionally, based on the comparison between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces, the design values ​​of the accompanying ground vias and / or the core vias can be adjusted simultaneously. Specifically, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, the number and / or spacing of the accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model are increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number and / or spacing of the accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model are decreased.

[0078] Step S204: Obtain the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model.

[0079] Please see details Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0080] Step S205: If the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions, return to the step of starting the substrate simulation model.

[0081] Specifically, step S205 includes:

[0082] Step S2051: Calculate the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region in the adjusted substrate simulation model.

[0083] Since the adjustment goal of this embodiment is to make the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region as equal as possible, the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region in the adjusted substrate simulation model is first calculated, and the success of the adjustment is determined based on the difference.

[0084] Step S2052: When the difference exceeds the first preset threshold and / or the common mode return loss of the substrate exceeds the second preset threshold, return to the step of starting the substrate simulation model.

[0085] Since it is difficult to make the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region completely equal in practical applications, this embodiment sets the preset condition as follows: the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region is less than a first preset threshold and / or the common-mode return loss of the substrate does not exceed a second preset threshold. In other words, the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region can be used as the adjustment target alone, or the final common-mode return loss of the substrate can be used as the adjustment target alone, or both can be used as adjustment targets simultaneously. The first preset threshold is the maximum difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region under the premise of ensuring normal operation of the substrate circuit, and the second preset threshold is the maximum value of the common-mode return loss of the substrate under the premise of ensuring normal operation of the substrate circuit. The first and second preset thresholds can be determined based on experience or historical experimental data.

[0086] Optionally, simulation software can be used to record the change curves of various parameters during the adjustment process, and the trend of the change curves can be used to assist in the adjustment. Specifically, the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model are adjusted step by step, and the common-mode impedance change curves of the substrate traces, the common-mode impedance change curves of the fan-out region, and the common-mode return loss change curves of the substrate simulation model are obtained through simulation software. The common-mode impedance change curve of the substrate traces indicates the change of the common-mode impedance of the substrate traces over time. The common-mode impedance change curve of the fan-out region indicates the change of the common-mode impedance of the fan-out region over time. The common-mode return loss change curve indicates the change of the common-mode return loss of the substrate over time. Then, based on the trend changes of the common-mode impedance change curves of the substrate traces, the common-mode impedance change curves of the fan-out region, and the common-mode return loss change curves of the substrate simulation model, the optimal design values ​​of the accompanying ground vias and / or the core vias are determined to make the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate meet the preset conditions.

[0087] The common-mode return loss optimization method provided in this embodiment first obtains a pre-constructed substrate simulation model based on the substrate link. Then, it starts the substrate simulation model to perform a simulation operation to collect the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces. With the goal of reducing the difference between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces, it compares the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces. Based on the comparison result, it adjusts the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model and then performs the simulation operation again to obtain the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model. If the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions, it returns to the step of starting the substrate simulation model and readjusts until the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate meet the preset conditions. The above solution adjusts the design values ​​of the accompanying ground vias and / or core vias by comparing the difference between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces. The adjustment steps are repeated until the preset target is achieved. The solution is simple and easy to operate, and it has a good effect on optimizing common-mode return loss.

[0088] Furthermore, this embodiment provides a scheme to adjust the design value of the accompanying ground holes by adjusting the number and / or spacing of the accompanying ground holes, and to adjust the design value of the core holes by adjusting the N / P spacing of the core holes. This further refines the scheme, improves its operability and selectivity, and thus improves the optimization effect of common mode return loss.

[0089] Furthermore, this embodiment provides a scheme for adjustment using the common-mode impedance variation curves of the substrate traces, the common-mode impedance variation curves of the fan-out region, and the common-mode return loss variation curves obtained by establishing a substrate simulation model. This can intuitively reflect the parameter changes before and after adjustment, improve the accuracy and clarity of the scheme, and thus improve the common-mode return loss optimization effect.

[0090] As one or more specific application embodiments of the present invention, the optimal implementation scheme or the scheme that the inventors most want to embody is described below in conjunction with specific application scenarios.

[0091] Figure 3This is a flowchart of a common-mode return loss optimization method according to an embodiment of the present invention. In this embodiment, a 3D finite element simulation tool (such as HFSS) is used to establish a substrate simulation model for the substrate SerDes circuit. The common-mode impedance of the fan-out region is measured using TDR (Time Domain Reflectometry, a technique for measuring impedance changes during signal transmission). Multiple simulation operations are performed to obtain the common-mode impedance curve of the substrate traces, the common-mode impedance change curve of the fan-out region, and the common-mode return loss change curve. Based on these curves, the optimal number of return ground vias (and accompanying ground vias) and / or the optimal value for increasing the N / P spacing of signal vias (core vias) are determined. Specifically, after each simulation, the common-mode impedance of the substrate traces is first analyzed based on the common-mode impedance curve, and then the common-mode impedance of the fan-out region is analyzed, comparing the difference between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces. When the common-mode impedance of the substrate traces is greater than the common-mode impedance of the fan-out region, reduce the number of return ground vias (accompanying ground vias) and / or reduce the N / P spacing of signal vias (core vias); when the common-mode impedance of the substrate traces is less than the common-mode impedance of the fan-out region, increase the number of return ground vias (accompanying ground vias) and / or increase the N / P spacing of signal vias (core vias).

[0092] Figure 4 This is a schematic diagram of the differential-mode impedance and common-mode impedance curves according to an embodiment of the present invention. Figure 4 As shown, the vertical axis represents the impedance value, and the horizontal axis represents the time value. Since the simulation model includes traces and fan-out regions, the simulation results also include traces and fan-out regions. The red curve is the differential impedance curve, and the green curve is the common-mode impedance curve. From the common-mode impedance curve, we can see the trend of common-mode impedance variation of the substrate traces and the trend of common-mode impedance variation of the fan-out region.

[0093] Figure 5 This is a schematic diagram of the borehole distribution before adjusting the number of return boreholes according to an embodiment of the present invention. Figure 6 This is a schematic diagram of the borehole distribution after adjusting the number of return boreholes according to an embodiment of the present invention. Figure 7 This is a schematic diagram comparing the common-mode return loss curves before and after adjusting the number of return ground holes according to an embodiment of the present invention. Figure 5 and Figure 6 As shown, after common-mode return loss optimization, eight return ground vias were added. Figure 7 As shown, the horizontal axis represents frequency (GHz) and the vertical axis represents amplitude (dB). The green curve is the common-mode return loss curve without common-mode return loss optimization, and the red curve is the common-mode return loss curve after common-mode return loss optimization. It can be seen that after adding 8 return ground vias, the common-mode return loss at a signal frequency of 28GHz decreased from -6.06dB to -14.73dB.

[0094] Figure 8 This is a schematic diagram comparing the distribution of core holes before and after adjusting the N / P spacing of the signal holes according to an embodiment of the present invention. Figure 9 This is a schematic diagram of the common-mode return loss curve before adjusting the N / P spacing of the core aperture according to an embodiment of the present invention. Figure 10 This is a schematic diagram of the common-mode return loss curve after adjusting the N / P spacing of the core aperture according to an embodiment of the present invention. Figure 8 As shown, after common-mode return loss optimization, the N / P spacing of the signal aperture increased from 400µm to 600µm. Figure 9 and Figure 10 As shown, the horizontal axis represents frequency (GHz) and the vertical axis represents amplitude (dB). The graph contains multiple pairs of differential lines, with curves of the same color corresponding to each other. It can be seen that after adjusting the N / P spacing of the signal aperture from 400um to 600um, the common-mode return loss at a signal frequency of 28GHz decreased from -5dB to -11.3dB.

[0095] This embodiment also provides a common-mode return loss optimization device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0096] This embodiment provides a common-mode return loss optimization device, such as... Figure 11 As shown, it includes:

[0097] The model acquisition module 1101 is used to acquire a substrate simulation model; the substrate simulation model is pre-built based on the substrate link; the substrate link includes substrate traces and fan-out regions.

[0098] Impedance acquisition module 1102 is used to start the simulation model of the substrate and acquire the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces.

[0099] The adjustment module 1103 is used to compare the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces in order to adjust the design values ​​of the accompanying ground vias and / or the core vias in the substrate simulation model.

[0100] The parameter acquisition module 1104 is used to acquire the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model.

[0101] The judgment module 1105 is used to return to the step of starting the substrate simulation model if the common mode impedance of the substrate trace, the common mode impedance of the fan-out region, and the common mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions.

[0102] In one alternative implementation, the adjustment module is further configured to:

[0103] If the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate trace, increase the number of accompanying ground vias in the substrate simulation model;

[0104] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, reduce the number of accompanying ground vias in the substrate simulation model.

[0105] In one alternative implementation, the adjustment module is further configured to:

[0106] If the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, increase the N / P spacing of the core vias in the substrate simulation model;

[0107] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, reduce the N / P spacing of the core vias in the substrate simulation model.

[0108] In one alternative implementation, the adjustment module is further configured to:

[0109] If the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate trace, increase the number of accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model.

[0110] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, reduce the number of accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model.

[0111] In an optional implementation, the determination module is further configured to:

[0112] Calculate the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region in the adjusted substrate simulation model;

[0113] When the difference exceeds a preset threshold and / or the common-mode return loss of the substrate exceeds a preset threshold, return to the step of starting the substrate simulation model.

[0114] In an alternative implementation, the device further includes a curve analysis module for:

[0115] Gradually adjust the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model to obtain the common-mode impedance variation curves of the substrate traces, the common-mode impedance variation curves of the fan-out region, and the common-mode return loss variation curves of the substrate simulation model.

[0116] Based on the common-mode impedance variation curves of the substrate traces, the common-mode impedance variation curves of the fan-out region, and the common-mode return loss variation curves of the substrate simulation model, the optimal values ​​for the accompanying ground via design and / or the optimal values ​​for the core via design that make the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate meet the preset conditions are determined.

[0117] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0118] In this embodiment, the common-mode return loss optimization device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0119] This invention also provides a computer device having the above-described features. Figure 11 The common-mode return loss optimization device shown.

[0120] Please see Figure 12 , Figure 12 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 12 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 12 Take a processor 10 as an example.

[0121] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0122] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0123] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0124] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0125] The computer device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 12 Taking the example of a connection between China and Israel via a bus.

[0126] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as a touchscreen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touchscreen.

[0127] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0128] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0129] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the protection scope of the present invention.

Claims

1. A common-mode return loss optimization method, characterized in that, The method includes: Obtain a substrate simulation model; the substrate simulation model is pre-built based on the substrate traces; the substrate traces include substrate wiring and fan-out regions; Start the substrate simulation model and collect the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces; The common-mode impedance of the fan-out region is compared with the common-mode impedance of the substrate traces to adjust the design values ​​of the accompanying ground vias and / or the core vias in the substrate simulation model. Obtain the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model; If the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions, return to the step of starting the substrate simulation model. The step of comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model includes: If the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, increase the number of accompanying ground vias in the substrate simulation model; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, decrease the number of accompanying ground vias in the substrate simulation model. Alternatively, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, the N / P spacing of the core vias in the substrate simulation model is increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the N / P spacing of the core vias in the substrate simulation model is decreased. Alternatively, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, increase the number of accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, decrease the number of accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model.

2. The method according to claim 1, characterized in that, If the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions, the step of returning to start the substrate simulation model includes: Calculate the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region in the adjusted substrate simulation model; When the difference exceeds the first preset threshold and / or the common-mode return loss of the substrate exceeds the second preset threshold, return to the step of starting the substrate simulation model.

3. The method according to claim 2, characterized in that, The method further includes: Gradually adjust the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model to obtain the common-mode impedance variation curve of the substrate traces, the common-mode impedance variation curve of the fan-out region, and the common-mode return loss variation curve of the substrate simulation model. Based on the common-mode impedance variation curves of the substrate traces, the common-mode impedance variation curves of the fan-out region, and the common-mode return loss variation curves of the substrate simulation model, the optimal values ​​for the accompanying ground via design and / or the optimal values ​​for the core via design are determined so that the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate meet the preset conditions.

4. A common-mode return loss optimization device, characterized in that, The device includes: The model acquisition module is used to acquire a substrate simulation model; the substrate simulation model is pre-constructed based on the substrate links; the substrate links include substrate traces and fan-out regions. The impedance acquisition module is used to start the substrate simulation model and acquire the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces. The adjustment module is used to compare the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces in order to adjust the design values ​​of the accompanying ground vias and / or the core vias in the substrate simulation model. The parameter acquisition module is used to acquire the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model. The judgment module is used to return to the step of starting the substrate simulation model if the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out region, and the common-mode return loss of the substrate in the adjusted substrate simulation model do not meet the preset conditions. The adjustment module is also used for: If the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, increase the number of accompanying ground vias in the substrate simulation model; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, decrease the number of accompanying ground vias in the substrate simulation model. Alternatively, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, the N / P spacing of the core vias in the substrate simulation model is increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the N / P spacing of the core vias in the substrate simulation model is decreased. Alternatively, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, increase the number of accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, decrease the number of accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model.

5. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the common-mode return loss optimization method according to any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the common-mode return loss optimization method according to any one of claims 1 to 3.

7. A computer program product, characterized in that, Includes computer instructions for causing a computer to execute the common-mode return loss optimization method according to any one of claims 1 to 3.

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