Method for reducing interface defects in silicon epitaxial growth process
Through the coordinated optimization of sidewall crystal plane engineering, crystal orientation matching epitaxy and femtosecond laser annealing, the interface defect problem in the hybrid back-gate structure was solved, low-defect interface formation was achieved, and device reliability and performance were improved.
Patent Information
- Application Number
- CN202510645759.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-19
- Publication Date
- 2025-09-16
Smart Images
Figure CN120656926A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure belongs to the field of semiconductor device manufacturing, and in particular, relates to a method for reducing interface defects during silicon epitaxial growth. Background Art
[0002] As integrated circuit technology advances into the nanometer scale, fully depleted silicon-on-insulator (FDSOI) technology has become a key area of advanced semiconductor manufacturing due to its superior short-channel effect suppression and static power consumption characteristics. In recent years, the industry has further proposed hybrid back-gate control structures. This structure, formed through selective epitaxial growth in specific regions and combined with a dual-gate coordinated control mechanism, significantly optimizes threshold voltage tunability and subthreshold swing characteristics.
[0003] To enhance the performance of hybrid back-gate control structures, current technologies primarily improve interface properties through the following methods: For example, high-temperature annealing processes (such as rapid thermal annealing or laser annealing) are used to repair lattice defects at the interface between the epitaxial silicon layer and the original top silicon layer, reducing dislocation density; or surface hydrogen passivation treatments (such as H2 plasma treatment or SiH4 annealing) are used to passivate interface dangling bonds and reduce interface state trap density. However, these methods face significant challenges at more advanced process nodes (e.g., below 5nm): high-temperature and long-term annealing can easily induce backplane dopant diffusion, leading to threshold voltage shift; conventional hydrogen passivation is inefficient in repairing deep-level defects and cannot effectively address quantum confinement effects caused by interface roughness.
[0004] While the hybrid back-gate structure offers significant advantages in performance control, its core bottleneck lies in interface defects between the epitaxial silicon layer and the original silicon. Specifically, selective epitaxial boundary effects lead to lattice mismatch and thermal expansion coefficient differences at the interface, resulting in a high density of dislocation defects. This increases the density of interface state traps, leading to increased leakage current and degraded device reliability. Existing high-temperature annealing and passivation processes are limited in performance at nodes below 5nm, and quantum tunneling effects caused by interface roughness further exacerbate leakage and noise.
[0005] These problems seriously restrict the threshold control accuracy and power consumption advantages of the hybrid back-gate structure. There is an urgent need to develop low-defect interface formation technology compatible with advanced processes to break through the key bottleneck in the development of FDSOI technology towards high performance and high reliability. Summary of the Invention
[0006] In view of this, in order to solve at least one technical problem in related technologies and other aspects, the present disclosure proposes a method for reducing interface defects during silicon epitaxial growth, comprising:
[0007] Providing an SOI substrate comprising a supporting silicon layer, a buried oxide layer and a top silicon layer, and depositing a mask layer on the top silicon layer of the SOI substrate;
[0008] coating a photoresist on at least a portion of the surface of the mask layer to form a protection zone, and etching away the mask layer, the top silicon layer, and the buried oxide layer outside the protection zone until the supporting silicon layer is exposed to obtain a mixed zone;
[0009] The photoresist in the protection zone is removed, and the sidewalls of the top silicon layer in the protection zone are anisotropically etched by plasma etching to expose the (110) crystal plane and form smooth sidewalls;
[0010] Epitaxial growth of silicon along the (100) and (110) crystal planes in the mixed region;
[0011] Femtosecond laser selective annealing was performed on the epitaxial interface of (100) crystal plane epitaxially grown silicon and (110) crystal plane epitaxially grown silicon to release dislocation pileup stress.
[0012] According to an embodiment of the present disclosure, the plasma etching process includes:
[0013] The sidewalls are obliquely bombarded by Ar / Cl2 plasma to expose the (110) crystal plane of the sidewalls.
[0014] According to an embodiment of the present disclosure, the incident tilt angle of the Ar / Cl2 plasma is 45°.
[0015] According to an embodiment of the present disclosure, the difference in interfacial atomic distance between the (110) crystal plane and the (100) crystal plane is less than 0.1%.
[0016] According to the embodiment of the present disclosure, in the femtosecond laser selective annealing, the laser pulse width is 140-169 fs, and the laser energy density is 0.4-0.6 J / cm 2 .
[0017] According to an embodiment of the present disclosure, laser selective annealing includes electron beam annealing, scanning halogen lamp annealing, ion beam annealing, and ultrafast laser annealing.
[0018] According to an embodiment of the present disclosure, in femtosecond laser selective annealing, the laser scanning time is less than 1 ns.
[0019] According to an embodiment of the present disclosure, the thickness of the top silicon layer is 15-55 nm, and the thickness of the buried oxide layer is 20-145 nm.
[0020] According to an embodiment of the present disclosure, the mask layer includes a silicon oxide layer and a silicon nitride layer formed in sequence to protect the top silicon layer.
[0021] According to an embodiment of the present disclosure, the thickness of the silicon oxide layer is 5-10 nm, and the thickness of the silicon nitride layer is 40-60 nm.
[0022] According to the embodiments of the present disclosure, the present disclosure systematically reduces the interface dislocation density and traps by designing a three-level collaborative optimization of "sidewall crystal plane engineering + crystal orientation matching epitaxy + local stress elimination". First, the (110) crystal plane of the top silicon layer sidewall is exposed by plasma etching, and the difference in the anisotropic etching rate of the crystal plane is used to form an atomically smooth sidewall. Then, silicon is epitaxially grown on the (100) crystal plane and the (110) crystal plane in the mixed area. Finally, ultrashort pulse selective annealing is performed on the interface area using a femtosecond laser. The ultrafast laser induces a transient non-equilibrium state, which promotes dislocation slip and recombination, effectively releases dislocation accumulation stress, and suppresses the deterioration of interface roughness caused by grain coarsening. No high temperature environment is required (conventional annealing >1000°C), reducing the thermal budget. The smooth sidewall is conducive to reducing defect nucleation sites, the crystal orientation matching epitaxial medium suppresses defect expansion, and the laser annealing is conducive to eliminating residual stress and forming a closed loop to reduce interface defects during silicon epitaxial growth. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 is a flow chart of a method for reducing interface defects during silicon epitaxial growth according to an embodiment of the present disclosure;
[0024] Figure 2 is a schematic diagram of the cross-sectional structure of the SOI substrate in Example 1 of the present disclosure;
[0025] Figure 3 is a schematic cross-sectional structural diagram of depositing a mask layer and coating a photoresist in Example 1 of the present disclosure;
[0026] Figure 4 is a schematic diagram of the structure after plasma etching treatment in Example 1 of the present disclosure;
[0027] Figure 5 It is a schematic diagram of the cross-sectional structure of silicon after epitaxial growth in Example 1 of the present disclosure.
[0028] In the drawings of this disclosure, the meanings of the reference numerals are:
[0029] 1-support silicon layer 1; 2-buried oxide layer; 3-top silicon layer; 4-silicon oxide layer; 5-silicon nitride layer; 6-photoresist; 7-epitaxial interface. DETAILED DESCRIPTION
[0030] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
[0031] The endpoints of the ranges and any values disclosed in this disclosure are not limited to the precise ranges or values, and these ranges or values should be understood to include values close to these ranges or values. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed in this disclosure.
[0032] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0033] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.
[0034] It should be noted that, unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by persons of ordinary skill in the art to which this disclosure belongs. Where references to "first," "second," or the like are used throughout this disclosure, such references are intended solely to distinguish similar objects and should not be construed as indicating or implying their relative importance, order of precedence, or implicitly specifying the quantity of the technical features being referred to. References to "first," "second," or the like should be understood to be interchangeable where appropriate.
[0035] In the description of the present disclosure, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the subsystem or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.
[0036] Throughout the drawings, identical elements are represented by identical or similar reference numerals. Conventional structures or configurations are omitted where they may cause confusion in understanding the present disclosure. Furthermore, the shapes, sizes, and positional relationships of the components in the drawings do not reflect actual size, proportion, or actual positional relationships. Furthermore, any reference symbols placed between parentheses in this disclosure should not be construed as limiting the present disclosure.
[0037] Similarly, in order to streamline the present disclosure and aid in understanding one or more of the various disclosed aspects, in the above description of exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. Descriptions with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" and the like mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in an appropriate manner.
[0038] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this disclosure.
[0039] In this disclosure, the term "FDSOI (fully depleted silicon on insulator)" refers to a transistor technology based on an SOI (silicon on insulator) substrate. Its core is the fabrication of a nanometer-thick silicon film on an ultra-thin insulating buried oxide layer (BOX). When voltage is applied to the transistor gate, the channel silicon layer is completely depleted (no free carriers), significantly suppressing short-channel effects (such as drain-induced barrier lowering and subthreshold leakage). Sub-5nm is the name of a process node in the semiconductor industry, representing critical transistor dimensions (such as gate length) entering the 5nm range or smaller. This node marks the device's entry into the deep nanoscale, approaching the physical limit.
[0040] In this disclosure, the term "back gate" refers to a gate located beneath the transistor substrate or buried oxide layer. It regulates the carrier concentration in the channel region by applying a voltage, assisting the top gate in achieving dual-gate coordinated control. "Hybrid region" refers to the heterogeneous integration of multiple materials or structures in key device regions (such as the channel, source / drain, or back gate interface). Independent voltages are applied to the back and top gates, creating a superimposed electric field that precisely regulates the depletion state of the channel region. Band engineering at the hybrid material interface can improve carrier mobility.
[0041] As FDSOI technology evolves to nodes below 5nm, hybrid back-gate control structures face severe challenges due to interface defects. The core of this disclosure is to optimize the epitaxial interface quality through crystal plane engineering and dynamic local annealing. First, atomically smooth sidewalls are created to reduce defect nucleation. Crystal orientation matching is used during the epitaxial process to suppress defect propagation. Finally, laser local annealing is used to eliminate residual stress and achieve terminal repair.
[0042] The present disclosure proposes a method for reducing interface defects during silicon epitaxial growth, comprising the following steps S101 to S105:
[0043] Step S101: providing an SOI substrate including a supporting silicon layer 1, a buried oxide layer 2 and a top silicon layer 3, and depositing a mask layer on the top silicon layer 3 of the SOI substrate;
[0044] Step S102: coating a photoresist 6 on at least a portion of the mask layer surface to form a protection zone, and etching away the mask layer, the top silicon layer 3, and the buried oxide layer 2 outside the protection zone until the supporting silicon layer 1 is exposed to obtain a mixed zone;
[0045] Step S103: removing the photoresist 6 in the protection zone, and performing anisotropic etching on the sidewalls of the top silicon layer 3 in the protection zone by plasma etching to expose the (110) crystal plane and form smooth sidewalls;
[0046] Step S104: epitaxially growing silicon along the (100) crystal plane and the (110) crystal plane in the mixed region;
[0047] Step S105: performing femtosecond laser selective annealing on the epitaxial interface 7 of the (100) crystal plane epitaxially grown silicon and the (110) crystal plane epitaxially grown silicon to release dislocation pileup stress.
[0048] According to the embodiments of the present disclosure, the present disclosure systematically reduces the interface dislocation density and traps by designing a three-level collaborative optimization of "sidewall crystal plane engineering + crystal orientation matching epitaxy + local stress elimination". First, the (110) crystal plane of the side wall of the top silicon layer 3 is exposed by plasma etching, and the difference in the anisotropic etching rate of the crystal plane is used to form an atomically smooth side wall. Then, silicon is epitaxially grown in the mixed area with the (100) crystal plane and the (110) crystal plane. Finally, a femtosecond laser is used to perform ultrashort pulse selective annealing on the interface area. The ultrafast laser induces a transient non-equilibrium state, which promotes dislocation slip and recombination, effectively releases dislocation accumulation stress, and suppresses the deterioration of interface roughness caused by grain coarsening. No high temperature environment is required (conventional annealing >1000°C), reducing the thermal budget. The smooth side wall is conducive to reducing defect nucleation sites, the crystal orientation matching epitaxial medium suppresses defect expansion, and the laser annealing is conducive to eliminating residual stress and forming a closed loop to reduce interface defects during silicon epitaxial growth.
[0049] Specifically, epitaxial growth of a silicon layer along the (110) crystal plane with smooth sidewalls can reduce the lattice mismatch stress concentration caused by surface roughness during subsequent epitaxial growth, inhibit the nucleation of dislocation defects from the source, and avoid jagged interface defects caused by traditional etching processes.
[0050] Specifically, epitaxially growing a silicon layer along the (100) crystal plane in the plane of the mixed region is beneficial to reducing the lattice distortion between the epitaxial layer and the original silicon layer, reducing edge dislocations or screw dislocations caused by crystal orientation deviation, and significantly improving the crystal continuity of the epitaxial interface.
[0051] Specifically, a femtosecond laser is used to perform ultrashort pulse selective annealing on the interface region. This treatment, while limiting the effect to a microscopic interface region, avoids the backplane dopant diffusion issues associated with traditional high-temperature annealing. Furthermore, the ultrafast laser induces a transient non-equilibrium state, promoting dislocation slip and recombination, effectively releasing dislocation accumulation stress while suppressing the deterioration of interface roughness caused by grain coarsening. Furthermore, the annealing region is precisely controlled to avoid thermal damage to surrounding device structures (such as the mask layer and buried oxide layer). Femtosecond laser annealing does not require a high-temperature environment (conventional annealing is >1000°C), reducing the thermal budget and making it compatible with temperature-sensitive advanced node metallization layers.
[0052] According to an embodiment of the present disclosure, the plasma etching process includes:
[0053] The sidewalls are obliquely bombarded by Ar / Cl2 plasma to expose the (110) crystal plane of the sidewalls.
[0054] According to the embodiment of the present disclosure, Ar / Cl2 mixed gas is used, combined with pulse modulation technology, by adjusting the ion incident angle, using Cl - Chemically active etching and Ar + The physical bombardment of the top silicon preferentially exposes the (110) crystal plane on the sidewall. This crystal plane has low surface energy and high etching anisotropy ratio, which can form atomically smooth inclined sidewalls. The inclined (110) crystal plane matches the (100) crystal plane of the flat epitaxial silicon in the hybrid region through lattice rotational symmetry, forming a semi-coherent interface. This is conducive to effectively alleviating lattice mismatch stress and inhibiting the nucleation of edge dislocations in the early stages of epitaxial growth.
[0055] According to an embodiment of the present disclosure, the incident tilt angle of the Ar / Cl2 plasma is 45°.
[0056] According to an embodiment of the present disclosure, the difference in interfacial atomic distance between the (110) crystal plane and the (100) crystal plane is less than 0.1%.
[0057] According to the embodiments of the present disclosure, the difference in interfacial atomic spacing is <0.1%, indicating that the lattice mismatch between the (100) crystal plane of the mixed region plane and the (110) crystal plane of the sidewall is extremely low, and the interface dislocation density (such as edge dislocations) is greatly reduced due to lattice matching.
[0058] According to the embodiment of the present disclosure, in the femtosecond laser selective annealing, the laser pulse width is 140-169fs, for example, 140fs, 145fs, 150s, 155fs, 160fs, 165fs, 169fs, etc., and the laser energy density is 0.4-0.6J / cm 2 , for example, it can be 0.4 J / cm 2 , 0.5J / cm 2 , 0.6J / cm 2 wait.
[0059] According to the disclosed embodiments, femtosecond lasers can generate ultrafast nonequilibrium thermal shock at the interface. This differential thermal expansion creates a transient compressive stress field at the interface, driving edge dislocations to slip and recombine along the slip system, thereby releasing the accumulated dislocation stress. Furthermore, laser energy is localized at the interface, achieving selective energy deposition and preferentially eliminating defects in high-strain areas (e.g., around dislocation lines).
[0060] According to an embodiment of the present disclosure, laser selective annealing includes electron beam annealing, scanning halogen lamp annealing, ion beam annealing, and ultrafast laser annealing.
[0061] According to an embodiment of the present disclosure, in femtosecond laser selective annealing, the laser scanning time is less than 1 ns.
[0062] According to an embodiment of the present disclosure, the thickness of the top silicon layer 3 is 15-55nm, for example, it can be 15nm, 25nm, 35nm, 45nm, 55nm, etc., and the thickness of the buried oxide layer 2 is 20-145nm, for example, it can be 20nm, 30nm, 50nm, 80nm, 100nm, 130nm, 145nm, etc.
[0063] According to an embodiment of the present disclosure, the mask layer includes a silicon oxide layer 4 and a silicon nitride layer 5 formed in sequence to protect the top silicon layer 3 .
[0064] According to the embodiments of the present disclosure, it is difficult to directly grow the harder silicon nitride material on the surface of the top silicon layer 3. Therefore, the silicon oxide layer 4 is first deposited directly on the surface of the top silicon layer 3. Its thermal expansion coefficient is relatively close to that of silicon, which can reduce the thermal stress mismatch caused by temperature fluctuations and prevent the top silicon layer 3 from cracking or warping in subsequent processes. When etching the top silicon layer 3 and the buried oxide layer 2, the silicon nitride layer 5 acts as a hard mask to ensure the integrity of the mask structure and prevent over-etching and punch-through. At the same time, silicon nitride has high hardness (~18 GPa) and high temperature resistance (melting point >1900°C), maintaining morphological stability during plasma etching or high-temperature epitaxial growth (such as selective epitaxial silicon), preventing mask deformation or cracking.
[0065] According to an embodiment of the present disclosure, the thickness of the silicon oxide layer 4 is 5-10 nm, for example, 5 nm, 8 nm, 10 nm, etc., and the thickness of the silicon nitride layer 5 is 40-60 nm, for example, 40 nm, 50 nm, 60 nm, etc.
[0066] It should be noted that the embodiments described are only part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, other embodiments obtained by ordinary technicians in this field without making creative work are all within the scope of protection of the present disclosure.
[0067] Example 1
[0068] Figure 2 is a schematic diagram of the cross-sectional structure of the SOI substrate in Example 1 of the present disclosure, Figure 3 It is a schematic cross-sectional structural diagram of depositing a mask layer and coating a photoresist 6 in Example 1 of the present disclosure.
[0069] like Figure 2 、 3 As shown, an SOI substrate including a supporting silicon layer 1, a buried oxide layer 2, and a top silicon layer 3 is provided. A silicon oxide layer 4 and a silicon nitride layer 5 are sequentially deposited on the top silicon layer 3 of the SOI substrate as mask layers. A photoresist 6 is coated on the surface of the mask layer to form a protection zone. The mask layer, top silicon layer 3, and buried oxide layer 2 outside the protection zone are then etched away until the supporting silicon layer 1 is exposed, thereby forming a mixed zone.
[0070] Figure 4 It is a schematic diagram of the structure after plasma etching treatment in Example 1 of the present disclosure.
[0071] like Figure 4 As shown, the photoresist 6 in the protection zone is removed, and the sidewall is bombarded at an angle of 45° by plasma etching using Ar / Cl2 plasma to expose the (110) crystal plane of the sidewall, thereby forming a smooth sidewall.
[0072] Figure 5 It is a schematic diagram of the cross-sectional structure of silicon after epitaxial growth in Example 1 of the present disclosure.
[0073] like Figure 5 As shown in FIG, silicon is epitaxially grown along the (100) crystal plane and the (110) crystal plane in the mixed region. The epitaxial interface 7 of the epitaxially grown silicon on the two crystal planes is subjected to femtosecond laser selective annealing, wherein the laser pulse width is 150 fs and the laser energy density is 0.5 J / cm 2 , to release the dislocation accumulation stress. It should be noted that Figure 5 In the figure, the epitaxial interface 7 is shown only in schematic form.
[0074] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present disclosure in detail. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.
Claims
1. A method for reducing interface defects during silicon epitaxial growth, comprising: Providing an SOI substrate comprising a supporting silicon layer, a buried oxide layer and a top silicon layer, and depositing a mask layer on the top silicon layer of the SOI substrate; coating a photoresist on at least a portion of the surface of the mask layer to form a protection zone, and etching away the mask layer, the top silicon layer, and the buried oxide layer outside the protection zone until the supporting silicon layer is exposed to obtain a mixed zone; Removing the photoresist in the protection zone, and anisotropically etching the sidewalls of the top silicon layer in the protection zone by plasma etching to expose the (110) crystal plane and form smooth sidewalls; Epitaxially growing silicon along the (100) crystal plane and the (110) crystal plane in the mixed region; The epitaxial interfaces of the (100) crystal plane epitaxially grown silicon and the (110) crystal plane epitaxially grown silicon are subjected to femtosecond laser selective annealing to release dislocation accumulation stress.
2. The method according to claim 1, wherein The plasma etching process comprises: The sidewall is obliquely bombarded by Ar / Cl2 plasma to expose the (110) crystal plane of the sidewall.
3. The method according to claim 2, wherein: The incident tilt angle of the Ar / Cl2 plasma is 45°.
4. The method according to claim 1, wherein The difference in interfacial atomic spacing between the (110) crystal plane and the (100) crystal plane is less than 0.1%.
5. The method according to claim 1, wherein In the femtosecond laser selective annealing, the laser pulse width is 140-169 fs, and the laser energy density is 0.4-0.6 J / cm 2 .
6. The method according to claim 5, wherein: Laser selective annealing includes electron beam annealing, scanning halogen lamp annealing, ion beam annealing, and ultrafast laser annealing.
7. The method according to claim 1, wherein In the femtosecond laser selective annealing, the laser scanning time is less than 1 ns.
8. The method according to claim 1, wherein The thickness of the top silicon layer is 15-55 nm, and the thickness of the buried oxide layer is 20-145 nm.
9. The method according to claim 1, wherein The mask layer includes a silicon oxide layer and a silicon nitride layer formed in sequence to protect the top silicon layer.
10. The method according to claim 9, wherein: The thickness of the silicon oxide layer is 5-10 nm, and the thickness of the silicon nitride layer is 40-60 nm.