High electron mobility transistors and integrated HEMT devices

Abstract

This invention provides a high electron mobility transistor and an integrated HEMT device. The high electron mobility transistor includes a composite cap layer, which comprises multiple stacked composite structure layers, including: a GaAs layer; In... x Ga 1‑x An As layer is disposed on the upper surface of the GaAs layer; wherein, a plurality of In... x Ga 1‑x The In composition of the As layer gradually increases along the epitaxial growth direction. The high electron mobility transistor provided in this embodiment uses a cap layer consisting of a GaAs layer and an In layer. x Ga 1‑x The alternating stacked structure of As layers, and multiple In layers x Ga 1‑x The In composition of the As layer gradually increases along the epitaxial growth direction. Because the composite cap layer has a near-superlattice periodic structure, it facilitates electron tunneling, thereby reducing resistance. The outermost In layer... x Ga 1‑x Using a high-In content material as the semiconductor in contact with ohmic metal in the As layer can significantly reduce the contact resistance of the device, thereby greatly improving the high-frequency electrical properties of high electron mobility transistors.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a high electron mobility transistor and an integrated HEMT device. Background Technology

[0002] Gallium arsenide pseudocrystalline high electron mobility transistors (GaAs pHEMTs), as three-terminal devices, possess higher electron mobility and lower scattering effects compared to other three-terminal devices, making them more suitable for applications with high frequency and noise requirements. GaAs pHEMTs are used in microwave RF chips as power amplifiers (PAs), low-noise amplifiers (LNAs), switches, and logic devices. Key performance parameters for GaAs pHEMT applications in microwave RF chips include power gain, operating frequency range, power-added efficiency (PAE), linearity, and noise figure. In GaAs pHEMT applications, reducing various parasitic parameters has become essential for improving the high-frequency electrical performance of the device. Among these, the contact resistance Rc, as a parasitic resistance that inevitably passes through the device's current path, is increasingly important for improving the high-frequency electrical performance of pHEMTs.

[0003] Therefore, how to reduce the contact resistance to improve the high-frequency electrical properties of high electron mobility transistors is one of the technical challenges that urgently needs to be solved. Summary of the Invention

[0004] Therefore, in order to overcome at least some of the defects and deficiencies in the prior art, embodiments of the present invention provide a high electron mobility transistor and an integrated HEMT device.

[0005] Specifically, in one aspect, embodiments of the present invention provide a high electron mobility transistor, the high electron mobility transistor comprising a composite cap layer, the composite cap layer comprising a plurality of stacked composite structure layers, the composite structure layers comprising: a GaAs layer; In x Ga 1-x An As layer is disposed on the upper surface of the GaAs layer; wherein, a plurality of In... x Ga 1-x The In content of the As layer gradually increases along the direction of epitaxial growth.

[0006] In a specific embodiment of the present invention, the outermost In x Ga 1-x The In component x in the As layer ranges from 0.35 to 0.40, and the In in the bottom layer... x Ga 1-x The In component x in the As layer ranges from 0.20 to 0.25.

[0007] In one specific embodiment of the present invention, the composite cap layer includes a first GaAs layer and a first In layer stacked sequentially from bottom to top. x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, third GaAs layer and third In x Ga 1-x As layer; the first In x Ga 1-x The In component x in the As layer ranges from 0.20 to 0.25, and the second In... x Ga 1-x The In component x in the As layer ranges from 0.25 to 0.35, and the third In... x Ga 1-x The range of In component x in the As layer is 0.35 to 0.40.

[0008] In a specific embodiment of the present invention, the first In x Ga 1-x The In component x in the As layer is 0.22, and the second In x Ga 1-x The In component x in the As layer is 0.35, and the third In x Ga 1-x The In component x in the As layer is 0.40.

[0009] In one specific embodiment of the present invention, the composite cap layer includes a first GaAs layer and a first In layer stacked sequentially from bottom to top. x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, third GaAs layer, third In x Ga 1-x As layer, fourth GaAs layer and fourth In x Ga 1-x As layer; the first In x Ga 1-x The In component x in the As layer ranges from 0.2 to 0.25, and the second In x Ga 1-x The In component x in the As layer ranges from 0.25 to 0.30, and the third In... x Ga 1-x The In component x in the As layer ranges from 0.30 to 0.35, and the fourth In... x Ga 1-xThe range of In component x in the As layer is 0.35 to 0.40.

[0010] In one specific embodiment of the present invention, the composite cap layer includes a first GaAs layer and a first In layer stacked sequentially from bottom to top. x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, third GaAs layer, third In x Ga 1-x As layer, fourth GaAs layer, fourth In x Ga 1-x As layer, fifth GaAs layer and fifth In x Ga 1-x As layer; the first In x Ga 1-x The In component x in the As layer ranges from 0.2 to 0.24, and the second In x Ga 1-x The In component x in the As layer ranges from 0.24 to 0.28, and the third In... x Ga 1-x The In component x in the As layer ranges from 0.28 to 0.32, and the fourth In... x Ga 1-x The In component x in the As layer ranges from 0.32 to 0.36, and the fifth In... x Ga 1-x The range of In component x in the As layer is 0.36 to 0.40.

[0011] In one specific embodiment of the present invention, the thickness of the GaAs layer ranges from 15 to 30 angstroms, and the outermost In layer... x Ga 1-x The thickness of the As layer ranges from 55 to 75 angstroms, and the innermost layer is In. x Ga 1-x The thickness of the As layer ranges from 75 to 150 angstroms, and the In layer in the middle is... x Ga 1-x The thickness of the As layer ranges from 65 to 85 angstroms, and the GaAs layer and the In layer... x Ga 1- x The doping concentration of the As layer ranges from 6E18 to 1E19 / cm². -3 .

[0012] In one specific embodiment of the present invention, the high electron mobility transistor further includes a substrate, a buffer layer, a first doped layer, a first isolation layer, a channel layer, a second isolation layer, a second doped layer, a barrier layer, a first blocking layer, a GaAs cap layer, and a second blocking layer stacked sequentially, wherein the composite cap layer is disposed on the second blocking layer.

[0013] In one specific embodiment of the present invention, the first barrier layer and the second barrier layer are InGaP barrier layers or AlAs barrier layers.

[0014] On the other hand, embodiments of the present invention also provide an integrated HEMT device comprising: a high electron mobility transistor as described above; and a PIN structure.

[0015] As can be seen from the above, the embodiments of the present invention configure the cap layer of the high electron mobility transistor as a composite cap layer. The composite cap layer includes multiple composite structure layers stacked together, and the composite structure layers include a GaAs layer and an In layer. x Ga 1-x As layer, by setting the cap layer to GaAs layer and In x Ga 1-x The alternating stacked structure of As layers, and multiple In layers x Ga 1-x The In composition of the As layer gradually increases along the epitaxial growth direction. Because the composite cap layer has a near-superlattice periodic structure, it facilitates electron tunneling, thereby reducing resistance. The outermost In layer... x Ga 1-x Using a high-In content material as the semiconductor in contact with ohmic metal in the As layer can significantly reduce the contact resistance of the device, thereby greatly improving the high-frequency electrical properties of high electron mobility transistors. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a traditional high electron mobility transistor.

[0018] Figure 2 This is a schematic diagram of the structure of a high electron mobility transistor provided in an embodiment of the present invention;

[0019] Figure 3 for Figure 2 A schematic diagram of the composite cap layer structure of a high electron mobility transistor;

[0020] Figure 4 This is a schematic diagram of another composite cap layer of the high electron mobility transistor of the present invention;

[0021] Figure 5 This is a schematic diagram of the structure of the composite cap layer of the high electron mobility transistor of the present invention;

[0022] Figures 6 to 10 for Figure 2 Schematic diagrams of the various stages in the fabrication process of medium-to-high electron mobility transistors;

[0023] Figure 11 This is a schematic diagram of the structure of an integrated HEMT device provided in an embodiment of the present invention.

[0024] Key component designations:

[0025] 11. First AlAs barrier layer; 12. GaAs cap layer; 13. Second AlAs barrier layer; 14. GaAs contact layer;

[0026] 20. Substrate; 21. Buffer layer; 22. First isolation layer; 23. Channel layer; 24. Second isolation layer; 25. Barrier layer; 26. First barrier layer; 27. GaAs cap layer; 28. Second barrier layer;

[0027] 30. Composite cap layer; 31. First GaAs layer; 32. First In layer x Ga 1-x As layer; 33, second GaAs layer; 34, second In x Ga 1-x As layer; 35. Third GaAs layer; 36. Third In x Ga 1-x As layer; 37. Fourth GaAs layer; 38. Fourth In x Ga 1-x As layer; 39. Fifth GaAs layer; 40. Fifth In x Ga 1-x As layer; 41. Source; 42. Drain; 43. Gate;

[0028] 50. PIN structure; 51. InGaP layer; 52. n + 52. GaAs layer; 53. InGaP layer; 54. IGaAs layer; 55. p + -GaAs layer; 55, first electrode; 56, second electrode; 101, isolation region. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments described in the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0030] It should be noted that all directional indicators (such as up, down, left, right, front, back, top, and bottom) in the embodiments of this invention are only used to explain the relative positional relationship and movement of the components in a specific posture (as shown in the attached figures). If the specific posture changes, the directional indicator will also change accordingly. Furthermore, the term "vertical" in the embodiments and claims refers to an angle of 90° between two components or a deviation of -5° to +5°, and the term "parallel" refers to an angle of 0° between two components or a deviation of -5° to +5°.

[0031] In the embodiments of this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0032] See Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a traditional high electron mobility transistor. Figure 2 This is a schematic diagram of a high electron mobility transistor provided in an embodiment of the present invention. The present invention provides a high electron mobility transistor, such as... Figure 2 As shown, the high electron mobility transistor includes a composite cap layer 30, which comprises multiple stacked composite structure layers, including a GaAs layer and an In layer. x Ga 1-x As layer, In x Ga 1-x An As layer is disposed on the upper surface of the GaAs layer. Among them, multiple In... x Ga 1-x The In content of the As layer gradually increases along the direction of epitaxial growth.

[0033] like Figure 1As shown, a conventional high electron mobility transistor (HEM) has a first AlAs barrier layer 11, a GaAs cap layer 12, a second AlAs barrier layer 13, and a GaAs contact layer 14 on the barrier layer. In conventional HEMs, the cap layer is usually made of GaAs material as the contact layer, i.e., the cap layer is set as GaAs contact layer 14, and AlAs material is formed as an etch barrier layer. Its ohmic contact resistance is generally in the range of 0.1Ω·mm to 0.2Ω·mm. As an etch barrier layer, AlAs has a relatively small impact on the device under low frequency conditions. However, with the gradual promotion of high frequency applications, reducing the contact resistance is becoming increasingly important as a way to improve the high frequency electrical performance of HEMs.

[0034] See Figure 2 In this embodiment of the invention, the traditional cap layer structure is modified into a composite cap layer 30. The composite cap layer 30 includes multiple composite structural layers stacked together, wherein the composite structural layers include a GaAs layer and an In layer. x Ga 1-x As layer, In x Ga 1-x An As layer is disposed on the upper surface of the GaAs layer. That is, the composite cap layer 30 includes multiple GaAs layers and multiple In layers. x Ga 1-x The As layers are alternately stacked, and multiple In layers are described. x Ga 1-x The In composition of the As layer gradually increases along the epitaxial growth direction. The approximately periodic stacked structure of the 30InGaAs / GaAs composite cap layer in high electron mobility transistors facilitates electron flow, thereby reducing resistance and improving device current density, transconductance, and gain. Simultaneously, the outermost In layer... x Ga 1-x The higher In content of the As layer, due to its extremely low bandgap, makes it more conducive to electrons crossing the potential barrier in ohmic contacts than GaAs, thereby reducing contact resistance. Furthermore, the gradual decrease in In content from top to bottom can mitigate the effects of lattice mismatch in high In content materials.

[0035] In this embodiment of the invention, the cap layer of the high electron mobility transistor is configured as a composite cap layer 30. The composite cap layer 30 includes multiple composite structure layers stacked together, including a GaAs layer and an In layer. x Ga 1-x As layer, by setting the cap layer to GaAs layer and In x Ga 1-x The alternating stacked structure of As layers, and multiple In layers x Ga 1-xThe In composition of the As layer gradually increases along the epitaxial growth direction. Because the composite cap layer 30 has a near-superlattice periodic structure, it facilitates electron tunneling, thereby reducing resistance. The outermost In layer... x Ga 1-x Using a high-In content material as the semiconductor in contact with the ohmic metal in the As layer can significantly reduce the contact resistance Rc of the device, thereby greatly improving the high-frequency electrical performance of high electron mobility transistors. Multiple In... x Ga 1- x The In composition of the As layer gradually decreases from top to bottom, which alleviates the stress caused by lattice mismatch and makes the In in direct contact with the metal more stable. x Ga 1-x The As layer can use a higher In composition material to further reduce ohmic contact resistance. Simulations comparing conventional high electron mobility transistors (HEMTs) with the HEMT of this invention reveal that the composite cap layer 30 of the HEMT of this invention has a lower cap layer resistance compared to conventional HEMTs. Simulation results show that the HEMT of this invention has a higher saturation current density and a higher peak transconductance, indicating higher gain. Small-signal simulations show that the HEMT of this invention has a greater current gain and an increased cutoff frequency from 93 GHz to 97 GHz, improving high-frequency characteristics.

[0036] See also Figure 2 The high electron mobility transistor provided in this embodiment of the invention further includes a substrate 20, a buffer layer 21, a first doped layer (not shown in the figure), a first isolation layer 22, a channel layer 23, a second isolation layer 24, a second doped layer (not shown in the figure), a barrier layer 25, a first blocking layer 26, a GaAs cap layer 27, and a second blocking layer 28 stacked sequentially, wherein the composite cap layer 30 is disposed on the second blocking layer 28.

[0037] Substrate 20 may be, for example, a semi-insulating GaAs substrate, serving as the basic support layer for the device and providing a crystal growth template. The buffer layer 21 may be made of GaAs, and may employ, for example, a multilayer AlGaAs / GaAs superlattice structure. The buffer layer 21 is used to transition between lattice mismatches and absorb stress from the substrate and the upper layer material. The first doped layer may be, for example, silicon (Si)-doped AlGaAs (n-type). The first isolation layer 22 may be, for example, undoped AlGaAs with a thickness of approximately 3-10 nm, to isolate the doped layer from the channel layer 23 and optimize carrier distribution. The channel layer 23 can be, for example, indium gallium arsenide (InGaAs) or gallium arsenide (GaAs); the second isolation layer 24 can be, for example, undoped AlGaAs, with a thickness similar to that of the first isolation layer 22, to reduce the impact of defects in the barrier layer 25 on the channel layer 23; the second doped layer can be, for example, silicon (Si) doped AlGaAs, with a doping concentration lower than that of the first doped layer, to supplement the carrier concentration and enhance conductivity; the barrier layer 25 is made of aluminum gallium arsenide (AlGaAs), and the barrier layer 25 and the channel layer 23 form a heterojunction, generating a strong interfacial electric field.

[0038] The first barrier layer 26 and the second barrier layer 28 primarily serve as etching barriers. In this embodiment, the first barrier layer 26 and the second barrier layer 28 can be, for example, InGaP or AlAs barrier layers, meaning the materials of the first barrier layer 26 and the second barrier layer 28 can include InGaP or AlAs. The high electron mobility transistor also includes a source 41, a drain 42, and a gate 43. The source 41 and the drain 42 are located on two different regions of the composite cap layer 30, and the gate 40 is disposed on the barrier layer 25 exposed by the first barrier layer 26.

[0039] Furthermore, in this embodiment, the outermost In x Ga 1-x The range of the In component x in the As layer can be, for example, 0.35 to 0.40, due to the In in the outermost layer x Ga 1-x The As layer contacts the metal; the higher the In content, the lower the barrier height, and thus the lower the ohmic contact resistance. The bottommost In layer... x Ga 1-x The range of the In component x in the As layer can be, for example, 0.20 to 0.25, and the In of the bottom layer... x Ga 1-x The As layer is closest to the underlying structure, so the In content should not be too high to prevent large lattice mismatch.

[0040] Preferably, the composite cap layer 30 of the high electron mobility transistor provided in this embodiment of the invention may include, for example, 3 to 5 stacked composite structure layers. Setting the composite cap layer 30 as a composite structure layer of 3 to 5 stacked layers can significantly reduce the contact resistance Rc of the device, greatly improve the high-frequency electrical performance of the high electron mobility transistor, and simultaneously reduce manufacturing difficulty and cost.

[0041] See Figure 3 In one embodiment of this invention, the composite cap layer 30 may, for example, include three stacked composite structural layers. Specifically, the composite cap layer 30 includes a first GaAs layer 31, a first In…, stacked sequentially from bottom to top. x Ga 1-x As layer 32, second GaAs layer 33, second In x Ga 1-x As layer 34, third GaAs layer 35 and third In x Ga 1-x As layer 36. Further, the first In x Ga 1-x The In component x in As layer 32 ranges from 0.20 to 0.25. Preferably, the first In... x Ga 1-x The In component x in As layer 32 is 0.22; the second In x Ga 1-x The In component x in As layer 34 ranges from 0.25 to 0.35. Preferably, the second In... x Ga 1-x The In component x in As layer 34 is 0.35; the third In x Ga 1-x The In component x in As layer 36 ranges from 0.35 to 0.40. Preferably, the third In... x Ga 1-x The In component x in As layer 36 is 0.40.

[0042] See Figure 4 In one embodiment of this invention, the composite cap layer 30 may, for example, include four stacked composite structure layers. Specifically, the composite cap layer 30 includes a first GaAs layer 31, a first In…, etc., stacked sequentially from bottom to top. x Ga 1-x As layer 32, second GaAs layer 33, second In x Ga 1-x As layer 34, third GaAs layer 35, third In x Ga 1-x As layer 36, fourth GaAs layer 37 and fourth In x Ga 1-xAs layer 38. Further, the first In... x Ga 1-x The In component x in As layer 32 ranges from 0.2 to 0.25. Preferably, the first In... x Ga 1-x The In component x in As layer 32 is 0.22; the second In x Ga 1-x The In component x in As layer 34 ranges from 0.25 to 0.30. Preferably, the second In... x Ga 1-x The In component x in As layer 34 is 0.28; the third In x Ga 1-x The In component x in As layer 36 ranges from 0.30 to 0.35. Preferably, the third In... x Ga 1-x The In component x in As layer 36 is 0.35; the fourth In x Ga 1-x The In component x in As layer 38 ranges from 0.35 to 0.40. Preferably, the fourth In... x Ga 1-x The In component x in As layer 38 is 0.40.

[0043] See Figure 5 In one embodiment of this invention, the composite cap layer 30 may, for example, include five stacked composite structure layers. Specifically, the composite cap layer 30 includes a first GaAs layer 31, a first In…, etc., stacked sequentially from bottom to top. x Ga 1-x As layer 32, second GaAs layer 33, second In x Ga 1-x As layer 34, third GaAs layer 35, third In x Ga 1-x As layer 36, fourth GaAs layer 37, fourth In x Ga 1-x As layer 38, fifth GaAs layer 39 and fifth In x Ga 1-x As layer 40. Further, the first In... x Ga 1-x The In component x in the As layer 32 ranges from 0.2 to 0.24. Preferably, the first In... x Ga 1-x The In component x in As layer 32 is 0.22; the second In x Ga 1-x The In component x in As layer 34 ranges from 0.24 to 0.28. Preferably, the second In... x Ga1-x The In component x in As layer 34 is 0.26; the third In x Ga 1-x The In component x in As layer 36 ranges from 0.28 to 0.32. Preferably, the third In... x Ga 1-x The In component x in As layer 36 is 0.30; the fourth In x Ga 1-x The In component x in As layer 38 ranges from 0.32 to 0.36. Preferably, the fourth In... x Ga 1-x The In component x in As layer 38 is 0.35; the fifth In x Ga 1-x The In component x in As layer 40 ranges from 0.36 to 0.40. Preferably, the fifth In... x Ga 1-x The In component x in As layer 40 is 0.40.

[0044] In this embodiment, the thickness of the GaAs layer can be, for example, 15–30 angstroms, and the GaAs layer and In… x Ga 1-x The As layers form a superlattice-like structure to reduce the difficulty for electrons to pass through the composite cap layer 30, thereby reducing contact resistance. The outermost In layer... x Ga 1-x The thickness of the As layer can range, for example, from 55 to 75 angstroms. At this thickness, the outermost In layer... x Ga 1-x The growth of the As layer does not result in mismatch and also reduces ohmic contact resistance. The In layer described in the intermediate layer... x Ga 1-x The thickness of the As layer ranges from 65 to 85 angstroms, because the In layer in the middle... x Ga 1-x The In content of the As layer gradually decreases, and its growth thickness can be slightly increased to reduce electrical resistance. The bottom layer of In... x Ga 1-x The thickness of the As layer ranges from 75 to 150 angstroms, due to the bottom layer of In... x Ga 1-x The As layer has the lowest In content, so its thickness can be set to 75–150 angstroms. The GaAs layer and the In... x Ga 1-x The As layers are all heavily doped with N-type doping, with doping concentrations ranging from 6E18 to 1E19 / cm³. -3 This doping concentration setting can reduce contact resistance.

[0045] Please see Figures 6 to 10 , Figures 6 to 10 This is a schematic diagram of the structure of the high electron mobility transistor of the present invention at each stage of the fabrication process.

[0046] First, such as Figure 6 As shown, a buffer layer 21, a first doped layer (not shown), a first isolation layer 22, a channel layer 23, a second isolation layer 24, a second doped layer (not shown), and a barrier layer 25 are sequentially stacked on the substrate 20. Next, as... Figure 7 As shown, a first barrier layer 26, a GaAs cap layer 27, a second barrier layer 28, and a composite cap layer 30 are sequentially grown on the barrier layer 25 from bottom to top. Then, as... Figure 8 As shown, a source electrode 41 and a drain electrode 42 are grown on the composite cap layer 30. Figure 9 As shown, the composite cap layer 30 and the second barrier layer 28 are etched to expose the GaAs cap layer 27. See also Figure 10 The GaAs cap layer 27 and the first barrier layer 26 are etched to expose the barrier layer 25, and a gate 53 is formed on the barrier layer 25.

[0047] The above preparation steps are only used to illustrate one method of preparing the high electron mobility transistor device of the present invention, and the present invention is not limited thereto.

[0048] See Figure 11 This invention also provides an integrated HEMT device, which includes a high electron mobility transistor and a PIN structure 50. The high electron mobility transistor is the high electron mobility transistor described in the foregoing embodiments. The PIN structure 50 may include InGaP layers 51 and 52 sequentially stacked on the composite cap layer 30. + -GaAs layer 52, InGaP layer 53, IGaAs layer 54 and p + -GaAs layer 55. A first electrode 55 and a second electrode 56 are also disposed on the PIN structure 50. The first electrode 55 is electrically connected to n. + -GaAs layer 52, second electrode 56 electrically connected to p + -GaAs layer. The first electrode 55 and the second electrode 56 can be fabricated in the same process as the source 41, drain 42, and gate 43. The buffer layer 21 on the substrate 20 can also have an isolation region 101 formed by ion implantation. The lattice mismatch problem between the PIN structure 50 and the composite cap layer 30 can be solved by the composite cap layer 30. The PIN structure 50 can be used as a diode.

[0049] Furthermore, it is understood that the foregoing embodiments are merely illustrative examples of the present invention. Provided that the technical features do not conflict, the structure is not contradictory, and the purpose of the invention is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high electron mobility transistor, characterized in that, The high electron mobility transistor includes a barrier layer, a composite cap layer, a source, a gate, and a drain. The composite cap layer and the gate are located on the barrier layer. The source and the drain are located on the composite cap layer on both sides of the gate. The composite cap layer includes multiple stacked composite structure layers, each of which includes: GaAs layer; In x Ga 1-x An As layer is disposed on the upper surface of the GaAs layer; Among them, multiple In x Ga 1-x The In content of the As layer gradually increases along the direction of epitaxial growth.

2. The high electron mobility transistor as described in claim 1, characterized in that, The outermost layer of In x Ga 1-x The In component x in the As layer ranges from 0.35 to 0.40, and the In in the bottom layer... x Ga 1-x The In component x in the As layer ranges from 0.20 to 0.

25.

3. The high electron mobility transistor as described in claim 1, characterized in that, The composite cap layer includes a first GaAs layer and a first In layer stacked sequentially from bottom to top. x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, third GaAs layer and third In x Ga 1-x As layer; the first In x Ga 1-x The In component x in the As layer ranges from 0.20 to 0.25, and the second In... x Ga 1-x The In component x in the As layer ranges from 0.25 to 0.35, and the third In... x Ga 1-x The range of In component x in the As layer is 0.35~0.

40.

4. The high electron mobility transistor as described in claim 3, characterized in that, The first In x Ga 1-x The In component x in the As layer is 0.22, and the second In x Ga 1-x The In component x in the As layer is 0.35, and the third In x Ga 1-x The In component x in the As layer is 0.

40.

5. The high electron mobility transistor as described in claim 1, characterized in that, The composite cap layer includes a first GaAs layer and a first In layer stacked sequentially from bottom to top. x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, third GaAs layer, third In x Ga 1-x As layer, fourth GaAs layer and fourth In x Ga 1-x As layer; the first In x Ga 1-x The In component x in the As layer ranges from 0.2 to 0.25, and the second In x Ga 1-x The In component x in the As layer ranges from 0.25 to 0.30, and the third In... x Ga 1-x The In component x in the As layer ranges from 0.30 to 0.35, and the fourth In... x Ga 1-x The range of In component x in the As layer is 0.35~0.

40.

6. The high electron mobility transistor as claimed in claim 1, characterized in that, The composite cap layer includes a first GaAs layer and a first In layer stacked sequentially from bottom to top. x Ga 1-x As layer, second GaAs layer, second In x Ga 1-x As layer, third GaAs layer, third In x Ga 1-x As layer, fourth GaAs layer, fourth In x Ga 1-x As layer, fifth GaAs layer and fifth In x Ga 1-x As layer; the first In x Ga 1-x The In component x in the As layer ranges from 0.2 to 0.24, and the second In x Ga 1-x The In component x in the As layer ranges from 0.24 to 0.28, and the third In... x Ga 1-x The In component x in the As layer ranges from 0.28 to 0.32, and the fourth In... x Ga 1- x The In component x in the As layer ranges from 0.32 to 0.36, and the fifth In... x Ga 1-x The range of In component x in the As layer is 0.36~0.

40.

7. The high electron mobility transistor as claimed in claim 1, characterized in that, The thickness of the GaAs layer ranges from 15 to 30 angstroms, and the outermost In... x Ga 1-x The thickness of the As layer ranges from 55 to 75 angstroms, and the bottom layer is In. x Ga 1-x The thickness of the As layer ranges from 75 to 150 angstroms, and the In layer in the middle is... x Ga 1-x The thickness of the As layer ranges from 65 to 85 angstroms, and the GaAs layer and the In layer... x Ga 1-x The doping concentration of the As layer ranges from 6E18 to 1E19 / cm². -3 .

8. The high electron mobility transistor according to any one of claims 1 to 7, characterized in that, The high electron mobility transistor further includes a substrate, a buffer layer, a first doped layer, a first isolation layer, a channel layer, a second isolation layer, a second doped layer, the barrier layer, a first blocking layer, a GaAs cap layer, and a second blocking layer stacked sequentially, with the composite cap layer disposed on the second blocking layer.

9. The high electron mobility transistor as described in claim 8, characterized in that, The first barrier layer and the second barrier layer are InGaP barrier layers or AlAs barrier layers.

10. An integrated HEMT device, characterized in that, include: The high electron mobility transistor as described in any one of claims 1 to 9; as well as A PIN structure is disposed on the composite cap layer, and an isolation region is provided between the composite cap layer below the PIN structure and the composite cap layer below the drain.

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