An encoder error identification circuit, method, and encoder system

Abstract

This application provides an encoder error detection circuit, method, and encoder system. The circuit includes: a signal input unit, a coil counting unit, an error detection unit, and a main control chip. A first terminal of the signal input unit is connected to the encoder, and a second terminal of the signal input unit is connected to the first terminal of the coil counting unit, the first terminal of the error detection unit, and the main control chip. The second terminals of the coil counting unit and the error detection unit are connected to the main control chip. The signal input unit receives a magnetic switch signal output from a magnetic switch in the encoder; wherein the magnetic switch signal is a Gray code. The coil counting unit outputs a wake-up signal based on the magnetic switch signal; the wake-up signal is used to wake up the main control chip. The error detection unit outputs an identification signal based on the magnetic switch signal. The main control chip determines the abnormal condition of the magnetic switch based on the identification signal from the error detection unit. When the magnetic switch is normal, it counts the number of turns based on the wake-up signal, avoiding errors in the count caused by magnetic switch damage.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to an encoder error identification circuit, method, and encoder system. Background Technology

[0002] An encoder is a device that converts physical quantities into electrical signals, and magnetic multi-turn technology is an important technology in encoders. Magnetic multi-turn encoders primarily utilize changes in a magnetic field to measure the rotation angle and number of turns. They typically consist of a permanent magnet, a magnetic sensor (such as a Hall element), and electronic circuitry. The permanent magnet is mounted on the rotating shaft, and the magnetic sensor detects changes in the magnetic field, thereby obtaining the angular position information and the number of turns of the rotating shaft.

[0003] Existing magnetic multi-turn technology uses two magnetic switches to form four sets of Gray codes (00-01-11-10) for signal change detection. Each change in the magnetic switch signal wakes up the main control chip to count turns. Therefore, for one encoder revolution, the main control chip is typically woken up four times. However, this technology suffers from a wiring harness problem: if a magnetic switch is damaged, the encoder will only wake up once per revolution, making it impossible to detect the damage and potentially leading to incorrect revolution counts, thus affecting the overall operational accuracy of the system. Summary of the Invention

[0004] This application provides an encoder error identification circuit, method, and encoder system to identify magnetic switch damage under low power conditions and avoid errors in the number of turns calculation.

[0005] In a first aspect, embodiments of this application provide an encoder error identification circuit, including: a signal input unit, a coil counting unit, an error identification unit, and a main control chip; a first terminal of the signal input unit is connected to the encoder, and a second terminal of the signal input unit is connected to the first terminal of the coil counting unit, the first terminal of the error identification unit, and the main control chip; the second terminal of the coil counting unit and the second terminal of the error identification unit are connected to the main control chip;

[0006] The signal input unit is used to receive the magnetic switch signal output by the magnetic switch in the encoder; wherein, the magnetic switch signal is Gray code;

[0007] The count unit is used to output a wake-up signal based on the magnetic switch signal; the wake-up signal is used to wake up the main control chip.

[0008] The error detection unit is used to output an identification signal based on the magnetic switch signal, which serves as the basis for identifying magnetic switch abnormalities and is sent to the main control chip to indicate the abnormality of the magnetic switch signal in the main control chip.

[0009] The main control chip is used to determine whether there is an abnormality in the magnetic switch based on the identification signal output by the error identification unit, and to perform counting based on the magnetic switch signal when the magnetic switch signal is normal.

[0010] In one embodiment, the error identification unit includes: a first identification subunit and a second identification subunit;

[0011] The first terminal of the first identification subunit is connected to the signal input unit, and the second terminal of the first identification subunit is connected to the main control chip; the first identification subunit is used to output a first identification signal according to the magnetic switch signal.

[0012] The first end of the second identification subunit is connected to the signal input unit, and the second end of the second identification subunit is connected to the main control chip; the second identification subunit is used to output a second identification signal according to the magnetic switch signal.

[0013] The main control chip is used to determine the abnormal condition of the magnetic switch based on the first identification signal or the second identification signal.

[0014] In one embodiment, the main control chip is used to determine that the magnetic switch is abnormal when the first identification signal or the second identification signal is at a first level.

[0015] In one embodiment, the magnetic switch signal includes: a first magnetic switch signal, a second magnetic switch signal, and a third magnetic switch signal, and the first identification subunit includes a first NOT gate, a second NOT gate, a third NOT gate, a first AND gate, a second AND gate, and a first diode;

[0016] The first terminal of the first NOT gate is used to receive the first magnetic switch signal, and the second terminal of the first NOT gate is connected to the first terminal of the first AND gate.

[0017] The first terminal of the second NOT gate is used to receive the second magnetic switch signal; the second terminal of the second NOT gate is connected to the second terminal of the first AND gate; the third terminal of the first AND gate is connected to the first terminal of the second AND gate.

[0018] The first terminal of the third NOT gate is used to receive the third magnetic switch signal, and the second terminal of the third NOT gate is connected to the second terminal of the second AND gate.

[0019] The third terminal of the second AND gate is connected to the main control chip. The third terminal of the second AND gate is connected to the wake-up pin of the main control chip through the first diode. The third terminal of the second AND gate is used to output the first identification signal.

[0020] In one embodiment, the second identification subunit includes a third AND gate, a fourth AND gate, and a second diode;

[0021] The first terminal of the third AND gate is used to receive the first magnetic switch signal, the second terminal of the third AND gate is used to receive the second magnetic switch signal, and the third terminal of the third AND gate is connected to the first terminal of the fourth AND gate.

[0022] The second terminal of the fourth AND gate is used to receive the third magnetic switch signal. The third terminal of the fourth AND gate is connected to the main control chip. The third terminal of the fourth AND gate is connected to the wake-up pin of the main control chip through the second diode. The third terminal of the fourth AND gate is used to output the second identification signal.

[0023] In one embodiment, the magnetic switch signal includes: a first magnetic switch signal, a second magnetic switch signal, and a third magnetic switch signal, and the coil counting unit includes a fifth AND gate, a fourth NOT gate, a sixth AND gate, an XOR gate, and a third diode;

[0024] The first terminal of the fifth AND gate is used to receive the first magnetic switch signal, the second terminal of the fifth AND gate is used to receive the second magnetic switch signal through the fourth NOT gate, and the third terminal of the fifth AND gate is connected to the first terminal of the sixth AND gate.

[0025] The first terminal of the XOR gate is used to receive the third magnetic switch signal, and the third terminal of the XOR gate is connected to the second terminal of the sixth AND gate.

[0026] The third terminal of the sixth AND gate is connected to the wake-up pin of the main control chip through the third diode. The third terminal of the sixth AND gate is used to output the wake-up signal.

[0027] In one embodiment, the counting unit further includes a delay unit, the first end of which is used to receive a third magnetic switch signal, and the second end of which is connected to the second end of an XOR gate.

[0028] In one embodiment, the delay unit includes a first resistor and a first capacitor;

[0029] The first end of the first resistor is used to connect to the third magnetic switch signal, and the second end of the first resistor is connected to the first end of the first capacitor and the second end of the XOR gate.

[0030] The second terminal of the first capacitor is grounded.

[0031] Secondly, embodiments of this application provide an encoder error identification method, the method comprising:

[0032] Acquire the identification signal and determine the abnormal condition of the magnetic switch based on the identification signal;

[0033] If the magnetic switch is working properly, counting is performed based on the magnetic switch signal.

[0034] In one embodiment, the identification signal includes a first identification signal and a second identification signal. Acquiring the identification signal and determining the abnormal condition of the magnetic switch based on the identification signal specifically includes:

[0035] If the first identification signal is at the first level, then the magnetic switch is determined to be faulty;

[0036] If the first identification signal is at the second level, then continue to determine whether the second identification signal is at the first level;

[0037] If the second identification signal is at the first level, then the magnetic switch is determined to be faulty.

[0038] Thirdly, embodiments of this application provide an encoder system, including an encoder and an encoder error identification circuit as described above;

[0039] The encoder is connected to the encoder error recognition circuit.

[0040] In one embodiment, the encoder includes a rotating shaft, an encoder disk that rotates along the axis of the rotating shaft, a magnetic element disposed on the rotating shaft, and three magnetic switches located within the magnetic field range of the magnetic element.

[0041] The magnetic switch is connected to the encoder error recognition circuit and is used to output the magnetic switch signal.

[0042] In one embodiment, the angle between the axial directions of two adjacent magnetic switches ranges from 60° to 120°.

[0043] In one embodiment, the angle between the axial directions of two adjacent magnetic switches is 120°.

[0044] This application provides an encoder error identification circuit, method, and encoder system. The circuit includes: a signal input unit, a coil counting unit, an error identification unit, and a main control chip. A first terminal of the signal input unit is connected to the encoder, and a second terminal of the signal input unit is connected to the first terminal of the coil counting unit, the first terminal of the error identification unit, and the main control chip. The second terminals of the coil counting unit and the error identification unit are connected to the main control chip. The signal input unit receives a magnetic switch signal output from a magnetic switch in the encoder; wherein the magnetic switch signal is a Gray code. The coil counting unit outputs a wake-up signal based on the magnetic switch signal; the wake-up signal is used to wake up the main control chip. The error identification unit outputs an identification signal based on the magnetic switch signal. The main control chip determines the abnormal condition of the magnetic switch based on the identification signal, and counts based on the magnetic switch signal when the magnetic switch is normal. By adding an error identification unit, the main control chip determines whether the magnetic switch is damaged based on the identification signal output by the error identification unit, and counts based on the wake-up signal when the magnetic switch is normal, avoiding errors in coil count calculation caused by magnetic switch damage. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0046] Figure 1 This is a schematic diagram of the structure of a magnetic switch provided in an embodiment of this application;

[0047] Figure 2 This is a schematic diagram of the encoder error recognition circuit provided in an embodiment of this application;

[0048] Figure 3 A schematic diagram of the encoder error recognition circuit provided in another embodiment of this application;

[0049] Figure 4 This is a waveform diagram of the signal when the rotating shaft rotates clockwise according to one embodiment of this application;

[0050] Figure 5 This is a signal waveform diagram of the rotating shaft reversing according to an embodiment of this application;

[0051] Figure 6 This is a signal waveform diagram of a magnetic switch T2 when it is damaged, provided in an embodiment of this application.

[0052] Figure 7 This is a signal waveform diagram of a magnetic switch T2 when it is damaged, provided in another embodiment of this application;

[0053] Figure 8 This is a flowchart of an encoder error identification method provided in an embodiment of this application.

[0054] Figure label:

[0055] 210 Signal Input Unit; 220 Error Code Recognition Unit; 230 Cycle Counting Unit; 240 Main Control Chip; 221 First Recognition Subunit; 222 Second Recognition Subunit; V1 First Magnetic Switch Signal; V2 Second Magnetic Switch Signal; V3 Third Magnetic Switch Signal; U1 First NOT Gate; U2 Second NOT Gate; U3 Third NOT Gate; U4 First AND Gate; U5 Second AND Gate; U6 Third AND Gate; U7 Fourth AND Gate; U8 Fourth NOT Gate; U9 Fifth AND Gate; U10 Sixth AND Gate; U11 XOR Gate; D1 First Diode; D2 Second Diode; D3 Third Diode; R1 First Resistor; C1 First Capacitor.

[0056] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0057] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0058] First, let me explain the terms used in this application:

[0059] Gray code: refers to a special binary encoding method. Its characteristic is that there is only one bit difference between two adjacent codewords. Due to the cyclic property of Gray code, there is only one bit difference between the largest and smallest numbers. Therefore, it is also called cyclic code or reflective code.

[0060] Multi-turn zero point: refers to the reference position that the encoder returns to after rotating multiple revolutions. This reference position is used to determine the starting position within each revolution of the encoder, helping the system to accurately count and identify the corresponding position. In encoder applications, multi-turn zero point is crucial because it provides a fixed reference point, ensuring a consistent benchmark for each measurement.

[0061] Existing technologies typically use two magnetic switches to generate four Gray code combinations (00-01-11-10). Each change in the magnetic switch signal wakes up the main control chip for rotation counting. Therefore, the main control chip is woken up four times for each encoder rotation. However, if one magnetic switch fails, the main control chip may only be woken up once per encoder rotation, making it impossible to accurately determine the switch's failure and leading to incorrect rotation counts, thus affecting the system's accuracy and reliability. The encoder error detection circuit provided in this application incorporates an error detection unit. The main control chip determines whether the magnetic switch is damaged based on the detection signal output by the error detection unit, and counts rotations based on the wake-up signal when the magnetic switch is functioning normally, thus avoiding errors in rotation counts caused by magnetic switch failure.

[0062] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0063] This application provides an encoder system, including an encoder and an encoder error identification circuit; wherein the encoder is connected to the encoder error identification circuit.

[0064] In one embodiment, the encoder includes a rotating shaft, an encoder code disk that rotates along the axis of the rotating shaft, a magnetic element disposed on the rotating shaft, and three magnetic switches located within the magnetic field range of the magnetic element; the magnetic switches are connected to an encoder error identification circuit and are used to output magnetic switch signals.

[0065] Specifically, if one magnetic switch is used, the encoder can only output two states, 0 and 1, per revolution. When the magnetic switch is damaged, the signal remains either high or low, making it impossible to detect the damage. If two magnetic switches are used, the encoder outputs a 00-01-11-10 combination per revolution. If one of the magnetic switches is damaged and remains high, the Gray code output for one revolution is 10-00. Analysis of the Gray code signal shows no abnormality; a 10-00 combination is normal, and the system cannot detect a damaged magnetic switch. If three magnetic switches are used, the encoder outputs a 001-101-100-110-010-011 combination per revolution. If the first magnetic switch is damaged and remains constantly high, the encoder outputs 101-101-100-110-110-111. The 110-111 combination is abnormal, indicating a damaged magnetic switch. The same logic applies to the damage of other magnetic switches. Using more than three magnetic switches would increase costs and is not the optimal choice. Therefore, this application uses three magnetic switches, which are only activated once after the encoder rotates one revolution. Secondly, the encoder error identification circuit can accurately identify magnetic switch damage by utilizing the characteristics of three-bit Gray code.

[0066] In one embodiment, the angle between the axial directions of two adjacent magnetic switches ranges from 60° to 120°.

[0067] In one embodiment, the angle between the axial directions of two adjacent magnetic switches is 120°.

[0068] Specifically, if the angle between the axes of two adjacent magnetic switches is 120°, each magnetic switch will change its state (from 0 to 1 or from 1 to 0) within a specific angular range during rotation. Each magnetic switch will only encounter the next state change position after rotating 120°. The angular interval between the points where the states of two adjacent magnetic switches change simultaneously is 60°. Within each 60° angular interval, the Gray code combination remains unchanged. This distribution makes the mechanical angle range corresponding to each Gray code relatively uniform. For example, when an object rotates to a certain position, the corresponding Gray code is 000. As it rotates, this Gray code will not change within the next 60° rotation angle range, ensuring that the mechanical angle range corresponding to each Gray code is clear during measurement or encoding, and preventing code group confusion due to uneven angle distribution. If the angle between the axes of two adjacent magnetic switches is not 120°, and is less than 120° (e.g., less than 60°), then during rotation, the states of the adjacent magnetic switches may change rapidly within a very short angular range, causing some Gray codes to remain unchanged within an angle range of less than 60°. If the angle between the axes of two adjacent magnetic switches is greater than 120° (e.g., greater than 180°), then there may be excessively large angle ranges between the two magnetic switches, while the angle ranges in other areas may be too small. When the angle between the two magnetic switches is less than 60° or greater than 180°, the encoding pattern of the Gray code will be disrupted, resulting in some Gray code combinations that should not exist, or some Gray code combinations that are missing, i.e., Gray code errors. Therefore, the angle between the axes of two adjacent magnetic switches should be between 60° and 180°. When the angle between the axes of two adjacent magnetic switches is 120°, the accuracy of Gray code encoding and the uniformity of angle measurement can be guaranteed; secondly, the fault tolerance of the encoder can be improved, thereby achieving the effect of waking up once the encoder rotates one revolution.

[0069] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a magnetic switch provided in one embodiment of this application. The encoder has three magnetic switches, with the axial directions of adjacent magnetic switches forming an angle of 120°. This design ensures that each switch can generate a different state at different angles when the encoder rotates; secondly, it improves the encoder's fault tolerance, achieving a wake-up time of only once per revolution of the encoder. Since each magnetic switch has two states, on (high level) and off (low level), the combined states of the three switches can form 2... 3There are 8 possible states, but only six are actually valid. When the encoder rotates one revolution, the magnetic switch signals output by the three magnetic switches T1, T2, and T3 are 001-101-100-110-010-011-011 or 001-011-010-110-100-101-001, respectively. These magnetic switch signals are Gray code. Using Gray code ensures that only one bit changes between adjacent states during encoder rotation, reducing the possibility of errors and confusion, and improving the accuracy and reliability of the encoder.

[0070] If the encoder outputs a magnetic switch signal of 000, it means that all magnetic switches are in a low-level state, which is typically the state when the encoder is not rotating or the power is not on. Therefore, this should not occur under normal operating conditions. State 111 means that all magnetic switches are in a high-level state. This state should also not occur under normal operating conditions, because the encoder is designed to maintain its state changes during rotation. If this state occurs, it indicates that the encoder may be faulty or not functioning properly.

[0071] V1, V2, and V3 represent magnetic switch signals. Which magnetic switch V1, V2, and V3 correspond to depends on the multi-turn zero-point selection. The relationship between V1, V2, V3, magnetic switches T1, T2, and T3, and the multi-turn zero-point is shown in Table 1. Table 1 illustrates the relationship between the multi-turn zero-point position selection and the magnetic switches and their signals. The multi-turn zero-point position is selected as the reference position for one revolution of the encoder. For example, if 101-100 is selected as the multi-turn zero-point, that is, when the Gray code changes from 101 to 100, the revolution count increases by 1, and when the Gray code changes from 100 to 101, the revolution count decreases by 1. In this case, V1 corresponds to T1, V2 corresponds to T2, and V3 corresponds to T3.

[0072] Table 1. Relationship between multi-turn zero position selection and magnetic switch and magnetic switch signal

[0073]

[0074] like Figure 2 As shown, Figure 2This is a schematic diagram of an encoder error recognition circuit provided in an embodiment of this application. The encoder error recognition circuit includes: a signal input unit 210, a coil counting unit 230, an error recognition unit 220, and a main control chip 240. The first terminal of the signal input unit 210 is connected to the encoder, and the second terminal of the signal input unit 210 is connected to the first terminal of the coil counting unit 230, the first terminal of the error recognition unit 220, and the main control chip 240. The second terminals of the coil counting unit 230 and the second terminal of the error recognition unit 220 are connected to the main control chip 240. The signal input unit 210 is used to receive the magnetic switch signal output by the magnetic switch in the encoder. The magnetic switch signal is a Gray code. The coil counting unit 230 is used to output a wake-up signal based on the magnetic switch signal. The wake-up signal is used to wake up the main control chip 240. The error recognition unit 220 is used to output an recognition signal based on the magnetic switch signal. The main control chip 240 is used to determine the abnormal condition of the magnetic switch based on the recognition signal, and to count based on the magnetic switch signal when the magnetic switch is normal.

[0075] Specifically, the signal input unit 210 receives the signal output from the magnetic switch from the encoder, and the signal is transmitted in Gray code form; the rotation counting unit 230 generates a wake-up signal based on the received magnetic switch signal, which activates the main control chip 240 for further processing; the error identification unit 220 generates an identification signal based on the magnetic switch signal, which is used to detect abnormalities in the magnetic switch signal, such as errors or signal loss. The use of Gray code helps reduce errors that may occur during signal conversion. The encoder error identification circuit provided in this application can effectively identify and process errors in the encoder signal, thereby improving system reliability and preventing errors in rotation calculation caused by magnetic switch damage.

[0076] In one embodiment, the output of the error detection unit 220 is also connected to the wake-up pin of the main control chip 240. If the identification signal output by the error detection unit 220 is high, the main control chip 240 can also be woken up. Since the main control chip 240 has two wake-up sources—the counting unit 230 and the error detection unit 220—after being woken up, the main control chip 240 needs to determine whether the magnetic switch is abnormal based on the identification signal. If the magnetic switch is not abnormal, it starts counting; if the magnetic switch is abnormal, the main control chip 240 stops counting.

[0077] In one embodiment, such as Figure 3 As shown, Figure 3This is a schematic diagram of an encoder error recognition circuit provided in another embodiment of this application. The error recognition unit 220 includes: a first recognition subunit 221 and a second recognition subunit 222; a first terminal of the first recognition subunit 221 is connected to a signal input unit 210, and a second terminal of the first recognition subunit 221 is connected to a main control chip 240; the first recognition subunit 221 is used to output a first recognition signal according to a magnetic switch signal; a first terminal of the second recognition subunit 222 is connected to a signal input unit 210, and a second terminal of the second recognition subunit 222 is connected to the main control chip 240; the second recognition subunit 222 is used to output a second recognition signal according to a magnetic switch signal; the main control chip 240 is used to determine the abnormal condition of the magnetic switch according to the first recognition signal or the second recognition signal.

[0078] Specifically, the output terminals of the first identification subunit 221 and the second identification subunit 222 are also connected to the wake-up pin of the main control chip 240. If the first identification signal and the second identification signal are at a high level, the main control chip 240 can also be woken up. Since the wake-up sources of the main control chip 240 are the counting unit 230, the first identification subunit 221 and the second identification subunit 222, the main control chip 240 also needs to determine whether the magnetic switch is abnormal based on the first identification signal or the second identification signal after being woken up. If the magnetic switch is not abnormal, it will start counting; if the magnetic switch is abnormal, the main control chip 240 will stop counting.

[0079] In one embodiment, the main control chip 240 is used to determine that the magnetic switch is abnormal when the first identification signal or the second identification signal is at a first level.

[0080] In one embodiment, the first level is a high level. After the main control chip 240 is woken up, it checks whether the first identification signal or the second identification signal is a high level. If the first identification signal or the second identification signal is a high level, it is confirmed that there is an abnormality in the magnetic switch in the encoder. Thus, in the case of an abnormal magnetic switch, the main control chip 240 cannot count revolutions based on the wake-up signal received, thereby avoiding revolution counting errors.

[0081] In one embodiment, please refer to Figure 3The magnetic switch signals include: a first magnetic switch signal V1, a second magnetic switch signal V2, and a third magnetic switch signal V3. The first identification subunit 221 includes a first NOT gate U1, a second NOT gate U2, a third NOT gate U3, a first AND gate U4, a second AND gate U5, and a first diode D1. The first terminal of the first NOT gate U1 is used to connect to the first magnetic switch signal V1, and the second terminal of the first NOT gate U1 is connected to the first terminal of the first AND gate U4. The first terminal of the second NOT gate U2 is used to connect to the second magnetic switch signal V2, and the second terminal of the second NOT gate U2 is connected to the second terminal of the first AND gate U4. The third terminal of the first AND gate U4 is connected to the first terminal of the second AND gate U5. The first terminal of the third NOT gate U3 is used to connect to the third magnetic switch signal V3, and the second terminal of the third NOT gate U3 is connected to the second terminal of the second AND gate U5. The third terminal of the second AND gate U5 is connected to the main control chip 240, and the third terminal of the second AND gate U5 is connected to the wake-up pin of the main control chip 240 through the first diode D1. The third terminal of the second AND gate U5 is used to output the first identification signal.

[0082] Specifically, during normal encoder operation, assuming magnetic switches T1, T2, and T3 are all in a normal state, the output signal is 101. In this state, the inputs to the second AND gate U5 are all low, therefore the output of the second AND gate U5 will also be low, causing the first identification signal output to be low. If one of the magnetic switches malfunctions, for example, if the second magnetic switch signal V2 remains low, the encoder state may change to combinations such as 101, 100, and 001. At this time, the output of the first AND gate U4 will be high, and the second AND gate U5 will output high, indicating a possible malfunction in the detection magnetic switch. The first identification signal will output high, and the main control chip 240 will be woken up.

[0083] In one embodiment, please refer to Figure 3 The second identification subunit 222 includes a third AND gate U6, a fourth AND gate U7, and a second diode D2. The first terminal of the third AND gate U6 is used to receive the first magnetic switch signal V1, the second terminal of the third AND gate U6 is used to receive the second magnetic switch signal V2, and the third terminal of the third AND gate U6 is connected to the first terminal of the fourth AND gate U7. The second terminal of the fourth AND gate U7 is used to receive the third magnetic switch signal V3, the third terminal of the fourth AND gate U7 is connected to the main control chip 240, the third terminal of the fourth AND gate U7 is connected to the wake-up pin of the main control chip 240 through the second diode D2, and the third terminal of the fourth AND gate U7 is used to output the second identification signal.

[0084] Specifically, when the encoder rotates normally, the output Gray code should not show abnormal states such as 000 or 111. If the system detects 111 or other abnormal combinations, it means that a magnetic switch is damaged. When the encoder's state reaches 111, both inputs of the fourth AND gate U7 are at low level, causing the fourth AND gate U7 to output at high level, thereby generating a second identification signal. The second identification signal is input to the wake-up pin of the main control chip 240 through the second diode D2, waking up the main control chip 240 and indicating that the magnetic switch is faulty.

[0085] In one embodiment, please refer to Figure 3 The magnetic switch signals include: a first magnetic switch signal V1, a second magnetic switch signal V2, and a third magnetic switch signal V3. The counting unit 230 includes a fifth AND gate U9, a fourth NOT gate U8, a sixth AND gate U10, an XOR gate U11, and a third diode D3. The first terminal of the fifth AND gate U9 is used to connect to the first magnetic switch signal V1, the second terminal of the fifth AND gate U9 is connected to the second magnetic switch signal V2 through the fourth NOT gate U8, and the third terminal of the fifth AND gate U9 is connected to the first terminal of the sixth AND gate U10. The first terminal of the XOR gate U11 is used to connect to the third magnetic switch signal V3, and the third terminal of the XOR gate U11 is connected to the second terminal of the sixth AND gate U10. The third terminal of the sixth AND gate U10 is connected to the wake-up pin of the main control chip 240 through the third diode D3, and the third terminal of the sixth AND gate U10 is used to output a wake-up signal.

[0086] In one embodiment, the counting unit 230 further includes a delay unit, the first end of which is used to receive the third magnetic switch signal V3, and the second end of which is connected to the second end of the XOR gate U11.

[0087] Specifically, in the circuit, when the third magnetic switch signal V3 changes from low to high, this change affects the behavior of the delay unit. The first capacitor C1 begins to charge, and the voltage gradually increases. However, due to the characteristics of the delay unit, the voltage increase is not instantaneous but rather a smooth process. The two inputs of the XOR gate U11 are affected by the first resistor R1 and the first capacitor C1. When the third magnetic switch changes from low to high, the charging process of the first capacitor C1 causes a brief combination of low and high levels at the input of the XOR gate U11. This state change is precisely the working principle of the XOR gate U11; when the two input levels are different, the output is high. Because the input of the XOR gate U11 experiences a short-term change between low and high levels, the XOR gate U11 outputs a brief high-level pulse. This means that although the state of the third magnetic switch signal V3 has changed to high, the output of the XOR gate U11 is still affected by the change in its input state, producing a momentary output signal. The two inputs of the sixth AND gate U10 receive the high-level pulse from the XOR gate U11. Since both inputs of the sixth AND gate U10 are also high when the XOR gate U11 outputs a high level, the sixth AND gate U10 will output a brief high-level pulse. This is because the sixth AND gate U10 is an AND gate, and its output will also be high when all inputs are high. The high-level pulse output by the sixth AND gate U10 will be transmitted to the wake-up pin of the main control chip 240 through the third diode D3.

[0088] Specifically, the delay unit enables smooth circuit transitions. It smoothly processes changes in the input signal, preventing immediate and drastic changes in the output signal when the encoder state changes, thanks to the charging and discharging process of the capacitor. This smooth signal change helps reduce false triggering caused by transient noise, thus improving system stability. Secondly, the delay unit can generate a pulse signal based on the magnetic switch signal to wake up the main control chip 240. Due to the delay characteristics of the RC delay unit, when the input signal (such as V3) transitions from low to high, the delay unit generates a brief high-level pulse. This pulse signal is then used to wake up the main control chip 240, bringing it into normal operation. This pulse generation mechanism ensures that the main control chip 240 is activated at the appropriate time, thereby saving power and improving response efficiency.

[0089] The delay unit can also be used to reduce power consumption. During encoder rotation, the main control chip 240 is only woken up when necessary, significantly reducing overall power consumption. This greatly reduces the power consumption of the main control chip 240 in standby mode, thus extending battery life. Secondly, the delay unit facilitates fault detection. The introduction of the RC delay unit helps detect faults promptly when the encoder's state is abnormal. For example, when a magnetic switch malfunctions and continuously outputs a fixed level, the RC delay unit can help the system identify this change and issue an alarm signal through subsequent logic processing. In other embodiments, the delay unit can have other structures; this example uses an RC delay unit for illustration.

[0090] In one embodiment, the delay unit includes a first resistor R1 and a first capacitor C1; the first end of the first resistor R1 is used to connect to the third magnetic switch signal V3, the second end of the first resistor R1 is connected to the first end of the first capacitor C1 and the second end of the XOR gate U11; the second end of the first capacitor C1 is grounded.

[0091] Specifically, the delay unit provides a certain delay when the input signal changes. The RC delay unit is implemented through the charging and discharging process of the first capacitor C1, introducing a time constant. This time constant determines the rate of change of the signal. For example, when the input signal changes, the first capacitor C1 will not react immediately, but will generate a gradually changing voltage based on the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1.

[0092] like Figure 4 As shown, Figure 4 This is a waveform diagram of the signal when the rotating shaft rotates clockwise according to one embodiment of this application. Clockwise rotation refers to the rotating shaft rotating counterclockwise. When the magnetic switch is normal, the Gray code will not show 000 or 111, so the outputs of the second AND gate U5 and the fourth AND gate U7 are both low, meaning both the first and second identification signals are low. When the Gray code changes from 100 to 110 to 010 to 011 to 001 to 101, the sixth AND gate U10 continuously outputs a low level, and the main control chip 240 is not woken up. When the Gray code changes from 101 to 100, the inputs of the fifth AND gate U9 are all high, so the fifth AND gate U9 outputs a high level. When the third magnetic switch signal V3 changes from high to low, due to the delay unit composed of the first resistor R1 and the first capacitor C1, the two inputs of the XOR gate U11 have a brief high and low level, and the XOR gate U11 outputs a brief high level. At this time, both inputs of the sixth AND gate U10 are briefly high, so the sixth AND gate U10 outputs a brief high-level pulse, which is the wake-up signal. The wake-up signal is input to the wake-up pin of the main control chip 240 through the third diode D3, and the main control chip 240 is woken up.

[0093] like Figure 5 As shown, Figure 5 This is a waveform diagram of the signal when the rotating shaft reverses according to one embodiment of this application. When the magnetic switch is normal, the Gray code will not show 000 and 111, so the outputs of the second AND gate U5 and the fourth AND gate U7 are both low, that is, the first identification signal and the second identification signal are both low. When the Gray code changes from 101 to 001 to 011 to 010 to 110 to 100, the sixth AND gate U10 always outputs a low level, and the main control chip 240 is not woken up. When the Gray code changes from 100 to 101, the inputs of the fifth AND gate U9 are all high, so the fifth AND gate U9 outputs a high level. When the third magnetic switch signal V3 changes from low to high, due to the delay unit composed of the first resistor R1 and the first capacitor C1, the two inputs of the XOR gate U11 have a brief low level and a high level, and the XOR gate U11 outputs a brief high level. At this time, both inputs of the sixth AND gate U10 are briefly high, so the sixth AND gate U10 outputs a brief high-level pulse, which is the wake-up signal. The wake-up signal is input to the wake-up pin of the main control chip 240 through the third diode D3, and the main control chip 240 is woken up.

[0094] The above describes the logic of the encoder error identification circuit when the magnetic switch is functioning normally. Next, this application will illustrate the logic of the encoder error identification circuit when the magnetic switch is damaged using two examples.

[0095] like Figure 6 As shown, Figure 6 This is a waveform diagram of the signal when the magnetic switch T2 is damaged according to an embodiment of this application. When the second magnetic switch signal V2 remains high, the Gray code change sequence during encoder forward rotation is 001-101-100-000-001. If 000 is present, the first AND gate U4 outputs a high level, and both inputs of the second AND gate U5 are high, so the second AND gate U5 outputs a high level, which is the first identification signal. This signal is input to the wake-up pin of the main control chip 240 through the first diode D1, waking up the main control chip 240. If the current Gray code sequence changes from 101 to 100, both inputs of the fifth AND gate U9 are high, so the fifth AND gate U9 outputs a high level. When the third magnetic switch signal V3 changes from high to low, due to the delay unit composed of the first resistor R1 and the first capacitor C1, the two inputs of the XOR gate U11 briefly experience high and low levels, causing the XOR gate U11 to output a brief high level. At this time, both inputs of the sixth AND gate U10 are briefly high, so the sixth AND gate U10 outputs a brief high-level pulse, which is the wake-up signal. The wake-up signal is input to the wake-up pin of the main control chip 240 through the third diode D3, and the main control chip 240 is woken up.

[0096] like Figure 7 As shown, Figure 7 This is a signal waveform diagram of the magnetic switch T2 when it is damaged, according to another embodiment of this application. When the second magnetic switch signal V2 is kept at a high level, the Gray code change sequence of the encoder during forward rotation is 011-111-110-010-011. When 111 is present, the third AND gate U6 outputs a high level, and both inputs of the fourth AND gate U7 are at a high level. Therefore, the fourth AND gate U7 outputs a high level, which is the second identification signal. This signal is input to the wake-up pin of the main control chip 240 through the second diode D2, and the main control chip 240 is woken up.

[0097] like Figure 8 As shown, Figure 8 This is a flowchart illustrating an encoder error identification method according to an embodiment of this application. The encoder error identification method includes the following steps:

[0098] Step S801: Obtain the identification signal and determine the abnormal condition of the magnetic switch based on the identification signal.

[0099] Step S802: If the magnetic switch is normal, count based on the magnetic switch signal.

[0100] Specifically, this application determines whether the magnetic switch is abnormal based on the identification signal. If the magnetic switch is abnormal, no counting is performed; if the magnetic switch is normal, counting is performed based on the magnetic switch signal. If 101-100 is selected as the multi-turn zero point, that is, when the Gray code changes from 101 to 100, the number of turns is incremented by 1, and when the Gray code changes from 100 to 101, the number of turns is decremented by 1. If other positions are selected for the multi-turn zero point, counting is performed according to the above counting logic.

[0101] In one embodiment, the identification signal includes a first identification signal and a second identification signal. Acquiring the identification signal and determining the abnormal condition of the magnetic switch based on the identification signal specifically includes the following steps:

[0102] If the first identification signal is at the first level, then the magnetic switch is determined to be faulty.

[0103] If the first identification signal is at the second level, then confirm whether the second identification signal is at the first level.

[0104] If the second identification signal is at the first level, then the magnetic switch is determined to be faulty.

[0105] Specifically, the logic for determining magnetic switch malfunction based on the first identification signal and the second identification signal in this application is described above and will not be repeated here.

[0106] In one embodiment, the main control chip 240 may be a micro central control chip or system-on-a-chip such as an MCU, DSP, MPU, or micro CPU that can process digital signals, analog signals, or perform signal control, instruction processing, and computation functions.

[0107] In the above embodiments, it should be understood that the main control chip 240 can be a central processing unit (CPU), or other general-purpose main control chip 240, digital signal processor (DSP), application-specific integrated circuit (ASIC), etc. The general-purpose main control chip 240 can be a micro main control chip 240, or any conventional main control chip 240. The steps of the method disclosed in this invention can be directly manifested as being executed by the hardware main control chip 240, or being executed by a combination of hardware and software modules in the main control chip 240.

[0108] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0109] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0110] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0111] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0112] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0113] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0114] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0115] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0116] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0117] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. An encoder error detection circuit, characterized in that, include: The system comprises a signal input unit, a loop counting unit, a bit error recognition unit, and a main control chip; the first end of the signal input unit is connected to the encoder, and the second end of the signal input unit is connected to the first end of the loop counting unit, the first end of the bit error recognition unit, and the main control chip; the second end of the loop counting unit and the second end of the bit error recognition unit are connected to the main control chip. The signal input unit is used to receive the magnetic switch signal output by the magnetic switch in the encoder; wherein, the magnetic switch signal is Gray code; the magnetic switch signal includes: a first magnetic switch signal, a second magnetic switch signal and a third magnetic switch signal; The count unit is used to output a wake-up signal based on the magnetic switch signal; the wake-up signal is used to wake up the main control chip. The bit error identification unit is used to output an identification signal based on the magnetic switch signal; the bit error identification unit includes: a first identification subunit and a second identification subunit; The first terminal of the first identification subunit is connected to the signal input unit, and the second terminal of the first identification subunit is connected to the main control chip; the first identification subunit is used to output a first identification signal according to the magnetic switch signal. The first end of the second identification subunit is connected to the signal input unit, and the second end of the second identification subunit is connected to the main control chip; the second identification subunit is used to output a second identification signal according to the magnetic switch signal; The main control chip is used to determine the abnormal condition of the magnetic switch based on the first identification signal or the second identification signal. When the first identification signal or the second identification signal is at a first level, the magnetic switch is determined to be abnormal; and when the magnetic switch is normal, the chip performs a count based on the magnetic switch signal.

2. The circuit according to claim 1, characterized in that, The first identification subunit includes a first NOT gate, a second NOT gate, a third NOT gate, a first AND gate, a second AND gate, and a first diode; The first terminal of the first NOT gate is used to receive the first magnetic switch signal, and the second terminal of the first NOT gate is connected to the first terminal of the first AND gate. The first terminal of the second NOT gate is used to receive the second magnetic switch signal, and the second terminal of the second NOT gate is connected to the second terminal of the first AND gate; the third terminal of the first AND gate is connected to the first terminal of the second AND gate. The first terminal of the third NOT gate is used to receive the third magnetic switch signal, and the second terminal of the third NOT gate is connected to the second terminal of the second AND gate. The third terminal of the second AND gate is connected to the main control chip, and the third terminal of the second AND gate is connected to the wake-up pin of the main control chip through the first diode. The third terminal of the second AND gate is used to output the first identification signal.

3. The circuit according to claim 2, characterized in that, The second identification subunit includes a third AND gate, a fourth AND gate, and a second diode; The first end of the third AND gate is used to receive the first magnetic switch signal, the second end of the third AND gate is used to receive the second magnetic switch signal, and the third end of the third AND gate is connected to the first end of the fourth AND gate; The second terminal of the fourth AND gate is used to receive the third magnetic switch signal, the third terminal of the fourth AND gate is connected to the main control chip, the third terminal of the fourth AND gate is connected to the wake-up pin of the main control chip through the second diode, and the third terminal of the fourth AND gate is used to output the second identification signal.

4. The circuit according to claim 1, wherein the magnetic switch signal includes: The first magnetic switch signal, the second magnetic switch signal, and the third magnetic switch signal are characterized in that the coil counting unit includes a fifth AND gate, a fourth NOT gate, a sixth AND gate, an XOR gate, and a third diode; The first terminal of the fifth AND gate is used to receive the first magnetic switch signal, the second terminal of the fifth AND gate is used to receive the second magnetic switch signal through the fourth NOT gate, and the third terminal of the fifth AND gate is connected to the first terminal of the sixth AND gate. The first terminal of the XOR gate is used to receive the third magnetic switch signal, and the third terminal of the XOR gate is connected to the second terminal of the sixth AND gate; The third terminal of the sixth AND gate is connected to the wake-up pin of the main control chip through the third diode, and the third terminal of the sixth AND gate is used to output the wake-up signal.

5. The circuit according to claim 4, characterized in that, The counting unit also includes a delay unit, the first end of which is used to receive the third magnetic switch signal, and the second end of which is connected to the second end of the XOR gate.

6. The circuit according to claim 5, characterized in that, The delay unit includes a first resistor and a first capacitor; The first end of the first resistor is used to receive the third magnetic switch signal, and the second end of the first resistor is connected to the first end of the first capacitor and the second end of the XOR gate. The second terminal of the first capacitor is grounded.

7. A method for encoder error identification, characterized in that, The method, applied to the encoder error identification circuit according to any one of claims 1-6, comprises: Acquire the identification signal and determine the abnormal condition of the magnetic switch based on the identification signal; If the magnetic switch is functioning normally, counting is performed based on the magnetic switch signal; The identification signal includes a first identification signal and a second identification signal; The acquisition of the identification signal and the determination of the abnormal condition of the magnetic switch based on the identification signal specifically include: If the first identification signal is at the first level, then the magnetic switch is determined to be abnormal; If the first identification signal is at the second level, then continue to determine whether the second identification signal is at the first level; If the second identification signal is at the first level, then the magnetic switch is determined to be faulty.

8. An encoder system, characterized in that, Includes an encoder and an encoder error detection circuit as described in any one of claims 1-6; The encoder is connected to the encoder error recognition circuit.

9. The encoder system according to claim 8, characterized in that, The encoder includes a rotating shaft, an encoder code disk that rotates along the axis of the rotating shaft, a magnetic component disposed on the rotating shaft, and three magnetic switches located within the magnetic field range of the magnetic component. The magnetic switch is connected to the encoder error identification circuit and is used to output a magnetic switch signal.

10. The encoder system according to claim 9, characterized in that, The angle between the axial directions of two adjacent magnetic switches ranges from 60° to 120°.

11. The encoder system according to claim 10, characterized in that, The angle between the axial directions of two adjacent magnetic switches is 120°.

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