Implementation method of RISC-V vector instruction, processor and computer program product
By generating multiple micro-operations and utilizing data buffers and blocking registers for control, the problems of poor performance and high power consumption during the RISC-V vector instruction splitting process are solved, achieving more efficient processor performance and lower power consumption.
CN120670024APending Publication Date: 2025-09-19SANECHIPS TECH CO LTD
Patent Information
- Application Number
- CN202411052128.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-01
- Publication Date
- 2025-09-19
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Figure CN120670024A_ABST
Abstract
The embodiment of the invention provides an RISC-V vector instruction implementation method, a processor and a computer program product, and the method comprises the steps: generating a plurality of micro-operations according to one RISC-V vector instruction; the micro-operations comprise a first type of micro-operations used for acquiring and storing a source operand required for realizing the RISC-V vector instruction and a second type of micro-operations used for executing operation according to the source operand so as to realize the RISC-V vector instruction; executing the first type of micro-operation to obtain and store all source operands required for realizing the RISC-V vector instruction; and executing the second type of micro-operation according to the source operand. According to the method and the device, the problems of poor performance, high power consumption and complicated functional unit design in the RISC-V vector instruction splitting process in related technologies are solved, and the effects of improving the RISC-V vector instruction splitting performance and reducing the power consumption of RISC-V vector instruction splitting and the complexity of functional unit design are achieved.
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Citation Information
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