Implementation method of risc-v non-single width vector instruction, processor

Abstract

The embodiment of the disclosure provides an implementation method of a RISC-V non-single width vector instruction, a processor, and the method comprises the steps: obtaining a plurality of micro-operations based on the non-single width vector instruction splitting, each micro-operation corresponds to a fixed number of source operands; and sending and executing the micro-operations. Through the embodiment of the disclosure, the problem that the splitting and implementation of the RISC-V non-single width vector instruction have a large area and high power consumption in the related art is solved, and the effect of reducing the area and power consumption of the splitting and implementation of the RISC-V non-single width vector instruction is achieved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more specifically, to a method for implementing RISC-V non-single-width vector instructions and a processor. Background Technology

[0002] The fifth-generation Reduced Instruction Set Computer-five (RISC-V) architecture boasts advantages such as complete open source, simple architecture, and modularity. RISC-V Vector Extension (V Extension) version 1.0 was officially released in 2021. Compared to the traditional Single Instruction Multiple Data (SIMD) architecture, the vector architecture features variable vector lengths, allowing the same binary code to run on processors with different vector lengths without recompilation, resulting in better flexibility and portability. In addition to the above advantages, RISC-V Vector Extension introduces the concept of Length Multiplier (LMUL), allowing instruction operations to operate on vectors with lengths exceeding the register lengths implemented in the architecture.

[0003] For RISC-V V extension instructions, based on the element widths of the source and destination registers, they are divided into three categories: Single-width: SEW = SEW OP SEW; Narrow: SEW = 2SEW OP SEW; Wide: 2SEW = SEW OP SEW or 2SEW = 2SEW OP SEW. Here, the element width (SEW) is the size of each element in the vector register, and OP represents the operation.

[0004] During instruction execution in the RISC-V V extended architecture, for single-width instructions (excluding the mask register), reading the values ​​of three registers is sufficient: two source operand registers and one destination register. Reading the destination register as a source is necessary due to the specific requirements of the RISC-V V extended architecture, which may necessitate preserving the original values ​​of inactive elements. Similarly, the execution unit only requires three source interfaces, each with a width equal to the vector register width (VLEN). The write-back channel only requires the width of one register.

[0005] In related technologies, the splitting and implementation of RISC-V non-single-width vector instructions presents problems of large area and high power consumption. Summary of the Invention

[0006] This disclosure provides a method and processor for implementing RISC-V non-single-width vector instructions, which at least solves the problems of large area and high power consumption in the splitting and implementation of RISC-V non-single-width vector instructions in related technologies.

[0007] According to one embodiment of this disclosure, a method for implementing RISC-V non-single-width vector instructions is provided, comprising: obtaining multiple micro-operations based on the non-single-width vector instruction decomposition, each micro-operation corresponding to a fixed number of source operands; and sending and executing the micro-operations.

[0008] According to another embodiment of this disclosure, a RISC-V architecture processor is provided, including a controller and an execution unit. The controller includes an instruction decoding unit that obtains multiple micro-operations based on non-single-width vector instruction decomposition, wherein each micro-operation corresponds to a fixed number of source operands. The execution unit is configured to receive and execute the micro-operations.

[0009] This disclosure provides a method for implementing RISC-V non-single-width vector instructions. It obtains multiple micro-operations by splitting the non-single-width vector instructions, with each micro-operation corresponding to a fixed number of source operands; the micro-operations are then sent and executed. This solves the problems of large area and high power consumption in the splitting and implementation of RISC-V non-single-width vector instructions in related technologies, achieving the effect of reducing the area and power consumption of RISC-V non-single-width vector instruction splitting and implementation. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating the number of source operand registers and destination registers for Narrow type instructions;

[0011] Figure 2 This is a diagram illustrating the number of source operand registers and destination registers for a Wild type instruction (2SEW = SEW OP SEW).

[0012] Figure 3 This is a diagram illustrating the number of source operand registers and destination registers for a Wild type instruction (2SEW = 2SEW OP SEW).

[0013] Figure 4 This is a flowchart of a method for implementing RISC-V non-single-width vector instructions according to an embodiment of this disclosure;

[0014] Figure 5 This is a structural example diagram of a RISC-V architecture processor according to an embodiment of this disclosure;

[0015] Figure 6This is a schematic diagram of the module design of an implementation device for RISC-V non-single-width vector instructions according to an embodiment of this disclosure;

[0016] Figure 7 This is a diagram illustrating the breakdown and data selection of the Wild type instruction (2SEW = SEW OP SEW);

[0017] Figure 8 This is a diagram illustrating the breakdown and data selection of the Wild type instruction (2SEW = 2SEW OP SEW);

[0018] Figure 9 This is a diagram illustrating the breakdown and data selection of Narrow type instructions (SEW = 2SEW OP SEW). Detailed Implementation

[0019] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings and examples.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0021] In related technologies, if the LMUL of the control status register vtype in the V extension is set to 1, VLEN = 4*SEW. Figure 1 This is a diagram illustrating the number of source and destination registers for Narrow type instructions, as shown below. Figure 1 As shown, for Narrow instructions, it can be seen that one source (vs2 in the figure) of the instruction requires two registers, while the other source and destination registers each only require one register. If this situation is to be accommodated, four source operand registers are required, which will increase the reading of source operand registers and the interface input of the source operand of the execution unit, thus increasing the area and power consumption.

[0022] Figure 2 This is a diagram illustrating the number of source and destination registers for a Wild type instruction (2SEW = SEW OP SEW). Figure 2 As shown, both sources require one register, and the destination register requires two registers. To accommodate this situation, four source operand registers are also needed. Furthermore, the result write-back also requires two registers, necessitating an additional write-back interface and further increasing the area.

[0023] Figure 3 This is a diagram illustrating the number of source and destination registers for a Wild type instruction (2SEW = 2SEW OP SEW), as shown below. Figure 3As shown, one source requires two registers, the destination requires two registers, and a total of five registers are needed. Writing back still requires two registers, so the resources consumed will be even greater.

[0024] This disclosure provides a method for implementing RISC-V non-single-width vector instructions. Figure 4 This is a flowchart of an implementation method for RISC-V non-single-width vector instructions according to an embodiment of this disclosure, as shown below. Figure 4 The process includes the following steps:

[0025] Step S402: Obtain multiple micro-operations based on non-single-width vector instruction splitting, with each micro-operation corresponding to a fixed number of source operands.

[0026] In this embodiment of the disclosure, before splitting the non-single-width vector instruction, it is necessary to first obtain and decode the aforementioned non-single-width vector instruction to confirm its type. In an exemplary embodiment, each micro-operation corresponds to a fixed number of source operands, including: each micro-operation corresponds to three source operands, wherein the third source operand is read from the destination register.

[0027] In this embodiment of the disclosure, when the vector length multiplier LMUL is 1 / 2 / 4, each decomposed micro-operation uop only needs to read three source operands, without adding any additional source operand read paths.

[0028] In this embodiment of the disclosure, by limiting each micro-operation to three source operands, the splitting and implementation area of ​​RISC-V non-single-width vector instructions can be effectively reduced.

[0029] In one exemplary embodiment, the non-single-width vector instruction includes at least one of the following: a narrow vector instruction; an extended wide vector instruction.

[0030] In this embodiment of the disclosure, during the splitting process, multiple micro-operations are obtained by splitting according to the type of non-single-width vector instruction.

[0031] In an exemplary embodiment, multiple micro-operations are obtained based on the splitting of non-single-width vector instructions, including: when the two source operand registers corresponding to the Wide vector instruction need to be expanded, the first source operand register and the second source operand register of each two adjacent micro-operations are the same, and the third source operand register of each micro-operation stores the original value of the destination register.

[0032] In this embodiment of the disclosure, each pair of adjacent micro-operation uops means that the first uop is adjacent to the second uop, the third uop is adjacent to the fourth uop, and so on.

[0033] In one exemplary embodiment, multiple micro-operations are obtained based on the splitting of non-single-width vector instructions, including: when a source operand register corresponding to a Wide vector instruction needs to be expanded, the first source operand registers of every two adjacent micro-operations are the same, and the third operand register of each micro-operation stores the original value of the destination register.

[0034] In an exemplary embodiment, multiple micro-operations are obtained based on the splitting of non-single-width vector instructions, including: for Narrow vector instructions, the first source operand register and the destination register of every two adjacent micro-operations are the same, and the third operand register of each micro-operation stores the original value of the destination register.

[0035] In one exemplary embodiment, multiple micro-operations are obtained based on the splitting of non-single-width vector instructions, including: for Narrow vector instructions, each pair of adjacent micro-operations constitutes a write-after-read dependency.

[0036] In one exemplary embodiment, multiple micro-operations are obtained based on the splitting of non-single-width vector instructions, including: for Narrow vector instructions, the destination register of the first micro-operation in every two adjacent micro-operations is the same as the third source operand register corresponding to the second micro-operation.

[0037] In an exemplary embodiment, multiple micro-operations are obtained based on non-single-width vector instruction splitting, including: when the first source operand register and the second source operand register of each two adjacent micro-operations are the same, or when the first source operand registers of each two adjacent micro-operations are the same, the corresponding source operand in the corresponding source operand register is selected for operation based on the counter value LMUM.

[0038] In this embodiment of the disclosure, for Wide vector instructions, the split uop selects the corresponding value in the source operand register for operation based on the counter value LMUM, i.e., whether it is the upper or lower half of the source operand register. For Narrow vector instructions, the split uop also selects the corresponding value in the source operand register for operation based on the counter value LMUM.

[0039] Step S404: Send and execute the micro-operation.

[0040] In one exemplary embodiment, sending micro-operations includes: for a Widen vector instruction, randomly sending each micro-operation, or sequentially sending each micro-operation, or pairing corresponding micro-operations from the same source operand register into a group and sending the micro-operations adjacent to each other.

[0041] In this embodiment, for Wide vector instructions, since there is no write-after-read dependency, each decomposed uop can be issued randomly. Ideally, adjacent instructions should be issued sequentially, such as uop1 and uop2, because they share some registers. This reduces register flipping and lowers power consumption. For Narrow vector instructions, there is a write-after-read dependency between adjacent uops. Therefore, uop2 can only be issued after a certain number of clock cycles following uop1. The number of cycles is determined by the instruction execution latency. Ideally, uop2 should be sent to the execution unit for execution as soon as the result of uop1 is written back. At this time, the write-back result of uop1 can be directly used by uop2 without having to read from the register file again, thus reducing power consumption.

[0042] In one exemplary embodiment, sending a micro-operation includes: for a Narrow vector instruction, pairing two corresponding micro-operations using the same source operand register into a group and sending the micro-operations sequentially and adjacently.

[0043] In one exemplary embodiment, sending micro-operations sequentially and adjacently includes: sending the current micro-operation and then sending the next micro-operation after a preset number of clock cycles.

[0044] In one exemplary embodiment, sending a micro-operation includes: for a Narrow vector instruction, controlling the writing back of the execution result of the current micro-operation and obtaining the source operand of the next micro-operation simultaneously.

[0045] In the embodiments disclosed herein, by employing different micro-operation strategies for different vector instruction types, it is possible to reduce the splitting of RISC-V non-single-width vector instructions and the power consumption of implementation.

[0046] In an exemplary embodiment, sending and executing a micro-operation includes: for a Narrow vector instruction, the first micro-operation in every two adjacent micro-operations saves the original value of the high half of the destination register, and the execution result of the first micro-operation is written to the low half of the destination register; the second micro-operation in every two adjacent micro-operations obtains the destination register value of the first micro-operation, and writes the execution result of the second micro-operation to the high half of the corresponding destination register, while the low half of the destination register remains unchanged.

[0047] In one exemplary embodiment, performing a micro-operation includes: determining the number of execution units for executing the micro-operation corresponding to the non-single-width vector instruction based on the number of elements in the non-single-width vector instruction; or, when the number of execution units for the micro-operation corresponding to the non-single-width vector instruction is fixed, increasing the number of executions of the execution units.

[0048] In this embodiment of the disclosure, the number of execution units for executing the micro-operations corresponding to the non-single-width vector instructions is determined based on the number of elements in the non-single-width vector instructions. This enables the number of execution units to be adjustable, effectively reducing the number of execution units and further reducing the splitting and implementation area of ​​RISC-V non-single-width vector instructions.

[0049] This disclosure provides a method for implementing RISC-V non-single-width vector instructions. It involves splitting the non-single-width vector instructions to obtain multiple micro-operations, each corresponding to a fixed number of source operands; then sending and executing these micro-operations. This solves the problems of large area and high power consumption in the splitting and implementation of RISC-V non-single-width vector instructions in related technologies, achieving the effect of reducing the area and power consumption of RISC-V non-single-width vector instruction splitting and implementation.

[0050] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this disclosure.

[0051] This disclosure also provides a processor based on a RISC-V architecture. Figure 5 This is an example structural diagram of a RISC-V architecture processor according to an embodiment of this disclosure, as shown below. Figure 5 As shown, the RISC-V architecture processor 50 includes a controller 510 and an execution unit 520. The controller 510 includes an instruction decoding unit 5101, which obtains multiple micro-operations based on non-single-width vector instruction splitting, wherein each micro-operation corresponds to a fixed number of source operands; the execution unit 520 is configured to receive and execute micro-operations.

[0052] In this embodiment of the disclosure, the RISC-V architecture processor 50 also includes conventional structures such as a data processing unit and registers, which will not be described in detail here. For example, the data processing unit can be used to process the source data and execution results of micro-operations, and select the source operand register elements to participate in the operation based on the micro-operation counter value LMUM. The registers can be used to store and read data from the source operand registers and the destination registers, and update the stored results according to the micro-operation write-back mechanism and dependencies.

[0053] This embodiment also provides an implementation apparatus for RISC-V non-single-width vector instructions, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0054] The RISC-V non-single-width vector instruction implementation apparatus provided in this disclosure embodiment may include a splitting module and a sending module. The splitting module is configured to split and obtain multiple micro-operations based on the non-single-width vector instruction, and each micro-operation corresponds to a fixed number of source operands. The sending module is configured to send and execute the micro-operations.

[0055] In the embodiments disclosed herein, the above-mentioned RISC-V non-single-width vector instruction implementation apparatus may further include different modules, and the naming and functional division of the modules may be selected in different ways according to the actual situation, without specific limitations.

[0056] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0057] Embodiments of this disclosure also provide a computer-readable storage medium storing a computer program configured to perform the steps in any of the above method embodiments when executed.

[0058] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0059] Embodiments of this disclosure also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0060] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0061] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0062] In one exemplary embodiment, the computer program product described above includes a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the methods described in various embodiments of this application.

[0063] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0064] It is obvious to those skilled in the art that the modules or steps of this disclosure described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this disclosure is not limited to any particular combination of hardware and software.

[0065] To enable those skilled in the art to better understand the technical solutions disclosed herein, the following description is provided in conjunction with different embodiments.

[0066] Example 1

[0067] This disclosure provides a method for implementing RISC-V non-single-width vector instructions. Compared to single-width vector instructions, which require simple decomposition into corresponding micro-operations (uops) via LMUL and have no correlation between the source operand registers and destination registers of the preceding and following uops, non-single-width instructions require decomposition into uops that only require three source operands, with the source operand registers and destination registers of the preceding and following uops being correlated. This disclosure considers the cases where LMUL is 1 / 2 / 4; for other values, decomposition is not necessary. Each uop decomposed in this way only needs to read three source operands, without adding additional source operand read paths, operand interfaces of the execution unit, or write-back channels for execution unit results.

[0068] Figure 6 This is a schematic diagram of the module design of an implementation device for RISC-V non-single-width vector instructions according to an embodiment of this disclosure, as shown below. Figure 6As shown, it includes an instruction cache module, an instruction decoding and instruction splitting module, a renaming module, an instruction issuing module, a data processing module, an instruction execution module, and a register file.

[0069] In this embodiment, the instruction cache module stores non-single-width instructions to be executed, facilitating their retrieval from this module. The instruction decoding and splitting module splits the corresponding non-single-width instructions into uops (uops) requiring only three source operands, based on different instruction types, and then sends them to the renaming module and instruction dispatch module. The renaming module renames registers. The instruction dispatch module sends the split uops to the execution unit, and the source operand register information is sent to the register file for data reading. For narrow-type instructions, write-after-read dependencies are checked to ensure data dependence. The data processing module processes the elements of the source operands and handles the write-back of execution results, based on the uop counter count and the elements operated on by the execution unit. The instruction execution module performs corresponding operations based on different instruction types, and the number of execution units can be configured. The register file is used to implement the reading, writing back, and storage of source operands.

[0070] Based on the above-described implementation apparatus for RISC-V non-single-width vector instructions, this disclosure provides a method for implementing RISC-V non-single-width vector instructions, comprising the following steps:

[0071] S1, instruction decoding and splitting.

[0072] In this embodiment, the instructions obtained from the instruction cache module are decoded and split according to the instruction type.

[0073] In this embodiment, under the most complex case of the RISC-V V architecture, LMUL=4, both Wild and Narrow type instructions will be split into 8 uops, but the splitting details are different.

[0074] For the Wild instruction (2SEW = SEW OP SEW), assuming the instruction form is op1 v24, v16, v8, its breakdown is shown in Table 1.

[0075] In this embodiment, src0, src1, and src2 represent source operand registers, where src0 is the first source operand register in the above embodiment, src1 is the second source operand register in the above embodiment, src2 is the third source operand register in the above embodiment, dst represents the destination register, and LMUM represents the counter value.

[0076] Table 1. Example of splitting the Wild instruction (2SEW = SEW OP SEW)

[0077]

[0078]

[0079] In this embodiment, for this type of Wild instruction, the source operand registers src0 and src1 read by the two adjacent uop instructions are the same, while the destination registers dst are different. src2 is used to store the original value of the destination register dst.

[0080] In this embodiment, for the Wild instruction (2SEW = 2SEW OP SEW), assuming the instruction form is op1 v24, v16, v8, the breakdown is shown in Table 2.

[0081] Table 2. Example of splitting the Wild instruction (2SEW = 2SEW OP SEW)

[0082] 1 op1 v24, v16, v8 v8 v16 v24 v24 0 2 op1 v25, v17, v8 v8 v17 v25 v25 1 3 op1 v26, v18, v9 v9 v18 v26 v26 2 4 op1 v27, v19, v9 v9 v19 v27 v27 3 5 op1 v28, v20, v10 v10 v20 v28 v28 4 6 op1 v29, v21, v10 v10 v21 v29 v29 5 7 op1 v30, v22, v11 v11 v22 v30 v30 6 8 op1 v31, v23, v11 v11 v23 v31 v31 7

[0083] In this embodiment, for this type of Wild instruction, the source operand register src0 read by the two adjacent uop instructions is the same, while the other source operand register src1 and the destination register dst are different, and src2 is used to store the original value of the destination register dst.

[0084] In this embodiment, for the Narrow instruction (SEW = 2SEW OP SEW), assuming the instruction form is op1 v24, v16, v8, the breakdown is shown in Table 3.

[0085] Table 3. Examples of splitting the Narrow instruction (SEW = 2SEW OP SEW)

[0086] 1 op1 v24, v16, v8 v8 v16 v24 v24 0 2 op1 v24, v17, v8 v8 v17 v24 v24 1 3 op1 v26, v18, v9 v9 v18 v25 v25 2 4 op1 v27, v19, v9 v9 v19 v25 v25 3 5 op1 v28, v20, v10 v10 v20 v26 v26 4 6 op1 v29, v21, v10 v10 v21 v26 v26 5 7 op1 v30, v22, v11 v11 v22 v27 v27 6 8 op1 v31, v23, v11 v11 v23 v27 v27 7

[0087] For this type of Narrow instruction, the source operand register src0 and the destination register dst are the same for two consecutive uop instructions, while the other source operand register src1 corresponds to a different one, and src2 is used to store the original value of the destination register dst. Unlike the Wild instruction, the destination register of the previous instruction (dst of uop1) is the source of the next instruction (src2 of uop2). Therefore, a write-after-read dependency occurs, allowing uop1 and uop2 to write the result back to the same register.

[0088] In this embodiment of the disclosure, the meaning of the two adjacent uops mentioned above is that the first uop is adjacent to the second uop, the third uop is adjacent to the fourth uop, and so on.

[0089] S2, Command Launch.

[0090] In this embodiment, for the Wild instruction, since there is no write-after-read dependency, each uop can be issued randomly. It is best to issue two adjacent instructions in sequence, such as uop1 and uop2, because they share some registers. This can reduce register toggling and reduce power consumption.

[0091] However, for Narrow instructions, there is a write-after-read dependency between two adjacent uop instructions. Therefore, uop2 can only be issued after a certain number of clock cycles after uop1 is issued. The number of cycles is determined by the instruction execution delay. Ideally, uop2 is sent to the execution unit for execution when the result of uop1 has just been written back. At this time, the write-back result of uop1 can be directly used by uop2 without having to read it from the register file again, thus reducing power consumption.

[0092] S3, Instruction Execution.

[0093] In this embodiment, in the RISC V architecture, a vector register contains many elements. To reduce area, the number of execution units is sometimes reduced, and a single uop is split into multiple operations sent to the execution units for processing. This is often used in floating-point execution units. For example, if the vector register has 8 elements but there are only 2 execution units, and each execution unit can only process one element at a time, then it needs to be split into 4 operations to process the elements sequentially. This requires more refined processing in the data processing module, including sequential selection of data before sending it to the execution units and sequential saving of the results after writing them back, before writing them back to the register file.

[0094] S4, Data Processing.

[0095] In this embodiment, the data processing process is described using LMUL=1 and VLEN=4SEW as an example.

[0096] Figure 7 This is a diagram illustrating the breakdown and data selection of the Wild type instruction (2SEW = SEW OP SEW), as shown below. Figure 7 As shown, the uop generated by this type of Wild instruction selects the corresponding value from the source operand registers for computation based on the counter value LMUM, i.e., whether it is the upper or lower half of the two source operand registers. If the number of execution units is less than the number of elements, the uop can be executed multiple times, with each time selecting the number of elements corresponding to the number of execution units for computation.

[0097] Figure 8 This is a diagram illustrating the breakdown and data selection of the Wild type instruction (2SEW = 2SEW OP SEW), as shown below. Figure 8 As shown, the uop split from this type of Wild instruction will also select the corresponding value in the source operand register to participate in the operation based on the counter value LMUM. At this time, only one source operand register vs2 needs this operation.

[0098] Figure 9 This is a diagram illustrating the breakdown and data selection of Narrow type instructions (SEW = 2SEW OP SEW), as shown below. Figure 9 As shown, the uops derived from this type of Narrow instruction also select the corresponding value in the source operand register for operation based on the counter value LMUM, as shown in vs1 in the diagram. Writing the result back requires special handling. For uop0, the original value of the high half of the destination register needs to be saved, and the result generated by its execution unit is only written back to the low half of the destination register. For uop1, the output of uop0 needs to be read, and then the low half of this output needs to be saved, while the high half of the destination register is filled with the result of uop1. In the RISC V architecture, the execution unit uses a mask to control whether the corresponding element is an active element (the element participating in the operation). When mask = 0, the result is the original value of the destination register; when mask = 1, the result is the result obtained from the operation on the source operand register. The original values ​​of the high and low halves of the destination register can be saved by controlling the high and low halves of the mask to be all 0, thus achieving the update of an entire register.

[0099] In summary, this disclosure provides a method for implementing RISC-V non-single-width vector instructions, limiting the bit width and number of source operand interfaces of the execution unit and the interface for reading source operands from the register file, thereby reducing area. For non-single-width instructions, i.e., Wide and Narrow instructions, the decomposition in the case of LMUL≥1 is used to achieve the instruction's functionality, and power consumption is effectively reduced through processing during instruction issuance. Furthermore, by reducing the number of execution units and related data processing operations, the area is further reduced while ensuring that the instruction functionality remains unchanged.

[0100] The RISC-V non-single-width vector instruction implementation method provided in this disclosure can be applied to general-purpose central processing units that support vector instructions, or digital signal processors, or vector processors or graphics processors.

[0101] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for implementing RISC-V non-single-width vector instructions, characterized in that, include: Multiple micro-operations are obtained by splitting non-single-width vector instructions, and each micro-operation corresponds to a fixed number of source operands; Send and execute the micro-operation; the non-single-width vector instruction includes at least one of the following: narrowing the Narrow vector instruction; expanding the Wide vector instruction; Sending and executing the micro-operation includes: for the Narrow vector instruction, the first micro-operation in every two adjacent micro-operations saves the original value of the high half of the destination register, and the execution result of the first micro-operation is written to the low half of the destination register; the second micro-operation in every two adjacent micro-operations obtains the destination register value of the first micro-operation, and writes the execution result of the second micro-operation into the high half of the corresponding destination register, while the low half of the destination register remains unchanged.

2. The method according to claim 1, characterized in that, Each of the micro-operations corresponds to a fixed number of source operands, including: Each of the micro-operations corresponds to three source operands, wherein the third source operand is read from the destination register.

3. The method according to claim 1, characterized in that, The method of obtaining multiple micro-operations based on non-single-width vector instruction splitting includes: When the two source operand registers corresponding to the Wild vector instruction need to be expanded, the first source operand register and the second source operand register of each two adjacent micro-operations are identical, and the third source operand register of each micro-operation stores the original value of the destination register.

4. The method according to claim 1, characterized in that, The method of obtaining multiple micro-operations based on non-single-width vector instruction splitting includes: When a source operand register corresponding to the Wild vector instruction needs to be expanded, the first source operand registers of each two adjacent micro-operations are identical, and the third operand register of each micro-operation stores the original value of the destination register.

5. The method according to claim 1, characterized in that, The method of obtaining multiple micro-operations based on non-single-width vector instruction splitting includes: For the Narrow vector instruction, the first source operand register and the destination register of every two adjacent micro-operations are the same, and the third operand register of each micro-operation stores the original value of the destination register.

6. The method according to claim 1, characterized in that, The method of obtaining multiple micro-operations based on non-single-width vector instruction splitting includes: For the Narrow vector instruction, each pair of adjacent micro-operations constitutes a write-after-read dependency.

7. The method according to claim 6, characterized in that, The method of obtaining multiple micro-operations based on non-single-width vector instruction splitting includes: For the Narrow vector instruction, the destination register of the first micro-operation in every two adjacent micro-operations is the same as the third source operand register corresponding to the second micro-operation.

8. The method according to claim 1, characterized in that, Sending the micro-operation includes: For the Wilden vector instruction, each micro-operation is sent randomly, or each micro-operation is sent sequentially, or two corresponding micro-operations from the same source operand register are paired up and sent adjacently.

9. The method according to claim 1, characterized in that, Sending the micro-operation includes: For the Narrow vector instruction, the corresponding two micro-operations using the same source operand register are paired into a group and sent sequentially, adjacent to each other.

10. The method according to claim 9, characterized in that, The sequential transmission of the micro-operations includes: After the current micro-operation is sent and a preset number of clock cycles have elapsed, the next micro-operation is sent.

11. The method according to claim 1, characterized in that, Sending the micro-operation includes: For the Narrow vector instruction, the write-back of the execution result of the current micro-operation and the retrieval of the source operand of the next micro-operation are performed simultaneously.

12. The method according to claim 1, characterized in that, Performing the micro-operation includes: The number of execution units for executing the micro-operation corresponding to the non-single-width vector instruction is determined based on the number of elements in the non-single-width vector instruction. Alternatively, if the number of execution units for the micro-operation corresponding to the non-single width vector instruction is fixed, the number of executions of the execution unit can be increased.

13. The method according to claim 1, characterized in that, The method of obtaining multiple micro-operations based on non-single-width vector instruction splitting includes: When the first source operand register and the second source operand register of each two adjacent micro-operations are the same, or when the first source operand registers of each two adjacent micro-operations are the same, the corresponding source operand in the corresponding source operand register is selected for operation based on the counter value LMUM.

14. A RISC-V architecture processor, comprising a controller and an execution unit, wherein the controller includes an instruction decoding unit, characterized in that, The instruction decoding unit obtains multiple micro-operations based on the splitting of non-single-width vector instructions, wherein each micro-operation corresponds to a fixed number of source operands; the execution unit is configured to receive and execute the micro-operations; the non-single-width vector instructions include at least one of the following: narrow vector instructions; wide vector instructions; executing the micro-operations includes: for the narrow vector instructions, the first micro-operation in every two adjacent micro-operations saves the original value of the high half of the destination register, and the execution result of the first micro-operation is written to the low half of the destination register; the second micro-operation in every two adjacent micro-operations obtains the destination register value of the first micro-operation, and writes the execution result of the second micro-operation into the high half of the corresponding destination register, while the low half of the destination register remains unchanged.

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