Method, electronic device, readable medium and program product for register renaming

Abstract

The present disclosure provides a register renaming method, comprising: parsing a current instruction to obtain a bit width and a number of a logical register; determining a target idle physical register table from a plurality of idle physical register tables according to the bit width of the logical register, and selecting a target physical register from the target idle physical register table; establishing a mapping relationship between the target physical register and the logical register based on a number of the target physical register and the number of the logical register, and storing the mapping relationship between the target physical register and the logical register and a use bit of the target physical register in a renaming mapping table; and updating all idle physical register tables according to the mapping relationship between the target physical register and the logical register and the use bit of the target physical register. The present disclosure also provides an electronic device, a readable medium and a program product.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a method for renaming registers, electronic devices, readable media, and program products. Background Technology

[0002] Register renaming is an important technique in computer architecture. By allocating multiple physical registers to logical registers, it can eliminate spurious dependencies between instructions and improve the execution bandwidth of pipelined instructions. However, current register renaming techniques only support one physical register corresponding to two logical registers, and only support the sharing of physical registers between multiple instructions in the same instruction cycle, resulting in a narrow scope of application. In addition, different operands occupy the full bit width of the physical register, reducing the utilization rate of the physical register and leading to resource waste. Summary of the Invention

[0003] This disclosure provides a method for renaming registers, an electronic device, a readable medium, and a program product.

[0004] In a first aspect, embodiments of this disclosure provide a method for renaming a register, including:

[0005] The current instruction is parsed to obtain the bit width and number of the logic register;

[0006] The target free physical register table is determined from multiple free physical register tables based on the bit width of the logical register, and a target physical register is selected from the target free physical register table, wherein different free physical register tables manage free physical registers with different bit widths;

[0007] A mapping relationship between the target physical register and the logical register is established based on the number of the target physical register and the number of the logical register. The mapping relationship between the target physical register and the logical register, as well as the usage bit of the target physical register, are stored in a renaming mapping table. The usage bit is used to indicate the usage of the data segment in the physical register.

[0008] Update all the free physical register tables according to the mapping relationship between the target physical register and the logical register, and the used bits of the target physical register.

[0009] In a second aspect, embodiments of this disclosure provide a processor, including:

[0010] The decoding unit is used to parse the current instruction and obtain the bit width and number of the logic register;

[0011] Physical registers are used to store the operation bits and calculation results of the current instruction;

[0012] The register renaming unit is configured to determine a target free physical register table from multiple free physical register tables based on the bit width of the logical register, select a target physical register from the target free physical register table, establish a mapping relationship between the target physical register and the logical register based on the number of the target physical register and the number of the logical register, store the mapping relationship between the target physical register and the logical register, as well as the usage bits of the target physical register, in a renaming mapping table, and update all the free physical register tables according to the mapping relationship between the target physical register and the logical register, as well as the usage bits of the target physical register.

[0013] Thirdly, embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the register renaming method described in any one of the embodiments of this disclosure.

[0014] Fourthly, embodiments of this disclosure provide a computer program product comprising a computer program that, when executed by a processor, implements the register renaming method described in any one of the embodiments of this disclosure.

[0015] The register renaming method provided in this disclosure parses the current instruction to obtain the bit width and number of the logical register; determines the target free physical register table from multiple free physical register tables based on the bit width of the logical register, selects the target physical register from the target free physical register table, stores the mapping relationship between the target physical register and the logical register, as well as the usage bits of the target physical register, in a renaming mapping table, and updates all free physical register tables according to the mapping relationship between the target physical register and the logical register, as well as the usage bits of the target physical register. Since different free physical register tables manage free physical registers with different bit widths, and during register renaming, not only is the mapping relationship between the target physical register and the logical register updated in the free physical register tables, but also the usage bits of the target physical register are updated, the remaining bit width in the target physical register can still be used by other instructions in different batches, realizing fine-grained allocation of physical registers, avoiding waste of physical register resources, improving the utilization efficiency of physical registers, and reducing the probability of all physical registers being used, thus reducing the pause of the processor pipeline caused by all physical registers being used, thereby improving the execution efficiency of the processor pipeline. Attached Figure Description

[0016] In the accompanying drawings of the embodiments disclosed herein:

[0017] Figure 1 A schematic block diagram of a processor is provided for embodiments of this disclosure;

[0018] Figure 2 A flowchart illustrating a register renaming method provided in this disclosure embodiment;

[0019] Figure 3 This diagram illustrates a block diagram of a processor provided in an embodiment of the present disclosure. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this disclosure, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0021] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0022] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0023] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0024] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0026] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0027] Register renaming technology is a renaming technique based on a renaming mapping table (RAT) and a free register list. The RAT is used to store the existing mapping relationship between logical registers and physical registers, and the free register list is used to record which physical registers are free (available) so that the number of the free physical register can be obtained when renaming registers.

[0028] In a first aspect, embodiments of this disclosure provide a method for renaming a register, which is performed within a processor framework.

[0029] Figure 1 This disclosure provides a schematic block diagram of a processor according to an embodiment. The processor includes:

[0030] Decoding unit 1 is used to parse instructions, obtain the encoding of operands and logic registers, and determine the bit width of logic registers based on the operands. For example, decoding unit 1 parses instructions according to different instruction set architectures to obtain the bit width and encoding of logic registers.

[0031] Physical register 2 includes a data portion and a usage bit portion. The data portion is used to temporarily store operands and calculation results of instructions; the usage bit portion is used to manage the state of the physical register. The bit width of the physical register can be designed according to the instruction set, and is not limited in this embodiment.

[0032] For example, taking the Reduced Instruction Set Computer (RISC-V) floating-point instruction set extension as an example, assuming the processor supports physical registers with a bit width of 128 bytes, and the data portion of the physical registers has a bit width of [127:0], since RISC-V floating-point calculation instructions support operands with a minimum bit width of 16 bits, four free physical register tables can be provided: 16-bit, 32-bit, 64-bit, and 128-bit, respectively, which are free physical register tables a, b, c, and d. Since the minimum supported operand bit width is 16 bits, and the register bit width is 128 bits, with 8 bits used, each bit in the used bits represents the usage status of the 16 bits of data in the physical register. For example, if the used bit of physical register P0 is 8'0000_1000, it means that [63:48] of P0 has been used. When any physical register is allocated in any free physical register table, all free physical register tables are updated according to the used bits.

[0033] In some embodiments, multiple free register tables can be maintained simultaneously, depending on the instruction set architecture and actual usage needs. When a free physical register table with a matching operand width cannot be found, a physical register can be obtained from a free physical register table with a width greater than the operand width; that is, a physical register is selected from a free physical register table that does not match the operand width. When selecting a physical register from a free physical register table that does not match the operand width, the width of the used bits of the physical register may remain unchanged or may be adjusted as needed. For example, an 8-bit used bit physical register supports a minimum 16-bit free physical register table. If only a minimum 32-bit free physical register table is available, the used bit physical register can be modified to 4 bits, with each bit representing the usage status of the 32-bit width of the physical register.

[0034] Register renaming unit 3 is used to determine the target free physical register table based on the bit width of the operand, allocate physical registers, and determine the target physical register from the target free physical register table.

[0035] In some embodiments, the register renaming unit 3 includes:

[0036] Rename mapping table 31 to record the mapping relationship between logical registers and target free physical registers, as well as the usage bits of the target free physical registers.

[0037] The Architecture Register File (ARF) 32 is used to maintain the numbers and usage bits of target physical registers. When an instruction is committed (retired), the physical register table can be partially released based on the number and usage bits of the target physical register, while multiple free physical register tables are updated, allowing the released physical registers to be renamed.

[0038] The free physical register table 33 is used to record the number and usage status of free physical registers. This embodiment of the disclosure includes multiple free physical register tables 33, each storing free physical registers of a corresponding bit width.

[0039] The instruction submission unit 4 is used to write the mapping relationship between the target physical register and the logical register corresponding to the instruction and the usage bits of the target physical register into the architecture register file 32 after the instruction is executed, and to release the release information in the architecture register file 32. The release information includes the target physical register number and usage bits used by the previous instruction, so as to update the usage bits and the free physical register table 33 in the physical register 2.

[0040] Figure 2 A flowchart illustrating a register renaming method provided in an embodiment of this disclosure. Figure 2 As shown in the embodiments of this disclosure, a method for renaming a register includes:

[0041] Step S201: Parse the current instruction to obtain the bit width and number of the logic register.

[0042] The current instruction is parsed to extract the bit width and number of the logic register.

[0043] In some embodiments, parsing the current instruction to obtain the bit width and number of the register includes: parsing the current instruction to obtain the operands of the current instruction and the number of the logical register; and determining the bit width of the logical register based on the operands.

[0044] The current instruction is parsed to extract its operands and logical register numbers. Then, the bit width of the logical registers is determined based on the operands.

[0045] For example, if the current instruction includes the first instruction 0 and the second instruction 1, the decoding unit parses the first instruction 0 and obtains the encoding of the logical register as X5, and the bit width (dst_size) of the operand as 16 bits.

[0046] Marked as: First instruction 0 logical id = x5, dst_size is 16-bit;

[0047] The decoding unit parses the first instruction 1 and obtains the encoding of the logic register as X6, and the bit width (dst_size) of the operand is 32 bits.

[0048] Marked as: Second instruction 1 logical id = x6, dst_size is 32-bit.

[0049] Step S202: Determine the target free physical register table from multiple free physical register tables based on the bit width of the logic register, and select the target physical register from the target free physical register table.

[0050] Among them, different free physical register tables manage free physical registers with different bit widths, that is, free physical registers with the same bit width are placed in one free physical register table for management.

[0051] In this embodiment of the disclosure, the target free physical register table is determined based on the bit width of the logic register, and then any physical register is selected from the target free physical register table as the target physical register.

[0052] For example, the first instruction 0 has a bit width of 16-bit. It obtains a physical register from the 16-bit free physical register table a as the target physical register. Assuming the target physical register is numbered P0, the used bit USED-bit = 8'h1(0000_0001) is used.

[0053] The second instruction 1 has a bit width of 32-bit. It retrieves the physical register from the 32-bit free physical register table b as the target physical register. Assuming the target physical register is numbered P2, the used bit USED-bit = 8'h3(0000_0011) is used at this time.

[0054] Step S203: Establish a mapping relationship between the target physical register and the logical register based on the number of the target physical register and the number of the logical register, and store the mapping relationship between the target physical register and the logical register, as well as the usage bits of the target physical register, in the renaming mapping table.

[0055] The usage bit is used to indicate the usage status of the data segment in the physical register. In this embodiment, when the usage bit is pulled high, it indicates that the usage bit is in use. When the usage bit is not pulled high, it indicates that the usage bit is not in use. The mapping relationship between the target physical register and the logical register, as well as the usage bit of the target physical register, can be referred to as the usage information of the physical register.

[0056] The renaming mapping table stores the mapping relationship between the target physical register and the logical register, as well as the used bits of the target physical register. For example: logical register X5 -> target physical register P0 (used-bit = 8'h1) and logical register X6 -> target physical register P2 (used-bit = 8'h3).

[0057] In this embodiment of the disclosure, the target physical register number and usage bits are stored in a renaming mapping table, which helps subsequent source operands to find the corresponding target physical register.

[0058] Step S204: Update all free physical register tables according to the mapping relationship between the target physical register and the logical register, and the used bits of the target physical register.

[0059] Once any physical register is allocated in any free physical register table, all existing free physical register tables are updated according to the usage bit of that physical register. The target free physical register is then removed from the free physical register table, indicating that the target free physical register has been allocated and is no longer a free physical register, and is in an unavailable state.

[0060] In some embodiments, determining a target free physical register table from multiple free physical register tables based on the bit width of the logical register includes:

[0061] If a free physical register matching the bit width of the logical register can be found in multiple free physical register tables, the free physical register matching the bit width of the logical register will be used as the target free physical register table.

[0062] If no free physical register matching the bit width of the logical register can be found in multiple free physical register tables, the target free physical register is selected from the free physical register table whose bit width is greater than that of the logical register.

[0063] For example, suppose the logic register has a bit width of 64 bits, but there is no free physical register in the free physical register table corresponding to the 64-bit register. Then, the target free physical register can be selected from the free physical register table with a bit width of 128 bits.

[0064] In some embodiments, after updating all free physical register tables according to the mapping relationship between the target physical register and the logical register and the used bits of the target physical register, the method further includes: if the remaining bit width of the target physical register does not match the bit width of the free physical register table, removing the target physical register from the mismatched free physical register table and moving the target physical register into the free physical register table that matches the remaining bit width.

[0065] For example, suppose the total width of the target physical register is 128 bits, and the target physical register is in the 128-bit free physical register table. If the current instruction occupies 64 bits, leaving 64 bits remaining, then the target physical register is removed from the 128-bit free physical register table and added to the 67-bit free physical register table.

[0066] In some embodiments, the result of the current instruction is written to a physical register after the current instruction has been executed.

[0067] When writing the result of the current instruction into a physical register, data of the corresponding bit width is written according to the number of the target physical register and the bits used.

[0068] In some embodiments, when the current instruction is submitted, the mapping relationship between the target physical register and the logical register corresponding to the current instruction, as well as the usage bits of the target physical register, are written into the architecture register.

[0069] In some embodiments, when the next instruction of the current instruction is committed, the target free physical register table corresponding to the bit width of the target physical register is updated based on the target physical register number and the used bits of the target physical register, that is, the mapping relationship between the target physical register and the logical register is released.

[0070] For example, the usage bit of physical register P0 corresponding to the first instruction 0 is: P0(1111_0011), and the usage bit of physical register P2 corresponding to the second instruction 1 is: P2(1111_1111). After physical registers P0 and P2 are released, the usage bit of physical register P0 is (1111_0010), and the usage bit of physical register P2 is (1111_1100).

[0071] When a physical register is freed, the physical register is updated according to the free information. That is, the free register table is reclaimed and updated according to the used bits of the physical register. After the update, physical register P0 can appear in the free register table with a bit width of 16-bit and 32-bit because it has 32 free bits. Physical register P2 can appear in the free register table with a bit width of 16-bit, 32-bit and 64-bit because it has 64 free bits.

[0072] The register renaming method provided in this disclosure parses the current instruction to obtain the bit width and number of the logical register; determines the target free physical register table from multiple free physical register tables based on the bit width of the logical register, selects the target physical register from the target free physical register table, stores the mapping relationship between the target physical register and the logical register, as well as the usage bits of the target physical register, in a renaming mapping table, and updates all free physical register tables according to the mapping relationship between the target physical register and the logical register, as well as the usage bits of the target physical register. Since different free physical register tables manage free physical registers with different bit widths, and during register renaming, not only is the mapping relationship between the target physical register and the logical register updated in the free physical register tables, but also the usage bits of the target physical register are updated, the remaining bit width in the target physical register can still be used by other instructions in different batches, realizing fine-grained allocation of physical registers, avoiding waste of physical register resources, improving the utilization efficiency of physical registers, and reducing the probability of all physical registers being used, thus reducing the pause of the processor pipeline caused by all physical registers being used, thereby improving the execution efficiency of the processor pipeline.

[0073] Secondly, embodiments of this disclosure provide a processor.

[0074] Figure 3 This diagram illustrates a block diagram of a processor provided in an embodiment of the present disclosure. Figure 3 As shown, an embodiment of this disclosure provides a processor comprising:

[0075] Decoding unit 1 is used to parse the current instruction and obtain the bit width and number of the logic register;

[0076] Physical register 2 is used to store the operation bits and calculation results of the current instruction;

[0077] Register renaming unit 3 is used to determine a target free physical register table from multiple free physical register tables according to the bit width of the logical register, select a target physical register from the target free physical register table, establish a mapping relationship between the target physical register and the logical register based on the number of the target physical register and the number of the logical register, store the mapping relationship between the target physical register and the logical register and the usage bit of the target physical register in a renaming mapping table, and update all the free physical register tables according to the mapping relationship between the target physical register and the logical register and the usage bit of the target physical register.

[0078] In some embodiments, the processor further includes an instruction submission unit 4, which is used to write the mapping relationship between the target physical register and the logical register corresponding to the current instruction and the usage bits of the target physical register into the architecture register file after the current instruction has been executed.

[0079] It should be noted that the processor is also used to perform other steps of the register renaming method provided in the embodiments of this disclosure, which will not be described in detail here for the sake of brevity.

[0080] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0081] This disclosure also provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the register renaming methods described in the above embodiments.

[0082] This disclosure also provides a computer program product, which includes a computer program that, when executed by a processor, implements any of the register renaming methods described in the above embodiments.

[0083] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0084] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0085] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0086] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0087] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A method for renaming a register, comprising: The current instruction is parsed to obtain the bit width and number of the logic register; If a free physical register matching the bit width of the logical register can be found in multiple free physical register tables, the free physical register table matching the bit width of the logical register shall be used as the target free physical register table. If no free physical register matching the bit width of the logical register can be found in the plurality of free physical register tables, the target free physical register table is selected from the free physical register tables whose bit width is greater than that of the logical register. Select a target physical register from the target free physical register table, wherein different free physical register tables manage free physical registers with different bit widths; A mapping relationship between the target physical register and the logical register is established based on the number of the target physical register and the number of the logical register. The mapping relationship between the target physical register and the logical register, as well as the usage bit of the target physical register, are stored in a renaming mapping table. The usage bit is used to indicate the usage of the data segment in the physical register. Update all the free physical register tables according to the mapping relationship between the target physical register and the logical register, and the used bits of the target physical register.

2. The method according to claim 1, wherein, The step of parsing the current instruction to obtain the register's bit width and number includes: The current instruction is parsed to obtain the operands of the current instruction and the number of the logical register; The bit width of the logic register is determined based on the operands.

3. The method according to claim 1, wherein, After updating all the free physical register tables according to the mapping relationship between the target physical register and the logical register, and the used bits of the target physical register, the method further includes: If the remaining bit width of the target physical register does not match the bit width of the free physical register table, the target physical register is removed from the mismatched free physical register table and moved into the free physical register table that matches the remaining bit width.

4. The method according to claim 1, wherein, Upon completion of the current instruction, the result of the current instruction is written into the physical register.

5. The method according to claim 1, wherein, When the current instruction is submitted, the mapping relationship between the target physical register and the logical register corresponding to the current instruction, as well as the usage bits of the target physical register, are written into the architecture register file.

6. The method according to claim 5, wherein, When the next instruction of the current instruction is submitted, the target free physical register table corresponding to the bit width of the target physical register is updated based on the number of the target physical register and the used bits of the target physical register.

7. A processor, comprising: The decoding unit is used to parse the current instruction and obtain the bit width and number of the logic register; Physical registers are used to store the operation bits and calculation results of the current instruction; The register renaming unit is configured to: If a free physical register matching the bit width of the logical register can be found in multiple free physical register tables, select the free physical register matching the bit width of the logical register as the target free physical register table; if no free physical register matching the bit width of the logical register can be found in the multiple free physical register tables, select the target free physical register from a free physical register table with a bit width greater than that of the logical register, select the target physical register from the target free physical register table, establish a mapping relationship between the target physical register and the logical register based on the number of the target physical register and the number of the logical register, store the mapping relationship between the target physical register and the logical register, and the usage bits of the target physical register in a renaming mapping table, and update all free physical register tables according to the mapping relationship between the target physical register and the logical register, and the usage bits of the target physical register.

8. A computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the register renaming method of any one of claims 1 to 6.

9. A computer program product comprising a computer program that, when executed by a processor, implements the register renaming method of any one of claims 1 to 6.

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