Instruction distribution apparatus and method, processor and electronic device

Abstract

Embodiments of the present disclosure provide an instruction distribution apparatus, method, processor and electronic device. The instruction distribution apparatus comprises a write selection module, a plurality of microinstruction queues and a read allocation module. The write selection module is configured to write microinstructions into the plurality of microinstruction queues; the plurality of microinstruction queues are configured to cache the written microinstructions; and the read allocation module is configured to read microinstructions from the plurality of microinstruction queues, obtain a target microinstruction group to be distributed in this time based on the read microinstructions, and perform a distribution operation. The instruction distribution apparatus improves the bandwidth of instruction distribution by setting the plurality of microinstruction queues and the scheduling method of the plurality of microinstruction queues, thereby promoting the improvement of the performance of the processor.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an instruction distribution apparatus, an instruction distribution method, a processor, and an electronic device. Background Technology

[0002] In a processor, the instruction pipeline can be divided into a front-end and a back-end, which work together to execute instructions. As the types and number of execution units on the back-end pipeline increase, the execution capability of the back-end continuously improves. At the same time, current software applications are placing increasingly higher demands on the front-end's execution capabilities. Therefore, enhancing the processor's front-end capabilities has become increasingly important. Summary of the Invention

[0003] At least one embodiment of this disclosure provides an instruction distribution apparatus, including: a write selection module, a plurality of microinstruction queues, and a read allocation module; wherein, the write selection module is configured to write microinstructions into the plurality of microinstruction queues; the plurality of microinstruction queues are configured to cache the written microinstructions; the read allocation module is configured to read microinstructions from the plurality of microinstruction queues, obtain a target microinstruction group to be distributed in this distribution based on the read microinstructions, and perform a distribution operation.

[0004] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the write selection module is further configured to write the microinstructions into the plurality of microinstruction queues according to a preset mapping relationship.

[0005] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the write selection module is further configured to, when the plurality of microinstruction queues are two microinstruction queues, write microinstructions from the same microinstruction source to the two microinstruction queues on an even basis according to a preset mapping relationship.

[0006] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the read allocation module includes: a reordering unit configured to read microinstructions from the plurality of microinstruction queues and reorder the read microinstructions according to the actual instruction order; a first determining unit configured to determine at least one microinstruction group including the target microinstruction group based on the reordered microinstructions and preset constraints; and a distribution unit configured to distribute the target microinstruction group.

[0007] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the distribution unit is further configured to distribute the target microinstruction group by reading a pointer, wherein, after the target microinstruction group is distributed, the reading pointer points to the next valid microinstruction position of the target microinstruction group.

[0008] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the first determining unit further includes a microinstruction register, wherein the microinstruction register is configured to store the reordered microinstructions read in the first reading when the target microinstruction group is obtained based on reordered microinstructions read twice.

[0009] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the write selection module includes: a second determining unit configured to determine at least one microinstruction group in the microinstructions according to preset constraints; and an allocation unit configured to write the microinstructions in the at least one microinstruction group into the plurality of microinstruction queues.

[0010] For example, in an instruction distribution device provided in at least one embodiment of this disclosure, the preset constraints include instruction attribute information and / or instruction execution information.

[0011] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the allocation unit is further configured to allocate microinstructions in the at least one microinstruction group to the plurality of microinstruction queues according to a preset mapping relationship.

[0012] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the allocation unit is further configured to dynamically allocate microinstructions from the at least one microinstruction group to the plurality of microinstruction queues.

[0013] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the distribution unit is further configured to record boundary information for each microinstruction group.

[0014] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the allocation unit is further configured to write the boundary information of each microinstruction group into the plurality of microinstruction queues, each microinstruction queue including a plurality of entries, each entry including a flag bit, wherein the flag bit indicates whether the microinstruction stored in the corresponding entry is the last microinstruction in each microinstruction group, and the boundary information includes the flag bit.

[0015] For example, at least one embodiment of this disclosure provides an instruction distribution apparatus that further includes a microinstruction quantity queue, wherein the allocation unit is further configured to write boundary information of each microinstruction group into the microinstruction quantity queue, and the microinstruction quantity queue is configured to store the number of microinstructions of each microinstruction group stored in each microinstruction queue, wherein the boundary information includes the number of microinstructions.

[0016] For example, in an instruction distribution apparatus provided in at least one embodiment of this disclosure, the read allocation module further includes: a distribution unit, which is further configured to obtain the target microinstruction group and perform the distribution operation based on the boundary information and the microinstructions read from the plurality of microinstruction queues.

[0017] At least one embodiment of this disclosure also provides an instruction distribution method, comprising: writing microinstructions into a plurality of microinstruction queues, the plurality of microinstruction queues being configured to cache the written microinstructions; reading microinstructions from the plurality of microinstruction queues; obtaining a target microinstruction group to be distributed in this distribution based on the read microinstructions; and performing a distribution operation.

[0018] For example, in an instruction distribution method provided in at least one embodiment of this disclosure, writing microinstructions into multiple microinstruction queues includes: writing the microinstructions into the multiple microinstruction queues according to a preset mapping relationship.

[0019] For example, in an instruction distribution method provided in at least one embodiment of this disclosure, the step of reading microinstructions from the plurality of microinstruction queues, obtaining a target microinstruction group to be distributed in this distribution based on the read microinstructions, and performing a distribution operation includes: reading microinstructions from the plurality of microinstruction queues and reordering the read microinstructions according to the actual instruction order; determining at least one microinstruction group including the target microinstruction group based on the reordered microinstructions and preset constraints; and distributing the target microinstruction group.

[0020] For example, in an instruction distribution method provided in at least one embodiment of this disclosure, distributing the target microinstruction group includes: distributing the target microinstruction group by reading a pointer, wherein, after the target microinstruction group is distributed, the reading pointer points to the next valid microinstruction position of the target microinstruction group.

[0021] For example, in an instruction distribution method provided in at least one embodiment of this disclosure, writing microinstructions into multiple microinstruction queues includes: determining at least one microinstruction group in the microinstructions according to preset constraints; and writing the microinstructions in the at least one microinstruction group into the multiple microinstruction queues.

[0022] For example, in an instruction distribution method provided in at least one embodiment of this disclosure, writing microinstructions from the at least one microinstruction group into the plurality of microinstruction queues includes: allocating the microinstructions from the at least one microinstruction group to the plurality of microinstruction queues according to a preset mapping relationship.

[0023] For example, in an instruction distribution method provided in at least one embodiment of this disclosure, writing microinstructions from the at least one microinstruction group into the plurality of microinstruction queues includes: dynamically allocating microinstructions from the at least one microinstruction group into the plurality of microinstruction queues.

[0024] For example, at least one embodiment of this disclosure provides an instruction distribution method that further includes: recording boundary information for each microinstruction group.

[0025] At least one embodiment of this disclosure also provides a processor, including the instruction dispatch apparatus provided in any embodiment of this disclosure.

[0026] At least one embodiment of this disclosure also provides an electronic device, including the processor provided in any embodiment of this disclosure. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0028] Figure 1 A schematic diagram illustrating an example of the front-end configuration of a CPU core;

[0029] Figure 2 A schematic block diagram of an instruction distribution apparatus provided for at least one embodiment of this disclosure;

[0030] Figure 3 A schematic diagram illustrating the operation of a write selection module provided in at least one embodiment of this disclosure;

[0031] Figure 4 A schematic block diagram of an instruction distribution apparatus provided for at least one embodiment of this disclosure;

[0032] Figure 5 A schematic diagram illustrating the operation of a read allocation module provided in at least one embodiment of this disclosure;

[0033] Figure 6 A schematic diagram of an instruction distribution device provided in at least one embodiment of this disclosure;

[0034] Figure 7 A schematic block diagram of another instruction distribution apparatus provided in at least one embodiment of this disclosure;

[0035] Figure 8A A schematic diagram of the operation of an allocation unit provided in at least one embodiment of this disclosure;

[0036] Figure 8B Another schematic diagram of the operation of an allocation unit provided in at least one embodiment of this disclosure;

[0037] Figure 9A A schematic diagram of a microinstruction queue provided for at least one embodiment of this disclosure;

[0038] Figure 9B Another schematic diagram of a microinstruction queue provided for at least one embodiment of this disclosure;

[0039] Figure 10 A schematic diagram of another instruction distribution apparatus provided for at least one embodiment of the present disclosure;

[0040] Figure 11 A schematic flowchart illustrating an instruction dispatch method provided for at least one embodiment of this disclosure;

[0041] Figure 12 A schematic block diagram of a processor provided for at least one embodiment of this disclosure;

[0042] Figure 13 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure; and

[0043] Figure 14 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0044] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0045] To enable those skilled in the art to better understand this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of this disclosure to the specific shapes, hardware, connections, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can utilize the concepts of this disclosure to construct further embodiments not mentioned herein by reading this specification.

[0047] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0048] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0049] The front-end and back-end are two closely cooperating key parts within the Central Processing Unit (CPU) core. Together, they drive the instruction processing flow, ensuring that the CPU can execute programs efficiently.

[0050] The front end is the starting point of the pipeline, primarily responsible for instruction fetching, decoding, and preliminary processing. It reads instructions (e.g., "machine instructions") from memory, a process controlled by the program counter, which points to the address of the instruction to be executed. The front end then reads instructions from the instruction cache based on the program counter's value. The instruction cache stores recently accessed instructions to reduce latency in accessing main memory. After fetching the instruction, the front end's decoding unit decodes it into one or more micro-operations (or "micro-instructions"), parses the instruction's opcode and operands, and determines the instruction type, such as arithmetic, logical, or branch instructions.

[0051] For example, the front-end also undertakes the important task of branch prediction. The branch predictor predicts the execution direction of branch instructions by analyzing the program's execution path. This includes the branch target buffer and the branch direction predictor, which help the front-end obtain subsequent instructions that may be executed in advance, reducing pipeline pauses. In addition, the front-end attempts to obtain subsequent instructions in advance, and implements instruction prefetching through an instruction prefetch queue to further optimize the efficiency of instruction fetching.

[0052] For example, another important function of the front-end is instruction scheduling. It performs initial scheduling on decoded instructions, optimizing the execution order of instructions, such as reducing data and structural conflicts through reordering. A key component of the front-end also includes an instruction queue, used to temporarily store decoded instructions, awaiting execution by the back-end.

[0053] The back-end is the back-end part of the CPU pipeline, primarily responsible for the actual execution of instructions and result processing. It receives instructions decoded by the front-end and performs operations such as instruction execution, data access, and result writing back. The back-end contains multiple execution units, such as integer arithmetic units, floating-point arithmetic units, and logical arithmetic units. These units are responsible for executing the decoded instructions and generating results. After the execution units complete instruction execution, the commit unit determines whether to write the result back to the target register or memory.

[0054] The backend is also responsible for accessing memory or cache to read or write data, including load and store operations. Data caches store recently accessed data, reducing latency in main memory access. Register files store register values ​​used during instruction execution. The backend also handles conflicts and pauses in the pipeline and ensures efficient pipeline operation. The pipeline control unit coordinates the various stages of the pipeline and handles conflicts and pauses.

[0055] In a pipeline, the front-end and back-end work closely together to process instructions. The front-end sends the decoded instructions to the back-end execution unit, which then writes the results back to registers or memory after execution. The back-end reports any exceptions encountered during execution to the front-end, which adjusts its instruction fetching and decoding strategies based on this information. This collaborative mechanism ensures that the CPU can execute programs efficiently. The front-end's instruction fetching and decoding capabilities directly affect the back-end's execution efficiency, which in turn influences the front-end's instruction scheduling strategy. Through efficient collaboration between the front-end and back-end, modern CPUs can achieve high-performance instruction processing, meeting the demands of complex computational tasks.

[0056] Figure 1 This is a schematic diagram illustrating an example of the front-end configuration of a CPU core. For example... Figure 1 As shown, the front-end 101 of this CPU core includes an instruction fetch unit, a decoding unit (also known as a decryption unit), and an issue unit (also known as a dispatch unit). The instruction fetch unit includes branch prediction 201 and selection logic 202; the decoding unit includes an instruction cache 203, instruction decoding 204, a microinstruction cache 205, and a microinstruction queue 206; the issue unit 207 is connected to the microinstruction queue 206. This CPU core has both an instruction cache and a microinstruction cache, thus featuring microarchitecture optimization. The instruction address fetched by the instruction fetch unit is predicted using branch prediction 201 to obtain the address of the next instruction to be executed. Simultaneously, the instruction address is selected by the selection logic 202 to determine whether instruction decoding is required to obtain microinstructions. If "yes," then execution proceeds. Figure 1 The path on the left requires decoding the instruction; if "no", then proceed... Figure 1The path on the right does not require decoding the instruction; instead, it accesses the microinstruction cache to obtain the corresponding microinstruction. For example, these microinstructions are usually organized in the form of microinstruction groups.

[0057] In processor design, a micro-Ops group in instruction dispatch refers to a collection of micro-instructions formed by breaking down complex instructions. Modern processors (especially CPUs using Complex Instruction Set Computer (CISC) architectures) typically break down complex instructions into simpler, parallelizable, or pipelining micro-instructions when executing them. These micro-instructions are grouped as logical units and uniformly scheduled by the processor's dispatch unit, distributing them to different execution units (such as the Arithmetic Logic Unit (ALU), load / store units, etc.).

[0058] As the types and number of execution units on the back-end pipeline increase, the execution capabilities of the back-end are constantly improving. At the same time, current software applications are placing increasingly higher demands on the execution capabilities of the front-end. Therefore, improving the processor capabilities of the front-end is becoming increasingly important, and increasing instruction dispatch bandwidth is a crucial aspect of this. Instruction dispatch bandwidth refers to the number of instructions that a processor can dispatch to different execution units per cycle.

[0059] The inventors of this disclosure have noted that current methods for increasing instruction dispatch bandwidth often involve simply increasing the number of read ports in the microinstruction queue. This increases timing risks in implementation, and a large number of read ports leads to an increase in the area of ​​the instruction dispatch device. Furthermore, reading microinstructions from the microinstruction queue and distributing microinstruction groups increases the critical path, thereby making it more difficult to increase the processor's clock speed.

[0060] This disclosure provides at least one embodiment of an instruction distribution apparatus and instruction distribution method, a processor, and an electronic device.

[0061] The instruction dispatching device includes a write selection module, multiple microinstruction queues, and a read allocation module. The write selection module is configured to write microinstructions to the multiple microinstruction queues; these queues are configured to cache the written microinstructions; the read allocation module is configured to read microinstructions from the queues, obtain the target microinstruction group for this dispatch based on the read microinstructions, and perform the dispatch operation. By setting up multiple microinstruction queues, this device increases the bandwidth of instruction dispatching, thereby improving processor performance. Furthermore, in at least one example, by setting a scheduling method for the multiple microinstruction queues, microinstructions can be flexibly scheduled, further enhancing processor performance.

[0062] The instruction dispatch method includes: writing microinstructions into multiple microinstruction queues, wherein the multiple microinstruction queues are configured to cache the written microinstructions; reading microinstructions from the multiple microinstruction queues; obtaining the target microinstruction group to be dispatched in this operation based on the read microinstructions; and performing the dispatch operation. This instruction dispatch method improves the bandwidth of instruction dispatch by setting up multiple microinstruction queues, thereby promoting processor performance improvement. Furthermore, in at least one example, by setting up a scheduling method for multiple microinstruction queues, microinstructions are flexibly scheduled, further promoting processor performance improvement. The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0063] Figure 2 This is a schematic block diagram of an instruction distribution device provided for at least one embodiment of the present disclosure.

[0064] like Figure 2 As shown, the instruction dispatch device 200 of this embodiment is located in the processor core pipeline and includes a write selection module 210, multiple microinstruction queues 2201~220n (n is a positive integer greater than 1), and a read allocation module 230. In the pipeline, the write selection module 210, the multiple microinstruction queues 220, and the read allocation module 230 are connected in sequence.

[0065] The write selection module 210 is configured to write microinstructions into multiple microinstruction queues 2201~220n; the multiple microinstruction queues 2201~220n are configured to cache the written microinstructions; the read allocation module 230 is configured to read microinstructions from the multiple microinstruction queues 2201~220n, obtain the target microinstruction group to be distributed in this distribution based on the read microinstructions, and perform the distribution operation.

[0066] For example, such as Figure 2 As shown, the multiple microinstruction queues 2201~220n can be represented as microinstruction queues numbered 2201, 2202, ..., and 220n, respectively, and are used to cache microinstructions corresponding to different microinstruction slots. For example, a microinstruction slot is a logical or physical location in the processor hardware reserved for different types of operations, used to classify and distribute the decoded microinstructions to the corresponding execution units. For example, the number of multiple microinstruction queues and the structure of each microinstruction queue can be designed according to the performance of the pipeline, and this embodiment does not limit them.

[0067] For example, each microinstruction queue includes a write port and a read port for managing the operations between writing and reading microinstructions. The write selection module 210 writes microinstructions to the microinstruction queue through the write port, and the read allocation module 230 reads microinstructions from the microinstruction queue through the read port and performs the allocation operation.

[0068] For example, the bandwidth of instruction distribution is matched with the number of read ports in the microinstruction queue, and the number of microinstructions distributed in each instruction distribution can be equal to the number of microinstructions that the read allocation module can read simultaneously each time. For example, reading the microinstruction queue and distributing the target microinstruction group occurs per cycle, which can be a processor machine cycle, i.e., the time cycle of a basic operation of the CPU under the control of a clock signal. Each machine cycle can include one or more clock cycles. For example, the read allocation module can read microinstructions from multiple microinstruction queues once or multiple times per clock cycle and distribute the microinstruction group. For example, the target microinstruction group can be the microinstruction group distributed in the current clock cycle, and the target microinstruction group can be one or more microinstruction groups. For example, the target microinstruction group can be distributed to the execution unit of the pipeline, which can include memory access units, fixed-point arithmetic units, or floating-point arithmetic units, etc.

[0069] For example, the microinstructions written can come from at least one microinstruction source, such as an instruction decoding channel and / or a micro-op cache (OC) fetch channel. For instance, the instruction decoding channel can read instructions from the instruction cache or memory and decode them into microinstructions. As another example, the OC channel can store decoded microinstructions; if the same instruction is executed again, it can be directly read from the OC cache without re-decoding. The instruction decoding channel can include single-channel or multi-channel instruction decoding channels, and the micro-op cache fetch channel can include single-channel or multi-channel micro-op cache fetch channels. In other words, this disclosure does not limit the number of microinstruction sources and can be applied to processor microarchitecture frameworks including single-channel or multi-channel decoding pipelines. At the same time, the microinstruction sources written to the microinstruction queue can be the same or different. For example, the instruction decoding channel and the OC fetch channel can jointly provide microinstructions to the microinstruction queue at the same time. For example, the instruction decoding channel or the microinstruction cache (OC) fetch channel can provide microinstructions to the microinstruction queue separately at the same time.

[0070] For example, the write selection module 210 can be further configured to alternately write microinstructions.

[0071] For example, in at least one embodiment of this disclosure, the write selection module 210 can be further configured to write microinstructions into multiple microinstruction queues according to a preset mapping relationship. For example, the preset mapping relationship can be to write microinstructions into multiple microinstruction queues 2201~220n respectively according to a fixed allocation of microinstruction queues.

[0072] The instruction dispatch apparatus provided in at least one embodiment of this disclosure adopts a design method of providing "multiple microinstruction queues". Without sacrificing the processor clock frequency, for example, without increasing the read port of a single microinstruction queue, the bandwidth of instruction dispatch can be increased, thereby improving the processor performance.

[0073] Figure 3 This is a schematic diagram of the operation of a write selection module provided in at least one embodiment of the present disclosure, which is a specific example of the write selection module writing microinstructions into multiple microinstruction queues according to a preset mapping relationship.

[0074] For example, in some embodiments, the write selection module is further configured to, when multiple microinstruction queues are divided into two microinstruction queues, write microinstructions from the same microinstruction source to the two microinstruction queues evenly according to a preset mapping relationship, that is, write them to the two microinstruction queues with the same probability over a long period of time (e.g., more than 1000 machine cycles). For example, the write selection module may write microinstructions from the same microinstruction source to the two microinstruction queues in the same proportion (50% each) within one machine cycle. For example, the same microinstruction source may include an instruction decoding channel or a microinstruction cache (OC) fetch channel.

[0075] like Figure 3 As shown, the sources of microinstructions can include the instruction decoding channel and the microinstruction cache (OC) fetch channel. For example... Figure 3 As shown, in this embodiment, the multiple microinstruction queues include two microinstruction queues, namely UOPQ-0 and UOPQ-1.

[0076] like Figure 3 As shown, each microinstruction slot can be represented by a slot. Figure 3 And the number of micro-instructions allocated to each slot in the subsequent diagrams, that is, each slot corresponds to one micro-instruction.

[0077] For example, such as Figure 3 As shown, the write bandwidths of the two channels are different. Taking 4 microinstructions as an example, the write bandwidth of the instruction decoding channel corresponds to slots 0 to 3 in the instruction decoding channel; taking 8 microinstructions as an example, the write bandwidth of the OC fetch channel corresponds to slots 0 to 7 in the OC fetch channel. For example, as... Figure 3 As shown, each microinstruction queue (UOPQ-0 and UOPQ-1) has 4 write ports, corresponding to slots-0 to slot-3 of UOPQ-0 and slots-4 to slot-7 of UOPQ-1, respectively.

[0078] For example, such as Figure 3As shown, if the microinstructions written originate from the instruction decoding channel, then the four microinstructions from the instruction decoding channel are evenly distributed into two microinstruction queues. For example, as... Figure 3 As shown, the microinstructions corresponding to slot-0 and slot-1 in the instruction decoding channel are written into slot-0 and slot-1 of UOPQ-0, and the microinstructions corresponding to slot-2 and slot-3 in the instruction decoding channel are written into slot-4 and slot-5 of UOPQ-1. If the microinstructions originate from the OC fetch channel, the eight microinstructions are evenly distributed into the two microinstruction queues. For example, the microinstructions corresponding to slots-0 to slot-3 in the OC fetch channel are written into slots-0 to slot-3 of UOPQ-0, and the microinstructions corresponding to slots-4 to slot-7 in the OC fetch channel are written into slots-4 to slot-7 of UOPQ-1.

[0079] Figure 3 This is just one example of distributing microinstructions from the same microinstruction source equally. The correspondence between the slot numbers in the aforementioned microinstruction source and the slot numbers in the microinstruction queue is not unique.

[0080] Furthermore, the scheme of distributing microinstructions into multiple microinstruction queues will vary depending on the number of microinstruction queues and the bandwidth of different microinstruction sources, and the embodiments disclosed herein do not impose any limitations on it.

[0081] Figure 4 This is a schematic block diagram of an instruction distribution apparatus provided in at least one embodiment of the present disclosure. Figure 2 A specific example of a command distribution device.

[0082] like Figure 4 As shown, the instruction dispatch device 400 is used for the processor core pipeline and includes a write selection module 410, multiple microinstruction queues 4201~420n (n is a positive integer greater than 1), and a read allocation module 430. The write selection module 410, the multiple microinstruction queues 4201~420n, and the read allocation module 430 are connected in sequence.

[0083] For example, such as Figure 4 As shown, the multiple microinstruction queues 4201~420n can be represented as microinstruction queues numbered 4201, 4202, ..., and 420n, respectively.

[0084] For example, such as Figure 4 As shown, the read allocation module 430 includes a reordering unit 431, a first determination unit 432, and a distribution unit 433. The reordering unit 431, the first determination unit 432, and the distribution unit 433 are connected in sequence.

[0085] For example, the reordering unit 431 is configured to read microinstructions from multiple microinstruction queues 4201-420n and reorder the read microinstructions according to the actual instruction order. For example, the actual instruction order refers to the original static order of instruction fetching at the pipeline front end, i.e., the address order of instruction fetching. When these microinstructions are written to the multiple microinstruction queues 4201-420n, for example, adjacent microinstructions in the actual instruction order might be written to different microinstruction queues. Therefore, when reading them from different microinstruction queues, their actual order can be restored through a reordering operation.

[0086] For example, the first determining unit 432 is configured to determine at least one microinstruction group including a target microinstruction group based on the reordered microinstructions and preset constraints, where "target microinstruction group" refers to the microinstruction group that is the object of operation. For example, in some embodiments, the preset constraints may include instruction attribute information and / or instruction execution information. For example, the preset constraints may include only instruction attribute information, only instruction execution information, or both instruction attribute information and instruction execution information. For example, instruction attribute information may include instruction length and data dependencies between instructions; instruction execution information may include the type and execution status of subsequent execution units.

[0087] For example, the first determining unit 432 can determine multiple microinstruction groups, among which the target microinstruction group is included.

[0088] For example, dispatch unit 433 is configured to dispatch target microinstruction sets. For example, dispatch unit 433 can dispatch target microinstruction sets to execution units in the pipeline.

[0089] The descriptions of the write selection module 410 and the multiple microinstruction queues 4201~420n mentioned above can be found in [reference needed]. Figure 2 The corresponding description is provided in the original text and will not be repeated here.

[0090] Figure 5 A schematic diagram of the operation of a read allocation module provided in at least one embodiment of this disclosure is shown. Figure 4 A specific example of the operation of the provided read allocation module.

[0091] for Figure 4 In the illustrated embodiment, after the first determining unit determines at least one microinstruction group including the target microinstruction group, the distribution unit distributes the target microinstruction group. At this point, after distributing the target microinstruction group, the distribution unit needs to determine the position for the next distribution.

[0092] For example, such as Figure 5 As shown, the dispatch unit is further configured to dispatch the target microinstruction group via a read pointer. For example, after the target microinstruction group is dispatched, the read pointer points to the next valid microinstruction location of the target microinstruction group.

[0093] like Figure 5 As shown, each dispatch can be divided into three cases: a, b, and c. In each case, two rows of slots (slot-0 to slot-7) represent the microinstructions read from the microinstruction queue in two separate transactions. That is, slots-0 to slot-7 in line 1 represent the microinstructions read from the queue this time, and slots-0 to slot-7 in line 2 represent the microinstructions read from the queue next time. The read pointer represents the starting position of the target microinstruction group, which is also the position of the microinstruction currently being dispatched.

[0094] Figure 5 In the accompanying diagrams, the gray slots represent invalid instructions that may exist in the pipeline, such as "bubbles." An invalid instruction means that there is no valid instruction in the current slot, resulting in an idle state.

[0095] like Figure 5 As shown, reading the pointer can be divided into the following three cases:

[0096] Case a: After completing the distribution of microinstruction group (GROUP-0 in a), the distribution unit will distribute the target microinstruction group (GROUP-1 in a) from the microinstructions read this time. That is to say, the microinstruction groups (GROUP-0 and GROUP-1) distributed in the two cases are microinstructions read from the same microinstruction queue in the same instance, and the position of the read pointer is still in the microinstruction read from the microinstruction queue this time (LINE 1).

[0097] Case b: After the distribution of microinstruction groups (GROUP-0 and GROUP-1 in b) is completed, the distribution unit will distribute the target microinstruction group (GROUP-2 in b) from the next microinstruction read. That is, the two distributed microinstruction groups (GROUP-1 and GROUP-2) are microinstructions read from the microinstruction queue at different times, and the read pointer position is in the next microinstruction read from the microinstruction queue (LINE 2).

[0098] Case c: Similar to case a, after the distribution of the microinstruction group (GROUP-0 in c) is completed, the distribution unit will distribute the target microinstruction group (GROUP-1 in c) from the microinstructions read this time. The target microinstruction groups (GROUP-0 and GROUP-1) distributed in the two cases are still the same microinstructions read from the microinstruction queue in the same instance, and the position of the read pointer is still in the microinstructions read from the microinstruction queue this time (LINE 1). The only difference is that there are invalid instructions in the target microinstruction group (GROUP-1 in c) being distributed.

[0099] like Figure 5As shown, invalid instructions exist in both case b (slot-7 in b) and case c (slot-6 and slot-7 in c). A microinstruction repositioning (or circuit design selection) is required to send valid instructions to the execution unit. Simultaneously, since there are target microinstruction groups consisting of microinstructions read across two reads, such as in cases a and c, the read allocation module needs to add registers to cache the microinstructions previously read from the microinstruction queue in the target microinstruction group.

[0100] For example, in at least one embodiment, the first determining unit further includes a microinstruction register. The microinstruction register is configured to store the reordered microinstructions from the first read if the target microinstruction set is obtained based on reordered microinstructions read twice.

[0101] Figure 6 This is a schematic diagram of an instruction distribution device provided in at least one embodiment of the present disclosure. Figure 6 for Figure 4 This is a specific example of an instruction dispatching device.

[0102] like Figure 6 As shown, the instruction dispatching device 600 includes a write selection module 610, a microinstruction queue UOPQ-0 and a microinstruction queue UOPQ-1, and a read allocation module 630, which are connected in sequence.

[0103] like Figure 6 As shown, the write selection module 610 allocates microinstructions from the instruction decoding channel and / or the OC fetch channel to UOPQ-0 and UOPQ-1 through path selection and microinstruction order. For example, the instruction decoding channel bandwidth is 4 microinstructions, the OC fetch channel bandwidth is 8 microinstructions, and the write bandwidth of the microinstruction queue is 8 microinstructions.

[0104] like Figure 6 As shown, microinstruction queues UOPQ-0 and UOPQ-1 are configured to cache the written microinstructions.

[0105] like Figure 6 As shown, the read allocation module 630 includes a reordering unit 631, a first determination unit 632, and a distribution unit 633.

[0106] like Figure 6 As shown, the reordering unit 631 reads microinstructions from UOPQ-0 and UOPQ1 respectively through read control, and reorders the read microinstructions according to the actual instruction order. For example, the read bandwidth of UOPQ-0 and UOPQ1 is 3 microinstructions, that is, each read operation can read 3 microinstructions from the microinstruction queue.

[0107] like Figure 6 As shown, the first determining unit 632 determines at least one microinstruction group including the target microinstruction group from the read microinstructions based on static and dynamic constraints, that is... Figure 6 The term "defining microinstruction sets" refers to the process of defining microinstruction sets. For example, static constraints can be fixed rules determined during the instruction decoding stage, directly related to processor hardware design and instruction set architecture characteristics, and independent of runtime state. Dynamic constraints, on the other hand, can be rules adjusted in real-time based on the processor's current state, relying on pipeline feedback, resource utilization, speculative execution states, etc., to optimize the scheduling and distribution of microinstruction sets. For instance, static constraints can be the instruction attribute information mentioned above. Similarly, dynamic constraints can be the instruction execution information mentioned above.

[0108] like Figure 6 As shown, the dispatch unit 633 dispatches the target microinstruction group. For example, when dispatching the target microinstruction group (such as GROUP 0), the dispatch unit 633 can dynamically match it to an idle execution unit and port according to the operation type of the microinstruction (such as arithmetic logic operation, memory access, floating-point operation). If a port conflict is encountered (such as two microinstructions contending for the same arithmetic logic unit port), the undispatched microinstructions will be temporarily stored in the dispatch unit 633, waiting for resource release. The dispatch unit 633 supports a multi-issue mechanism, allowing multiple independent microinstructions to be dispatched to different ports in parallel within the same cycle. It can also simultaneously employ an out-of-order scheduling strategy to enable independent instructions to bypass blocking operations and execute ahead of time to improve parallelism.

[0109] The instruction distribution apparatus provided in at least one embodiment of the present disclosure also adopts the design method of "determining the microinstruction group after writing to the microinstruction queue" and "distributing instructions using a read pointer". Without sacrificing the processor clock frequency, for example without increasing the number of individual microinstruction queue read ports, the bandwidth of instruction distribution is increased, thereby improving processor performance.

[0110] Figure 7 A schematic block diagram of another instruction distribution apparatus provided for at least one embodiment of this disclosure, for Figure 2 Another specific example of the provided instruction distribution device.

[0111] like Figure 7 As shown, the instruction dispatching device 700 includes a write selection module 710, multiple microinstruction queues 720, and a read allocation module 730. The write selection module 710, the multiple microinstruction queues 7201~720n (n is a positive integer greater than 1), and the read allocation module 730 are connected in sequence.

[0112] For example, such as Figure 7 As shown, the write selection module 710 includes a second determination unit 711 and an allocation unit 712.

[0113] For example, such as Figure 7 As shown, the multiple microinstruction queues 7201~720n can be represented as microinstruction queues numbered 7201, 7202, ..., and 720n, respectively.

[0114] For example, in at least one embodiment of this disclosure, the second determining unit 711 is configured to determine at least one microinstruction group in the microinstructions according to preset constraints. For example, in at least one embodiment of this disclosure, the allocation unit 712 is configured to write the microinstructions from at least one microinstruction group into a plurality of microinstruction queues 7201-720n. As described above, the preset constraints may include instruction attribute information and / or instruction execution information.

[0115] For a description of the aforementioned microinstruction queues 720 and read allocation module 730, please refer to [link to relevant documentation]. Figure 2 The corresponding description is provided in the original text and will not be repeated here.

[0116] The instruction dispatch apparatus provided in at least one embodiment of this disclosure defines microinstruction groups before writing microinstructions into multiple microinstruction queues, and adopts a method such as writing microinstruction group boundary information, which can avoid writing invalid instructions into the microinstruction queues, thereby saving circuit overhead.

[0117] Figure 8A This is a schematic diagram illustrating the operation of an allocation unit provided in at least one embodiment of the present disclosure. Figure 8B Another schematic diagram of the operation of an allocation unit provided for at least one embodiment of this disclosure. Figure 8A and Figure 8B for Figure 7 Two specific examples of how the distribution unit works.

[0118] like Figure 8A and Figure 8B As shown, multiple microinstruction queues include UOPQ-0 and UOPQ-1, and the write bandwidth of each microinstruction queue is 3 microinstructions.

[0119] For example, the allocation unit can be further configured to allocate microinstructions from at least one microinstruction group to multiple microinstruction queues according to a preset mapping relationship. The preset mapping relationship can be a fixed allocation method. For example, allocating fixed numbers and / or a fixed number of microinstructions to fixed microinstruction queues. Figure 8A As shown, the allocation unit can allocate the microinstructions corresponding to slot-0 to slot-2 to UOPQ-0, and allocate the microinstructions corresponding to slot-3 to slot-5 to UOPQ-1.

[0120] For example, the allocation unit can be further configured to dynamically allocate microinstructions from at least one microinstruction group to multiple microinstruction queues. For instance, dynamic allocation can be based on runtime conditions such as load, dependencies, and resource availability. This allocation scheme fully utilizes every entry in the microinstruction queue and avoids writing invalid microinstructions into the queue. For example, as... Figure 8B As shown, at least one set of microinstructions is rearranged and written into UOPQ-0 and UOPQ-1. Figure 8B As shown, each microinstruction can be written into UOPQ-0 or UOPQ-1.

[0121] When writing microinstructions to the microinstruction queue, the valid microinstruction group boundaries also need to be written to the microinstruction queue to facilitate the identification of microinstruction groups when reading microinstructions from the queue. For example, the allocation unit can also be configured to record the boundary information of each microinstruction group.

[0122] Figure 9A This is a schematic diagram of a microinstruction queue provided for at least one embodiment of the present disclosure. Figure 9B Another schematic diagram of a microinstruction queue provided for at least one embodiment of this disclosure. Figure 9A and Figure 9B These are two specific examples of writing valid microinstruction group boundaries into the microinstruction queue.

[0123] For example, such as Figure 9A and Figure 9B As shown, the microinstruction queue can store microinstruction decoding information and microinstruction boundary information. For example, microinstruction decoding information may include microinstruction opcode, operand source and target information, etc., and microinstruction boundary information can be stored in the microinstruction queue in the following manner.

[0124] For example, in at least one embodiment of this disclosure, the allocation unit may be further configured to write boundary information of each microinstruction group into multiple microinstruction queues, each microinstruction queue including multiple entries, each entry including a flag bit. For example, the flag bit indicates whether the microinstruction stored in the corresponding entry is the last microinstruction in each microinstruction group, and the boundary information includes the flag bit.

[0125] For example, such as Figure 9AAs shown, the microinstruction queue can contain multiple entries. Each entry defines a microinstruction group boundary, and the boundary of the last microinstruction in the microinstruction group is marked to facilitate determining the target microinstruction group for distribution. Each entry can include microinstruction decoding information and microinstruction group boundary information. The boundary information includes a flag bit, which can be set to 1 bit. When the microinstruction is the end position of the microinstruction group (i.e., the last instruction in the microinstruction group), the bit is set to 1; otherwise, it remains 0. It should be noted that this embodiment does not limit the length and configuration of the flag bit.

[0126] For example, the allocation unit can be further configured to write the boundary information of each microinstruction group into the microinstruction quantity queue, which is configured to store the number of microinstructions stored in each microinstruction queue for each microinstruction group, and the boundary information includes the number of microinstructions.

[0127] For example, the microinstruction count queue can be one or more of multiple microinstruction queues, that is, multiple microinstruction queues can include the microinstruction count queue.

[0128] For example, such as Figure 9B As shown, multiple microinstruction queues may include UOPQ-0, UOPQ-1, and UOPQ-2. UOPQ-0 and UOPQ-1 serve as microinstruction queues to store microinstruction decoding information, while UOPQ-2 serves as a microinstruction count queue to store the number of microinstructions in a microinstruction group. That is, each microinstruction group stores the number of microinstructions in each microinstruction group in either UOPQ-0 or UOPQ-1.

[0129] For example, the read allocation module may also include a distribution unit. This distribution unit is further configured to acquire a target microinstruction group and perform a distribution operation based on boundary information and microinstructions read from multiple microinstruction queues.

[0130] For example, in such Figure 9A In the boundary information storage method shown, the distribution unit reads the flag bit in each entry of the microinstruction queue to determine the boundary of the microinstruction group, thereby obtaining the target microinstruction group and performing the distribution operation. For example, in... Figure 9B In the boundary information storage method shown, when the distribution unit reads the microinstruction queue, it needs to read the values ​​of UOPQ-0 / 1 / 2. Based on the number of microinstructions in the microinstruction group stored in UOPQ-2, the microinstructions for that part are read from UOPQ-0 / 1. UOPQ-0 / 1 is read in units of microinstructions, while UOPQ-2 is read in units of microinstruction groups.

[0131] Figure 10A schematic diagram of another instruction distribution apparatus provided for at least one embodiment of the present disclosure. Figure 10 for Figure 7 This is a specific example of an instruction dispatching device.

[0132] like Figure 10 As shown, the instruction dispatching device 1000 includes a write selection module 1010, a microinstruction queue UOPQ-0 and a microinstruction queue UOPQ-1, and a read allocation module 1030.

[0133] like Figure 10 As shown, the write selection module 1010 allocates microinstructions from the instruction decoding channel and the OC fetch channel to the microinstruction queues UOPQ-0 and UOPQ-1 through path selection and microinstruction order. For example, the instruction decoding channel has a bandwidth of 4 microinstructions (slot-0 to slot-3), the OC fetch channel has a bandwidth of 8 microinstructions (slot-0 to slot-7), and the write bandwidth of the microinstruction queues is 8 microinstructions (slot-0 to slot-7).

[0134] like Figure 10 As shown, the write selection module 1010 includes a second determining unit 1011 and an allocation unit 1012. For example, the second determining unit 1011 determines at least one microinstruction group from the microinstructions from the instruction decoding channel and the OC fetch channel according to static and dynamic constraints, that is... Figure 10 The "define microinstruction group" is defined in the text. The allocation unit 1012 allocates the microinstructions from at least one defined microinstruction group to microinstruction queues UOPQ-0 and UOPQ-1. The allocation method can be seen in the above example. Figure 8A and Figure 8B Examples of the description will not be repeated here.

[0135] like Figure 10 As shown, multiple microinstruction queues can be microinstruction queue UOPQ-0 and microinstruction queue UOPQ-1 (or more microinstruction queues). The structure and configuration of microinstruction queues can be found above. Figure 9A and Figure 9B The examples described will not be repeated here. The read bandwidth for each microinstruction queue is 3 microinstructions (slot-0 to slot-2).

[0136] like Figure 10 As shown, the read allocation module 1030 includes a distribution unit 1031. The distribution unit 1031 determines the target microinstruction group from the microinstruction groups read from the microinstruction queue and distributes it to the execution unit, i.e., Figure 10 The instruction distribution bandwidth is 6 microinstructions (slot-0 to slot-5).

[0137] At least one embodiment of this disclosure also provides an instruction dispatch method. Figure 11 A schematic flowchart illustrating an instruction dispatch method provided in at least one embodiment of this disclosure, which may correspond to, for example, an instruction dispatch method. Figure 1 , Figure 4 or Figure 7 The instruction distribution device shown.

[0138] like Figure 11 As shown, the instruction distribution method provided in at least one embodiment of this disclosure includes at least steps S1110-S1120. For example, this instruction distribution method can be applied to the instruction distribution apparatus provided in any of the above embodiments of this disclosure.

[0139] Step S1110: Write microinstructions to multiple microinstruction queues, which are configured to cache the written microinstructions.

[0140] Step S1120: Read microinstructions from multiple microinstruction queues, obtain the target microinstruction group to be distributed in this operation based on the read microinstructions, and perform the distribution operation.

[0141] For example, in at least one embodiment of the instruction distribution method, step S1110 may further include: writing the microinstructions into multiple microinstruction queues according to a preset mapping relationship.

[0142] For example, in at least one embodiment of the instruction distribution method, step S1110 may further include: when multiple microinstruction queues are divided into two microinstruction queues, writing microinstructions from the same microinstruction source into the two microinstruction queues on an even basis according to a preset mapping relationship.

[0143] For example, in at least one embodiment of the instruction distribution method, step S1120 may further include steps S1121-S1123.

[0144] Step S1121: Read microinstructions from multiple microinstruction queues and reorder the read microinstructions according to the actual instruction order.

[0145] Step S1122: Determine at least one microinstruction group including the target microinstruction group based on the reordered microinstructions and preset constraints.

[0146] Step S1123: Distribute the target microinstruction group.

[0147] For example, in the instruction distribution method provided in at least one embodiment of this disclosure, step S1123 may further include: distributing the target microinstruction group by reading the pointer, wherein after the target microinstruction group is distributed, the reading pointer points to the next valid microinstruction position of the target microinstruction group.

[0148] For example, in the instruction distribution method provided in at least one embodiment of this disclosure, step S1122 may further include: when the target microinstruction group is obtained based on reordered microinstructions read twice, storing the reordered microinstructions read for the first time in the microinstruction register.

[0149] For example, in the instruction distribution method provided in at least one embodiment of this disclosure, step S1110 may further include steps S1111-S1112.

[0150] Step S1111: Determine at least one microinstruction group in the microinstruction according to preset constraints.

[0151] Step S1112: Write the microinstructions from at least one microinstruction group into multiple microinstruction queues.

[0152] For example, in the instruction distribution method provided in at least one embodiment of this disclosure, the preset constraints in step S1111 or step S1122 include instruction attribute information and / or instruction execution information.

[0153] For example, in the instruction distribution method provided in at least one embodiment of this disclosure, step S1112 may further include: allocating microinstructions in at least one microinstruction group to multiple microinstruction queues according to a preset mapping relationship.

[0154] For example, in the instruction distribution method provided in at least one embodiment of this disclosure, step S1112 may further include: dynamically allocating microinstructions in at least one microinstruction group to multiple microinstruction queues.

[0155] For example, the instruction distribution method provided in at least one embodiment of this disclosure may further include: recording boundary information of each microinstruction group.

[0156] For example, in the instruction distribution method provided in at least one embodiment of this disclosure, step S1112 may further include: writing the boundary information of each microinstruction group into multiple microinstruction queues, each microinstruction queue including multiple entries, each entry including a flag bit, wherein the flag bit indicates whether the microinstruction stored in the corresponding entry is the last microinstruction in each microinstruction group, and the boundary information includes the flag bit.

[0157] For example, in the instruction distribution method provided in at least one embodiment of this disclosure, step S1112 may further include: writing the boundary information of each microinstruction group into a microinstruction quantity queue, wherein the microinstruction quantity queue is configured to store the number of microinstructions stored in each microinstruction queue for each microinstruction group, and the boundary information includes the number of microinstructions.

[0158] For example, the instruction distribution method provided in at least one embodiment of this disclosure may further include step S1113.

[0159] Step S1113: Based on the boundary information and the microinstructions read from multiple microinstruction queues, obtain the target microinstruction group and perform the distribution operation.

[0160] It should be noted that the functions or beneficial effects of each step in the instruction distribution method provided in any embodiment of this disclosure can be found in the description of the instruction distribution apparatus provided in any embodiment of this disclosure, and will not be repeated here.

[0161] It should also be noted that the execution order of the various steps of the instruction dispatch method in the various embodiments of this disclosure is not limited. Although the execution process of each step has been described in a specific order above, this does not constitute a limitation on the embodiments of this disclosure. The various steps in the instruction dispatch method can be executed serially or in parallel, which can be determined according to actual needs.

[0162] For example, compared to the above description, the instruction distribution method provided in at least one embodiment of this disclosure may include more or fewer steps, and the embodiments of this disclosure do not limit this.

[0163] Figure 12 This is a schematic block diagram of a processor provided for at least one embodiment of the present disclosure.

[0164] like Figure 12 As shown, the processor 1200 includes an instruction dispatching device 1210. The instruction dispatching device 1210 can be any of the instruction dispatching devices provided in the above embodiments of this disclosure.

[0165] For example, processor 1200 may be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit with data processing capabilities and / or program execution capabilities.

[0166] For example, in the case where the processor 1200 is a central processing unit (CPU), the CPU includes a pipeline that includes units or components such as branch prediction, instruction fetch, decoding, issue and rename, execution unit, and instruction dispatch. For example, the issue and rename unit includes the aforementioned instruction dispatch device 1210.

[0167] For example, in embodiments of this disclosure, the central processing unit (CPU) may employ an x86 architecture, ARM architecture, RISC architecture (e.g., RISC-V), MIPS architecture, etc. The processor 1200 may be a general-purpose processor or a dedicated processor, and may be a single-core processor or a multi-core processor. The processor in embodiments of this disclosure may be a processor of any architecture and any instruction set, and this disclosure does not impose any limitations on it.

[0168] At least some embodiments of this disclosure also provide an electronic device that includes the processor of any of the above embodiments.

[0169] Figure 13 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0170] like Figure 13 As shown, the electronic device 1300 includes a processor 1310. A description of the processor 1310 can be found in [reference needed]. Figure 12 The corresponding description of the processor 1200 will not be repeated here.

[0171] Figure 14 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0172] The electronic devices in this disclosure may include mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 14 The illustrated electronic device 1400 is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0173] For example, such as Figure 14 As shown, in some examples, electronic device 1400 includes processor 1401 (e.g., central processing unit, graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1402 or a program loaded from storage device 1408 into random access memory (RAM) 1403. For example, processor 1401 can be the processor provided in any of the above embodiments. Various programs and data required for the operation of the computer system are also stored in RAM 1403. Processor 1401, ROM 1402, and RAM 1403 are connected via bus 1404. Input / output (I / O) interface 1405 is also connected to bus 1404.

[0174] For example, the following components can be connected to I / O interface 1405: input devices 1406 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1407 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices including, for example, magnetic tapes, hard disks, etc.; and communication devices 1409, such as network interface cards like LAN cards and modems, etc. Communication device 1409 allows electronic device 1400 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1410 is also connected to I / O interface 1405 as needed. Removable media 1411, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 1410 as needed so that computer programs read from them can be installed into storage devices as needed. Although Figure 14 An electronic device 1400 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0175] For example, the electronic device 1400 may further include a peripheral interface (not shown). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1409 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0176] For example, the electronic device 1400 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or any combination of data processing device and hardware. The embodiments disclosed herein do not limit this.

[0177] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0178] The following points need to be explained:

[0179] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0180] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0181] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. An instruction distribution device, comprising: The module includes a write selection module, multiple microinstruction queues, and a read allocation module; among which, The write selection module is configured to write microinstructions into the plurality of microinstruction queues; The multiple microinstruction queues are configured to cache the written microinstructions; The read allocation module is configured to read microinstructions from the plurality of microinstruction queues, obtain the target microinstruction group to be distributed in this distribution based on the read microinstructions, and perform a distribution operation, wherein the distribution operation includes distributing the target microinstruction group to the execution unit; The read allocation module includes: The reordering unit is configured to read microinstructions from the plurality of microinstruction queues and reorder the read microinstructions according to the actual instruction order; The first determining unit is configured to determine at least one microinstruction group including the target microinstruction group based on the reordered microinstructions and preset constraints; and The distribution unit is configured to distribute the target microinstruction group.

2. The instruction distribution device according to claim 1, wherein, The write selection module is further configured to write the microinstructions into the plurality of microinstruction queues according to a preset mapping relationship.

3. The instruction distribution device according to claim 2, wherein, The write selection module is further configured to, when the plurality of microinstruction queues are two microinstruction queues, write microinstructions from the same microinstruction source to the two microinstruction queues evenly according to a preset mapping relationship.

4. The instruction distribution device according to claim 1, wherein, The distribution unit is further configured to distribute the target microinstruction group by reading a pointer. Wherein, after the target microinstruction group is distributed, the read pointer points to the next valid microinstruction position of the target microinstruction group.

5. The instruction distribution device according to claim 4, wherein, The first determining unit further includes a microinstruction register, wherein the microinstruction register is configured to store the reordered microinstructions read in the first read when the target microinstruction group is obtained based on reordered microinstructions read twice.

6. The instruction distribution apparatus according to claim 1, wherein, The write selection module includes: The second determining unit is configured to determine at least one group of microinstructions from the microinstructions according to preset constraints; and The allocation unit is configured to write microinstructions from the at least one microinstruction group into the plurality of microinstruction queues.

7. The instruction distribution apparatus according to claim 1 or 6, wherein, The preset constraints include instruction attribute information and / or instruction execution information.

8. The instruction distribution apparatus according to claim 6, wherein, The allocation unit is further configured to allocate microinstructions in the at least one microinstruction group to the plurality of microinstruction queues according to a preset mapping relationship.

9. The instruction distribution apparatus according to claim 6, wherein, The allocation unit is further configured to dynamically allocate microinstructions from the at least one microinstruction group to the plurality of microinstruction queues.

10. The instruction distribution apparatus according to claim 6, wherein, The allocation unit is also configured to record boundary information for each microinstruction group.

11. The instruction distribution apparatus according to claim 10, wherein, The allocation unit is further configured to write the boundary information of each microinstruction group into the plurality of microinstruction queues, each microinstruction queue including multiple entries, each entry including a flag bit. The flag bit indicates whether the microinstruction stored in the corresponding entry is the last microinstruction in each microinstruction group, and the boundary information includes the flag bit.

12. The instruction dispatch apparatus according to claim 10 further includes a microinstruction quantity queue. in, The allocation unit is further configured to write the boundary information of each microinstruction group into the microinstruction quantity queue. The microinstruction quantity queue is configured to store the number of microinstructions stored in each microinstruction queue for each microinstruction group, and the boundary information includes the number of microinstructions.

13. The instruction distribution apparatus according to any one of claims 10-12, wherein, The distribution unit is further configured to obtain the target microinstruction group and perform the distribution operation based on the boundary information and the microinstructions read from the plurality of microinstruction queues.

14. An instruction dispatch method, comprising: Microinstructions are written to multiple microinstruction queues, which are configured to cache the written microinstructions. Microinstructions are read from the plurality of microinstruction queues, a target microinstruction group to be distributed in this distribution is obtained based on the read microinstructions, and a distribution operation is performed, wherein the distribution operation includes distributing the target microinstruction group to the execution unit; The step of reading microinstructions from the plurality of microinstruction queues, obtaining the target microinstruction group to be distributed in this operation based on the read microinstructions, and performing the distribution operation includes: Microinstructions are read from the plurality of microinstruction queues and reordered according to the actual instruction order; Determine at least one microinstruction group including the target microinstruction group based on the reordered microinstructions and preset constraints; and Distribute the target microinstruction group.

15. The instruction dispatch method according to claim 14, wherein, The step of writing microinstructions into multiple microinstruction queues includes: The microinstructions are written into the multiple microinstruction queues according to a preset mapping relationship.

16. The instruction dispatch method according to claim 14, wherein, Distributing the target microinstruction group includes: distributing the target microinstruction group by reading a pointer. Wherein, after the target microinstruction group is distributed, the read pointer points to the next valid microinstruction position of the target microinstruction group.

17. The instruction dispatch method according to claim 14, wherein, The step of writing microinstructions into multiple microinstruction queues includes: At least one microinstruction group is determined in the microinstructions according to preset constraints; and The microinstructions in the at least one microinstruction group are written into the plurality of microinstruction queues.

18. The instruction dispatch method according to claim 17, wherein, The step of writing microinstructions from the at least one microinstruction group into the plurality of microinstruction queues includes: The microinstructions in the at least one microinstruction group are distributed to the plurality of microinstruction queues according to a preset mapping relationship.

19. The instruction dispatch method according to claim 17, wherein, The step of writing microinstructions from the at least one microinstruction group into the plurality of microinstruction queues includes: The microinstructions in the at least one microinstruction group are dynamically allocated to the plurality of microinstruction queues.

20. The instruction distribution method according to claim 17, further comprising: Record the boundary information of each microinstruction group.

21. A processor comprising an instruction dispatching apparatus according to any one of claims 1-13.

22. An electronic device comprising the processor according to claim 21.

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