Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes a light-emitting element, a first power signal line, a second power signal line, a light-emitting control signal line, a first scan line, and a plurality of pixel driving circuits. Adjacent rows of pixel driving circuits are mirror-arranged. Each pixel driving circuit includes a driving transistor and a first light-emitting control transistor. By placing a first node electrically connected to the anode of the light-emitting element by the first light-emitting control transistor between the first power signal line and the light-emitting control signal line, the first node can be made close to the middle region of the pixel driving circuit. This reduces the difference in the length of the conduction path between the mirror-arranged adjacent rows of pixel driving circuits and the anode of the light-emitting element. This reduces the potential difference of the light-emitting elements corresponding to the mirror-arranged adjacent rows of pixel driving circuits, thereby reducing the brightness difference of the light-emitting elements corresponding to the mirror-arranged adjacent rows of pixel driving circuits and improving the brightness uniformity of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) display technology has many advantages, such as self-illumination, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, wide operating temperature range, and the ability to achieve flexible display and large-area full-color display. It is widely recognized in the industry as the display technology with the greatest development potential.

[0003] Currently, to improve the yield and performance of OLED display panels, the pixel driving circuits in odd-numbered rows are mirrored with those in even-numbered rows. Currently, the key nodes for the electrical connection between the transistors and light-emitting elements in the pixel driving circuit are located on the bottom of the pixel driving circuit. This results in a staggered arrangement of key nodes in each row after mirroring. Since the light-emitting elements in each row are arranged at equal intervals, the length of the conduction path between the key nodes and corresponding light-emitting elements in odd-numbered rows is dependent on the length of the conduction path between the key nodes and corresponding light-emitting elements in even-numbered rows. This leads to a potential difference between the light-emitting elements in odd-numbered and even-numbered rows, ultimately resulting in a significant difference in brightness between the light-emitting elements in odd and even rows.

[0004] Therefore, it is necessary to provide a display panel and display device to improve this deficiency. Summary of the Invention

[0005] The embodiments of this application provide a display panel and a display device that can improve the uniformity of brightness of the display panel.

[0006] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, including a light-emitting element, a first power signal line, a second power signal line, a light-emitting control signal line, a first scan line, and a plurality of pixel driving circuits. The plurality of pixel driving circuits are arranged in an array to form multiple rows and multiple columns of pixel driving circuits, with adjacent rows of pixel driving circuits mirrored. Each pixel driving circuit includes:

[0007] A driving transistor is connected in series with the light-emitting element between the first power signal line and the second power signal line;

[0008] A first light-emitting control transistor is connected in series between the driving transistor and the light-emitting element, and is electrically connected to the anode of the light-emitting element at the first node. The first light-emitting control gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line.

[0009] The first reset transistor is electrically connected to the first node and the first scan line. The orthographic projections of the first power signal line, the light emission control signal line, and the first scan line on the reference plane are arranged sequentially along the column direction from the driving transistor to the first reset transistor. The reference plane is parallel to the light-emitting surface of the display panel.

[0010] Wherein, the orthographic projection of the first node on the reference plane is located between the orthographic projections of the first power signal line and the light emission control signal line on the reference plane.

[0011] Optionally, the first light-emitting control transistor includes a first light-emitting control active portion, one end of which is electrically connected to the anode of the light-emitting element;

[0012] Wherein, the orthographic projection of the first light-emitting control active part on the reference plane is located between the orthographic projections of the first power signal line and the light-emitting control signal line on the reference plane.

[0013] Optionally, the extension direction of the first light-emitting control active portion is parallel to the extension direction of the light-emitting control signal line, and the extension direction of the first light-emitting control gate is perpendicular to the extension direction of the light-emitting control signal line.

[0014] Optionally, the driving transistor includes a driving active portion, which includes a first sub-part and a second sub-part with different extending directions;

[0015] Wherein, in a direction perpendicular to the extension direction of the light-emitting control signal line, the first sub-part overlaps with the first light-emitting control active part; and in a direction along the extension direction of the light-emitting control signal line, the second sub-part overlaps with the first light-emitting control active part.

[0016] Optionally, the light emission control signal line is disposed on a different layer from the first light emission control gate.

[0017] Optionally, the light emission control signal line is disposed on the same layer as the first power supply signal line.

[0018] Optionally, the display panel includes:

[0019] The first active layer includes the first light-emitting control active part;

[0020] A first gate layer is disposed on the first active layer and includes the first light-emitting control gate;

[0021] A first source-drain layer is disposed on the first gate layer and includes the light emission control signal line and the first power supply signal line.

[0022] Optionally, the pixel driving circuit includes a storage capacitor and a second light-emitting control transistor, and the display panel includes:

[0023] The first gate layer includes the first electrode of the storage capacitor;

[0024] The second gate layer includes the second electrode of the storage capacitor;

[0025] The display panel further includes a first connecting portion, and the second electrode plate is electrically connected to the second light-emitting control transistor through the first connecting portion. The orthographic projection of the second electrode plate on the reference plane partially overlaps with the orthographic projection of the light-emitting control signal line on the reference plane.

[0026] Optionally, the first connecting part is disposed in the same layer as the first power signal line and the light emission control signal line, and is made of the same material;

[0027] Wherein, in a direction perpendicular to the extension direction of the light-emitting control signal line, the first connection portion is located on the side of the light-emitting control signal line away from the first power signal line.

[0028] According to a second aspect of this application, a display device is provided, including a display panel as described above.

[0029] In the display panel of this application embodiment, by placing the first node, which is electrically connected to the anode of the first light-emitting control transistor and the light-emitting element, between the first power signal line and the light-emitting control signal line, the first node can be made close to the middle area of ​​the pixel driving circuit. This reduces the difference in the length of the conduction path between the anode of the light-emitting element and the adjacent rows of pixel driving circuits in a mirror configuration. This reduces the potential difference of the light-emitting elements corresponding to the adjacent rows of pixel driving circuits in a mirror configuration, thereby reducing the brightness difference of the light-emitting elements corresponding to the adjacent rows of pixel driving circuits in a mirror configuration and improving the brightness uniformity of the display panel.

[0030] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0033] Figure 1 A top view of a display panel provided for an embodiment of this application;

[0034] Figure 2 A schematic diagram of a pixel driving circuit in a display panel provided for an embodiment of this application;

[0035] Figure 3 A stack-up diagram of pixel driving circuitry in a display panel provided for embodiments of this application;

[0036] Figure 4 A schematic diagram of the film layer structure of a display panel provided for an embodiment of this application;

[0037] Figure 5 A film diagram of the active layer provided for embodiments of this application;

[0038] Figure 6 A film layer diagram of the first gate layer provided for embodiments of this application;

[0039] Figure 7 A stack-up diagram of the active layer and the first gate layer in a display panel provided for embodiments of this application;

[0040] Figure 8 A film layer diagram of the second gate layer in a display panel provided for embodiments of this application;

[0041] Figure 9 A stack-up diagram of the active layer, the first gate layer, and the second gate layer in a display panel provided for embodiments of this application;

[0042] Figure 10 A film layer diagram of the first source / drain layer in a display panel provided for embodiments of this application;

[0043] Figure 11 A stack-up diagram of the active layer, first gate layer, second gate layer, and first source / drain layer in a display panel provided for embodiments of this application;

[0044] Figure 12 A film layer diagram of the second source / drain layer in a display panel provided for embodiments of this application;

[0045] Figure 13 A stack-up diagram of the active layer, first gate layer, second gate layer, first source-drain layer, and second source-drain layer in a display panel provided for embodiments of this application;

[0046] Figure 14 A film layer diagram of the anode layer in a display panel provided for embodiments of this application;

[0047] Figure 15A stack-up diagram of the active layer, first gate layer, second gate layer, first source-drain layer, second source-drain layer, and anode layer in a display panel provided for embodiments of this application;

[0048] Figure 16 A schematic diagram of a display device provided for an embodiment of this application. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0050] Embodiments of this application provide a display panel, which includes a light-emitting element, a first power signal line, a second power signal line, a light-emitting control signal line, a first scan line, and multiple pixel driving circuits. The multiple pixel driving circuits are arranged in an array to form multiple rows of pixel driving circuits and multiple columns of pixel driving circuits. One row of two adjacent rows of pixel driving circuits is mirrored with the other row. The pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a first reset transistor. The driving transistor and the light-emitting element are connected in series between the first power signal line and the second power signal line. The first light-emitting control transistor is connected in series between the driving transistor and the light-emitting element and is electrically connected to the anode of the light-emitting element at a first node. The first light-emitting control gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line. The first reset transistor is electrically connected to the first node and the first scan line. The orthographic projections of the first power signal line, the light-emitting control signal line, and the first scan line on the reference plane are arranged sequentially along the column direction from the driving transistor to the first reset transistor. The reference plane is parallel to the light-emitting surface of the display panel. The orthographic projection of the first node on the reference plane is located between the orthographic projections of the first power signal line and the light-emitting control signal line on the reference plane.

[0051] In the embodiments of this application, by placing the first node, which is electrically connected to the anode of the first light-emitting control transistor and the light-emitting element, between the first power signal line and the light-emitting control signal line, the first node can be made close to the middle area of ​​the pixel driving circuit. This reduces the difference in the length of the conduction path between the anode of the light-emitting element and the adjacent rows of pixel driving circuits in the mirror configuration. This reduces the potential difference of the light-emitting elements corresponding to the adjacent rows of pixel driving circuits in the mirror configuration, thereby reducing the brightness difference of the light-emitting elements corresponding to the adjacent rows of pixel driving circuits in the mirror configuration and improving the brightness uniformity of the display panel.

[0052] Please see Figure 1 and Figure 2 , Figure 1 A top view of a display panel provided for an embodiment of this application. Figure 2 This is a schematic diagram of the pixel driving circuit in a display panel provided in an embodiment of this application. The display panel 100 includes a display area AA and a border area NA, with the border area NA located around the display area AA. The display area AA is the area used to display an image. The display panel includes a light-emitting element EL, a first power signal line VDD, a second power signal line VSS, a light-emitting control signal line EM, a first scan line Scan1, and multiple pixel driving circuits PD located in the display area AA. The multiple pixel driving circuits PD are arranged in an array to form multiple rows of pixel driving circuits and multiple columns of pixel driving circuits, with one row of adjacent pixel driving circuits mirroring the other row.

[0053] It should be noted that the mirroring of two adjacent rows of pixel driving circuits means that the orthographic projection of the pattern of one row of pixel driving circuits onto the reference plane can be symmetrical about an imaginary axis of symmetry with the orthographic projection of the pattern of the other row of pixel driving circuits onto the reference plane. The patterns of the conductive structures connecting the two adjacent rows of pixel driving circuits do not need to be mirrored.

[0054] Combination Figure 2 As shown, the pixel driving circuit PD includes a driving transistor T1, a first light-emitting control transistor T6, and a first reset transistor T7. The driving transistor T1 is connected in series with the light-emitting element EL between the first power signal line VDD and the second power signal line VSS. The first light-emitting control transistor T6 is connected in series between the first power signal line VDD and the light-emitting element EL. The anodes of the first light-emitting control transistor T6 and the light-emitting element EL are electrically connected to the first node C, and the first light-emitting control gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM. The first reset transistor T7 is electrically connected to the first node C and the first scan line Scan1. It should be noted that the first node C refers to the portion where the first light-emitting control transistor T6 and the light-emitting element EL overlap.

[0055] Combination Figure 2 and Figure 3 As shown, Figure 3 The stack-up diagram of the pixel driving circuit in the display panel provided in the embodiments of this application shows that the orthographic projection of the first node C on the reference plane is located between the orthographic projections of the first power signal line VDD and the light emission control signal line EM on the reference plane, and the reference plane is parallel to the light emitting surface of the display panel.

[0056] In the embodiments of this application, by placing the first node C, which is electrically connected to the anode of the first light-emitting control transistor T6 and the light-emitting element EM, between the first power signal line VDD and the light-emitting control signal line EM, the first node C can be made close to the middle region of the pixel driving circuit PD. This reduces the difference in the length of the conduction path between the anode of the two adjacent rows of pixel driving circuits PD and the light-emitting element EL in a mirrored configuration. This reduces the potential difference of the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in a mirrored configuration, thereby reducing the brightness difference of the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in a mirrored configuration and improving the brightness uniformity of the display panel.

[0057] In some embodiments, such as Figure 2 As shown, the pixel driving circuit PD includes a driving transistor T1, a switching transistor T2, a compensation transistor T3, a second reset transistor T4, a second light-emitting control transistor T5, a first light-emitting control transistor T6, a first reset transistor T7, a third reset transistor T8, and a storage capacitor Cst.

[0058] like Figure 2As shown, the first electrode of driving transistor T1 is electrically connected to the second node A, the second electrode of driving transistor T1 is electrically connected to the third node B, and the driving gate of driving transistor T1 is electrically connected to the fourth node Q; the first electrode of switching transistor T2 is electrically connected to the data line Data, the second electrode of switching transistor T2 is electrically connected to the second node A, and the switching gate of switching transistor T2 is electrically connected to the second scan line Scan2; the first electrode of compensation transistor T3 is electrically connected to the fourth node Q, the second electrode of compensation transistor T3 is electrically connected to the third node B, and the compensation gate of compensation transistor T3 is electrically connected to the first scan signal line Scan2; the first electrode of the second reset transistor T4 is electrically connected to the second reset signal line VI2, the second electrode of the second reset transistor T4 is electrically connected to the fourth node Q, and the second reset gate of the second reset transistor T4 is electrically connected to the third scan line Scan3; the first electrode of the second light-emitting control transistor T5 is electrically connected to the first power supply signal line VDD, the second electrode of the second light-emitting control transistor T5 is electrically connected to the second node A, and the second electrode of the second light-emitting control transistor T5 is electrically connected to the fourth node Q. The gates of the two light-emitting control transistors are electrically connected to the light-emitting control signal line EM; the first electrode of the first light-emitting control transistor T6 is electrically connected to the third node B, the second electrode of the first light-emitting control transistor T6 is electrically connected to the first node C, and the first light-emitting control gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM; the first electrode of the first reset transistor T7 is electrically connected to the first reset signal line VI1, the second electrode of the first reset transistor T7 is electrically connected to the first node A, and the first reset gate of the first reset transistor T7 is electrically connected to the first scan line Scan1; the first electrode of the third reset transistor T8 is electrically connected to the third reset signal line VI3, the second electrode of the third reset transistor T8 is electrically connected to the second node A, and the third reset gate of the third reset transistor T8 is electrically connected to the first scan signal line Scan1; the first plate of the storage capacitor Cst is electrically connected to the first power supply signal line VDD, and the second plate of the storage capacitor Cst is electrically connected to the fourth node Q; the anode of the light-emitting device EL is electrically connected to the first node C, and the cathode of the light-emitting device EL is electrically connected to the second power supply signal line VSS.

[0059] In the embodiments of this application, the first power signal line VDD is used to provide a constant voltage high-level signal to the pixel driving circuit PD, and the second power signal line VSS is used to provide a constant voltage low-level signal to the pixel driving circuit PD.

[0060] It should be noted that in the embodiments of this application, the first electrode of the transistor is one of the source and the drain, and the second electrode is the other of the source and the drain. Furthermore, the first electrode and the second electrode of each transistor may be the same or different.

[0061] The following is about Figure 2 and Figure 3 The structure shown describes the film structure of the pixel driving circuit of this application.

[0062] In some embodiments, please refer to Figure 4 , Figure 4 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. The display panel 100 includes a substrate 11, an active layer 12 disposed on the substrate 11, a first gate insulating layer 13 disposed on the active layer 12, a first gate layer 14 disposed on the first gate insulating layer 13, a second gate insulating layer 15 disposed on the first gate insulating layer 14, a second gate layer 16 disposed on the second gate insulating layer 15, a first interlayer dielectric layer 17 disposed on the second gate layer 16, a first source / drain layer 18 disposed on the first interlayer dielectric layer 17, a second interlayer dielectric layer 19 disposed on the first source / drain layer 18, a second source / drain layer 20 disposed on the second interlayer dielectric layer 19, and a planarization layer 21 disposed on the second source / drain layer 20.

[0063] In some embodiments, please refer to Figure 4 The substrate 11 can be a single-layer substrate formed of organic or inorganic materials, or it can be a double-layer or multi-layer substrate formed of at least one of organic and inorganic materials. The organic material can be, but is not limited to, polyimide, and the inorganic material can be, but is not limited to, glass.

[0064] like Figure 4 As shown, the active layer 12 is disposed on the substrate 11. The material of the active layer 12 includes metal oxide semiconductor material or silicon semiconductor material. Specifically, the metal oxide semiconductor material can be indium gallium zinc oxide, and the silicon semiconductor material can be amorphous silicon or low-temperature polycrystalline silicon.

[0065] In embodiments of this application, the active layer 12 is made of low-temperature polycrystalline silicon.

[0066] like Figure 4 As shown, the first gate insulating layer 13, the second gate insulating layer 15, the first interlayer dielectric layer 17, and the second interlayer dielectric layer 19 are respectively disposed on the corresponding metal layer or active layer, so that the metal layers or active layers of different layers are separated and insulated. The first gate insulating layer 13, the second gate insulating layer 15, the first interlayer dielectric layer 17, and the second interlayer dielectric layer 19 can be a single-layer structure or a stacked structure formed of at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0067] like Figure 4As shown, the first gate layer 14, the second gate layer 16, the first source-drain layer 18, and the second source-drain layer 20 are respectively disposed on the corresponding insulating layer or interlayer dielectric layer. The first gate layer 14, the second gate layer 16, the first source-drain layer 18, and the second source-drain layer 20 can be a single-layer structure formed by at least one of copper, molybdenum, titanium, aluminum, silver, etc., or a stacked structure of two or more layers formed by at least two of the above-mentioned metal materials.

[0068] like Figure 4 As shown, the planarization layer 21 is disposed on the second source-drain layer 20. The material of the planarization layer 21 can be at least one inorganic insulating material selected from silicon nitride, silicon oxide, or silicon oxynitride, or it can be an organic insulating material with leveling properties.

[0069] like Figure 4 As shown, the display panel also includes a light-emitting device layer, which is disposed on the side of the planarization layer 21 away from the second source-drain layer 20. The light-emitting device layer includes an anode layer 22 disposed on the planarization layer 21, a pixel definition layer 23 disposed on the anode layer 22, a spacer layer 24 disposed on the pixel definition layer 23, a light-emitting material layer and a cathode layer (not shown in the figure) disposed on the pixel definition layer 23.

[0070] like Figure 5 As shown, Figure 5 The active layer diagram provided for the embodiments of this application includes an active layer 12 comprising a driving active portion T1A of a driving transistor T1, a switching active portion T2A of a switching transistor T2, a compensating active portion T3A of a compensating transistor T3, a second reset active portion T4A of a second reset transistor T4, a second light-emitting control active portion T5A of a second light-emitting control transistor T5, a first light-emitting control active portion T6A of a first light-emitting control transistor T6, a first reset active portion T7A of a first reset transistor T7, and a third reset active portion T8A of a third reset transistor T8.

[0071] like Figure 5 As shown, the driving active unit T1A, the switching active unit T2A, the compensation active unit T3A, the second reset active unit T4A, the first light emission control active unit T5A, the second light emission control active unit T6A, the first reset active unit T7A, and the third reset active unit T8A are connected to each other. The switching active unit T2A is elongated and extends along the column direction Y. The driving active unit T1A is disposed between the first light emission control active unit T5A and the second light emission control active unit T6A.

[0072] Combination Figure 4 and Figure 5As shown, one end of the first light-emitting active control unit T6A is electrically connected to the anode of the light-emitting element EL, and the orthographic projection of the first light-emitting active unit T6A on the reference plane is located between the orthographic projections of the first power supply signal line VDD and the light-emitting control signal line EM on the reference plane.

[0073] Combination Figure 4 and Figure 5 As shown, the first end of the first light-emitting control active part T6A and the first end of the first reset active part T7A are connected to the first node C, which is the part shown in the dashed box in the figure. By placing the orthographic projection of the first light-emitting control active part T6A on the reference plane between the orthographic projections of the first power signal line VDD and the light-emitting control signal line EM on the reference plane, the first node C can be closer to the middle area of ​​the pixel driving circuit PD. This reduces the potential difference between the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in a mirrored configuration, thereby reducing the brightness difference between the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in a mirrored configuration and improving the brightness uniformity of the display panel.

[0074] In some embodiments, the extension direction of the first light-emitting control active part T6A is parallel to the extension direction of the light-emitting control signal line EM.

[0075] Combination Figure 4 and Figure 5 As shown, the first light-emitting control active part T6A and the light-emitting control signal line EM both extend along the row direction X. By setting the first light-emitting control active part T6A horizontally, the first node C can be closer to the middle area of ​​the pixel driving circuit. This can further reduce the potential difference between the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in the mirrored arrangement, thereby reducing the brightness difference between the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in the mirrored arrangement and improving the brightness uniformity of the display panel.

[0076] In some embodiments, combined with Figure 4 and Figure 5 As shown, the driving active part T1A is L-shaped. The driving active part T1A includes a first sub-part T1A1 and a second sub-part T1A2 with different extending directions. The first sub-part T1A1 extends along the column direction Y, and the second sub-part T1A2 extends along the row direction X.

[0077] Combination Figure 4 and Figure 5As shown, along the direction perpendicular to the extension direction of the light-emitting control signal line EM (i.e., column direction Y), the first sub-part T1A1 partially overlaps with the first light-emitting control active part T6A; along the extension direction of the light-emitting control signal line (i.e., row direction X), the second sub-part T1A2 partially overlaps with the first light-emitting control active part T6A. By setting the driving active part T1A in an "L" shape formed by the first sub-part T1A1 and the second sub-part T1A2, the space enclosed by the first sub-part T1A1 and the second sub-part T1A2 is used to place the first light-emitting control active part T6A, thereby reducing the distance between the driving active part T1A and the first light-emitting control active part T6A in the column direction Y, so that the first node C is closer to the middle area of ​​the pixel driving circuit. This further reduces the potential difference of the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in the mirror arrangement, thereby reducing the brightness difference of the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in the mirror arrangement, and improving the brightness uniformity of the display panel.

[0078] like Figure 6 As shown, Figure 6 The first gate layer 14 provided in the embodiments of this application includes a driving gate T1G of driving transistor T1, a switching gate T2G of switching transistor T2, a compensation gate T3G of compensation transistor T3, a second reset gate T4G of second reset transistor T4, a second light-emitting control gate T5G of second light-emitting control transistor T5, a first light-emitting control gate T6G of first light-emitting control transistor T6, a first reset gate T7G of first reset transistor T7, a third reset gate T8G of third reset transistor T8, and a first plate Cst1 of storage capacitor Cst.

[0079] Combination Figures 4 to 7 As shown, Figure 7 The stack-up diagram of the active layer and the first gate layer in the display panel provided in the embodiments of this application shows that the driving gate T1G includes a first main body T1G1 and an extension T1G2. The extension T1G2 extends from the side of the first main body T1G1 near the first light-emitting control gate T6G along the row direction X. The orthographic projection of the first main body T1G1 on the reference plane overlaps with the orthographic projection of the first sub-part T1A1 on the reference plane, and the orthographic projection of the extension T1G2 on the reference plane overlaps with the orthographic projection of the second sub-part T1A2 on the reference plane. The driving gate T1G can be reused as the first plate Cst1 of the storage capacitor Cst.

[0080] Combination Figures 4 to 7As shown, the first light-emitting control gate T6G extends perpendicularly to the extension direction of the light-emitting control signal line EM. The first light-emitting control gate T6G is elongated and extends along the column direction Y. The orthographic projection of the first light-emitting control gate T6G on the reference plane partially overlaps with the orthographic projection of the first light-emitting control active part T6A on the reference plane. The second light-emitting control gate T5G extends along the row direction X. The orthographic projection of the second light-emitting control gate T5G on the reference plane partially overlaps with the orthographic projection of the second light-emitting control active part T5A on the reference plane. The first light-emitting control gate T6G and the second light-emitting control gate TG5 are connected to simultaneously receive the light-emitting control signal transmitted by the light-emitting control signal line EM.

[0081] like Figure 8 As shown, Figure 8 The image shows a film layer diagram of the second gate layer in a display panel provided in an embodiment of this application. The second gate layer 16 includes a second electrode Cst2 of a storage capacitor Cst, a first reset signal line VI1, and the first four signal lines VI1 extend along the row direction X.

[0082] Combination Figure 8 and Figure 9 As shown, Figure 9 The stack-up diagram of the active layer, the first gate layer and the second gate layer in the display panel provided in the embodiments of this application shows that the second electrode Cst and the first electrode Cst1 are partially overlapped on the orthogonal projection on the reference plane to form the storage capacitor Cst.

[0083] In some embodiments, in conjunction with the figures Figures 4 to 9 As shown, the light-emitting control signal line EM and the first light-emitting control gate T6G are disposed in different layers. By disposing the light-emitting control signal line EM and the first light-emitting control gate T6G in different film layers, the metal pattern of the first gate layer 14 can be prevented from obscuring the portion of the active layer 12 that connects the first light-emitting control active portion T6A and the first reset active portion T7A, ensuring that the portion connecting the first light-emitting control active portion T6A and the first reset active portion T7A can be conductive.

[0084] In some embodiments, the light emission control signal line EM and the first power supply signal line VDD are disposed on the same layer. By placing the light emission control signal line EM on the same film layer as the first power supply signal line VDD, it is possible to ensure that the portion connecting the first light emission control active part T6A and the first reset active part T7A can be conductive without adding other film layer structures.

[0085] In some embodiments, the display panel includes a first connection portion 181, and a second electrode plate C12 is electrically connected to a second light-emitting control transistor T5 through the first connection portion 181. The orthographic projection of the second electrode plate C12 on the reference plane partially overlaps with the orthographic projection of the light-emitting control signal line EM on the reference plane. By adding the first connection portion 181, the second electrode plate C12 is bridged to one end of the second light-emitting control active portion T5A of the second light-emitting control transistor T5. This not only allows the first power signal received by the second electrode plate C12 to be transmitted to the second light-emitting control transistor T5, but also avoids short-circuiting between the first power signal line VDD and the light-emitting control signal line EM.

[0086] In some embodiments, the first connection portion 181 is disposed on the same layer as the first power signal line VDD and the light emission control signal line EM, and is made of the same material. The first connection portion 181 is located on the side of the light emission control signal line EM away from the first power signal line VDD, perpendicular to the extension direction of the light emission control signal line EM. By using the film layer containing the first power signal line VDD to place the first connection portion 181, and placing the first connection portion 181 on the side of the light emission control signal line EM away from the first power signal line VDD, sufficient space can be reserved between the light emission control signal line EM and the first power signal line VDD for placing the first light emission control transistor T6. This allows the first node C to be close to the middle region of the pixel driving circuit PD without short-circuiting the first power signal line VDD and the light emission control signal line EM. This reduces the difference in the conduction path length between the anodes of the two adjacent rows of mirrored pixel driving circuits PD and the light emission element EL, thereby reducing the potential difference of the light emission elements corresponding to the two adjacent rows of mirrored pixel driving circuits, and thus reducing the brightness difference of the light emission elements corresponding to the two adjacent rows of mirrored pixel driving circuits, improving the brightness uniformity of the display panel.

[0087] like Figure 10 As shown, Figure 10 The first source-drain layer in the display panel provided in the embodiment of this application is a film layer diagram. The first source-drain layer 18 includes a second reset signal line VI2, a third scan line Scan3, a second scan line Scan2, a first power signal line VDD, a light emission control signal line EM, a first reset signal line VI1, and a first connection portion 181. The second reset signal line VI2, the third scan line Scan3, the second scan line Scan2, the first power signal line VDD, the light emission control signal line EM, and the first reset signal line VI1 are arranged sequentially at intervals along the column direction Y from the driving transistor T1 to the first reset transistor T7, and extend along the row direction X.

[0088] like Figure 11 As shown, Figure 11The stack-up diagram of the active layer, first gate layer, second gate layer and first source-drain layer in the display panel provided in the embodiments of this application shows that the third scan line Scan3 of the first source-drain layer 18 extends in the same direction as the third scan line Scan3 of the first gate layer 14, and overlaps in the orthographic projection portion on the reference plane.

[0089] Combination Figure 10 and Figure 11 As shown, the second electrode C12 is electrically connected to the first terminal of the second light-emitting control active part T5A of the second light-emitting control transistor T5 via the first connection part 181, so as to transmit the first power supply signal to the second light-emitting control transistor T5. The orthographic projection of the second electrode C12 on the reference plane partially overlaps with the orthographic projection of the light-emitting control signal line EM on the reference plane.

[0090] like Figure 12 and Figure 13 As shown, Figure 12 A film layer diagram of the second source / drain layer in a display panel provided for embodiments of this application. Figure 13 The stack-up diagram of the active layer, first gate layer, second gate layer, first source-drain layer and second source-drain layer in the display panel provided in the embodiments of this application is shown. The second source-drain layer includes a data line Data and a second power signal line VSS. The data line Data and the second power signal line VSS extend along the column direction Y and are spaced apart along the row direction X.

[0091] like Figure 14 and Figure 15 As shown, Figure 14 A film layer diagram of the anode layer in a display panel provided for embodiments of this application. Figure 15 The stack-up diagram of the active layer, first gate layer, second gate layer, first source-drain layer, second source-drain layer, and anode layer in the display panel provided for embodiments of this application is shown. The anode layer 22 includes multiple patterned anodes, including a first anode 221, a second anode 222, and a third anode 223. The first anode 221, the second anode 222, and the third anode 223 correspond to light-emitting elements of different colors. The light-emitting elements EL include red, green, and blue light-emitting elements. The red light-emitting element includes the first anode 221, the green light-emitting element includes the second anode 222, and the blue light-emitting element includes the third anode 223. It should be noted that, since the luminous efficiency and luminous lifetime of the blue light-emitting element are relatively low, by making the area of ​​the third anode 223 larger than the areas of the first anode 221 and the second anode 222, and by making the area of ​​the light-emitting layer of the blue light-emitting device larger than the areas of the light-emitting layers of the red and green light-emitting elements, the lifetime and luminous efficiency of the blue light-emitting element can be increased.

[0092] like Figure 14 and Figure 15 As shown, the first anode 221 and the second anode 222 are arranged side by side with intervals, and the third anode 223 is disposed on one side of the first anode 221 and the second anode 222 along the column direction Y. The first anode 221, the second anode 222 and the third anode 223 are electrically connected to three adjacent pixel driving circuits in the same row of pixel driving circuits.

[0093] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a display device. Please refer to [link to relevant documentation]. Figure 16 , Figure 16 This is a schematic diagram of a display device provided in an embodiment of this application. The display device 1000 includes a display panel 100 and a housing 200, with the display panel 100 disposed on the housing 200. The display panel 100 can be any of the display panels provided in the above embodiments. The display device provided in the embodiments of this application can achieve the same technical effects as the display panels provided in any of the above embodiments, and will not be described in detail here.

[0094] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel and a display device. The display panel includes a light-emitting element, a first power signal line, a second power signal line, a light-emitting control signal line, a first scan line, and a plurality of pixel driving circuits. Adjacent rows of pixel driving circuits are mirrored. The pixel driving circuit includes a driving transistor and a first light-emitting control transistor. By placing a first node electrically connected to the anode of the light-emitting element by the first light-emitting control transistor between the first power signal line and the light-emitting control signal line, the first node can be made close to the middle area of ​​the pixel driving circuit. This reduces the difference in the length of the conduction path between the mirrored adjacent rows of pixel driving circuits and the anode of the light-emitting element. This reduces the potential difference of the light-emitting elements corresponding to the mirrored adjacent rows of pixel driving circuits, thereby reducing the brightness difference of the light-emitting elements corresponding to the mirrored adjacent rows of pixel driving circuits and improving the brightness uniformity of the display panel.

[0095] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0096] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0097] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0098] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized by, The system includes a light-emitting element, a first power signal line, a second power signal line, a light-emitting control signal line, a first scan line, and multiple pixel driving circuits. These pixel driving circuits are arranged in an array to form multiple rows and multiple columns of pixel driving circuits. Adjacent rows of pixel driving circuits are mirrored. Each pixel driving circuit includes: A driving transistor is connected in series with the light-emitting element between the first power signal line and the second power signal line; A first light-emitting control transistor is connected in series between the driving transistor and the light-emitting element, and is electrically connected to the anode of the light-emitting element at a first node. The first light-emitting control gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line. The first reset transistor is electrically connected to the first node and the first scan line. The orthographic projections of the first power signal line, the light emission control signal line, and the first scan line on the reference plane are arranged sequentially along the column direction from the driving transistor to the first reset transistor. The reference plane is parallel to the light-emitting surface of the display panel. Wherein, the orthographic projection of the first node on the reference plane is located between the orthographic projections of the first power signal line and the light emission control signal line on the reference plane.

2. The display panel of claim 1, wherein, The first light-emitting control transistor includes a first light-emitting control active part, one end of which is electrically connected to the anode of the light-emitting element; Wherein, the orthographic projection of the first light-emitting control active part on the reference plane is located between the orthographic projections of the first power signal line and the light-emitting control signal line on the reference plane.

3. The display panel of claim 2, wherein, The extension direction of the first light-emitting control active part is parallel to the extension direction of the light-emitting control signal line, and the extension direction of the first light-emitting control gate is perpendicular to the extension direction of the light-emitting control signal line.

4. The display panel of claim 2, wherein, The driving transistor includes a driving active portion, which includes a first sub-part and a second sub-part with different extending directions. Wherein, in a direction perpendicular to the extension direction of the light-emitting control signal line, the first sub-part overlaps with the first light-emitting control active part; and in a direction along the extension direction of the light-emitting control signal line, the second sub-part overlaps with the first light-emitting control active part.

5. The display panel of any one of claims 1 to 4, wherein, The light emission control signal line is disposed on a different layer from the first light emission control gate.

6. The display panel of claim 5, wherein, The light emission control signal line is arranged on the same layer as the first power supply signal line.

7. The display panel of claim 5, wherein, The display panel includes: The first active layer includes the first light-emitting control active part; A first gate layer is disposed on the first active layer and includes the first light-emitting control gate; A first source-drain layer is disposed on the first gate layer and includes the light emission control signal line and the first power supply signal line.

8. The display panel of any one of claims 1 to 4, wherein, The pixel driving circuit includes a storage capacitor and a second light-emitting control transistor, and the display panel includes: The first gate layer includes the first electrode of the storage capacitor; The second gate layer includes the second electrode of the storage capacitor; The display panel further includes a first connecting portion, and the second electrode plate is electrically connected to the second light-emitting control transistor through the first connecting portion. The orthographic projection of the second electrode plate on the reference plane partially overlaps with the orthographic projection of the light-emitting control signal line on the reference plane.

9. The display panel as described in claim 8, characterized in that, The first connecting part is disposed in the same layer as the first power signal line and the light emission control signal line, and is made of the same material; Wherein, in a direction perpendicular to the extension direction of the light-emitting control signal line, the first connection portion is located on the side of the light-emitting control signal line away from the first power signal line.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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