Display drive circuit and display device

Abstract

The application discloses a display driving circuit and a display device. The display driving circuit comprises a scan control module and an output module. The scan control module comprises forward control units, reverse control units and first control nodes which are symmetrically arranged. The forward control units comprise first transistors and first leakage protection modules, and the reverse control units comprise second transistors and second leakage protection modules. The forward control units and the reverse control units are used for realizing forward and reverse scanning functions of the scan control module according to signals input into control ends of the transistors, and outputting first control signals to the output module through the first control nodes. The output module is used for performing pull-up control and / or pull-down control according to the first control signals, so as to output driving signals. Therefore, the technical scheme of the application optimizes the display driving circuit, can avoid or reduce leakage current, and thus ensures the output stability of the driving signals.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display driving circuit and display device. Background Technology

[0002] After long-term operation, the threshold voltage drift of the thin-film transistor in the existing GOA circuit is prone to leakage, which in turn leads to the malfunction of the GOA circuit. Figure 1 This is a schematic diagram of the pull-up control circuit in an existing display driver circuit. (See also...) Figure 1 In the pull-up and bootstrap phases of the GOA circuit, when the scan control node Qn' in each display driver circuit is at a high potential, several leakage paths may exist. For example, in forward scan mode, the leakage path is between thin-film transistor t2 and thin-film transistor t12; in reverse scan mode, the leakage path is between thin-film transistor t1 and the sixth thin-film transistor t12. This causes the potential of the scan control node Qn' to decrease during the pull-up phase, resulting in insufficient opening of the thin-film transistors in the output circuit controlled by the signal output from the scan control node Qn'. Consequently, the time required for voltage changes at the signal output terminal of the output circuit (e.g., voltage dropping from 90% to 10%) increases, potentially leading to incorrect charging or insufficient charging, which severely affects the output stability of the gate drive signal. Therefore, how to optimize the display driver circuit to avoid leakage or reduce leakage current is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0003] The purpose of this application is to provide a display driving circuit and a display device that can optimize the display driving circuit to avoid leakage or reduce leakage current.

[0004] This application provides a display driving circuit, including: a scanning control module and an output module; the scanning control module includes a symmetrically arranged forward control unit, a reverse control unit, and a first control node; wherein, the forward control unit includes a first transistor and a first leakage protection module, the first path terminal of the first transistor is used to receive a forward scanning voltage, the second path terminal of the first transistor is connected to the first control node, and the first leakage protection module is connected to the first path terminal of the first transistor and / or the first control node; wherein, the reverse control unit includes a second transistor and a second leakage protection module, the first path terminal of the second transistor is used to receive a reverse scanning voltage, the second path terminal of the second transistor is connected to the first control node, and the second leakage protection module is connected to the first path terminal of the second transistor and / or the first control node; the forward control unit and the reverse control unit are used to enable the scanning control module to perform forward and reverse scanning functions according to the signals input to the control terminals of each transistor, and output a first control signal to the output module through the first control node; the output module is used to perform pull-up control and / or pull-down control according to the first control signal to output a driving signal.

[0005] In one embodiment, the output module includes a level maintenance unit; the level maintenance unit includes an inverter and a second control node; the inverter is used to perform level maintenance control according to a first control signal during the non-display phase to output a second control signal through the second control node, so that the drive signal output by the output module is maintained at a low level or a high level; and / or, the output module includes a first level control unit; the first level control unit is used to perform either pull-up control or pull-down control according to the second control signal output by the level maintenance unit, so that the output module outputs a drive signal representing either a low level or a high level; and / or, the output module includes a stage transmission unit; the stage transmission unit includes a third transistor, the control terminal of the third transistor is connected to the first control node to receive the first control signal, the first path terminal of the third transistor receives a first clock control signal, and the second path terminal of the third transistor outputs the stage transmission signal.

[0006] In one embodiment, the output module includes at least two first-level control units; the output module further includes a second-level control unit, a first output node, a third-level control unit, a second output node, and an isolation unit; the isolation unit is used to isolate the control signals of the second-level control unit and the third-level control unit; when one of the at least two first-level control units is used to perform either pull-up control or pull-down control, it outputs a first driving signal representing either a low level or a high level to the first output node; when the second-level control unit is used to perform either pull-up control or pull-down control, it outputs a first driving signal representing either a low level or a high level to the first output node; when the other of the at least two first-level control units is used to perform either pull-up control or pull-down control, it outputs a second driving signal representing either a low level or a high level to the second output node; when the third-level control unit is used to perform either pull-up control or pull-down control, it outputs a second driving signal representing either a low level or a high level to the second output node; wherein, the first driving signal and the second driving signal are respectively used to drive the horizontal scan lines of two adjacent levels in the display panel.

[0007] In one embodiment, the output module further includes a fourth level control unit, which is connected to the first control node and the second control node, and is used to adjust the level of the first control signal output by the first control node according to the second control signal output by the level maintenance unit.

[0008] In one embodiment, the first leakage protection module includes a fourth transistor and a fifth transistor. The control terminal of the fourth transistor receives a second clock control signal, and the first path terminal of the first transistor receives a forward scanning voltage through a path formed with the fourth transistor. The control terminal of the fifth transistor is connected to a first control node, the first path terminal of the fifth transistor receives a first reference voltage, and the second path terminal of the fifth transistor is connected to a path between the first transistor and the fourth transistor. And / or, the second leakage protection module includes a sixth transistor and a seventh transistor. The control terminal of the sixth transistor receives a second clock control signal, and the first path terminal of the second transistor receives a reverse scanning voltage through a path formed with the sixth transistor. The control terminal of the seventh transistor is connected to the first control node, the first path terminal of the seventh transistor receives a first reference voltage, and the second path terminal of the seventh transistor is connected to a path between the second transistor and the sixth transistor. And / or, the inverter includes a single-stage inverter and a source follower cascaded therewith, and the level maintenance unit further includes a second control transistor. The system comprises two control nodes; wherein a single-stage inverter includes an eighth transistor and a ninth transistor, the control terminal of the eighth transistor receives a first reference voltage or is connected to a first control node, the first path terminal of the eighth transistor receives the first reference voltage, the second path terminal of the eighth transistor is connected to the first path terminal of the ninth transistor, the second path terminal of the ninth transistor receives a second reference voltage, and the control terminal of the ninth transistor is connected to the first control node; wherein a source follower includes a tenth transistor and an eleventh transistor, the control terminal of the tenth transistor is connected to the second path terminal of the eighth transistor, the first path terminal of the tenth transistor receives the first reference voltage, the second path terminal of the tenth transistor is connected to a second control node, the control terminal of the eleventh transistor is connected to the first control node, the first path terminal of the eleventh transistor is connected to the second control node, and the second path terminal of the eleventh transistor receives a second reference voltage; wherein the first reference voltage is one of a reference high voltage and a reference low voltage, and the second reference voltage is the other of a reference high voltage and a reference low voltage.

[0009] In one embodiment, the fourth level control unit includes a twelfth transistor and a third leakage protection module; the control terminal of the twelfth transistor is connected to the second control node of the level maintenance unit to receive a second control signal, the first path terminal of the twelfth transistor is connected to the first control node, and the second path terminal of the twelfth transistor is used to receive a second reference voltage; the third leakage protection module includes a thirteenth transistor and a fourteenth transistor, the control terminal of the thirteenth transistor receives a second clock control signal, and the second path terminal of the twelfth transistor receives the second reference voltage through a path formed with the thirteenth transistor, the control terminal of the fourteenth transistor is connected to the first control node, the first path terminal of the fourteenth transistor receives a first reference voltage, and the second path terminal of the fourteenth transistor is connected to the path between the twelfth and thirteenth transistors.

[0010] In one embodiment, the second-level control unit includes a fifteenth transistor, a first capacitor, and a first output node. The control terminal of the fifteenth transistor is connected to the first control node, and the control terminal of the fifteenth transistor is also connected to the first output node through the first capacitor. The first path terminal of the fifteenth transistor receives a first clock control signal, and the second path terminal of the fifteenth transistor is connected to the first output node. The first-level control unit connected to the first output node includes an eighteenth transistor. The control terminal of the eighteenth transistor is connected to the second control node to receive a second control signal. The first path terminal of the eighteenth transistor is connected to the first output node, and the second path terminal of the eighteenth transistor receives a second reference voltage. The third-level control unit includes a sixteenth transistor, a second capacitor, and a second output node. The control terminal of the sixteenth transistor is connected to the second output node through the second capacitor. The output node has a first path terminal of the sixteenth transistor receiving a third clock control signal, and a second path terminal of the sixteenth transistor connected to the second output node. A first level control unit connected to the second output node includes a nineteenth transistor, whose control terminal is connected to the second control node to receive a second control signal. The first path terminal of the nineteenth transistor is connected to the second output node, and the second path terminal of the nineteenth transistor receives a second reference voltage. The isolation unit includes a seventeenth transistor, whose control terminal receives a first reference voltage. The first path terminal of the seventeenth transistor is connected to the control terminal of the fifteenth transistor, and the second path terminal of the seventeenth transistor is connected to the control terminal of the sixteenth transistor. The capacitance value of the first capacitor is greater than 0 and less than or equal to 500 fF, and the capacitance value of the second capacitor is greater than 0 and less than or equal to 300 fF.

[0011] In one embodiment, the display driving circuit uses an eight-phase clock to provide each clock control signal; and / or, in the eight-phase clock, the k-th clock is advanced by T / 8 compared to the (k+1)-th clock, where 1≤k<8; and / or, the duty cycle of the high level in each clock control signal is T / 4; and / or, the phase difference between the first driving signal and the second driving signal is T / 8.

[0012] This application also provides a display device, including a display panel and at least one display driving circuit as described above, wherein each display driving circuit is electrically connected to the display panel to output a driving signal to drive the horizontal scan lines in the display panel.

[0013] In one embodiment, multiple display driving circuits are connected in a multi-stage cascade manner, and the multiple display driving circuits are used to drive all or part of the pixel rows in the display panel; each display driving circuit is used to generate a first driving signal and a second driving signal to drive two pixel rows; wherein the phase difference of the driving signals of adjacent pixel rows in the display panel is T / 8.

[0014] This application provides a display driving circuit and a display device. The display driving circuit incorporates leakage protection modules at key locations in the forward and reverse control units to form a symmetrical low-leakage structure. This effectively prevents or reduces leakage during the pull-up or pull-down control of the first control node's potential, thereby improving forward and reverse scanning functionality. This ensures the first control node's potential conforms to the expected design at each stage, allowing the thin-film transistors in the output module, controlled by the first control signal output from the first control node, to fully open. This ensures the voltage change time of the output driving signal from the output module meets the expected design, avoiding incorrect charging or insufficient charging, and thus ensuring the output stability of the driving signal. Therefore, the technical solution of this application optimizes the display driving circuit, preventing or reducing leakage current, thereby ensuring the output stability of the driving signal. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0016] Figure 1 This is a schematic diagram of the pull-up control circuit in an existing display driver circuit.

[0017] Figure 2 This is a schematic diagram of the display driving circuit provided in the first embodiment of this application.

[0018] Figure 3 This is a schematic diagram of the structural framework of the display driving circuit provided in the second embodiment of this application.

[0019] Figure 4 This is a schematic diagram of the structure of a display driver circuit provided in some current implementation methods.

[0020] Figure 5 This is a timing diagram of the display driver circuit provided in some current implementation methods.

[0021] Figure 6 This is a schematic diagram of the display driving circuit as exemplified in an embodiment of this application.

[0022] Figure 7 This is a schematic diagram of the display driving circuit of Example 1 of this application.

[0023] Figure 8 This is a timing diagram of the display driver circuit of Example 1 of this application.

[0024] Figure 9 This is a schematic diagram of the package of the display driver circuit of Example 1 of this application.

[0025] Figure 10This is a schematic diagram of the cascaded multiple display driver circuits provided in this application.

[0026] Figure 11 A schematic diagram of the cascaded structure of the middle 5 stages of the GOA circuit.

[0027] Figure 12 This is a schematic diagram of the display driving circuit of Example 2 of this application.

[0028] Figure 13 This is a timing diagram of the display driver circuit of Example 2 of this application.

[0029] Figure 14 This is a schematic diagram of the display driving circuit of Example 3 of this application.

[0030] Figure 15 This is a schematic diagram of the display driving circuit of Example 4 of this application.

[0031] Figure 16 This is a schematic diagram of the display driving circuit of Example 5 of this application. Detailed Implementation

[0032] First Embodiment

[0033] Figure 2 This is a schematic diagram of the display driving circuit provided in the first embodiment of this application. See also... Figure 2This is a schematic diagram of the display driving circuit provided in the first embodiment of this application. The display driving circuit provided in this embodiment includes a scan control module 101 and an output module 100. The scan control module 101 includes a symmetrically arranged forward control unit 1011, a reverse control unit 1012, and a first control node Q1n. The forward control unit 1011 includes a first transistor T1 and a first leakage protection module M1. The first terminal of the first transistor T1 is used to receive the forward scan voltage VBD, and the second terminal of the first transistor T1 is connected to the first control node Q1n. The first leakage protection module M1 is connected to the first terminal of the first transistor T1 and / or the first control node Q1n. The reverse control unit 1012 includes a second transistor T2 and a second leakage protection module M2. The first terminal of the second transistor T2 is used to receive the reverse scan voltage VFD, and the second terminal of the second transistor T2 is connected to the first control node Q1n. The second leakage protection module M2 is connected to the first terminal of the second transistor T2 and / or the first control node Q1n. The forward control unit 1011 and the reverse control unit 1012 are used to enable the scanning control module 101 to perform forward and reverse scanning functions based on the signals from the control terminals of each input transistor, and to output a first control signal to the output module 100 through the first control node Q1n. The output module 100 is used to perform pull-up control and / or pull-down control based on the first control signal to output a drive signal.

[0034] In one embodiment, the first leakage protection module M1 and the second leakage protection module M2 can be individual components for implementing leakage protection, or they can be a combination of multiple components to achieve leakage protection. For example, a high threshold transistor with an inverted width-to-length ratio is specifically selected in the leakage protection module to reduce the impact of leakage by utilizing the low leakage characteristics of the device. As another example, the leakage protection module includes two transistors. The control terminal of one of the two transistors receives a second clock control signal, and the first path terminal of either the first transistor T1 or the second transistor T2 receives a scan voltage through a path formed with one of the two transistors. The control terminal of the other transistor is connected to a first control node Q1n, the first path terminal of the other transistor receives a reference high voltage, and the second path terminal of the other transistor is connected to the path between the first transistor T1 and one of the two transistors.

[0035] The technical solution of this embodiment optimizes the display driving circuit, which can avoid or reduce leakage current, thereby ensuring the output stability of the driving signal. Furthermore, under low temperature and electrical bias stress conditions, the threshold voltage of the thin-film transistor is easily forward biased, leading to an increase in the off-state leakage current. This causes the potential of the first control node Q1n to further decrease during the pull-up phase, resulting in less complete opening of the thin-film transistor controlled by the first control signal output from the first control node Q1n in the output module 100. The voltage change of the output driving signal of the output module 100 (e.g., voltage dropping from 90% to 10%) takes longer, making it more prone to incorrect charging or insufficient charging, which may seriously affect the output stability of the driving signal. Therefore, in the technical solution of this embodiment, the display driving circuit sets leakage protection modules at key locations in the forward control unit 1011 and the reverse control unit 1012, which can also avoid or improve the above problems, thereby achieving normal startup at low temperatures.

[0036] Second Embodiment

[0037] Figure 3 This is a schematic diagram of the structural framework of the display driving circuit provided in the second embodiment of this application. See also... Figure 3 This is a schematic diagram of the structural framework of the display driving circuit provided in the second embodiment of this application. The display driving circuit provided in this embodiment includes a scan control module 101 and an output module 100. The scan control module 101 includes a symmetrically arranged forward control unit 1011, a reverse control unit 1012, and a first control node Q1n. The forward control unit 1011 includes a first transistor T1 and a first leakage protection module M1. The first terminal of the first transistor T1 is used to receive the forward scan voltage VBD, and the second terminal of the first transistor T1 is connected to the first control node Q1n. The first leakage protection module M1 is connected to the first terminal of the first transistor T1 and / or the first control node Q1n. The reverse control unit 1012 includes a second transistor T2 and a second leakage protection module M2. The first terminal of the second transistor T2 is used to receive the reverse scan voltage VFD, and the second terminal of the second transistor T2 is connected to the first control node Q1n. The second leakage protection module M2 is connected to the first terminal of the second transistor T2 and / or the first control node Q1n. The forward control unit 1011 and the reverse control unit 1012 are used to enable the scanning control module 101 to perform forward and reverse scanning functions based on the signals from the control terminals of each input transistor, and to output a first control signal to the output module 100 through the first control node Q1n. The output module 100 is used to perform pull-up control and / or pull-down control based on the first control signal to output a drive signal.

[0038] In one embodiment, the output module 100 may include a level maintenance unit 102; the level maintenance unit 102 includes an inverter and a second control node Q2n; the inverter is used to perform level maintenance control according to the first control signal during the non-display stage to output a second control signal through the second control node Q2n, so that the drive signal output by the output module 100 is kept in a low level state or a high level state.

[0039] In one embodiment, when the transistor in the level maintenance unit 102 is N-type, it is a pull-down maintenance unit; when the transistor in the level maintenance unit 102 is P-type, it is a pull-up maintenance unit.

[0040] In one embodiment, the inverter may include a cascaded single-stage inverter and a source follower. The technical solution of this embodiment, through the inverter in the output module 100, can enhance the level maintenance capability during non-display stages (e.g., enhance pull-down maintenance capability or enhance pull-up maintenance capability), and can suppress the multi-gate problem caused by clock feedthrough.

[0041] In one embodiment, the output module 100 further includes a first level control unit 103; the first level control unit 103 is used to perform either pull-up control or pull-down control according to the second control signal output by the level maintenance unit 102, so that the output module 100 outputs a drive signal representing either a low level or a high level.

[0042] In one embodiment, when the first level control unit 103 is a single-type NMOS / PMOS circuit, it can use a second control signal for either pull-up control or pull-down control. Optionally, when the first level control unit 103 is a CMOS type circuit, it can directly use the first control signal output by the first control node Q1n for pull-up control and pull-down control.

[0043] In one embodiment, the output module 100 includes at least two first level control units 103; the output module 100 also includes a second level control unit 104, a first output node, a third level control unit 105, a second output node, and an isolation unit 106; the isolation unit 106 is used to isolate the control signals of the second level control unit 104 and the third level control unit 105; one of the at least two first level control units 103, when performing either pull-up control or pull-down control, outputs a first drive signal representing either a low level or a high level to the first output node; the second level control unit 104 is used to perform pull-up control and pull-down control... When one of the two pull-up controls is used to perform pull-up control and pull-down control, a first drive signal representing the other of low level and high level is output to the first output node; when another of the at least two first level control units 103 is used to perform pull-up control and pull-down control, a second drive signal representing the other of low level and high level is output to the second output node; when the third level control unit 105 is used to perform pull-up control and pull-down control, a second drive signal representing the other of low level and high level is output to the second output node; wherein, the first drive signal and the second drive signal are respectively used to drive the horizontal scan lines of two adjacent levels in the display panel.

[0044] Thus, the technical solution of this embodiment allows each display driver circuit in the GOA circuit to reuse a portion of functional modules and / or its control nodes (e.g., scan control module 101, first control node Q1n, level maintenance unit 102 in output module 100, etc.) and output two drive signals to drive the horizontal scan lines of two adjacent levels in the display panel respectively. In this embodiment, by isolating the control signals of the second level control unit 104 and the third level control unit 105 through the isolation unit 106, the second level control unit 104 and the third level control unit 105 can output two drive signals without bootstrapping loss. Therefore, the technical solution of this embodiment not only improves the circuit efficiency of the display driver circuit, but also enables the display device equipped with the display driver circuit of this embodiment to achieve a narrow bezel design.

[0045] In one embodiment, the output module 100 further includes a fourth level control unit 108, which is connected to the first control node Q1n and the second control node Q2n, and is used to adjust the level of the first control signal output by the first control node Q1n according to the second control signal output by the level maintenance unit 102.

[0046] The technical solution of this embodiment, through the fourth level control unit 108, helps to maintain the level of the first control signal in both high and low states, reducing the impact of the intermediate state caused by leakage on the signal.

[0047] In one embodiment, the output module 100 further includes a transmission unit 107; the transmission unit 107 includes a third transistor, the control terminal of the third transistor is connected to the first control node Q1n to receive a first control signal, the first path terminal of the third transistor receives a first clock control signal, and the second path terminal of the third transistor outputs a transmission signal.

[0048] Thus, in this embodiment, the display driving circuit can reduce the pressure on its driving node load through the cascading unit 107, and improve its low-temperature cascading capability. The second level signal control unit 104 and the third level control unit 105 are responsible for charging and discharging the internal circuits of the pixels in the display panel, while the cascading unit 107 is responsible for charging and discharging the signal cascading process within the GOA circuit. Even under conditions of low temperature and positive threshold voltage drift, the GOA circuit can still drive the corresponding load. Therefore, this embodiment improves the low-temperature cascading capability.

[0049] Based on the technical concept of the above technical solution, the following example of a circuit structure is provided to illustrate the above technical solution:

[0050] In some of the current implementation methods (see...) Figure 1 , Figures 4 to 5 The GOA circuit includes multiple cascaded GOA units, each GOA unit corresponding to a single horizontal scan line driving the display panel (i.e., the GOA unit is similar to the display driving circuit in this embodiment). See also Figure 4 The main structure of the GOA unit includes a pull-up control part 101' and an output module 100'. The output module 100 includes a pull-up part 104', a key pull-down part 103', and a pull-down holding part 102'. The pull-up part also includes a bootstrap capacitor C1' responsible for raising the potential. The pull-up control part uses an existing design (such as...). Figure 1 (As shown). Figure 4 The structure of the GOA unit shown has the following shortcomings:

[0051] 1. In some current implementations, after prolonged operation, the threshold voltage drift of the thin-film transistors in the GOA unit can easily cause leakage current, leading to malfunction of the GOA circuit. For example... Figure 4 and Figure 5As shown, during the pull-up and bootstrap phases of the GOA circuit, the scan control node Qn' of each GOA unit is at a high potential and has several leakage current paths. For example, the scan control node Qn' can leak current to the level signal VGL through thin-film transistors t1, t2, and t12. It should be noted that in the forward scan mode, the leakage path is thin-film transistor t1 and the sixth thin-film transistor t12; in the reverse scan mode, the leakage path is thin-film transistor t2 and t12. Under conditions of decreasing temperature and electrical bias stress, the threshold voltage of the thin-film transistor is easily forward biased, leading to an increase in the off-state leakage current. This causes the potential of the scan control node Qn' to decrease during the pull-up phase, resulting in less sufficient opening of the thin-film transistor t15 in the pull-up circuit 104'. The time required for the voltage at the signal output terminal Gn to drop from 90% to 10% becomes longer, leading to incorrect charging or insufficient charging, which will seriously affect the output stability of the gate drive signal Gn.

[0052] 2. In some current implementations of the GOA circuit, the GOA unit may experience multi-gate issues (i.e., multiple scan signals output from a single row of pixels within a single frame) due to clock feedthrough, leading to malfunction of the GOA circuit. For example... Figure 4 and Figure 5 As shown, due to the clock feedthrough of the first clock control signal CT1_n to the thin-film transistor t15, the thin-film transistor t15 is abnormally turned on. During non-display periods, the drive signal output from the signal output terminal Gn is repeatedly and incorrectly coupled from its normal potential to a high potential, resulting in abnormal in-plane charging and affecting the normal display of the panel. Furthermore, under conditions of increased temperature and electrical bias stress, the threshold voltage of the thin-film transistor is prone to negative bias, which exacerbates the clock feedthrough phenomenon, reducing the stability of the drive signal output from the signal output terminal Gn and even causing output errors. 3. Because the turn-on time of the drive signal output from the signal output terminal Gn is very short, and the pull-down action time of adjacent GOA units and the point waveform of the scan control node Qn' are basically similar, and adjacent GOA units have the same complex circuit structure, this is detrimental to the implementation of a narrow bezel on the panel.

[0053] Therefore, in order to solve the technical problems existing in the GOA unit of the GOA circuit in some current implementations, and based on the technical concept of the technical solution of the foregoing embodiments, the following example illustrates a display driving circuit. Figure 6 This is a schematic diagram of the display driving circuit as an example of an embodiment of this application. See also: Figure 6The system includes: a scan control module 101 and an output module 100; the scan control module 101 includes a symmetrically arranged forward control unit 1011, a reverse control unit 1012, and a first control node Q1n; wherein, the forward control unit 1011 includes a first transistor T1 and a first leakage protection module M1, the first leakage protection module M1 includes a fourth transistor T4 and a fifth transistor T5; the control terminal of the first transistor T1 receives a first-stage input signal Cn+, the first path terminal of the first transistor T1 is used to receive the forward scan voltage VBD, and the second path terminal of the first transistor T1 is connected to the first control node Q1n; the control terminal of the fourth transistor T4 receives a second clock control signal CT2-n, and the first path terminal of the first transistor T1 receives the forward scan voltage VBD through the path formed with the fourth transistor T4; the control terminal of the fifth transistor T5 is connected to the first control node Q1n, the first path terminal of the fifth transistor T5 receives a first reference voltage VG1, and the second path terminal of the fifth transistor T5 is connected to the path between the first transistor T1 and the fourth transistor T4. The structure of the first leakage protection module can provide leakage protection for the first control node Q1n: When the first control node Q1n is high and the forward scanning voltage VBD is low, the first control node Q1n needs to be maintained at a high voltage for a period of time to wait for the bootstrap phase to arrive. During this holding time, there is a leakage path formed by the first transistor T1, the fourth transistor T4, and the forward scanning voltage VBD. However, since the fifth transistor T5 is turned on when the first control node Q1n is high, the second path terminal N2 of the fifth transistor T5 (the path between the first transistor T1 and the fourth transistor T4) receives the first reference voltage VG1 as high, blocking the leakage path of the first control node Q1n, thus achieving leakage protection for the first control node Q1n. The reverse control unit 1012 includes a second transistor T2 and a second leakage protection module M2. The second leakage protection module M2 includes a sixth transistor T6 and a seventh transistor T7. The control terminal of the second transistor T2 receives a second-stage input signal Cn-. The first path terminal of the second transistor T2 is used to receive the reverse scanning voltage VFD. The second path terminal of the second transistor T2 is connected to the first control node Q1n. The control terminal of the sixth transistor T6 receives a second clock control signal CT2-n. The first path terminal of the second transistor T2 receives the reverse scanning voltage VFD through the path formed with the sixth transistor T6. The control terminal of the seventh transistor T7 is connected to the first control node Q1n. The first path terminal of the seventh transistor T7 receives a first reference voltage VG1. The second path terminal of the seventh transistor T7 is connected to the path between the second transistor T2 and the sixth transistor T6.The second leakage protection module provides leakage protection for the first control node Q1n. When the first control node Q1n is high and the reverse scanning voltage VFD is low, Q1n needs to be held at a high voltage for a period of time to wait for the bootstrap phase. During this holding period, a leakage path exists formed by the second transistor T2, the sixth transistor T6, and the reverse scanning voltage VFD. However, since the seventh transistor T7 is turned on when the first control node Q1n is high, the second path terminal N1 of the seventh transistor T7 (the path between the second transistor T2 and the sixth transistor T6) receives the first reference voltage VG1 and is high, thus blocking the leakage path of the first control node Q1n and achieving leakage protection for Q1n.

[0054] In one embodiment, the forward scan voltage VBD can be either a reference high voltage VGH or a reference low voltage VGL, and the reverse scan voltage VFD can be the other of the reference high voltage VGH and the reference low voltage VGL.

[0055] Thus, in the technical solution of this example, when the scanning control module 101 of the display driving circuit outputs a control signal to pull up a specific component in the output module 100, the scanning control module 101 acts as a pull-up control module. Furthermore, by symmetrically configuring two leakage protection modules, the scanning control module 101 forms a symmetrical low-leakage structure. This not only avoids or improves the leakage problem caused by threshold voltage drift of the transistors in the scanning control module 101 after long-term operation, but also avoids or improves the problem of increased off-state leakage current caused by forward bias of the transistors in the scanning control module 101 under conditions of decreased temperature and electrical bias stress. Therefore, the scanning control module 101 can better and more stably output the first control signal to the output module 100 according to the expected design, thereby fully opening the relevant transistors of the output module 100 and ensuring that the time required for the voltage change of the drive signal output by the output module 100 meets the expected design, avoiding incorrect charging or insufficient charging, and thus ensuring the stability of the drive signal output by the output module 100.

[0056] In one embodiment, the output module 100 may include a level maintenance unit 102, which includes a cascaded single-stage inverter and a source follower and a second control node Q2n.

[0057] The single-stage inverter includes an eighth transistor T8 and a ninth transistor T9. The control terminal of the eighth transistor T8 receives a first reference voltage VG1 or is connected to a first control node Q1n. The first path terminal of the eighth transistor T8 receives the first reference voltage VG1. The second path terminal of the eighth transistor T8 is connected to the first path terminal of the ninth transistor T9. The second path terminal of the ninth transistor T9 receives a second reference voltage VG2. The control terminal of the ninth transistor T9 is connected to the first control node Q1n.

[0058] The source follower includes a tenth transistor T10 and an eleventh transistor T11. The control terminal of the tenth transistor T10 is connected to the second path terminal of the eighth transistor T8. The first path terminal of the tenth transistor T10 receives a first reference voltage VG1. The second path terminal of the tenth transistor T10 is connected to a second control node Q2n. The control terminal of the eleventh transistor T11 is connected to a first control node Q1n. The first path terminal of the eleventh transistor T11 is connected to the second control node Q2n. The second path terminal of the eleventh transistor T11 receives a second reference voltage VG2.

[0059] In one embodiment, the first reference voltage VG1 is either a reference high voltage VGH or a reference low voltage VGL, and the second reference voltage VG2 is the other of the reference high voltage VGH and the reference low voltage VGL.

[0060] In this embodiment, the technical solution uses an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11 to form a two-stage inverter. The first stage of the single-stage inverter has a smaller gain, while the second stage of the source follower has a greater gain than the first stage, so that the gain increases step by step, thereby enabling the inverter to have a strong level maintenance capability.

[0061] In one embodiment, the aforementioned inverter is capable of inverting the input and output. Optionally, the aforementioned inverter may include an NMOS transistor.

[0062] Thus, in the technical solution of this example, the inverter included in the level maintenance unit 102 of the output module 100 of the display driver circuit has a strong level maintenance capability (e.g., pull-down maintenance capability) during non-display stages, thereby suppressing the multi-gate phenomenon caused by clock feedthrough. Furthermore, even under conditions of increased temperature and electrical bias stress, where the threshold voltage of the transistor in the output module 100 is prone to negative bias, the multi-gate phenomenon caused by clock feedthrough can also be effectively suppressed. The level maintenance unit 102 in the output module 100 of the display driver circuit ensures the stability and correctness of the output drive signal.

[0063] When the output control signal causes a specific component in the output module 100 to be pulled up, the scan control module 101 acts as a pull-up control module. Furthermore, by symmetrically configuring two leakage protection modules, the scan control module 101 forms a symmetrical low-leakage structure. This not only avoids or improves the leakage problem caused by threshold voltage drift of the transistors in the scan control module 101 after long-term operation, but also avoids or improves the problem of increased off-state leakage current caused by forward bias of the transistors in the scan control module 101 under conditions of decreased temperature and electrical bias stress. Therefore, the scan control module 101 can better and more stably output the first control signal to the output module 100 according to the intended design, thereby fully opening the relevant transistors of the output module 100. This ensures that the time required for the voltage change of the drive signal output by the output module 100 meets the intended design, avoiding incorrect charging or insufficient charging, and thus ensuring the stability of the drive signal output by the output module 100.

[0064] In one embodiment, the output module 100 or the scanning control module 101 may further include a fourth level control unit 108, which includes a twelfth transistor T12 and a third leakage protection module, the third leakage protection module including a thirteenth transistor T13 and a fourteenth transistor T14;

[0065] The control terminal of the twelfth transistor T12 is connected to the second control node Q2n of the level maintenance unit 102 to receive the second control signal. The first path terminal of the twelfth transistor T12 is connected to the first control node Q1n. The second path terminal of the twelfth transistor T12 is used to receive the second reference voltage VG2.

[0066] The control terminal of the thirteenth transistor T13 receives the second clock control signal CT2-n, and the second path terminal of the twelfth transistor T12 receives the second reference voltage VG2 through the path formed with the thirteenth transistor T13. The control terminal of the fourteenth transistor T14 is connected to the first control node Q1n, the first path terminal of the fourteenth transistor T14 receives the first reference voltage VG1, and the second path terminal of the fourteenth transistor T14 is connected to the path between the twelfth transistor T12 and the thirteenth transistor T13.

[0067] The third leakage protection module provides leakage protection for the first control node Q1n. When the first control node Q1n is high and the second reference voltage VG2 is low, Q1n needs to maintain a high voltage for a period of time to wait for the bootstrap phase. During this period, a leakage path exists between the twelfth transistor T12, the thirteenth transistor T13, and the second reference voltage VG2. However, since the fourteenth transistor T14 is turned on when Q1n is high, its second terminal N3 (the path between the twelfth transistor T12 and the thirteenth transistor T13) receives a high first reference voltage VG1, thus blocking the leakage path of Q1n and providing leakage protection for Q1n.

[0068] Thus, in the technical solution of this example, the leakage protection module in the fourth level control unit 108 can cooperate with the leakage protection module in the scanning control module 101 to further avoid or improve the problem of leakage caused by the threshold voltage drift of the transistor in the scanning control module 101 after long-term operation.

[0069] In one embodiment, the output module 100 may include two first level control units 103, a second level control unit 104, a first output node Gn1, a third level control unit 105, a second output node Gn2, and an isolation unit 106;

[0070] The second-level control unit 104 includes a fifteenth transistor T15, a first capacitor C1, and a first output node Gn1. The control terminal of the fifteenth transistor T15 is connected to the first control node Q1n, and the control terminal of the fifteenth transistor T15 is also connected to the first output node Gn1 through the first capacitor C1 (which acts as a bootstrap). The first path terminal of the fifteenth transistor T15 receives the first clock control signal CT1-n, and the second path terminal of the fifteenth transistor T15 is connected to the first output node Gn1. Thus, the second-level control unit 104 can perform pull-up control or pull-down control on the first drive signal output by the first output node Gn1.

[0071] The first level control unit 103 connected to the first output node Gn1 includes an eighteenth transistor T18. The control terminal of the eighteenth transistor T18 is connected to the second control node Q2n to receive a second control signal (output by the level maintenance unit 102). The first path terminal of the eighteenth transistor T18 is connected to the first output node Gn1, and the second path terminal of the eighteenth transistor T18 receives a second reference voltage VG2. Thus, the first level control unit 103 connected to the first output node Gn1 can perform either pull-up control or pull-down control on the first drive signal output by the first output node Gn1 (opposite to the second level control unit 104).

[0072] The third-level control unit 105 includes a sixteenth transistor T16, a second capacitor C2, and a second output node Gn2. The control terminal of the sixteenth transistor T16 is connected to the second output node Gn2 through the second capacitor C2 (which acts as a bootstrap capacitor). The first path terminal of the sixteenth transistor T16 receives the third clock control signal CT3-n, and the second path terminal of the sixteenth transistor T16 is connected to the second output node Gn2. Thus, the third-level control unit 105 can perform pull-up or pull-down control on the second drive signal output from the second output node Gn2.

[0073] The first level control unit 103 connected to the second output node Gn2 includes a nineteenth transistor T19. The control terminal of the nineteenth transistor T19 is connected to the second control node Q2n to receive a second control signal. The first path terminal of the nineteenth transistor T19 is connected to the second output node Gn2, and the second path terminal of the nineteenth transistor T19 receives a second reference voltage VG2. Thus, the first level control unit 103 connected to the second output node Gn2 can perform either pull-up control or pull-down control on the second drive signal output by the second output node Gn2 (opposite to the third level control unit 105).

[0074] The isolation unit 106 includes a seventeenth transistor T17. The control terminal of the seventeenth transistor T17 receives a first reference voltage VG1. The first path terminal of the seventeenth transistor T17 is connected to the control terminal of the fifteenth transistor T15, and the second path terminal of the seventeenth transistor T17 is connected to the control terminal of the sixteenth transistor T16.

[0075] In the technical solution of this example, the two first level control units 103, the second level control unit 104, the first output node Gn1, the third level control unit 105, the second output node Gn2, and the isolation unit 106 in the output module 100 of the display driving circuit, in the above-mentioned circuit cooperation mode, enable the display driving circuit to multiplex the scan control module 101 and the level maintenance unit 102 to generate driving signals (first driving signal and second driving signal) for two pixel rows (or two horizontal scan lines) in the display panel. Therefore, the technical solution of this example can improve the circuit efficiency of the entire display driving circuit and also realize the narrow bezel design requirements of the display device.

[0076] Specifically, the display driving circuit multiplexes the scan control module 101 and the level maintenance circuit, enabling it to output the second driving signal for the (n+1)th level pixel row without bootstrapping loss while simultaneously completing the normal output of the first driving signal for the nth level pixel row.

[0077] In one embodiment, the seventeenth transistor T17 in the isolation unit 106 can be a normally-on isolation transistor; the first path terminal of the seventeenth transistor T17 is connected to the control terminal of the fifteenth transistor T15, which is equivalent to being connected to the first control node Q1n; the second path terminal of the seventeenth transistor T17 is connected to the control terminal of the sixteenth transistor T16, which is equivalent to forming a third control node Q3n at the control terminal of the sixteenth transistor T16. Since the third control node Q3n controls the third level control unit 105, the seventeenth transistor T17 can reduce the bootstrap loss caused by node sharing. In addition, the second drive signal output by the third level control unit 105 will not be erroneously coupled due to the first drive signal output by the second level control unit 104 (e.g., erroneous coupling during pull-up), avoiding the second drive signal being coupled from the normal high potential to a higher level, thereby solving the phenomenon of abnormal charging in the display panel and ensuring the normal display of the display panel.

[0078] In one embodiment, the output module 100 may further include a cascading unit 107, which includes a third transistor T3;

[0079] The control terminal of the third transistor T3 is connected to the first control node Q1n to receive the first control signal. The first path terminal of the third transistor T3 receives the first clock control signal CT1-n. The output stage of the second path terminal of the third transistor T3 transmits the signal Cn.

[0080] In one embodiment, the output module 100 may also be connected to a fifth level control unit 109 connected to the cascading unit 107. The fifth level control unit 109 includes a twentieth transistor T20. The control terminal of the twentieth transistor T20 is connected to the second control node Q2n (level maintenance unit 102). The first path terminal of the twentieth transistor T20 is connected to the second path terminal of the third transistor. The second path terminal of the twentieth transistor T20 receives a second reference voltage VG2.

[0081] Thus, the technical solution of this example, by designing the transmission unit 107 in the output module 100, can reduce the pressure on the drive load of the display drive circuit and improve the low-temperature transmission capability.

[0082] The first reference voltage VG1 can be either the reference high voltage VGH or the reference low voltage VGL, and the second reference voltage VG2 can be either the reference high voltage VGH or the reference low voltage VGL.

[0083] The first level control module, the fourth level control module, and the fifth level control unit 109 all control the transmitted signals to maintain them at the intended design potential at the correct time through the second control signal output by the second control node Q2n via the level maintenance unit 102. Specifically, the two first level control units 103, under the control of the second control signal, can maintain the first and second drive signals at a preset design potential (e.g., pulled down to a reference low voltage VGL) at the correct time. The fourth level control unit 108, under the control of the second control signal, can maintain the first control signal at the intended design potential (e.g., pulled down to a reference low voltage VGL) at the correct time. The fifth level control unit 109... Figure 3 (Not shown) can be controlled by a second control signal to maintain the stage output signal Cn at the intended design potential (e.g., pulled down to the reference low voltage VGL) at the correct timing.

[0084] In one embodiment, the capacitance value of the first capacitor C1 can be greater than 0 and less than or equal to 500fF, and the capacitance value of the second capacitor C2 can be greater than 0 and less than or equal to 300fF.

[0085] In one embodiment, the display driving circuit or the display device equipped with the above-described display driving circuit provides each clock control signal using an eight-phase clock. In one embodiment, in the eight-phase clock, the k-th clock is advanced by T / 8 compared to the (k+1)-th clock, where 1 ≤ k < 8. In one embodiment, the duty cycle of the high level in each clock control signal is T / 4. In one embodiment, the phase difference between the first driving signal and the second driving signal is T / 8.

[0086] It should be understood that the aforementioned nodes (such as the first control node Q1n, the second control node Q2n, the third control node Q3n, etc.) can be virtual nodes that facilitate a clear description of the circuit structure; in addition, the aforementioned nodes can also be physical ports set according to actual needs.

[0087] In summary, the aforementioned display driver circuit optimizes the leakage path of the GOA circuit while maintaining forward and reverse scanning capabilities, and suppresses the effects of clock feedthrough. This addresses the issue of thin-film transistor threshold voltage offset caused by temperature variations and electrical bias stress. Furthermore, since the same display driver circuit can output two drive signals to drive two pixel rows of the display panel, the number of display driver circuits in the display device can be reduced, facilitating the implementation of narrow bezel designs. Therefore, the aforementioned display driver circuit solves the technical problem of display abnormalities caused by the susceptibility of some currently implemented GOA circuits to functional failure over wide temperature ranges.

[0088] Based on the circuit structure of the display driver circuit described above, the following are further examples:

[0089] Example 1:

[0090] Figure 7 This is a schematic diagram of the display driving circuit of Example 1 of this application. See also... Figure 7 This example provides a display driving circuit constructed from N-type thin-film transistors (e.g., using LTPO TFT), including: a scan control module 101 and an output module 100; the scan control module 101 includes a symmetrically arranged forward control unit 1011, a reverse control unit 1012, and a first control node Q1n; wherein, the forward control unit 1011 includes a first transistor T1 and a first leakage protection module M1, the first leakage protection module M1 includes a fourth transistor T4 and a fifth transistor T5; the control terminal of the first transistor T1 receives a first-stage input signal Cn+, the first path terminal of the first transistor T1 is used to receive the forward scan voltage VBD, and the second path terminal of the first transistor T1 is connected to the first control node Q1n; the control terminal of the fourth transistor T4 receives a second clock control signal CT2-n, and the first path terminal of the first transistor T1 receives the forward scan voltage VBD through the path formed with the fourth transistor T4; the control terminal of the fifth transistor T5 is connected to the first control node Q1n, and the first path terminal of the fifth transistor T5 receives a reference high voltage. VGH, the second path terminal of the fifth transistor T5 is connected to the path between the first transistor T1 and the fourth transistor T4; wherein, the reverse control unit 1012 includes a second transistor T2 and a second leakage protection module M2, the second leakage protection module M2 includes a sixth transistor T6 and a seventh transistor T7; the control terminal of the second transistor T2 receives the second stage input signal Cn-, the first path terminal of the second transistor T2 is used to receive the reverse scan voltage VFD, and the second path terminal of the second transistor T2 is connected to the first control node Q1n; the control terminal of the sixth transistor T6 receives the second clock control signal CT2-n, and the first path terminal of the second transistor T2 receives the reverse scan voltage VFD through the path formed with the sixth transistor T6, the control terminal of the seventh transistor T7 is connected to the first control node Q1n, the first path terminal of the seventh transistor T7 receives the reference high voltage VGH, and the second path terminal of the seventh transistor T7 is connected to the path between the second transistor T2 and the sixth transistor T6.

[0091] In one embodiment, the output module 100 may include a level maintenance unit 102, two first level control units 103, a second level control unit 104, a third level control unit 105, an isolation unit 106, a fourth level control unit 108, a cascade unit 107, and a fifth level control unit 109; wherein, the level maintenance unit 102 includes a cascaded single-stage inverter and a source follower, and a second control node Q2n; the single-stage inverter includes an eighth transistor T8 and a ninth transistor T9, the control terminal of the eighth transistor T8 receives a reference high voltage VGH, the first path terminal of the eighth transistor T8 receives the reference high voltage VGH, and the second path terminal of the eighth transistor T8 is connected to the first path terminal of the ninth transistor T9. The path connection is as follows: the second path of the ninth transistor T9 receives the reference low voltage VGL, and the control terminal of the ninth transistor T9 is connected to the first control node Q1n; the source follower includes the tenth transistor T10 and the eleventh transistor T11. The control terminal of the tenth transistor T10 is connected to the second path of the eighth transistor T8, the first path of the tenth transistor T10 receives the reference high voltage VGH, and the second path of the tenth transistor T10 is connected to the second control node Q2n. The control terminal of the eleventh transistor T11 is connected to the first control node Q1n, the first path of the eleventh transistor T11 is connected to the second control node Q2n, and the second path of the eleventh transistor T11 receives the reference low voltage VGL.

[0092] In one embodiment, the output module 100 may further include a fourth level control unit 108, including a twelfth transistor T12 and a third leakage protection module, the third leakage protection module including a thirteenth transistor T13 and a fourteenth transistor T14; the control terminal of the twelfth transistor T12 is connected to the second control node Q2n of the level maintenance unit 102 to receive a second control signal, the first path terminal of the twelfth transistor T12 is connected to the first control node Q1n, and the second path terminal of the twelfth transistor T12 is used to receive a reference low voltage VGL; the control terminal of the thirteenth transistor T13 receives a second clock control signal CT2-n, and the second path terminal of the twelfth transistor T12 receives the reference low voltage VGL through the path formed with the thirteenth transistor T13; the control terminal of the fourteenth transistor T14 is connected to the first control node Q1n, the first path terminal of the fourteenth transistor T14 receives a reference high voltage VGH, and the second path terminal of the fourteenth transistor T14 is connected to the path between the twelfth transistor T12 and the thirteenth transistor T13.

[0093] The second-level control unit 104 includes a fifteenth transistor T15, a first capacitor C1, and a first output node Gn1. The control terminal of the fifteenth transistor T15 is connected to the first control node Q1n, and the control terminal of the fifteenth transistor T15 is also connected to the first output node Gn1 through the first capacitor C1 (which acts as a bootstrap). The first path terminal of the fifteenth transistor T15 receives the first clock control signal CT1-n, and the second path terminal of the fifteenth transistor T15 is connected to the first output node Gn1. Thus, the second-level control unit 104 can pull up the first drive signal output from the first output node Gn1. The first level connected to the first output node Gn1... Control unit 103 includes an eighteenth transistor T18. The control terminal of the eighteenth transistor T18 is connected to the second control node Q2n to receive a second control signal (output by the level maintenance unit 102). The first path terminal of the eighteenth transistor T18 is connected to the first output node Gn1, and the second path terminal of the eighteenth transistor T18 receives a reference low voltage VGL. Thus, the first level control unit 103 connected to the first output node Gn1 can perform pull-down control on the first drive signal output by the first output node Gn1 (opposite to the second level control unit 104). The third level control unit 105 includes a sixteenth transistor T16, a second capacitor C2, and a second output. At node Gn2, the control terminal of the sixteenth transistor T16 is connected to the second output node Gn2 via the second capacitor C2 (which acts as a bootstrap capacitor). The first path terminal of the sixteenth transistor T16 receives the third clock control signal CT3-n, and the second path terminal of the sixteenth transistor T16 is connected to the second output node Gn2. Thus, the third level control unit 105 can pull up the second drive signal output from the second output node Gn2. The first level control unit 103 connected to the second output node Gn2 includes the nineteenth transistor T19. The control terminal of the nineteenth transistor T19 is connected to the second control node Q2n to receive the second control signal. The first path terminal of transistor 9 is connected to the second output node Gn2, and the second path terminal of transistor 19 receives the reference low voltage VGL; thus, the first level control unit 103 connected to the second output node Gn2 can pull down the second drive signal output by the second output node Gn2 (opposite to the third level control unit 105); the isolation unit 106 includes transistor 17, the control terminal of transistor 17 receives the reference high voltage VGH (normally on), the first path terminal of transistor 17 is connected to the control terminal of transistor 15, and the second path terminal of transistor 17 is connected to the control terminal of transistor 16.

[0094] The stage transmission unit 107 includes a third transistor T3; the control terminal of the third transistor T3 is connected to the first control node Q1n to receive a first control signal, the first path terminal of the third transistor T3 receives the first clock control signal CT1-n, and the second path terminal of the third transistor T3 outputs the stage transmission signal Cn. A fifth level control unit 109 is connected to the stage transmission unit 107. The fifth level control unit 109 includes a twentieth transistor T20; the control terminal of the twentieth transistor T20 is connected to the second control node Q2n (level maintenance unit 102), the first path terminal of the twentieth transistor T20 is connected to the second path terminal of the third transistor T3, and the second path terminal of the twentieth transistor T20 receives a reference low voltage VGL.

[0095] The capacitance of the first capacitor C1 can be greater than 0 and less than or equal to 500fF, and the capacitance of the second capacitor C2 can be greater than 0 and less than or equal to 300fF. The display driving circuit uses an eight-phase clock to provide the clock control signals. In the eight-phase clock, the k-th clock is advanced by T / 8 compared to the (k+1)-th clock, where 1 ≤ k < 8. The duty cycle of the high level in each clock control signal is T / 4. The phase difference between the first driving signal and the second driving signal is T / 8.

[0096] Figure 8 This is a timing diagram of the display driver circuit in Example 1 of this application. See also... Figure 8 The operating timing sequence of the display driver circuit in Example 1 includes:

[0097] (1) T1 stage: The second clock control signal CT2-n and the second stage input signal Cn- provide a high potential, and the first clock control signal CT1-n provides a low potential; in the scan control module 101 (or pull-up control circuit), the sixth transistor T6, the second transistor T2, and the seventh transistor T7 are turned on, and the first control node Q1n is charged to a high level; in the level maintenance unit 102 (or pull-up maintenance circuit), the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the second control node Q2n outputs a low level opposite to the first control node Q1n; the seventeenth transistor T17 of the isolation unit 106 is turned on, the fifteenth transistor T15 in the second level control unit 104 is turned on, the third transistor T3 in the stage transmission unit 107 is turned on, and the sixteenth transistor T16 in the third level control unit 105 is turned on, the first output node Gn1 outputs a first drive signal representing a low level, and the second output node Gn2 outputs a second drive signal representing a low level.

[0098] The voltage of the first capacitor C1 (bootstrap capacitor) and the voltage of the second capacitor C2 (bootstrap capacitor) are the difference between the level of the first control node Q1n and the reference low voltage VGL, which is equal to VGH-VGL.

[0099] (2) T2 stage: The first clock control signal CT1-n, the second clock control signal CT2-n, and the second stage input signal Cn- provide a low potential, and the third clock control signal CT3-n starts to rise to a high level; at this time, the voltage of the second capacitor C2C2 is maintained at VGH-VGL; the sixteenth transistor T16 pushes the third control node Q3n to a higher level due to the bootstrap effect, and the second output node Gn2 outputs the second drive signal representing the high level; it should be noted that when the third control node Q3n bootstraps to a higher potential than VGH, the seventeenth transistor T17 (isolation tube) is turned off, and the first control node Q1n will not rise with the third control node Q3n, thus avoiding adverse problems such as bootstrap level loss in the future.

[0100] (3) T3 stage: The first clock control signal CT1-n provides a high potential, the second clock control signal CT2-n and the second stage input signal Cn- provide a low potential, and the third clock control signal CT3-n begins to drop back to a low level; the bootstrap effect of the third control node Q3n disappears as the third clock control signal CT3-n returns to a low level, and the second output node Gn2 outputs a second drive signal representing a low level; at this time, the voltage of the first capacitor C1 is maintained at VGH-VGL, and the fifteenth transistor T15 pushes the first control node Qn1 to a higher level due to the bootstrap effect, and the first output node Gn1 outputs a first drive signal representing a high level.

[0101] (4) T4 stage: The first clock control signal CT1-n, the second clock control signal CT2-n, and the second stage input signal Cn- provide low potential; the bootstrap effect of the first control node Q1n disappears as the first clock control signal CT1-n returns to low, and the first output node Gn1 outputs the first drive signal representing the low level.

[0102] (5) T5 stage: The second clock control signal CT2-n and the first stage input signal Cn+ provide a high potential, and the first clock control signal CT1-n and the second stage input signal Cn- provide a low potential; the fourth transistor T4, the first transistor T1, and the fifth transistor T5 in the scan control module 101 are turned on, and the first control node Q1n is discharged to a low level; in the level maintenance unit 102 (or pull-down maintenance circuit), the inverter composed of the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 outputs a high level opposite to the first control node Q1n, and maintains the first control node Q1n at the reference low level VGL during the non-display time.

[0103] In one embodiment, the above-described display driving unit can be packaged. Figure 9 This is a schematic diagram of the display driver circuit of Example 1 of this application. See also... Figure 9 The first clock control signal CT1-n, the second clock control signal CT2-n, and the third clock control signal CT3-n can be provided by an eight-phase clock. For example, the first clock control signal CT1-n is the first clock signal CLK1 in the eight-phase clock, the second clock control signal CT2-n is the fifth clock signal CLK5 in the eight-phase clock, and the third clock control signal CT3-n is the second clock signal CLK2, the eighth clock signal CLK8, or the seventh clock signal CLK7 in the eight-phase clock.

[0104] Figure 10 This is a schematic diagram of the cascaded multiple display driver circuits provided in this application. In one embodiment, when the GOA circuit adopts... Figure 10 The display driver circuit shown is cascaded and uses an eight-phase clock. Each display driver circuit is controlled by three clock signal lines, namely CT1-n, CT2-n, and CT3-n.

[0105] Figure 11 A schematic diagram of the cascaded structure of the middle 5 stages of the display driver circuit in the example GOA circuit. See also... Figure 11 This example illustrates the cascaded structure of the five intermediate display driver circuits in the GOA circuit; combined with Figure 11 It can be seen that in the aforementioned cascaded structures of the five intermediate display driver circuits in the GOA circuit, the first clock control signal CT1-n of the nth stage display driver circuit is provided by the first clock signal line CLK1, the second clock control signal CT2-n is provided by the fifth clock signal line CLK5, and the third clock control signal CT3-n is provided by the eighth clock signal line CLK8; the first clock control signal CT1-n of the n-4th and n+4th stage display driver circuits is provided by the fifth clock signal line CLK5, the second clock control signal CT2-n is provided by the first clock signal line CLK1, and the third clock control signal CT3-n is provided by the fourth clock signal line CLK4; the first clock control signal CT1-n of the n-2th stage display driver circuit is provided by the seventh clock signal line CLK7, the second clock control signal CT2-n is provided by the third clock signal line CLK3, and the third clock control signal CT3-n is provided by the sixth clock signal line CLK6. The first clock control signal CT1-n of the (n+2)th level display driver unit is provided by the third clock signal line CLK3, the second clock control signal CT2-n is provided by the seventh clock signal line CLK7, and the first clock control signal CT1-n is provided by the second clock signal line CLK2. The stage output signals Cn-4 and Cn+4 of the (n-4)th and (n+4)th level display driver circuits serve as the stage input signals of the nth level display driver unit, and the stage output signals of the nth level display driver unit serve as the stage input signals of the (n-4)th and (n+4)th level display driver circuits.

[0106] Figure 11 Different options for loading the clock control signal are provided, demonstrating the different output results of different implementations when the third clock control signal CT3-n loads the seventh clock signal CLK7, the eighth clock signal CLK8, and the first clock signal CLK1, respectively; when the second clock control signal CT2-n loads the seventh clock signal CLK7, the second drive signal Gn2 outputs Gn-2; when the second clock control signal CT2-n loads the eighth clock signal CLK8, the second drive signal Gn2 outputs Gn-1; when the second clock control signal CT2-n loads the first clock signal CLK1, the second drive signal Gn2 outputs Gn+1.

[0107] It is understood that the GOA circuit provided in the above embodiment uses 8 clock signal lines (eight-phase clock) for control. For other GOA circuits that use 4 clock signal lines, 6 clock signal lines, etc. for control, a similar structure can also be adopted, which will not be elaborated here.

[0108] Example 2:

[0109] Figure 12 This is a schematic diagram of the display driving circuit of Example 2 of this application. See also... Figure 12 This example provides a display driving circuit that replaces the N-type thin-film transistor in Example 1 with a P-type transistor (e.g., using an LTPS TFT) and interchanges the reference high voltage VGH and reference low voltage VGL in Example 1, which can achieve the normal operation requirements of the display driving circuit in the GOA circuit.

[0110] Figure 13 This is a timing diagram of the display driver circuit of Example 2 of this application. See also... Figure 13 The operating timing sequence of the display driver circuit in Example 2 includes:

[0111] (1) T1 stage: The second clock control signal CT2-n and the second stage input signal Cn- provide a low potential, and the first clock control signal CT1-n provides a high potential; in the scan control module 101 (or pull-up control circuit), the sixth transistor T6, the second transistor T2, and the seventh transistor T7 are turned on, and the first control node Q1n is charged to a low level; in the level maintenance unit 102 (or pull-down maintenance circuit), the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the second control node Q2n outputs a high level opposite to that of the first control node Q1n; the seventeenth transistor T17 of the isolation unit 106 is turned on, the fifteenth transistor T15 in the second level control unit 104 is turned on, the second transistor T2 in the stage transmission unit 107 is turned on, and the sixteenth transistor T16 in the third level control unit 105 is turned on, the first output node Gn1 outputs a first drive signal representing a high level, and the second output node Gn2 outputs a second drive signal representing a high level.

[0112] The voltage of the first capacitor C1 (bootstrap capacitor) and the voltage of the second capacitor C2 (bootstrap capacitor) are the difference between the level of the first control node Q1n and the reference high voltage VGH, which is equal to VGL-VGH.

[0113] (2) T2 stage: The first clock control signal CT1-n, the second clock control signal CT2-n, and the second stage input signal Cn- provide high potential, and the third clock control signal CT3-n starts to rise to low level; at this time, the voltage of the second capacitor C2 is maintained at VGL-VGH; the sixteenth transistor T16 pushes the third control node Q3n to a lower level due to the bootstrap effect, and the second output node Gn2 outputs the second drive signal representing the low level; it should be noted that when the third control node Q3n bootstraps to a lower potential than VGH, the seventeenth transistor T17 (isolation tube) is turned off, and the first control node Q1n will not decrease with the third control node Q3n, thus avoiding adverse problems such as bootstrap level loss in the future.

[0114] (3) T3 stage: The first clock control signal CT1-n provides a low potential, the second clock control signal CT2-n and the second stage input signal Cn- provide a high potential, and the third clock control signal CT3-n starts to rise back to a high level; the bootstrap effect of the third control node Q3n disappears as the third clock control signal CT3-n returns to a high level, and the second output node Gn2 outputs a second drive signal representing a high level; at this time, the voltage of the first capacitor C1 is maintained at VGL-VGH, and the fifteenth transistor T15 pushes the first control node Qn1 to a lower level due to the bootstrap effect, and the first output node Gn1 outputs a first drive signal representing a low level.

[0115] (4) T4 stage: The first clock control signal CT1-n, the second clock control signal CT2-n, and the second stage input signal Cn- provide high potential; the bootstrap effect of the first control node Q1n disappears as the first clock control signal CT1-n returns to high, and the first output node Gn1 outputs the first drive signal representing the high level.

[0116] (5) T5 stage: The second clock control signal CT2-n and the first stage input signal Cn+ provide a low potential, and the first clock control signal CT1-n and the second stage input signal Cn- provide a high potential; the fourth transistor T4, the first transistor T1, and the fifth transistor T5 in the scan control module 101 are turned on, and the first control node Q1n is discharged to a high level; in the level maintenance unit 102 (or pull-down maintenance circuit), the inverter composed of the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 outputs a low level opposite to the first control node Q1n, and maintains the first control node Q1n at the reference high level VGH during the non-display time.

[0117] In one embodiment, the first clock control signal CT1-n, the second clock control signal CT2-n, and the third clock control signal CT3-n can be provided by an eight-phase clock. For example, the first clock control signal CT1-n is the first clock signal CLK1 in the eight-phase clock, the second clock control signal CT2-n is the fifth clock signal CLK5 in the eight-phase clock, and the third clock control signal CT3-n is the second clock signal CLK2, the eighth clock signal CLK8, or the seventh clock signal CLK7 in the eight-phase clock.

[0118] Example 3:

[0119] Figure 14 This is a schematic diagram of the display driving circuit of Example 3 of this application. See also... Figure 14 This example provides a display driving circuit that changes the inverter of the level maintenance unit 102 in Example 1 from a unipolar MOS (N-type or P-type) to a CMOS type (i.e., the eighth transistor T8 uses an LTPS TFT), while the remaining transistors use oxide TFTs. The difference between this example and the eighth transistor T8 in Example 1 is that the control terminal of the eighth transistor T8 in this example is connected to the first control node Q1n (not receiving the reference high voltage VGH). The specific driving timing diagram is the same as in the first embodiment; please refer to [link to relevant documentation]. Figure 8 .

[0120] Example 4

[0121] Figure 15 This is a schematic diagram of the display driving circuit of Example 4 of this application. See also... Figure 15This example provides a display driving circuit composed of N-type thin-film transistors (e.g., LTPO TFT) and P-type thin-film transistors (e.g., LTPS TFT), including: an output module 100 and a scan control module 101 composed of N-type thin-film transistors; the scan control module 101 includes a symmetrically arranged forward control unit, a reverse control unit, and a first control node Q1n; wherein, the forward control unit includes a first transistor T1 and a first leakage protection module, the first leakage protection module including a fourth transistor T4 and a fifth transistor T5; the control terminal of the first transistor T1 receives a first-stage input signal Cn+, the first path terminal of the first transistor T1 is used to receive the forward scan voltage VBD, and the second path terminal of the first transistor T1 is connected to the first control node Q1n; the control terminal of the fourth transistor T4 receives a second clock control signal CT2-n, and the first path terminal of the first transistor T1 receives the forward scan voltage VBD through the path formed with the fourth transistor T4; the control terminal of the fifth transistor T5 is connected to the first control node Q1n, and the first path terminal of the fifth transistor T5 receives a reference high voltage. The voltage VGH is applied, and the second path terminal of the fifth transistor T5 is connected to the path between the first transistor T1 and the fourth transistor T4. The reverse control unit includes a second transistor T2 and a second leakage protection module M2, which includes a sixth transistor T6 and a seventh transistor T7. The control terminal of the second transistor T2 receives the second-stage input signal Cn-, and the first path terminal of the second transistor T2 is used to receive the reverse scanning voltage VFD. The second path terminal of the second transistor T2 is connected to the first control node Q1n. The control terminal of the sixth transistor T6 receives the second clock control signal CT2-n, and the first path terminal of the second transistor T2 receives the reverse scanning voltage VFD through the path formed with the sixth transistor T6. The control terminal of the seventh transistor T7 is connected to the first control node Q1n, and the first path terminal of the seventh transistor T7 receives the reference high voltage VGH. The second path terminal of the seventh transistor T7 is connected to the path between the second transistor T2 and the sixth transistor T6.

[0122] In one embodiment, the output module 100 may include two first level control units 103, a second level control unit 104, a third level control unit 105, an isolation unit 106, a cascading unit 107, and a fifth level control unit 109; wherein, the output module 100 in this example differs from the output module 100 in Example 1 in that it does not have a level maintenance unit 102 and a fourth level control unit 108 configured, and both the first level control units 103 and the fifth level control unit 109 include P-type thin film transistors.

[0123] Thus, compared to the display driver circuit in Example 1, the display driver circuit in this example does not require constructing a second control node Q2n with a level opposite to that of the first control node Q1n to control the node pull-down. The display driver circuit in this example configures the transistors in the two first-level control units 103 and the fifth-level control unit 109 that implement pull-down control as P-type thin-film transistors (e.g., LTPS TFTs), and directly uses the first control node Q1n to control the P-type thin-film transistors, thereby completing the pull-down. The operating timing of the display driver circuit in this example can be referred to the operating timing of Example 1 (see...). Figure 8 ).

[0124] Example 5:

[0125] Figure 16 This is a schematic diagram of the display driving circuit of Example 5 of this application. See also... Figure 16 This example provides a display driving circuit composed of N-type thin-film transistors (e.g., LTPO TFT) and P-type thin-film transistors (e.g., LTPS TFT), including: an output module 100 and a scan control module 101 composed of P-type thin-film transistors; in one embodiment, the output module 100 may include two first level control units 103, a second level control unit 104, a third level control unit 105, an isolation unit 106, a cascading unit 107, and a fifth level control unit 109; wherein, the difference between the output module 100 of this example and the output module 100 in Example 4 is that both first level control units 103 and the fifth level control unit 109 include N-type thin-film transistors. Therefore, the transistor type configuration in the display driving circuit of this example is exactly the opposite of the transistor type configuration in the display driving circuit provided in Example 4.

[0126] Thus, compared to the display driving circuit in Example 2, the display driving circuit in this example does not require constructing a second control node Q2n with a level opposite to that of the first control node Q1n to control the node pull-up. The display driving circuit in this example configures the transistors in the two first-level control units 103 and the fifth-level control unit 109 that implement pull-up control as N-type thin-film transistors (e.g., LTPO TFTs), and directly uses the first control node Q1n to control the N-type thin-film transistors, thereby completing the pull-up. The operating timing of the display driving circuit in this example can be referred to the operating timing of Example 2 (see...). Figure 13 ).

[0127] This application also provides a display device, including a display panel and at least one display driving circuit as described in any of the above embodiments, wherein each display driving circuit is electrically connected to the display panel to output a driving signal to drive horizontal scan lines in the display panel.

[0128] In one embodiment, multiple display driving circuits are connected in a multi-stage cascade manner, and the multiple display driving circuits are used to drive all or part of the pixel rows in the display panel; each display driving circuit is used to generate a first driving signal and a second driving signal to drive two pixel rows. In one embodiment, the phase difference between the driving signals of adjacent pixel rows in the display panel is T / 8.

[0129] In one embodiment, the display device can be a display device for in-cell touch LCD display applications. In-cell touch LCD is a technology that integrates a touch sensor into a liquid crystal display (LCD).

[0130] The technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A display driving circuit, characterized in that, include: Scan control module and output module; The scanning control module includes a forward control unit, a reverse control unit, and a first control node arranged symmetrically. The forward control unit includes a first transistor and a first leakage protection module. The first path terminal of the first transistor is used to receive a forward scanning voltage, and the second path terminal of the first transistor is connected to the first control node. The first leakage protection module includes a fourth transistor and a fifth transistor. The control terminal of the fourth transistor receives a second clock control signal, and the first path terminal of the first transistor receives the forward scanning voltage through a path formed with the fourth transistor. The control terminal of the fifth transistor is connected to the first control node, and the first path terminal of the fifth transistor receives a first reference voltage. The second path terminal of the fifth transistor is connected to the path between the first transistor and the fourth transistor. The reverse control unit includes a second transistor and a second leakage protection module. The first path terminal of the second transistor is used to receive the reverse scanning voltage, and the second path terminal of the second transistor is connected to the first control node. The second leakage protection module includes a sixth transistor and a seventh transistor. The control terminal of the sixth transistor receives the second clock control signal, and the first path terminal of the second transistor receives the reverse scanning voltage through a path formed with the sixth transistor. The control terminal of the seventh transistor is connected to the first control node, and the first path terminal of the seventh transistor receives the first reference voltage. The second path terminal of the seventh transistor is connected in the path between the second transistor and the sixth transistor. The forward control unit and the reverse control unit are used to enable the scanning control module to perform forward and reverse scanning functions according to the signals of the control terminals of each input transistor, and to output a first control signal to the output module through the first control node; The output module is used to perform pull-up control and / or pull-down control according to the first control signal to output a drive signal.

2. The display driving circuit according to claim 1, characterized in that, The output module includes a level maintenance unit; the level maintenance unit includes an inverter and a second control node; the inverter is used to perform level maintenance control according to the first control signal during the non-display phase to output a second control signal through the second control node, so that the drive signal output by the output module is maintained in a low level state or a high level state; and / or, The output module includes a first level control unit; the first level control unit is used to perform either the pull-up control or the pull-down control according to the second control signal output by the level maintenance unit, so that the output module outputs the drive signal representing either a low level or a high level; And / or, The output module includes a transmission unit; the transmission unit includes a third transistor, the control terminal of the third transistor is connected to the first control node to receive the first control signal, the first path terminal of the third transistor receives the first clock control signal, and the second path terminal of the third transistor outputs the transmission signal.

3. The display driving circuit according to claim 2, characterized in that, The output module includes at least two first level control units; The output module further includes a second level control unit, a first output node, a third level control unit, a second output node, and an isolation unit; The isolation unit is used to isolate the control signals of the second level control unit and the third level control unit; When one of the at least two first level control units is used to perform either the pull-up control or the pull-down control, it outputs a first drive signal representing either a low level or a high level to the first output node; when the second level control unit is used to perform the other of the pull-up control or the pull-down control, it outputs a first drive signal representing either a low level or a high level to the first output node. When one of the at least two first level control units is used to perform either the pull-up control or the pull-down control, it outputs a second drive signal representing either a low level or a high level to the second output node; when the third level control unit is used to perform either the pull-up control or the pull-down control, it outputs a second drive signal representing either a low level or a high level to the second output node. The first driving signal and the second driving signal are used to drive the horizontal scan lines of two adjacent levels in the display panel, respectively.

4. The display driving circuit according to claim 2, characterized in that, The output module further includes a fourth level control unit, which is connected to the first control node and the second control node, and is used to adjust the level of the first control signal output by the first control node according to the second control signal output by the level maintenance unit.

5. The display driving circuit according to any one of claims 1 to 4, characterized in that, The inverter includes a single-stage inverter and a cascaded source follower thereto. The level maintenance unit further includes a second control node. The single-stage inverter includes an eighth transistor and a ninth transistor. The control terminal of the eighth transistor receives the first reference voltage or is connected to the first control node. The first path terminal of the eighth transistor receives the first reference voltage. The second path terminal of the eighth transistor is connected to the first path terminal of the ninth transistor. The second path terminal of the ninth transistor receives a second reference voltage. The control terminal of the ninth transistor is connected to the first control node. The source follower includes a tenth transistor and an eleventh transistor. The control terminal of the tenth transistor is connected to the second path terminal of the eighth transistor. The first path terminal of the tenth transistor receives the first reference voltage. The second path terminal of the tenth transistor is connected to the second control node. The control terminal of the eleventh transistor is connected to the first control node. The first path terminal of the eleventh transistor is connected to the second control node. The second path terminal of the eleventh transistor receives the second reference voltage. The first reference voltage is one of a reference high voltage and a reference low voltage, and the second reference voltage is the other of a reference high voltage and a reference low voltage.

6. The display driving circuit according to claim 5, characterized in that, The fourth-level control unit includes a twelfth transistor and a third leakage protection module; The control terminal of the twelfth transistor is connected to the second control node of the level maintenance unit to receive the second control signal; the first path terminal of the twelfth transistor is connected to the first control node; and the second path terminal of the twelfth transistor is used to receive the second reference voltage. The third leakage protection module includes a thirteenth transistor and a fourteenth transistor. The control terminal of the thirteenth transistor receives the second clock control signal, and the second path terminal of the twelfth transistor receives the second reference voltage through the path formed with the thirteenth transistor. The control terminal of the fourteenth transistor is connected to the first control node, the first path terminal of the fourteenth transistor receives the first reference voltage, and the second path terminal of the fourteenth transistor is connected to the path between the twelfth transistor and the thirteenth transistor.

7. The display driving circuit according to claim 5, characterized in that, The second level control unit includes a fifteenth transistor, a first capacitor, and a first output node. The control terminal of the fifteenth transistor is connected to the first control node, and the control terminal of the fifteenth transistor is also connected to the first output node through the first capacitor. The first path terminal of the fifteenth transistor receives a first clock control signal, and the second path terminal of the fifteenth transistor is connected to the first output node. The first level control unit connected to the first output node includes an eighteenth transistor. The control terminal of the eighteenth transistor is connected to the second control node to receive the second control signal. The first path terminal of the eighteenth transistor is connected to the first output node, and the second path terminal of the eighteenth transistor receives the second reference voltage. The third level control unit includes a sixteenth transistor, a second capacitor, and a second output node. The control terminal of the sixteenth transistor is connected to the second output node through the second capacitor. The first path terminal of the sixteenth transistor receives a third clock control signal, and the second path terminal of the sixteenth transistor is connected to the second output node. The first level control unit connected to the second output node includes a nineteenth transistor. The control terminal of the nineteenth transistor is connected to the second control node to receive the second control signal. The first path terminal of the nineteenth transistor is connected to the second output node, and the second path terminal of the nineteenth transistor receives the second reference voltage. The isolation unit includes a seventeenth transistor, the control terminal of which receives the first reference voltage, the first path terminal of which is connected to the control terminal of the fifteenth transistor, and the second path terminal of which is connected to the control terminal of the sixteenth transistor. Wherein, the capacitance value of the first capacitor is greater than 0 and less than or equal to 500fF, and the capacitance value of the second capacitor is greater than 0 and less than or equal to 300fF.

8. The display driving circuit according to claim 7, characterized in that, The display driving circuit uses an eight-phase clock to provide clock control signals for each clock; and / or, In the eight-phase clock, the k-th clock is advanced by T / 8 compared to the (k+1)-th clock, where 1 ≤ k < 8; and / or, The duty cycle of the high level in each clock control signal is T / 4; and / or, The phase difference between the first driving signal and the second driving signal is T / 8.

9. A display device, characterized in that, It includes a display panel and at least one display driving circuit as described in any one of claims 1 to 8, wherein each of the display driving circuits is electrically connected to the display panel to output a driving signal to drive the horizontal scan lines within the display panel.

10. The display device according to claim 9, characterized in that, The plurality of display driving circuits are connected in a multi-level cascading manner, and the plurality of display driving circuits are used to drive all or part of the pixel rows in the display panel; Each of the aforementioned display driving circuits is used to generate a first driving signal and a second driving signal to drive two pixel rows; The phase difference of the driving signals of adjacent pixel rows in the display panel is T / 8.

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