Piezoelectric device, method for manufacturing the same, and electronic device

Abstract

The embodiment of the application provides a piezoelectric device and a preparation method thereof and an electronic device, and relates to the technical field of piezoelectric devices. The piezoelectric device comprises a substrate, a transducer and a plated interconnection line. The substrate comprises a base layer and a thin film layer, the base layer comprises a first region and a second region, the thin film layer covers the first region, and the orthographic projection of the thin film layer on a reference plane is located outside the orthographic projection of the second region on the reference plane, the reference plane being a plane in which a length direction and a width direction of the substrate are located. The plated interconnection line comprises a first plated interconnection line part and a second plated interconnection line part, the first plated interconnection line part covers the second region, and the second plated interconnection line part covers the surface of the thin film layer. In this way, the reliability of the piezoelectric device can be improved, and the piezoelectric device will not fail.

Description

Technical Field

[0001] This application relates to the field of piezoelectric device technology, and in particular to a piezoelectric device, its preparation method, and an electronic device. Background Technology

[0002] Currently, piezoelectric devices, such as mobile phones, tablets, and televisions, incorporate piezoelectric components, including filters, to improve communication quality by filtering signals. Filters using multilayer thin-film substrates offer advantages over single-layer substrate filters, including higher energy efficiency, lower loss, lower temperature sensitivity, and wider bandwidth. However, due to the weak interfacial bonding of multilayer thin-film substrates, these filters suffer from low reliability and are prone to failure. Summary of the Invention

[0003] This application provides a piezoelectric device and its preparation method, as well as an electronic device, which can improve the reliability of the piezoelectric device and ensure that the piezoelectric device will not fail.

[0004] This application provides a piezoelectric device comprising a substrate and electroplated interconnects. The substrate includes a base layer and a thin film layer. The base layer includes a first region and a second region. The thin film layer covers the first region, and its orthographic projection onto a reference plane lies outside the orthographic projection of the second region onto the reference plane. The reference plane is a plane containing the length and width directions of the substrate. The electroplated interconnects include a first electroplated interconnect portion and a second electroplated interconnect portion. The first electroplated interconnect portion covers the second region, and the second electroplated interconnect portion covers the surface of the thin film layer.

[0005] In response to the problem of filter failure in traditional technologies, the inventors of this application, after careful analysis, discovered that filter failure is mainly a layered failure. The reasons for delamination include: 1. A mismatch between the coefficient of thermal expansion (CTE) of the encapsulation protective layer and the multilayer thin-film substrate. A large difference between their CTEs leads to significant stress and separation. 2. Low bonding strength between the encapsulation protective layer and the multilayer thin-film substrate, making them prone to separation. 3. The use of a cutting wheel to separate multiple filters during filter fabrication can cause chipping and crack propagation. To address the first two reasons, the inventors improved the CTE and bonding strength of the encapsulation protective layer, matching its CTE to that of the multilayer thin-film substrate and increasing their bonding strength. For the third reason, improvements to the cutting method, such as optimizing cutting precision, reducing blade wobble, increasing trimming frequency, and using laser cutting, can reduce chipping. However, even after these improvements, the modified filters still fail after reliability testing.

[0006] To address the issue of existing piezoelectric devices (such as filters) failing after reliability tests such as thermal cycling (TC) and thermal shock (TS), downstream manufacturing processes (e.g., molding), or long-term use, the inventors of this application, through careful analysis, discovered that filter failure is primarily due to delamination. The causes of delamination include: 1. Mismatch in the coefficient of thermal expansion (CTE) between the polyimide (PI) material and the substrate material. 2. Low bonding strength between the polyimide material and the substrate material. 3. The use of a cutting wheel to separate multiple filters during filter fabrication, leading to chipping and crack propagation. Regarding the first two causes, the inventors of this application have improved the CTE and bonding strength of the PI material to achieve CTE matching and enhance bonding strength. Regarding the third cause, chipping can be reduced by improving the cutting method, such as optimizing cutting precision, reducing blade wobble, increasing the trimming frequency, and using laser cutting instead. However, even after these improvements, the modified filter still fails after reliability testing.

[0007] Therefore, the inventors of this application further analyzed the improved filter and discovered that delamination occurs at fixed positions on the filter's edges, with the delamination concentrated at the substrate thin film interface. After careful analysis, the delamination was determined to be caused by structural defects in existing filters. Specifically, in existing filters, the electroplated interconnects are disposed on the surface of the thin film layer. During filter fabrication, the thin film layer between the electroplated interconnects and the substrate layer cannot be etched away. During cutting with a cutting wheel, the mechanical or thermal stress of the cutting wheel causes cracks and delamination at the thin film interface. These cracks propagate after reliability testing, downstream manufacturing processes, or long-term use, leading to device failure.

[0008] In view of this, this application provides a piezoelectric device (e.g., a filter) in which a thin film layer covers a first region, and the orthographic projection of the first region onto a reference plane is located outside the orthographic projection of the second region onto the reference plane. The reference plane is the plane containing the length and width directions of the substrate, i.e., the thin film layer covers the first region but not the second region; the first electroplated interconnect portion directly covers the second region of the substrate layer, i.e., there is no thin film layer between the first electroplated interconnect portion and the substrate layer. Therefore, during the fabrication process of the piezoelectric device, when the second electroplated interconnect portion between adjacent piezoelectric devices is cut by cutting, the thin film layer will not be cut. Thus, the thin film layer will not delaminate or crack, thereby improving the reliability of the piezoelectric device.

[0009] Therefore, the inventors of this application provide a new structure for a piezoelectric device that fundamentally avoids cracking and delamination of the thin film layer, improves the reliability of the piezoelectric device, and will not fail after undergoing reliability tests such as temperature cycling tests and temperature shock tests or after downstream production processes, thus ensuring the reliability of the device for long-term application.

[0010] In some possible implementations, the thin film layer includes a tilted body and a main body. The second electroplated interconnect portion includes a transition electroplated interconnect portion and a third electroplated interconnect portion, with both ends of the transition electroplated interconnect portion connected to the first electroplated interconnect portion and the third electroplated interconnect portion, respectively. The transition electroplated interconnect portion covers the tilted body, and the third electroplated interconnect portion covers the main body.

[0011] In this way, a transition electroplated interconnect section covered on the inclined body is provided between the first and third electroplated interconnect sections, allowing for a smooth transition of the electroplated interconnects. This avoids cracking and corrosion from residual chemicals at the step formed between the thin film layer and the substrate layer, and improves the uniformity of current density and electroplating height. Notably, current density and electroplating height are positively correlated; improved current sealing uniformity also leads to improved electroplating height uniformity.

[0012] In some possible implementations, the tilted body has a tilted surface, the main body has a mating surface, the tilted surface and the mating surface are connected, the angle between the tilted surface and the mating surface is an obtuse angle, and the angle between the surface of the substrate layer and the thin film layer in contact with the tilted surface is an acute angle. The transition electroplated interconnect portion covers the tilted surface, and the third electroplated interconnect portion covers the mating surface.

[0013] In this way, by tilting the inclined surface (or etched surface) of the thin film layer to the surface in contact with the substrate and the mating surface, cracking of electroplated interconnects at the step formed between the thin film layer and the substrate layer and corrosion by residual chemicals can be avoided, thereby improving the uniformity of current density and electroplating height.

[0014] In some possible implementations, the piezoelectric device also includes a cut surface, with the distance between the tilted body and the cut surface gradually increasing along the direction from the substrate to the body.

[0015] This avoids cracking of electroplated interconnects at the steps formed between the thin film layer and the substrate layer, and improves the uniformity of current density and electroplating height.

[0016] In some possible implementations, the thickness of the tilted body gradually increases in the thickness direction of the base layer along the direction from the cut surface to the tilted body.

[0017] This avoids cracking of electroplated interconnects at the steps formed between the thin film layer and the substrate layer, and improves the uniformity of current density and electroplating height.

[0018] In some possible implementations, the width of the first electroplated interconnect portion is greater than the width of the second electroplated interconnect portion.

[0019] This increases the effectiveness of the electrical connection between the electroplated interconnects and the conductive pillars of the piezoelectric device, reducing the transmission of mechanical stress. Furthermore, it reduces the effective resistance of the electroplated interconnects, improves the consistency of current density and plating height, thereby increasing the yield of the piezoelectric device.

[0020] In some possible implementations, the width of the first electroplated interconnect portion gradually increases along the direction from the first region to the second region, or the width of the second electroplated interconnect portion gradually increases.

[0021] This can further improve the consistency of current density and electroplating height.

[0022] In some possible implementations, the thin film layer includes a passivation film layer and a piezoelectric film layer, with the passivation film layer located between the piezoelectric film layer and the substrate layer, and a portion of the electroplated interconnects disposed on the surface of the piezoelectric film layer facing away from the passivation film layer.

[0023] In some possible implementations, the piezoelectric film layer is made of lithium tantalate or lithium niobate, and / or the passivation film layer is made of silicon dioxide.

[0024] In some possible implementations, the piezoelectric device further includes a transducer, a conductive sheet, a metal layer, and a conductive pillar. The transducer and the conductive sheet are both disposed on the surface of the thin film layer facing away from the substrate layer. The conductive sheet is electrically connected to the transducer. The metal layer covers the conductive sheet. The conductive pillar is located on the side of the metal layer facing away from the first surface. One end of the electroplated interconnect is electrically connected to the metal layer. The metal layer is electrically connected to the conductive sheet and the conductive pillar, respectively.

[0025] In some possible implementations, the substrate material is silicon, aluminum oxide, or silicon carbide.

[0026] A second aspect of this application provides a method for fabricating a piezoelectric device, wherein the piezoelectric device includes a substrate and electroplated interconnects, the substrate including a thin film layer and a base layer stacked thereon, and the method for fabricating the piezoelectric device includes:

[0027] The thin film layer in the cutting area is removed by etching.

[0028] Electroplated interconnects are formed on the surface of the thin film layer and on the first surface of the substrate layer within the cutting area.

[0029] In this way, by placing the etching process of the thin film layer before the formation of the electroplated interconnects, the electroplated interconnects come into contact with the substrate layer, thus avoiding the influence of cutting vibrations on the thin film layer.

[0030] In some possible implementations, the thin film layer in the cut area is removed by an etching process, including:

[0031] A protective adhesive layer is formed on the side of the thin film layer facing away from the substrate layer;

[0032] Remove the protective adhesive layer to create a notch;

[0033] The thin film layer inside the notch is removed by etching to form a tilted surface;

[0034] Remove the protective adhesive layer after the inclined surface is formed.

[0035] A third aspect of this application also provides an electronic device, which includes a piezoelectric device on a circuit board as described in any of the first aspects, the piezoelectric device being electrically connected to the circuit board. Attached Figure Description

[0036] Figure 1 An exploded schematic diagram of an electronic device provided in this application embodiment;

[0037] Figure 2 This is a cross-sectional schematic diagram of a filter in a traditional technology.

[0038] Figure 3 For filters in two conventional techniques Figure 2 A top-view cross-sectional view of the multilayer thin film substrate, conductive sheet, and metal layer at the dashed line in the middle;

[0039] Figure 4 for Figure 3 A cross-sectional view along the CC direction;

[0040] Figure 5 A cross-sectional schematic diagram of a piezoelectric device provided in an embodiment of this application;

[0041] Figure 6 for Figure 5 A top-view cross-sectional view of the substrate, conductive sheet, and metal layer at point O;

[0042] Figure 7 for Figure 5 Enlarged view of point P in the middle;

[0043] Figure 8 A top cross-sectional view of the substrate, conductive sheet, and metal layer of another piezoelectric device provided in an embodiment of this application;

[0044] Figure 9A This is a first schematic diagram illustrating a method for fabricating a piezoelectric device according to an embodiment of this application.

[0045] Figure 9B This is a second schematic diagram illustrating a method for fabricating a piezoelectric device according to an embodiment of this application;

[0046] Figure 9C A third schematic diagram illustrating a method for fabricating a piezoelectric device according to an embodiment of this application;

[0047] Figure 9D This is a fourth schematic diagram illustrating a method for fabricating a piezoelectric device according to an embodiment of this application;

[0048] Figure 9E This is a fifth schematic diagram illustrating a method for fabricating a piezoelectric device according to an embodiment of this application;

[0049] Figure 9F The sixth schematic diagram illustrates a method for fabricating a piezoelectric device according to an embodiment of this application;

[0050] Figure 9G The seventh schematic diagram illustrates a method for fabricating a piezoelectric device according to an embodiment of this application;

[0051] Figure 9H This is the eighth schematic diagram of a method for fabricating a piezoelectric device according to an embodiment of this application.

[0052] Explanation of reference numerals in the attached figures:

[0053] 100. Piezoelectric devices;

[0054] 110. Base layer; 111. First surface; 1111. First region; 1112. Second region;

[0055] 120. Thin film layer; 121. Piezoelectric film layer; 122. Passivation film layer; 123. Inclined surface; 124. Mating surface; 126. Inclined surface; 127. Inclined body; 1271. Inclined subbody; 128. Main body; 1281. Main subbody;

[0056] 130. Transducer; 140. Electroplated interconnect; 141. First electroplated interconnect section; 142. Second electroplated interconnect section; 1421. Transition electroplated interconnect section; 1422. Third electroplated interconnect section;

[0057] 150. Conductive sheet; 160. Metal layer; 170. Conductive pillar; 180. Solder ball; 190. Encapsulation protective layer;

[0058] 200. Display screen; 300. Mid-frame; 400. Back cover; 500. Battery; 600. Circuit board assembly; 700. Circuit board;

[0059] 10. Protective adhesive layer; 20. Metal interconnect layer;

[0060] X: length direction; Y: width direction; Z: thickness direction. Detailed Implementation

[0061] This application provides an electronic device, which can be a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, or a communication electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc.

[0062] For example, the following explanation uses a mobile phone as an example of an electronic device. Figure 1 As shown, Figure 1 This is a schematic diagram of an exploded electronic device provided in an embodiment of this application.

[0063] See also Figure 1 As shown, the electronic device may include a display screen 200, a mid-frame 300, a back cover 400, a battery 500, and a circuit board assembly 600. The back cover 400 and the display screen 200 are located on opposite sides of the mid-frame 300, forming an accommodating space with the mid-frame 300. The accommodating space houses components such as the battery 500, the circuit board assembly 600, and a camera module.

[0064] The display screen 200 can be a liquid crystal display (LCD), an organic light emitting diode (OLED) display screen, etc.

[0065] like Figure 1 As shown, the circuit board assembly 600 may include a circuit board 700, a piezoelectric device 100, etc. The circuit board 700 may be a printed circuit board (PCB). The circuit board 700 is used to carry the piezoelectric device 100 and is electrically connected to the piezoelectric device 100.

[0066] Among them, the piezoelectric device 100 can be a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a film bulk acoustic resonator (FBAR), a laterally excited bulk acoustic resonator (XBAR), a surface acoustic wave delay line, a surface acoustic wave convolutional device, a surface acoustic wave sensor, etc.

[0067] The following explanation uses piezoelectric device 100 as an example of a filter. Piezoelectric device 100 is used to pass signals of a specific frequency while blocking signals of other frequencies, thereby improving signal quality.

[0068] In addition, the piezoelectric device 100 can be packaged in the form of wafer-level package (WLP), wafer-level chip-scale package (WLCSP), and chip-scale package (CSP).

[0069] Figure 2 This is a cross-sectional schematic diagram of a filter in traditional technology. Figure 3 For filters in two conventional techniques Figure 2 A top-view cross-sectional view showing the combination of the multilayer thin-film substrate, conductive sheet, and metal layer at the dashed line. Figure 4 for Figure 3 A cross-sectional view along the CC direction. Figure 3 and Figure 4 In the diagram, A represents the cutting area, and B represents the etched surface of the thin film layer 720.

[0070] In traditional technologies, such as Figure 2As shown, the filter 100' includes a multilayer thin-film substrate 700, electroplated interconnects 730, a metal layer 740, conductive pillars 750, interdigitated transducers 760, an encapsulation protective layer 770, conductive sheets 780, and solder balls 790. The multilayer thin-film substrate 700 includes a substrate layer 710 and a thin-film layer 720 stacked together. The substrate layer 710 is made of silicon. The thin-film layer 720 includes a passivation layer 722 and a piezoelectric layer 721 stacked together. The passivation layer 722 is located between the substrate layer 710 and the piezoelectric layer 721. The piezoelectric layer 721 is made of lithium tantalate (LiTaO, abbreviated as LT), and the passivation layer 722 is made of silicon dioxide (SiO2). Both the interdigital transducer (IDT) 760 and the conductive sheet 780 are disposed on the surface of the piezoelectric layer 721. A metal layer 740 covers the conductive sheet 780. A conductive post 750 is located on the side of the metal layer 740 facing away from the conductive sheet 780, with its two ends connected to a solder ball 790 and the metal layer 740, respectively. One end of an electroplated interconnect 730 is electrically connected to the metal layer 740. The electroplated interconnect 730 is located between the encapsulation protective layer 770 and the thin film layer 720; that is, the electroplated interconnect 730 is disposed on the surface of the thin film layer 720 facing away from the substrate layer 710, with a portion of the thin film layer 720 located between the electroplated interconnect 730 and the substrate layer 710. During the fabrication of the filter 100', through an electroplating process, the electroplated interconnect 730 transfers electrons to the metal layer 740, thereby generating the conductive post 750 on the side of the metal layer 740 facing away from the thin film layer 720. The encapsulation protective layer 770 is made of polyimide (PI) material, and the encapsulation protective layer 770 and the multilayer thin film substrate 700 form a cavity to accommodate the IDT.

[0071] In the conventional fabrication process of filter 100', electroplated interconnects 730 are first fabricated on the surface of thin film layer 720 facing away from substrate layer 710, and then a portion of thin film layer 720 is removed by etching (e.g., removing the substrate layer 710). Figure 3 or Figure 4 Thin film layer 720 in region A) to form a cut area (e.g. Figure 4 or Figure 5 As shown in Figure A), the substrate layer 710, electroplated interconnects 730, and thin film layer 720 located within the cutting area are finally cut using a cutting wheel to obtain multiple layers as shown in Figure A. Figure 2 The filter shown is 100'.

[0072] However, due to the weak bonding of the multilayer thin film substrate 700, the reliability of the filter 100' in the conventional technology is low. The filter 100' in the conventional technology will fail after undergoing reliability tests such as thermal cycling (TC) and thermal shock (TS), or after downstream production processes (such as molding), or after long-term use.

[0073] Regarding the failure problem of filter 100' in conventional technology, the inventors of this application, after careful analysis, found that the failure of filter 100' is mainly delamination failure. The reasons for delamination are as follows: 1. The coefficient of thermal expansion (CTE) of the encapsulation protective layer 770 is mismatched with that of the multilayer thin film substrate 700. The difference between the CTE of the encapsulation protective layer 720 and the multilayer thin film substrate 700 is too large, easily generating significant stress between them and leading to separation. 2. The bonding strength between the encapsulation protective layer 770 and the multilayer thin film substrate 700 is low, making them prone to separation. 3. During the fabrication process of filter 100', multiple filters 100' are separated by a cutting wheel, which causes chipping. The issues include crack propagation, etc. To address the first two reasons, the inventors of this application improved the thermal expansion coefficient (CTE) and adhesion of the encapsulation protective layer 770 material, allowing the thermal expansion coefficient of the encapsulation protective layer 770 to match that of the multilayer thin film substrate 700, and improving the adhesion between the encapsulation protective layer 770 and the multilayer thin film substrate 700. Regarding the third reason, improvements to the cutting method, such as optimizing cutting precision, reducing blade wobble, increasing the trimming frequency, and using laser cutting instead, can reduce chipping. However, even after these improvements, the improved filter 100' still failed after reliability testing.

[0074] Therefore, the inventors of this application further analyzed the improved filter 100' and found that delamination occurred at the fixed edge position of the filter 100', with the delamination concentrated at the substrate thin film interface. After careful analysis, the delamination was determined to be caused by structural defects in the filter 100' of the conventional technology. Specifically, as... Figure 4As shown, in conventional technology, the electroplated interconnects 730 of the filter 100' are disposed on the surface of the thin film layer 720. During the etching process of the thin film layer 720, the thin film layer located between the electroplated interconnects 730 and the substrate layer 710 cannot be etched away. As a result, during the cutting process of the cutting wheel, the mechanical stress or thermal stress of the cutting wheel will cause cracks and delamination at the thin film interface of the thin film layer 720. After the cracks have undergone reliability testing, or after downstream production processes, or after long-term use, they will propagate and cause device failure.

[0075] In view of this, the inventors of this application provide a piezoelectric device 100 with a new structure, which fundamentally avoids cracking and delamination of the thin film layer 120, improves the reliability of the piezoelectric device 100, and will not fail after undergoing reliability tests such as temperature cycling tests and temperature shock tests or after downstream production processes, thus ensuring the reliability of the device for long-term application.

[0076] Figure 5 This is a cross-sectional schematic diagram of a piezoelectric device provided in an embodiment of this application. Figure 6 for Figure 5 A top-view cross-sectional view showing the assembly of the substrate, conductive sheet, and metal layer at point O. Figure 7 for Figure 5 An enlarged schematic diagram of point P in the middle. Wherein, Figures 5 to 7 This is only used to illustrate the structure of the piezoelectric device 100 and does not constitute a limitation on the specific structure of the piezoelectric device 100.

[0077] like Figure 5 As shown, the piezoelectric device 100 provided in this embodiment may include a substrate, a transducer 130, electroplated interconnects 140, a conductive pad 150, a metal layer 160, conductive pillars 170, solder balls 180, and an encapsulation protective layer 190. The substrate includes a base layer 110 and a thin film layer 120. The base layer 110 includes a first surface 111 and a second surface disposed opposite to each other. The thin film layer 120 is disposed on the first surface 111 of the base layer 110.

[0078] In this embodiment, the thin film layer 120 may include multiple stacked thin films, for example... Figure 7 As shown, the thin film layer 120 may include two thin films stacked together. Of course, the thin film layer 120 may also be composed of more than two thin films.

[0079] For example, such as Figure 7 As shown, the thin film layer 120 may include a passivation film layer 122 and a piezoelectric film layer 121. The passivation film layer 122 is located between the piezoelectric film layer 121 and the substrate layer 110. The transducer 130 is disposed on the surface of the piezoelectric film layer 121 facing away from the passivation film layer 122. A portion of the electroplated interconnect line 140 is disposed on the surface of the piezoelectric film layer 121 facing away from the passivation film layer 122.

[0080] In some examples, the passivation film 122 may also be referred to as a passivation layer. Additionally, in some embodiments, the piezoelectric film 121 may also be referred to as a piezoelectric layer or a piezoelectric material.

[0081] In some embodiments, the passivation film 122 can be made of silicon dioxide. Since silicon dioxide has good temperature drift characteristics, it can improve the overall temperature drift characteristics of the piezoelectric device 100, thereby enhancing the performance of the piezoelectric device 100. Of course, the passivation film 122 can also be made of other materials, such as quartz.

[0082] In some embodiments, the piezoelectric film layer 121 may be made of lithium tantalate (LiTaO3, abbreviated as LT) or lithium niobate (LiNbO3, abbreviated as LN). Of course, the piezoelectric film layer 121 may also be made of other materials. In addition, the piezoelectric film layer 121 may be a single-layer structure or a multi-layer structure.

[0083] The substrate layer 110 provides support for the thin film layer 120, ensuring the overall strength of the piezoelectric device 100. The substrate layer 110 can be made of materials such as silicon, aluminum oxide, silicon carbide, sapphire, or quartz. When monocrystalline silicon is used as the substrate layer 110, a layer of polycrystalline silicon is placed on top as a trap-rich layer for carrier capture.

[0084] See also Figure 5 As shown, both the conductive sheet 150 and the transducer 130 are disposed on the surface of the thin film layer 120 facing away from the first surface 111, and the conductive sheet 150 is electrically connected to the transducer 130. A metal layer (also referred to as a thickening layer) 160 covers the conductive sheet 150 and is electrically connected to it. The conductive post 170 can also be called under-bump metallization (UBM). The conductive post 170 is located on the side of the metal layer 160 facing away from the first surface 111, with one end connected to the metal layer 160 and the other end connected to the solder ball 180.

[0085] For example, transducer 130 can be an interdigital transducer (IDT). An interdigital transducer has a metal pattern shaped like the crossed fingers of two hands formed on the surface of thin film layer 120, and its function is to achieve acoustic-to-electrical energy conversion. Furthermore, the interdigital transducer can also act as a filter. In this embodiment, the metal material and processing method used for the interdigital transducer are not particularly limited. As an example, the interdigital transducer can be fabricated using a lift-off process. As another example, to suppress stray modes, the metal material used in the interdigital transducer can be a high-density metal such as Au, Ta, W, or Cu. As yet another example, the surface of the interdigital transducer is covered with a thin passivation layer, such as SiO2, to isolate moisture and improve reliability.

[0086] The conductive post 170 is made of a conductive material. For example, the conductive post 170 can be a copper post, in which case the material of the conductive post 170 is copper.

[0087] like Figure 5 As shown, the encapsulation protective layer 190 covers the surface of the electroplated interconnect 140, the surface of the metal layer 160 not covered by the conductive pillar 170, and part of the surface of the substrate. The encapsulation protective layer 190 and the substrate form a cavity to accommodate the transducer 130. The conductive pillar 170, the electroplated interconnect 140, the metal layer 160, and the conductive sheet 150 are all located inside the encapsulation protective layer 190.

[0088] The encapsulation protective layer 190 has a through-hole, and a conductive post 170 is disposed inside the through-hole. The metal layer 160 can be exposed through the through-hole and electrically connected to the conductive post 170. The encapsulation protective layer 190 can prevent moisture or external environmental factors from affecting the internal structure of the piezoelectric device 100, thereby improving the reliability of the piezoelectric device 100. In addition, the encapsulation protective layer 190 and the substrate can form a cavity to accommodate the transducer 130.

[0089] The packaging protection layer 190 can be a packaging structure formed by packaging forms such as wafer-level package (WLP), wafer-level chip-scale package (WLCSP), and chip-scale package (CSP). No specific restrictions are placed on the specific structure of the packaging protection layer 190.

[0090] like Figure 6As shown, the substrate layer 110 includes a first region 1111 and a second region 1112. The orthographic projections of the first region 1111 and the second region 1112 onto a reference plane do not overlap. The reference plane is the plane containing the length direction X and the width direction Y of the substrate. The thin film layer 120 covers the first region 1111, and the orthographic projection of the thin film layer 120 onto the reference plane is located outside the orthographic projection of the second region 1112 onto the reference plane.

[0091] The first region 1111 can be understood as the region on the first surface 111 covered by the thin film layer 120. The second region 1112 can be understood as the region on the first surface 111 that is not covered by the thin film layer 120, or in other words, the second region 1112 can also be understood as the region where the substrate layer 110 is exposed.

[0092] like Figure 5 As shown, the electroplated interconnect 140 includes a first electroplated interconnect portion 141 and a second electroplated interconnect portion 142. The first electroplated interconnect portion 141 covers the second region 1112, and its orthographic projection on the reference plane is located outside the orthographic projection of the first region 1111 on the reference plane. The second electroplated interconnect portion 142 covers the surface of the thin film layer 120 and is electrically connected to the metal layer 160. Its orthographic projection on the reference plane is located outside the second region 1112. Therefore, a portion of the electroplated interconnect 140 is disposed on the first surface 111, and another portion is disposed on the surface of the thin film layer 120.

[0093] Since the first electroplated interconnect portion 141 is disposed on the first surface 111 of the substrate layer 110, during the fabrication process of the piezoelectric device 100, the thin film layer 120 is first etched to expose a portion of the first surface 111 of the substrate layer 110, and then the electroplated interconnect 140 is formed, so that a portion of the electroplated interconnect 140 is disposed on the first surface 111.

[0094] By covering the first region 111 with the thin film layer 120, and having its orthographic projection on the reference plane located outside the orthographic projection of the second region 1112 on the reference plane, i.e., the thin film layer 120 covers the first region 1111 but not the second region 1112; and by directly covering the second region 1112 of the substrate layer 110 with the first electroplated interconnect portion 141, i.e., there is no thin film layer 120 between the first electroplated interconnect portion 141 and the substrate layer 110, the etched surface of the thin film layer 120 (such as...) Figure 7If there is no thin film layer 120 between the cut surface B of the piezoelectric device 100 and the cut surface B of the piezoelectric device 100, then during the fabrication process of the piezoelectric device 100, the first electroplated interconnection portion 141 between adjacent piezoelectric devices 100 is cut off by cutting. When the electroplated interconnection 140 between two adjacent piezoelectric devices 100 is separated, the thin film layer 120 will not be subjected to cutting vibration, and the thin film layer 120 will not delaminate or crack, which can improve the reliability of the piezoelectric device 100.

[0095] The etched surface of the thin film layer 120 can be understood as the surface formed after etching the thin film layer 120. The purpose of etching the thin film layer 120 is to prevent the thin film layer 120 from contacting the cutting equipment (e.g., a cutting wheel) during the cutting process, thus preventing the thin film layer 120 from delaminating. Additionally, the thin film layers 120 of multiple piezoelectric devices 100 are separated to obtain multiple piezoelectric devices 100 simultaneously. Furthermore, the cutting surface B of the piezoelectric device 100 is the surface formed after separating the multiple piezoelectric devices 100 through a cutting process.

[0096] like Figure 7 As shown, due to the etched surface of the thin film layer 120 (such as...) Figure 7 As shown in Figure 123, a stepped structure is formed between the etched surface and the first surface 111 of the substrate 110. When the angle between the etched surface and the first surface 111 is close to a 90° right angle, the electroplated interconnect 140, when grown at the stepped structure, is prone to defects such as cracking and breakage. This leads to increased resistance and decreased current density of the electroplated interconnect 140, resulting in poor current density consistency across the entire surface and poor electroplating height consistency, thus reducing the yield and reliability of the piezoelectric device 100. The current density consistency is positively correlated with the electroplating height consistency, where electroplating height refers to the height of the conductive pillar 170 generated by the electroplating process.

[0097] In view of this, in some possible implementations, such as Figure 7 As shown, the thin film layer may include a tilted body 127 and a main body 128. The second electroplated interconnect portion 142 includes a transition electroplated interconnect portion 1421 and a third electroplated interconnect portion 1422. The two ends of the transition electroplated interconnect portion 1421 are connected to the first electroplated interconnect portion 141 and the third electroplated interconnect portion 1422, respectively. The transition electroplated interconnect portion 1421 covers the tilted body 127, and the third electroplated interconnect portion 1422 covers the main body 128. The tilted body 127 allows the electroplated interconnect 140 to smoothly transition at the step formed between the thin film layer 120 and the substrate layer 110, reducing or eliminating cracking or breakage defects at the corresponding growth positions of the electroplated interconnect 140, ensuring that the resistance of the electroplated interconnect 140 does not increase and the current density does not decrease, thereby improving the current density uniformity of the entire surface, improving the electroplating height uniformity, and improving the yield and reliability of the piezoelectric device 100.

[0098] The cross-section of the inclined body 127 is similar to a right triangle, and the cross-section of the inclined body 127 is perpendicular to the base layer 110.

[0099] In some embodiments, such as Figure 7 As shown, the inclined body 127 has an inclined surface 123, and the main body 128 has a mating surface 124. The inclined surface 123 is connected to the mating surface 124, and the inclined surface 123 is located between the mating surface 124 and the first surface 111. The included angle between the inclined surface 123 and the mating surface 124 is (e.g., ...). Figure 7 (As shown in F) is an obtuse angle, the angle between the first surface 111 where the substrate layer 110 and the thin film layer 120 contact and the inclined surface 123 (as shown in F) is an obtuse angle. Figure 7 (As shown in E) is an acute angle. The transition electroplated interconnect portion 1421 covers the inclined surface 123, and the third electroplated interconnect portion 1422 covers the mating surface 124. The conductive sheet 150 and the transducer 130 are both disposed on the mating surface 124.

[0100] In this way, by tilting the inclined surface 123 (or etched surface) of the thin film layer to the first surface 111 where the substrate and the thin film layer 120 contact, and to the mating surface 124, cracking of the electroplated interconnect 140 at the step formed between the thin film layer 120 and the substrate layer 110 and corrosion by residual chemicals can be avoided, thereby improving the uniformity of current density and the uniformity of electroplating height.

[0101] It should be noted that the inclined surface 123 is not an absolutely flat plane, but a relatively flat plane. In this case, the angle between the inclined surface 123 and the first surface 111 can be understood as the maximum angle between any point on the inclined surface 123 and the first surface 111. Similarly, the angle between the inclined surface 123 and the mating surface 124 can be understood as the maximum angle between any point on the inclined surface 123 and the mating surface 124.

[0102] The angle between the inclined surface 123 and the first surface 111 is not specifically limited here. For example, the angle between the inclined surface 123 and the first surface 111 can be less than or equal to 60°, so that the electroplated interconnect 140 transitions more smoothly between the first surface 111 and the inclined surface 123, which can further reduce the probability of defects such as cracking or breakage of the electroplated interconnect 140.

[0103] It should be noted that the angle between the inclined surface 123 and the first surface 111 can also exceed 60°. For example, the angle between the inclined surface 123 and the first surface 111 can also be 65°, 70°, 80°, etc.

[0104] The angle between the inclined surface 123 and the mating surface 124 is not specifically limited here. For example, the angle between the inclined surface 123 and the mating surface 124 can be greater than or equal to 120°, so that the electroplated interconnect 140 transitions more smoothly between the mating surface 124 and the inclined surface 123, which can further reduce the probability of defects such as cracking or breakage of the electroplated interconnect 140.

[0105] It should be noted that the angle between the inclined surface 123 and the mating surface 124 can also be less than 120°. For example, the angle between the inclined surface 123 and the mating surface 124 can also be 110°, 115°, 118°, etc.

[0106] In some embodiments, see continue to see Figure 7 As shown, the piezoelectric device 100 also includes a cut surface B along the direction from the substrate layer 110 to the body 128 (e.g., Figure 7 (in the Z direction), the distance between the inclined body 127 and the cutting surface B (e.g., in the Z direction), Figure 7 The gradual increase in the height of the plating layer (as shown in the middle L) can prevent the electroplated interconnect 140 from cracking at the step formed between the thin film layer 120 and the substrate layer 110, thereby improving the uniformity of current density and plating height.

[0107] In some embodiments, see continue to see Figure 7 As shown, along the direction from the cutting surface B to the inclined body 127 (e.g.) Figure 7 The thickness of the inclined body 127 in the thickness direction of the base layer 110 (e.g., in the X direction), is as follows: Figure 7 The gradual increase in the height of H (as shown in the middle) can prevent the electroplated interconnect 140 from cracking at the step formed between the thin film layer 120 and the substrate layer 110, thereby improving the uniformity of current density and electroplating height.

[0108] See also Figure 7 As shown, the tilted body 127 includes a plurality of tilted sub-body 1271 arranged along the thickness direction of the substrate layer 110, and the main body 128 includes a plurality of main sub-body 1281 arranged along the thickness direction of the substrate layer 110. Thus, each film includes one tilted sub-body 1271 and one main sub-body 1281.

[0109] Among them, such as Figure 7 As shown, each inclined sub-body 1271 has an inclined surface that contacts the transition electroplated interconnect portion 1421, and all inclined surfaces 126 together constitute an inclined surface 123. The angle between the inclined surface 126 and the mating surface 124 is an obtuse angle, and the angle between the first surface 111, which contacts the substrate layer 110 and the thin film layer 120, and the inclined surface 126 is an acute angle. This can prevent the electroplated interconnect 140 from cracking at the step formed between the thin film layer 120 and the substrate layer 110, and improve the uniformity of current density and electroplating height.

[0110] It should be noted that the inclined surface 126 is not an absolutely flat plane, but a relatively flat plane. In this case, the angle between the inclined surface 126 and the first surface 111 can be understood as the maximum angle between any point on the inclined surface 126 and the first surface 111. Similarly, the angle between the inclined surface 126 and the mating surface 124 can be understood as the maximum angle between any point on the inclined surface 126 and the mating surface 124.

[0111] In some embodiments, the angle between the inclined surface 126 and the first surface 111 may be less than or equal to 60°. Of course, the angle between the inclined surface 126 and the first surface 111 may be greater than 60°.

[0112] In some embodiments, the included angles between two adjacent inclined surfaces 126 and the first surface 111 may be different, for example... Figure 5 As shown, the thin film layer 120 may include a piezoelectric film layer 121 and a passivation film layer 122. The angle between the inclined surface 126 of the piezoelectric film layer 121 and the first surface 111 can be smaller than the angle between the inclined surface 126 of the passivation layer and the first surface 111. This reduces the manufacturing difficulty of the inclined surface 126 of different films, thereby reducing the manufacturing difficulty of the inclined surface 123 of the thin film layer 120.

[0113] Of course, in some embodiments, the angle between the inclined surface 126 of two adjacent films and the first surface 111 may be the same, except that the angle between the inclined surface 126 of two adjacent films and the first surface 111 may be different.

[0114] In some embodiments, the angle between the inclined surface 126 and the mating surface 124 may be greater than or equal to 120°. Of course, the angle between the inclined surface 126 and the mating surface 124 may be less than 120°.

[0115] In some embodiments, see continue to see Figure 7 As shown, along the direction from the base layer 110 to the main body 128 (e.g.) Figure 7 (in the Z direction), the distance between the inclined subbody 1271 and the cutting surface B (e.g., in the Z direction), Figure 7 The M-shaped platen gradually increases in size, which can prevent the electroplated interconnect 140 from cracking at the step formed between the thin film layer 120 and the substrate layer 110, and improve the uniformity of current density and electroplating height.

[0116] In some embodiments, see continue to see Figure 7 As shown, along the direction from the cutting surface B to the inclined body 127 (e.g.) Figure 7 The thickness of the tilted subbody 1271 in the thickness direction of the base layer 110 (e.g., in the X direction), is as follows: Figure 7The height of the plated interconnect 140 gradually increases (as shown in the figure), which can prevent the plated interconnect 140 from cracking at the step formed between the thin film layer 120 and the substrate layer 110, and improve the uniformity of current density and plated height.

[0117] Figure 8 This is a top cross-sectional view of the substrate, conductive sheet, and metal layer of another piezoelectric device provided in an embodiment of this application. Figure 8 This is only used to illustrate the width variation relationship of the electroplated interconnect 140 and does not limit the specific structure of the electroplated interconnect 140.

[0118] To further improve current density consistency, in some possible implementations, the width of the first electroplated interconnect portion 141 is greater than the width of the second electroplated interconnect portion 142. Specifically, that is, as... Figure 8 As shown, the width of the first electroplated interconnect portion 141 located to the left of the boundary line between the first region 1111 and the second region 1112 is greater than the width of the second electroplated interconnect portion 142 located to the right of the boundary line between the first region 1111 and the second region 1112. This allows for maximum utilization of the length or width of the substrate layer 110, thereby increasing the width of the electroplated interconnect 140, reducing the electroplating of the interconnect 140, improving the uniformity of current density across the entire surface, improving the uniformity of plating height, and increasing the yield of the piezoelectric device 100. Furthermore, it can also increase the effectiveness of the electrical connection between the electroplated interconnect 140 and the conductive post 170.

[0119] In some embodiments, such as Figure 8 As shown, along the direction from the first region 1111 to the second region 1112 (e.g.) Figure 8 In the Y direction, the width of the first electroplated interconnect portion 141 gradually increases, which can further improve the consistency of current density and the consistency of electroplating height.

[0120] Of course, the width design of the first electroplated interconnect section 141, in addition to... Figure 8 In addition to the above, in other embodiments, the first electroplated interconnect portion 141 may also be a design with equal width.

[0121] In some embodiments, such as Figure 8 As shown, along the direction from the first region 1111 to the second region 1112 (e.g.) Figure 8 In the Y direction, the width of the second electroplated interconnect portion 142 gradually increases, which can further improve the consistency of current density and the consistency of electroplating height.

[0122] Figure 9A This is a first schematic diagram of a method for fabricating a piezoelectric device according to an embodiment of this application. Figure 9B This is a second schematic diagram illustrating a method for fabricating a piezoelectric device according to an embodiment of this application. Figure 9C This is a third schematic diagram illustrating a method for fabricating a piezoelectric device according to an embodiment of this application. Figure 9D This is a fourth schematic diagram illustrating a method for fabricating a piezoelectric device according to an embodiment of this application. Figure 9E This is a fifth schematic diagram illustrating a method for fabricating a piezoelectric device according to an embodiment of this application. Figure 9F This is a sixth schematic diagram illustrating a method for fabricating a piezoelectric device according to an embodiment of this application. Figure 9G This is the seventh schematic diagram of a method for fabricating a piezoelectric device according to an embodiment of this application. Figure 9H This is the eighth schematic diagram of a method for fabricating a piezoelectric device according to an embodiment of this application.

[0123] This application also provides a method for fabricating a piezoelectric device 100, which can be used to fabricate the piezoelectric device 100 provided in this application. The method for fabricating the piezoelectric device 100 includes the following steps:

[0124] S101, Prepare the intermediate layer.

[0125] First, a substrate is provided, comprising a base layer 110 and a thin film layer 120 stacked together. Then, a conductive layer is formed on the surface of the thin film layer 120 facing away from the base layer 110. Next, a conductive sheet 150 and a transducer 130 are formed on the surface of the thin film layer 120 facing away from the base layer 110 using semiconductor processes such as spin coating, exposure, development, evaporation, magnetron sputtering, or lift-off, to obtain... Figure 9A The intermediate layer shown.

[0126] The conductive layer can be made of a conductive metal, or other conductive materials. Additionally, the substrate layer 110 can be made of silicon, aluminum oxide, silicon carbide, sapphire, quartz, etc. The thin film layer 120 may include a passivation film layer 122 and a piezoelectric film layer 121 stacked together. The passivation film layer 122 can be made of silicon dioxide, and the piezoelectric film layer 121 can be made of lithium-ion (LT). The transducer 130 is an integrated dielectric transducer (IDT).

[0127] It should be noted that, in addition to fabricating the transducer 130 and conductive sheet 150 in the order of "spraying, exposure, development, evaporation or magnetron sputtering, lift-of", they can also be fabricated in the order of evaporation or magnetron sputtering followed by spraying, exposure, development, etching, and resist removal. Figure 9A The intermediate layer shown.

[0128] S102. The thin film layer 120 in the cutting area is removed by etching process to form an inclined surface 123.

[0129] Specifically, in the area corresponding to the cutting path, part or all of the thin film layer 120 can be removed by a dry etching process, so that the thin film layer 120 in the cutting area is removed, exposing the first surface 111 of the substrate layer 110. At the same time, the angle between the etched surface (tilted surface 123) of the thin film layer 120 and the first surface 111 is set to an acute angle. For example, the angle between the etched surface and the first surface 111 can be 65°, or other angles.

[0130] In some embodiments, the angle between the etched surface (tilted surface 123) of the thin film layer 120 and the first surface 111 can be set to an acute angle by adjusting techniques such as spin coating, development, and etching. Specifically, this may include the following steps:

[0131] S1021, Form a protective adhesive layer 10 on the side of the thin film layer 120 facing away from the substrate layer 110, such as Figure 9B As shown.

[0132] Specifically, a protective adhesive layer 10 can be formed through a spin coating process to obtain, as shown in the figure. Figure 9B The structure shown. The thickness of the protective adhesive layer 10 can be 2–10 μm. The material of the protective adhesive layer 10 can be photoresist.

[0133] S1022, Remove part of the protective adhesive layer 10 to form a notch (e.g., Figure 9C (as shown in the middle U).

[0134] Specifically, through the development process, the exposure intensity, focal point, and development conditions are adjusted to make the cross-section of the developed protective layer 10 have a top-cut shape, forming a notch (such as...). Figure 9C As shown in Figure U), the result is as follows: Figure 9C The structure shown.

[0135] S1023. The thin film layer 120 inside the notch is removed by etching process to form an inclined surface 123.

[0136] Specifically, the thin film layer 120 not protected by the protective adhesive layer 10 can be removed by etching using methods such as dry etching (e.g., ICP etching, RIE, etc.), forming an inclined surface 123 tilted to the first surface 111, resulting in... Figure 9D The structure shown.

[0137] S1024. After forming the inclined surface 123, remove the protective adhesive layer 10 to obtain the following: Figure 9E The structure shown.

[0138] S103. The metal interconnect layer 20 is formed using semiconductor processes such as spin coating, exposure, development, evaporation, or magnetron sputtering. Alternatively, the metal interconnect layer 20 can be prepared by first evaporating or magnetron sputtering, followed by spin coating, exposure, development, etching, and resist removal, to obtain the desired result. Figure 9F The structure shown.

[0139] Specifically, the metal interconnect layer 20 includes electroplated interconnects 140 and a metal layer 160, with the metal layer 160 electrically connected to the electroplated interconnects 140. Therefore, in some embodiments, the metal layer 160 and the electroplated interconnects 140 can be formed simultaneously using semiconductor processes such as spin coating, exposure, development, evaporation, or magnetron sputtering. Alternatively, the metal layer 160 and the electroplated interconnects 140 can be fabricated separately.

[0140] S104. Form a top cover assembly, the top cover assembly including an encapsulation protective layer 190, conductive pillars 170 and solder balls 180, to obtain as shown in the figure. Figure 9G The structure shown.

[0141] Specifically, a corresponding encapsulation protective layer 190 can be formed according to the corresponding encapsulation form, without limitation. In addition, the encapsulation protective layer 190 may include a two-layer structure, and the encapsulation protective layer 190 and the substrate can form a cavity to accommodate the transducer 130.

[0142] Electrons are transferred to the metal layer 160 using electroplated interconnects 140, and then conductive pillars 170 are electroplated on the surface of the metal layer 160 facing away from the thin film layer 120 using an electroplating process. After the conductive pillars 170 are formed, solder balls 180 are connected to the side of the conductive pillars 170 facing away from the metal layer 160.

[0143] S105. Cut the layer structure within the cutting area to obtain multiple piezoelectric devices 100.

[0144] Specifically, at least one of wheel cutting and laser cutting can be used to cut the electroplated interconnects 140, the base layer 110, and the encapsulation protective layer 190 within the cutting area, for example... Figure 9H As shown, through the cutter wheel (such as...) Figure 9H The piezoelectric device 100 is cut as shown in Figure R, so that multiple piezoelectric devices 100 are separated to obtain multiple piezoelectric devices 100.

[0145] Therefore, in the fabrication process of the piezoelectric device 100, the etching process of the thin film layer 120 precedes the process of fabricating the electroplated interconnects 140. This can result in a piezoelectric device 100 without the thin film layer 120 below the electroplated interconnects 140 in the cutting area, thus the cutting process will not affect the thin film layer 120.

[0146] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0147] The devices or elements referred to in the embodiments of this application or implied herein must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the embodiments of this application. In the description of the embodiments of this application, "a plurality of" means two or more, unless otherwise precisely specified.

[0148] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the present application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0149] The term "multiple" in this article refers to two or more. The term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Furthermore, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects; in formulas, the character " / " indicates a "division" relationship between the preceding and following related objects.

[0150] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application.

[0151] It is understood that, in the embodiments of this application, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

Claims

1. A piezoelectric device (100), characterized in that, Includes substrate and electroplated interconnects (140); The substrate includes a base layer (110) and a thin film layer (120). The base layer (110) includes a first region (1111) and a second region (1112). The thin film layer (120) covers the first region (1111), and its orthographic projection on a reference plane is located outside the orthographic projection of the second region (1112) on the reference plane. The reference plane is the plane containing the length and width directions of the substrate. The electroplated interconnect (140) includes a first electroplated interconnect portion (141) and a second electroplated interconnect portion (142), wherein the first electroplated interconnect portion (141) covers the second region (1112) and the second electroplated interconnect portion (142) covers the surface of the thin film layer (120). The width of the first electroplated interconnect portion (141) is greater than the width of the second electroplated interconnect portion (142); along the direction from the first region (1111) to the second region (1112), the width of the first electroplated interconnect portion (141) gradually increases, and the width of the second electroplated interconnect portion (142) gradually increases.

2. The piezoelectric device (100) according to claim 1, characterized in that, The thin film layer (120) includes an inclined body (127) and a main body (128); The second electroplated interconnect section (142) includes a transition electroplated interconnect section (1421) and a third electroplated interconnect section (1422). The two ends of the transition electroplated interconnect section (1421) are connected to the first electroplated interconnect section (141) and the third electroplated interconnect section (1422) respectively. The transition electroplated interconnect section (1421) covers the inclined body (127), and the third electroplated interconnect section (1422) covers the main body (128).

3. The piezoelectric device (100) according to claim 2, characterized in that, The inclined body (127) has an inclined surface (123), the main body (128) has a mating surface (124), the inclined surface (123) is connected to the mating surface (124), the angle between the inclined surface (123) and the mating surface (124) is an obtuse angle, and the angle between the surface of the substrate layer (110) and the thin film layer (120) in contact with the inclined surface (123) is an acute angle; The transition electroplated interconnect portion (1421) covers the inclined surface (123), and the third electroplated interconnect portion (1422) covers the mating surface (124).

4. The piezoelectric device (100) according to claim 2 or 3, characterized in that, The piezoelectric device (100) also includes a cut surface (B), and the distance between the tilted body (127) and the cut surface (B) gradually increases along the direction from the substrate layer (110) to the body (128).

5. The piezoelectric device (100) according to claim 4, characterized in that, Along the direction from the cut surface (B) to the inclined body (127), the thickness of the inclined body (127) gradually increases in the thickness direction of the base layer (110).

6. A method for preparing a piezoelectric device (100), used to prepare the piezoelectric device (100) as described in any one of claims 1-5, characterized in that, The piezoelectric device (100) includes a substrate and electroplated interconnects (140), the substrate including a thin film layer (120) and a base layer (110) stacked together, and the fabrication method includes: The thin film layer (120) in the cutting area is removed by etching process. Electroplated interconnects (140) are formed on the surface of the thin film layer (120) and on the surface of the base layer (110) within the cutting area.

7. The preparation method according to claim 6, characterized in that, The removal of the thin film layer (120) in the cutting area by etching process includes: A protective adhesive layer (10) is formed on the side of the thin film layer (120) facing away from the substrate layer (110). Remove a portion of the protective adhesive layer (10) to form a notch; The thin film layer (120) within the notch is removed by an etching process to form an inclined surface (123). The protective adhesive layer (10) is removed after the inclined surface (123) is formed.

8. An electronic device, characterized in that, The circuit board (700) includes the piezoelectric device (100) as described in any one of claims 1 to 5, wherein the piezoelectric device (100) is electrically connected to the circuit board (700).

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