A method for fabricating a silicon-based germanium epitaxial window structure and a semiconductor device

Abstract

This invention discloses a method for fabricating a silicon-based germanium epitaxial window structure and a semiconductor device. The method includes: forming a first trench on the exposed surface of the top silicon layer of an SOI; forming a dielectric layer on the exposed surface of the top silicon layer and filling the first trench; forming a second trench on the surface of the dielectric layer, with the bottom of the second trench nested in the first trench; forming a dielectric isolation layer between the second trench and the first trench; removing the dielectric isolation layer; forming a third trench on the surface of the dielectric layer with its bottom located in the top silicon layer; and forming a germanium epitaxial layer in the third trench. This invention effectively prevents the formation of Si-C bond polymers on the silicon surface and forms a good germanium-silicon epitaxial interface, which can greatly reduce the formation of germanium epitaxial defects and achieve better device detection performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a method for fabricating a silicon-based germanium epitaxial window structure and a semiconductor device thereof. Background Technology

[0002] When fabricating silicon-based germanium photodetectors, the epitaxial growth of germanium silicon is very sensitive to the surface properties of the silicon trenches in the epitaxial window. Germanium epitaxy needs to be carried out on a clean silicon surface, otherwise various epitaxial defects can easily form.

[0003] Existing methods for forming silicon trenches typically involve first forming a protective dielectric layer on a silicon layer, and then using a dry etching process for the dielectric (e.g., etching the dielectric layer until the surface of the silicon layer is exposed, thereby forming a silicon trench on the surface of the dielectric layer as an epitaxial window).

[0004] However, dry etching processes for dielectric materials typically require the use of high-energy plasmas formed by carbon-fluorine gases (such as CF4) for etching (e.g., capacitively coupled plasma etching). During plasma etching, the plasma gas discharges and undergoes collisional dissociation to generate unsaturated molecules (such as CF2). Driven by high ion energy, carbon is easily implanted into the silicon surrounding the trench and reacts with the silicon to form a Si-C bonded polymer film on the epitaxial interface. This results in a failure to obtain a pure silicon surface, thus adversely affecting the high-quality epitaxy of germanium.

[0005] Therefore, it is necessary to find a method that can effectively avoid the formation of Si-C bonds on the epitaxial interface to improve the epitaxial defects of germanium-silicon. Summary of the Invention

[0006] The purpose of this invention is to overcome the above-mentioned defects in the prior art and to provide a method for preparing a silicon-based germanium epitaxial window structure and a semiconductor device.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] This invention provides a method for fabricating a silicon-based germanium epitaxial window structure, comprising:

[0009] A first trench is formed on the exposed surface of the top silicon layer of SOI;

[0010] A dielectric layer is formed on the exposed surface of the top silicon layer, and the first trench is filled in;

[0011] A second trench is formed on the surface of the dielectric layer, and the bottom of the second trench is nested in the first trench, and a dielectric isolation layer is formed between the second trench and the first trench;

[0012] Remove the dielectric isolation layer and form a third trench on the surface of the dielectric layer with its bottom located in the top silicon layer;

[0013] A germanium epitaxial layer is formed in the third trench.

[0014] Furthermore, the first trench is formed using a first photolithography and dry etching process for silicon, and the second trench is formed using a second photolithography and dry etching process for dielectric materials. Specifically, the photomask used in the first photolithography and dry etching process is used in the second photolithography and dry etching process. The photolithography parameters are adjusted so that the critical dimension of the formed second trench is smaller than the critical dimension of the first trench. The etching parameters are also adjusted so that the bottom of the second trench is located above the bottom of the first trench, and the bottom of the formed second trench is nested within the first trench. A dielectric isolation layer is formed between the second trench and the first trench.

[0015] Furthermore, the first photolithography and dry etching process for silicon includes a first photolithography and inductively coupled plasma dry etching process for silicon, and the second photolithography and dry etching process for the dielectric includes a second photolithography and capacitively coupled plasma dry etching process for the dielectric.

[0016] Furthermore, a wet etching process is used to remove the dielectric isolation layer.

[0017] Further, the step of forming a dielectric layer on the exposed surface of the top silicon layer and filling the first trench specifically includes:

[0018] A first dielectric layer of silicon dioxide is formed on the exposed surface of the top silicon layer and on the inner wall surface of the first trench using a thermal oxidation process.

[0019] A second silicon dioxide dielectric layer is formed on the surface of the first dielectric layer using a deposition process, thereby filling the first trench; wherein the dielectric layer includes the second dielectric layer and the first dielectric layer, and the dielectric isolation layer is formed of at least the material of the first dielectric layer.

[0020] Furthermore, after forming the second dielectric layer, the method further includes: using an ion implantation process to form an active device in the top silicon layer surrounding the first trench.

[0021] Furthermore, it also includes: firstly patterning the top silicon layer to form a waveguide on the buried oxide layer of SOI, and then forming the first trench with its bottom located in the waveguide on the exposed surface of the waveguide; when forming the first dielectric layer, the first dielectric layer is also formed on the exposed surface and side of the waveguide; and when forming the second dielectric layer, the second dielectric layer is also filled on the buried oxide layer around the waveguide, and the formed active device is located in the waveguide around the first trench.

[0022] Furthermore, after forming the second dielectric layer, the method further includes: using a deposition process to form a third dielectric layer of silicon dioxide with a thickness of 10-200 nm on the surface of the second dielectric layer to cover the first trench, and then forming the second trench on the surface of the third dielectric layer; wherein the dielectric layer includes the third dielectric layer, the second dielectric layer and the first dielectric layer.

[0023] Furthermore, the etching depth of the first trench is 10-100 nm, the difference between the critical dimension of the first trench and the critical dimension of the second trench is 1-2 nm, and the distance between the bottom of the second trench and the bottom of the first trench is 1-2 nm.

[0024] The present invention also provides a semiconductor device comprising a silicon-based germanium epitaxial window structure prepared according to the above-described preparation method.

[0025] As can be seen from the above technical solution, the present invention first performs dry etching on silicon to form a first trench on the exposed surface of the top silicon layer, and fills the first trench with a dielectric layer. Then, it performs dry etching on the dielectric layer to form a second trench with a smaller critical size nested in the first trench. After that, it wet-removes the dielectric isolation layer on the first trench to form an epitaxial window (third trench). The dielectric layer material retained between the first trench and the second trench can be used as an isolation layer, thus avoiding direct contact with silicon when forming the second trench. This effectively prevents the formation of Si-C bond polymers on the silicon surface and forms a good germanium-silicon epitaxial interface, which can greatly reduce the formation of germanium epitaxial defects and achieve better device detection performance. Attached Figure Description

[0026] Figure 1 This is a flowchart illustrating a preferred embodiment of the preparation method of a silicon-based germanium epitaxial window structure according to the present invention.

[0027] Figures 2-10 According to a preferred embodiment of the present invention Figure 1 A schematic diagram of the process steps for preparing a silicon-based germanium epitaxial window structure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0029] The following combination Figures 1-10 The specific embodiments of the present invention will be further described in detail below.

[0030] refer to Figure 1 The present invention discloses a method for fabricating a silicon-based germanium epitaxial window structure, comprising the following steps:

[0031] Step S1: Form a first trench 16 on the exposed surface of the top silicon layer 13 of SOI.

[0032] like Figures 2-3 As shown, an SOI substrate is used. The SOI substrate includes a bottom silicon layer 11, a buried oxide layer 12, and a top silicon layer 13 stacked sequentially.

[0033] First, a first trench 16 is formed on the exposed surface of the top silicon layer 13 of the SOI using a first photolithography and dry etching process for silicon. The first trench 16 serves as a pre-window for forming a germanium epitaxial window.

[0034] In some embodiments, before forming the first trench 16, the top silicon layer 13 is patterned to form a pattern of a silicon waveguide 14 located on the buried oxide layer 12. A gap 15 exists between the waveguide 14 and other patterned structures on the top silicon layer 13. Then, the first trench 16, with its bottom located within the waveguide 14, is formed on the exposed surface of the waveguide 14 (i.e., the exposed surface of the top silicon layer 13).

[0035] In some embodiments, a first trench 16 is formed on the exposed surface of waveguide 14 (top silicon layer 13) using a first photolithography and inductively coupled plasma (ICP) dry etching process directly targeting silicon.

[0036] It is worth noting that, unlike existing methods that use dry etching to form germanium epitaxial windows, this invention employs a direct dry etching process targeting silicon to form a first trench 16 on the exposed surface of the top silicon layer 13 (waveguide 14), serving as a preparatory window for germanium epitaxy. In other words, the etching is performed directly on the silicon surface.

[0037] In existing methods for forming germanium epitaxial windows using dry etching, to protect the silicon layer surface during ion implantation to form active devices and to prevent the formation of germanium epitaxial layers on the silicon layer surface outside the epitaxial window, a silicon dioxide dielectric layer is typically formed first to protect the silicon layer surface. Then, a silicon trench is formed using a dry etching process with a high selectivity between silicon dioxide and silicon. Since etching the silicon trenches for the epitaxial window requires etching until the silicon layer surface is exposed, and the silicon dioxide dielectric layer is relatively thick, capacitively coupled plasma (CCP) dry etching is generally used to improve the etching rate and avoid over-etching the silicon layer surface (only exposing the silicon layer surface at the bottom of the silicon trench is required). Because CCP etching uses carbon-fluorine gases such as CF4, and high-energy plasma is needed to accelerate the etching rate, this process is highly efficient. During plasma etching, plasma gas discharge and collisional dissociation produce unsaturated CF2 molecules. Driven by high ion energy, carbon is injected into the silicon surrounding the trench and reacts with the silicon to form a Si-C bonded polymer film on the epitaxial interface. This results in the inability to obtain a pure silicon surface, thus adversely affecting the high-quality epitaxy of germanium.

[0038] In this invention, an inductively coupled plasma dry etching process is employed to form a first trench 16 on the exposed surface of waveguide 14 (top silicon layer 13). Its key advantages are the ability to increase ion density under low ion energy conditions, thereby improving the etching rate while minimizing damage to the silicon surface. It also effectively prevents carbon from the photoresist from being excited and implanted into the silicon layer of waveguide 14. Furthermore, when using inductively coupled plasma dry etching, the probability of carbon implantation into the silicon layer can be further controlled by using carbon-free etching gases (e.g., SF6, Cl2, SiCl4). During etching, volatile substances are generated through a reaction and are removed as gas from the vacuum line, resulting in a pure silicon surface.

[0039] In some embodiments, the etching depth of the first trench 16 is 10 to 100 nm, and the bottom of the first trench 16 is located in the waveguide 14 to isolate it from the buried oxide layer 12 below.

[0040] Step S2: Form a dielectric layer 19 on the exposed surface of the top silicon layer 13 and fill the first trench 16.

[0041] like Figure 4 As shown, a silicon dioxide first dielectric layer 17 is formed on the exposed surface of waveguide 14 (top silicon layer 13) and the inner wall surface of the first trench 16 using a thermal oxidation process. The formation of a silicon dioxide thermal oxide layer on the inner wall surface of the first trench 16 by thermal oxidation repairs the roughness of the inner wall surface of the first trench 16 (edge ​​of the epitaxial preparation window) caused by etching, thereby further improving the surface finish of the obtained inner wall surface of the first trench 16.

[0042] When the first dielectric layer 17 is formed, it can also be formed on the exposed top and side surfaces of other patterned structures on the waveguide 14 and the top silicon layer 13, thus covering the entire surface of the waveguide 14 pattern.

[0043] Next, an active device needs to be formed in the waveguide 14 surrounding the first trench 16 by ion implantation. Since the thickness of the first dielectric layer 17 formed by thermal oxidation is relatively thin and cannot meet the requirements for the thickness of the dielectric protective layer during ion implantation, a second dielectric layer of a certain thickness needs to be formed on the surface of the first dielectric layer 17.

[0044] like Figure 5 As shown, a second dielectric layer, such as silicon dioxide, is formed on the surface of the first dielectric layer 17 using a deposition process, and the first trench 16 is filled. The second dielectric layer and the first dielectric layer 17 form an integral fourth dielectric layer 18.

[0045] This allows the second dielectric layer to also fill the buried oxide layer 12 in the void 15 around the waveguide 14, thus filling the void 15 completely.

[0046] Subsequently, a chemical mechanical polishing process was used to planarize the surface of the fourth dielectric layer 18 (the second dielectric layer) to obtain a flat surface of the fourth dielectric layer 18, and the final thickness of the fourth dielectric layer 18 was adjusted to meet the requirements of the dielectric protective layer thickness range during ion implantation, so as to avoid the total thickness of the first dielectric layer 17 and the second dielectric layer being too thick.

[0047] like Figure 6 As shown, an active device structure (not shown) is formed in the waveguide 14 surrounding the first trench 16 using an ion implantation process.

[0048] like Figure 7As shown, after ion implantation, a deposition process is used to form a third dielectric layer, such as silicon dioxide, on the surface of the fourth dielectric layer 18 (second dielectric layer), covering the first trench 16. This forms a dielectric layer 19 composed of the third dielectric layer, the second dielectric layer, and the first dielectric layer 17 on the exposed surface of the waveguide 14 (top silicon layer 13), filling the first trench 16.

[0049] In some embodiments, the thickness of the third dielectric layer is 10–200 nm.

[0050] Step S3: A second trench 20 is formed on the surface of the dielectric layer 19, and the bottom of the second trench 20 is nested in the first trench 16, forming a dielectric isolation layer 21 between the second trench 20 and the first trench 16.

[0051] like Figure 8 As shown, a second trench 20 is formed on the surface of the dielectric layer 19 (third dielectric layer) using a second photolithography and dry etching process for the dielectric.

[0052] In some embodiments, a second photolithography and capacitively coupled plasma dry etching process for the medium is used to form the second trench 20.

[0053] The same photomask used in the first photolithography and dry etching processes for forming the first trench 16 is also used in the second photolithography and dry etching processes for forming the second trench 20. By adjusting photolithography parameters, such as photolithography energy and focal length, the critical dimension of the width of the formed second trench 20 is made smaller than the critical dimension of the width of the first trench 16. Furthermore, by adjusting etching parameters, such as etching time, the bottom of the second trench 20 is positioned above the bottom of the first trench 16, and the bottom of the formed second trench 20 is nested within the first trench 16, with a certain gap maintained between the trench walls of the second trench 20 and the trench walls of the first trench 16. In this way, a dielectric isolation layer 21 of a certain thickness is formed between the second trench 20 and the first trench 16. In other words, the dielectric isolation layer 21 is located on the inner wall surface of the first trench 16, and the bottom trench wall of the second trench 20 is formed on the surface of the dielectric isolation layer 21.

[0054] In some embodiments, the difference between the critical width dimension of the first trench 16 and the critical width dimension of the second trench 20 is 1 to 2 nm, that is, the one-sided gap between the trench wall of the second trench 20 and the trench wall of the first trench 16 is 0.5 to 1 nm. Furthermore, the distance between the bottom of the second trench 20 and the bottom of the first trench 16 is 1 to 2 nm. This defines the thickness of the dielectric isolation layer 21 on the side and bottom surfaces of the first trench 16.

[0055] Theoretically, the dielectric isolation layer 21 is formed at least of the material of the first dielectric layer 17. In this embodiment, the dielectric isolation layer 21 is formed of the first dielectric layer 17 and the remaining portion of the second dielectric layer material after etching.

[0056] As can be seen, since the critical dimension of the width of the second trench 20 is smaller than that of the first trench 16, and the bottom of the second trench 20 is located above the bottom of the first trench 16, the etching during the formation of the second trench 20 is limited to the silicon dioxide dielectric layer 19 and does not contact the silicon on the surface of the first trench 16. Therefore, the second trench 20 can be formed using a conventional capacitively coupled plasma dry etching process for the dielectric, which not only improves the etching rate but also effectively avoids the formation of Si-C bonded polymers, laying a good foundation for the subsequent formation of a good germanium-silicon epitaxial interface and reducing germanium epitaxial defects.

[0057] Step S4: Remove the dielectric isolation layer 21 and form a third trench 22 on the surface of the dielectric layer 19 with its bottom located in the top silicon layer 13.

[0058] like Figure 9 As shown, a wet etching process is used to remove the dielectric isolation layer 21 located on the inner wall surface of the first trench 16.

[0059] In some embodiments, when the dielectric layer 19 is made of silicon dioxide, hydrofluoric acid (DHF) is used to completely remove the silicon dioxide dielectric isolation layer 21. The chemical reaction formula is as follows:

[0060] SiO2 + 4HF = SiF4↑ + 2H2O;

[0061] The SiF4 produced in the reaction can be removed through a gas exhaust system.

[0062] By employing a selective wet etching process, the dielectric layer 19 material can be effectively removed, avoiding the consumption of silicon at the walls of the first trench 16. This allows for the formation of a third trench 22, the final germanium epitaxial window, based on the first trench 16. Therefore, the integrated scheme of optimizing the germanium epitaxial interface through multi-step etching, as described in this invention, effectively avoids the formation of Si-C polymer bonds on the silicon surface within the epitaxial window that could affect the epitaxial interface. This reduces interface defects, improves the quality of the germanium epitaxial layer, and consequently reduces germanium epitaxial defects.

[0063] The material of the dielectric layer 19 is not limited to silicon dioxide and can be determined depending on the actual situation.

[0064] Step S5: Form a germanium epitaxial layer 23 in the third trench 22.

[0065] like Figure 10As shown, finally, germanium is epitaxially grown in the epitaxial window formed by the third trench 22 using a germanium epitaxial growth process, and the germanium surface is planarized using a chemical mechanical polishing process to form a germanium epitaxial layer 23 in the epitaxial window.

[0066] A semiconductor device according to the present invention includes, for example, a silicon-based germanium epitaxial window structure prepared according to the above-described method for preparing the present invention. Figure 10 The silicon-based germanium epitaxial window structure is shown.

[0067] refer to Figure 10 A semiconductor device of the present invention is fabricated on an SOI substrate. The SOI substrate includes a bottom silicon layer 11, a buried oxide layer 12, and a top silicon layer 13 stacked sequentially.

[0068] A semiconductor device according to the present invention includes a dielectric layer 19 fabricated on a top silicon layer 13, a third trench 22 fabricated downward from the surface of the dielectric layer 19, a germanium epitaxial window formed by the third trench 22, and a germanium epitaxial layer 23 fabricated in the epitaxial window. The bottom of the epitaxial window (third trench 22) is located in the top silicon layer 13 and is isolated from the buried oxide layer 12 below the top silicon layer 13.

[0069] In some embodiments, a silicon waveguide 14 is formed on the buried oxide layer 12 by patterning the top silicon layer 13. A gap 15 is provided between the waveguide 14 and other patterned structures on the top silicon layer 13, and a dielectric layer 19 is also filled in the gap 15, tightly connected to the buried oxide layer 12. The bottom of the epitaxial window (third trench 22) is located in the waveguide 14 and is isolated from the underlying buried oxide layer 12.

[0070] In some embodiments, an active device structure (not shown) is fabricated in waveguide 14 surrounding the epitaxial window.

[0071] In some embodiments, a semiconductor device of the present invention includes a silicon-based germanium photodetector having the above-described silicon-based germanium epitaxial window structure. The germanium epitaxial layer 23 formed within the epitaxial window serves as the light-absorbing layer of the silicon-based germanium photodetector.

[0072] In summary, this invention first performs ICP dry etching on silicon to form a first trench 16 on the exposed surface of the top silicon layer 13, and fills the first trench 16 with a dielectric layer 19. Then, it performs CCP dry etching on the dielectric layer 19 to form a second trench 20 with a smaller critical size nested in the first trench 16. Afterward, it wet-removes the dielectric isolation layer 21 on the first trench 16 to form an epitaxial window (third trench 22). The dielectric layer 19 material retained between the first trench 16 and the second trench 20 can be used as an isolation layer, thus avoiding direct contact with silicon during the dry etching to form the second trench 20. This effectively prevents the formation of Si-C bonds on the silicon surface and forms a good germanium-silicon epitaxial interface, which can greatly reduce the formation of germanium epitaxial defects and achieve better device detection performance.

[0073] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A method for fabricating a silicon-based germanium epitaxial window structure, characterized in that, include: A first trench is formed on the exposed surface of the top silicon layer of SOI; A dielectric layer is formed on the exposed surface of the top silicon layer, and the first trench is filled in; A second trench is formed on the surface of the dielectric layer, and the bottom of the second trench is nested in the first trench, and a dielectric isolation layer is formed between the second trench and the first trench; A wet etching process is used to remove the dielectric isolation layer, and a third trench with its bottom located in the top silicon layer is formed on the surface of the dielectric layer. A germanium epitaxial layer is formed in the third trench.

2. The method for preparing a silicon-based germanium epitaxial window structure according to claim 1, characterized in that, The first trench is formed using a first photolithography and dry etching process for silicon, and the second trench is formed using a second photolithography and dry etching process for dielectric materials. Specifically, the photomask used in the first photolithography and dry etching process is used in the second photolithography and dry etching process. The photolithography parameters are adjusted so that the critical dimension of the formed second trench is smaller than the critical dimension of the first trench. The etching parameters are also adjusted so that the bottom of the second trench is located above the bottom of the first trench, and the bottom of the formed second trench is nested within the first trench. A dielectric isolation layer is formed between the second trench and the first trench.

3. The method for preparing a silicon-based germanium epitaxial window structure according to claim 2, characterized in that, The first photolithography and dry etching process for silicon includes a first photolithography and inductively coupled plasma dry etching process for silicon, and the second photolithography and dry etching process for dielectric includes a second photolithography and capacitively coupled plasma dry etching process for dielectric.

4. The method for preparing a silicon-based germanium epitaxial window structure according to claim 1, characterized in that, The step of forming a dielectric layer on the exposed surface of the top silicon layer and filling the first trench specifically includes: A first dielectric layer of silicon dioxide is formed on the exposed surface of the top silicon layer and on the inner wall surface of the first trench using a thermal oxidation process. A second silicon dioxide dielectric layer is formed on the surface of the first dielectric layer using a deposition process, thereby filling the first trench; wherein the dielectric layer includes the second dielectric layer and the first dielectric layer, and the dielectric isolation layer is formed of at least the material of the first dielectric layer.

5. The method for preparing a silicon-based germanium epitaxial window structure according to claim 4, characterized in that, After forming the second dielectric layer, the method further includes: forming an active device in the top silicon layer surrounding the first trench using an ion implantation process.

6. The method for preparing a silicon-based germanium epitaxial window structure according to claim 5, characterized in that, Also includes: First, the top silicon layer is patterned to form a waveguide on the buried oxide layer of SOI, and then the first trench with its bottom located in the waveguide is formed on the exposed surface of the waveguide. When forming the first dielectric layer, the first dielectric layer is also formed on the exposed surface and sidewalls of the waveguide; and when forming the second dielectric layer, the second dielectric layer is also filled on the buried oxide layer surrounding the waveguide, and the formed active device is located in the waveguide surrounding the first trench.

7. The method for preparing a silicon-based germanium epitaxial window structure according to claim 4, characterized in that, After forming the second dielectric layer, the method further includes: using a deposition process to form a third dielectric layer of silicon dioxide with a thickness of 10~200nm on the surface of the second dielectric layer to cover the first trench, and then forming the second trench on the surface of the third dielectric layer; wherein, the dielectric layer includes the third dielectric layer, the second dielectric layer and the first dielectric layer.

8. The method for preparing a silicon-based germanium epitaxial window structure according to claim 2, characterized in that, The etching depth of the first trench is 10~100nm, the difference between the critical dimension of the first trench and the critical dimension of the second trench is 1~2nm, and the distance between the bottom of the second trench and the bottom of the first trench is 1~2nm.

9. A semiconductor device, characterized in that, Including the silicon-based germanium epitaxial window structure prepared by the preparation method according to any one of claims 1 to 8.

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