Vertical led chip and method of manufacturing the same

Abstract

The application relates to the technical field of optoelectronic manufacturing, and particularly discloses a vertical LED chip and a preparation method thereof. The preparation method of the vertical LED chip comprises the following steps: sequentially forming an N-type semiconductor layer, a multi-quantum well layer, a P-type semiconductor layer, a current blocking layer, a P-type conductive reflection layer, an insulating layer, an N-type conductive reflection layer and a metal bonding layer on a patterned substrate, then bonding with a conductive substrate, and removing the patterned substrate; thinning a protruding part of the N-type semiconductor layer, etching a step, forming a passivation protective layer and a P electrode. The height of the protruding part after thinning is less than or equal to 1.5 micrometers, and the difference between the inclination angle of the sidewall of the protruding part after thinning and the inclination angle of the sidewall of the protruding part before thinning is less than or equal to 10 degrees. By implementing the application, the brightness and reliability of the vertical LED chip can be improved.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic manufacturing technology, and in particular to a vertical LED chip and its fabrication method. Background Technology

[0002] In recent years, vertical LED chips have gradually become an important development direction in the semiconductor lighting field due to their excellent heat dissipation performance and high light output capability. Compared with the traditional horizontal structure, vertical LED chips significantly reduce thermal resistance, improve current carrying capacity and luminous efficiency by distributing electrodes on both sides of the chip, making them suitable for high-power and high-brightness applications.

[0003] In existing vertical LED chips, the N-electrode is often fabricated directly on the N-type semiconductor layer, with a conductive substrate serving as the P-electrode. However, the high resistivity of the N-type semiconductor layer leads to uneven current distribution and a significant reduction in luminous brightness. On the other hand, in existing LED chips based on patterned substrates, after peeling, the N-type semiconductor layer in contact with it often forms a pyramid structure. During step etching, the etching depth varies at different locations, often damaging other functional layers and reducing chip yield and reliability. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a vertical LED chip and its preparation method, which has high brightness and high reliability.

[0005] To address the aforementioned technical problems, this invention provides a method for fabricating a vertical LED chip, comprising: (1) An N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer are sequentially formed on a patterned substrate, and a first hole is formed to expose the N-type semiconductor layer to obtain an epitaxial wafer; wherein the N-type semiconductor layer includes a protrusion and a body portion that are in contact with the patterned substrate; (2) A current blocking layer is formed on the epitaxial wafer, the current blocking layer covering the P-type semiconductor layer and the hole wall of the first hole; (3) A P-type conductive reflective layer is formed on the current blocking layer to obtain a first intermediate; wherein the P-type conductive reflective layer is electrically connected to the P-type semiconductor layer through a second hole provided on the current blocking layer; (4) An insulating layer, an N-type conductive reflective layer and a metal bonding layer are sequentially formed on the first intermediate to obtain a second intermediate; (5) Bond the second intermediate to the conductive substrate and remove the patterned substrate; (6) Thinning the protrusion to obtain a third intermediate; wherein the height of the protrusion after thinning is less than or equal to 1.5 μm, and the difference between the inclination angle of the sidewall of the protrusion after thinning and the inclination angle of the sidewall of the protrusion before thinning is less than or equal to 10°. (7) A third hole is formed on the third intermediate to expose the current blocking layer, thereby obtaining a fourth intermediate; (8) A passivation protective layer and a P electrode are formed on the fourth intermediate to obtain the finished vertical LED chip.

[0006] As an improvement to the above technical solution, the patterned substrate is provided with multiple raised patterns, the height of which is 1μm~2.5μm; and / or The thickness of the N-type semiconductor layer is 2μm to 5μm, the height of the protrusion before thinning is 1μm to 2.5μm, and the height of the protrusion after thinning is 0.6μm to 1.2μm.

[0007] As an improvement to the above technical solution, step (6) includes: (6.1) A first photoresist layer is formed on one side of the N-type semiconductor layer of the third intermediate; (6.2) Etch to thin the first photoresist layer to expose the top of the protrusion; (6.3) Using the first gas as the reaction gas, the protrusion is thinned by dry etching, and the first photoresist layer is thinned at the same time; (6.4) Remove the remaining first photoresist layer; The thickness of the first photoresist layer before thinning is 1 μm to 2 μm greater than the height of the protrusion before thinning.

[0008] As an improvement to the above technical solution, in step (6.2), the first photoresist layer is thinned by dry etching using a second gas as the reaction gas; wherein the second gas includes O2; the process parameters for dry etching include: upper power of 100W~300W, lower power of 50W~200W, chamber pressure of 3mtorr~10mtorr, and flow rate of the second gas of 40sccm~80sccm; and / or In step (6.3), the first gas is selected from one or more of Cl2, BCl3, Ar, and SF6; the dry etching process parameters include: upper power of 100W~500W, lower power of 50W~200W, chamber pressure of 3mtorr~10mtorr, and flow rate of the first gas of 40sccm~80sccm.

[0009] As an improvement to the above technical solution, in step (6.3), the first gas is a mixture of Cl2, BCl3 and SF6, and the volume ratio of Cl2, BCl3 and SF6 is (3~5):(2~5):(0.1~1), so that the ratio of the etching rate of the first photoresist layer to the etching rate of the protrusion during the dry etching process is 1:(0.8~1.2).

[0010] As an improvement to the above technical solution, in step (6.2), the second gas is a mixture of O2 and C4F6, and the volume ratio of O2 to C4F6 is (2~3):1.

[0011] As an improvement to the above technical solution, step (7) includes: (7.1) A second photoresist layer is formed on one side of the N-type semiconductor layer of the third intermediate; (7.2) Etching away the N-type semiconductor layer, multiple quantum well layer, and P-type semiconductor layer in the first preset region to form a third hole exposing the current blocking layer; wherein the current blocking layer at the bottom of the third hole is etched and thinned, and a pyramid-like morphology is formed on the surface; the thinning thickness of the current blocking layer is ≤0.3μm; (7.3) Remove the remaining second photoresist layer.

[0012] As an improvement to the above technical solution, step (3) includes: (3.1) Etch the current blocking layer to form a second hole surrounding the first hole; (3.2) Form a P-type conductive reflective layer and pattern it to expose the current blocking layer of the second preset region; (3.3) A P-type metal extension layer is formed to obtain a first intermediate; wherein the P-type metal extension layer covers the P-type conductive reflective layer and the current blocking layer of the second preset region; Step (8) includes: (8.1) A passivation protective layer is formed on the fourth intermediate; (8.2) Remove the passivation protective layer and current blocking layer of the third preset area to expose the P-type metal extension layer; the third preset area is located in the third hole and is disposed near the edge of the conductive substrate; (8.3) A P electrode is formed, wherein the P electrode is electrically connected to the P-type metal extension layer.

[0013] As an improvement to the above technical solution, step (4) includes: (4.1) An insulating layer is formed on the first intermediate; (4.2) A fourth hole is formed on the insulating layer on the bottom wall of the first hole to expose the N-type semiconductor layer; (4.3) An N-type conductive reflective layer is formed and patterned, wherein the N-type conductive reflective layer is electrically connected to the N-type semiconductor layer through the fourth hole; the projection of the N-type conductive reflective layer on the conductive substrate at least partially overlaps with the projection of the P-type conductive reflective layer on the conductive substrate. (4.4) A metal bonding layer is formed to obtain the second intermediate.

[0014] Accordingly, the present invention also discloses a vertical LED chip, which is prepared by the above-described method for preparing a vertical LED chip.

[0015] Implementing this invention has the following beneficial effects: In one embodiment of the present invention, the fabrication method of a vertical LED chip comprises three aspects: First, the current extraction of the N-type semiconductor layer is achieved through the N-type conductive reflective layer, metal bonding layer, and conductive substrate within a first hole. These layers have low resistivity, improving the uniformity of current distribution and thus enhancing the uniformity of light emission. Second, after stripping the patterned substrate to expose the N-type semiconductor layer, the protrusions are thinned to a height less than or equal to 1.5 μm, and the difference between the tilt angle of the sidewall of the thinned protrusion and that of the protrusion before thinning is less than or equal to 10°. This significantly reduces etching damage to the current-blocking layer during subsequent step etching, optimizing reliability; it also maintains the light extraction function of the protrusion, ensuring high brightness of the vertical LED chip. Third, the current introduced by the P-electrode is distributed through the P-type conductive reflective layer and injected into different positions of the P-type semiconductor layer through a second hole, optimizing the current distribution and improving the uniformity of light emission. Fourthly, by preparing N-type conductive reflective layers and P-type conductive reflective layers respectively to reflect the light emitted from the multi-quantum-well layer, the light reflectivity and brightness are effectively improved. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the epitaxial wafer structure after step S1 in one embodiment of the present invention; Figure 2 This is a schematic diagram of the epitaxial wafer structure after step S2 in one embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the first intermediate obtained in step S3 of an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the first intermediate obtained in step S33 in another embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the second intermediate obtained in step S4 of an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of the second intermediate body after step S5 in one embodiment of the present invention; Figure 7 This is a schematic diagram illustrating the principle of N-type semiconductor layer thinning in steps S61-S64 of an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of the fourth intermediate obtained in step S7 of an embodiment of the present invention; Figure 9 This is a schematic diagram illustrating the thinning principle of the current blocking layer during the step etching process in S71~S73 of an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of the vertical LED chip obtained in step S8 of an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It is hereby declared that the directional terms such as up, down, left, right, front, back, inside, and outside used in this text are based solely on the accompanying drawings and are not intended to specifically limit the invention.

[0018] One embodiment of the present invention provides a method for fabricating a vertical LED chip, which includes the following steps: S1: An N-type semiconductor layer, a multiple quantum well layer, and a P-type semiconductor layer are sequentially formed on a patterned substrate, and a first hole is formed to expose the N-type semiconductor layer to obtain an epitaxial wafer; The patterned substrate 1 is a patterned sapphire substrate, but is not limited to this. The patterned substrate 1 has multiple raised patterns, the height of which is 0.8 μm to 3 μm, preferably 1 μm to 2.5 μm. During the subsequent growth of the N-type semiconductor layer 21, these raised patterns allow the N-type semiconductor layer 21 to form protrusions 211, which can improve light extraction efficiency and increase the brightness of the vertical LED chip.

[0019] The N-type semiconductor layer 21 can be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited to these. Preferably, it is an N-type GaN layer. The thickness of the N-type semiconductor layer 21 is 1 μm to 5 μm, preferably 2 μm to 5 μm. When based on the patterned substrate 1, the N-type semiconductor layer 21 includes a protrusion 211 and a body 212 that contact the patterned substrate 1. The height of the protrusion 211 is the same as the height of the protrusion pattern, which is 0.8 μm to 3 μm, preferably 1 μm to 2.5 μm.

[0020] The multiple quantum well layer 22 is an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer, or an AlGaN-AlGaN type MQW layer, but is not limited to these. The p-type semiconductor layer 23 can be a p-type GaN layer, a p-type AlGaN layer, or a p-type GaAs layer, but is not limited to these. Preferably, the multiple quantum well layer 22 is an InGaN-GaN type MQW layer, and the p-type semiconductor layer 23 is a p-type GaN layer.

[0021] Specifically, the N-type semiconductor layer 21, the multiple quantum well layer 22, and the P-type semiconductor layer 23 together constitute the epitaxial layer, which has a thickness of 4 μm to 8 μm. It should be noted that in some embodiments, the epitaxial layer may also include one or more of the buffer layer, intrinsic semiconductor layer, stress buffer layer, electron blocking layer, and ohmic contact layer commonly used in the art, but is not limited thereto.

[0022] Preferably, in some embodiments, after forming the N-type semiconductor layer 21, the multiple quantum well layer 22, and the P-type semiconductor layer 23, a step of forming a transparent conductive layer 25 is further included. The transparent conductive layer 25 may be an ITO layer, an IZO layer, or an AZO layer, but is not limited to these. Preferably, the transparent conductive layer 25 is an ITO layer. The thickness of the transparent conductive layer 25 is 10 nm to 200 nm. By providing the transparent conductive layer 25, the current spread can be effectively improved, allowing the current flowing in from the P-electrode 43 to be uniformly distributed through the transparent conductive layer 25 before entering the multiple quantum well layer 22, thereby improving the luminous brightness of the vertical LED chip.

[0023] Specifically, after forming the N-type semiconductor layer 21, the multiple quantum well layer 22, and the P-type semiconductor layer 23, the first hole 24 is formed by etching. Specifically, the first hole 24 can be formed by dry etching or wet etching processes, but is not limited thereto. Preferably, in some embodiments, the first hole 24 is formed by dry etching to optimize etching accuracy.

[0024] Specifically, see Figure 1 In some implementations, the first hole 24 is located in the central region of the epitaxial layer, so that the subsequently formed P-type conductive reflective layer 41 and the second hole 31 are both arranged around the first hole 24. This allows the current injected through the P-type conductive reflective layer 41 to flow through multiple points to the N-type conductive reflective layer 6 located in the first hole 24, thereby optimizing the current distribution and improving the luminous brightness.

[0025] S2: Forming a current blocking layer on the epitaxial wafer; Specifically, see Figure 2The current blocking layer 3 covers the P-type semiconductor layer 23 and the hole walls (including its sidewalls and bottom walls) of the first hole 24. By introducing the current blocking layer 3, the current spread under high current density can be further optimized, and the reliability of the vertical LED chip can be improved.

[0026] Specifically, the current blocking layer 3 is a SiO2 layer or an Al2O3 layer, but is not limited to these. Preferably, it is a SiO2 layer. The thickness of the current blocking layer 3 is 0.5μm to 1.5μm to maintain an appropriate thickness after subsequent step etching, thereby improving the reliability of the vertical LED chip; however, its thickness cannot be too large, otherwise the operating voltage of the vertical LED chip will be too high.

[0027] S3: A P-type conductive reflective layer is formed on the current blocking layer to obtain the first intermediate; Specifically, the P-type conductive reflective layer 41 reflects light, allowing light emitted from the quantum well layer 22 to exit from the N-type semiconductor layer 21 after being reflected by the P-type conductive reflective layer 41 and the N-type conductive reflective layer 6. The P-type conductive reflective layer 41 also guides the current from the P-electrode 43 into the P-type semiconductor layer 23. See details... Figure 3 By creating a second hole 31 in the current blocking layer 3, the P-type conductive reflective layer 41 can be electrically connected to the P-type semiconductor layer 23.

[0028] Specifically, the P-type conductive reflective layer 41 is made of one or more of Ag, Al, Ti, Ni, and TiW, but is not limited thereto. Preferably, the P-type conductive reflective layer 41 is an Ag / TiW stacked structure. The thickness of the P-type conductive reflective layer 41 is 100nm to 1000nm, preferably 150nm to 800nm.

[0029] Specifically, in the finished vertical LED chip, the P-type conductive reflective layer 41 can cover the entire area corresponding to the current blocking layer 3, or it can only cover the current blocking layer 3 corresponding to the N-type semiconductor layer 21. Of course, the P-type conductive reflective layer 41 in the area of ​​the first hole 24 will be in an intermittent state to avoid electrical conduction between the P-type conductive reflective layer 41 and the N-type conductive reflective layer 6, thereby preventing a short circuit in the vertical LED chip.

[0030] Preferably, in some embodiments, step S3 includes: S31: Etch the current blocking layer to form a second hole surrounding the first hole; Specifically, the current blocking layer 3 can be etched using a photolithography etching process to form the second hole 31. The number of second holes 31 can be one or more, preferably multiple. By using multiple second holes 31 arranged around the first hole 24, the current can be distributed, improving the uniformity of current distribution and increasing the luminous brightness.

[0031] S32: Form a P-type conductive reflective layer and pattern it to expose the current blocking layer of the second preset area; Specifically, a photoresist layer can be formed on the current blocking layer 3 first, and after exposure and development, a P-type conductive reflective layer 41 can be formed. Then, the photoresist layer can be removed by a photoresist peeling process. Alternatively, the P-type conductive reflective layer 41 can be formed first, and then patterned by a photolithography etching process.

[0032] Specifically, after the P-type conductive reflective layer 41 is patterned, the current blocking layer 3 of the second preset region 200 can be exposed. The second preset region 200 is located on one side of the first hole 24.

[0033] More specifically, in the finished vertical LED chip, the inner boundary of the projection of the second preset region 200 onto the conductive substrate 8 is the outer boundary of the projection of the P-type semiconductor layer 23 onto the conductive substrate 8. This approach reduces the amount of metal used, lowers production costs, and ensures high light reflectivity. It also reduces the area of ​​the P-electrode 43, increasing the light-emitting area and improving brightness.

[0034] S33: Form a P-type metal extension layer to obtain the first intermediate; Specifically, the P-type metal extension layer 42 is a stacked structure commonly used in the art, composed of Au, Ti, Cr, Pt, Cu, etc. Preferably, it can be a Ti / Pt / Au / Cr, Cr / Pt / Au / Ti, Cr / Pt / Au / Cr, etc., but it is not limited to these. The thickness of the P-type metal extension layer 42 is 300nm~2000nm, preferably 500nm~1500nm.

[0035] Specifically, see Figure 4 The P-type metal extension layer 42 covers the P-type conductive reflective layer 41 and the current blocking layer 3 of the second preset area 200. It mainly serves to disperse current and also protect the P-type metal extension layer 42, thereby improving the reliability of the vertical LED chip.

[0036] S4: An insulating layer, an N-type conductive reflective layer, and a metal bonding layer are sequentially formed on the first intermediate to obtain the second intermediate; Specifically, insulating layer 5 is a SiO2 layer, an Al2O3 layer, and a SiN layer. x The insulating layer 5 is a stacked structure consisting of one or more of the following layers, but is not limited thereto. Preferably, in some embodiments, the insulating layer 5 is a stacked structure formed of a SiO2 layer and an Al2O3 layer. The thickness of the insulating layer 5 is 500 nm to 1500 nm. The insulating layer 5 can insulate the N-type conductive reflective layer 6 from the P-type conductive reflective layer 41 and the P-type metal extension layer 42. Accordingly, see [link to relevant documentation]. Figure 5To better achieve the insulation function, the insulation layer 5 is covered with a P-type conductive reflective layer 41 and a P-type metal extension layer 42.

[0037] Specifically, the N-type conductive reflective layer 6 serves to reflect light, since the P-type conductive reflective layer 41 does not completely cover the entire multi-quantum well layer 22. Therefore, the N-type conductive reflective layer 6 is further introduced. Furthermore, the N-type conductive reflective layer 6 is electrically connected to the N-type semiconductor layer 21 through a fourth hole 51 disposed on the insulating layer 5, thus achieving electrical connection of the N-type semiconductor layer 21. Specifically, the N-type conductive reflective layer 6 is made of one or more of Ag, Al, Ti, Ni, and TiW, but is not limited to these. Preferably, the N-type conductive reflective layer 6 is an Ag / TiW stacked structure. The thickness of the N-type conductive reflective layer 6 is 100nm~1000nm, preferably 150nm~800nm.

[0038] Specifically, the metal bonding layer 7 is made of one or more of Au, Sn, AuSn alloy, and NiSn alloy. Preferably, the metal bonding layer 7 is a Ti / Au / Sn stacked structure or a Ti / Ni / Sn stacked structure. The thickness of the metal bonding layer 7 is 1 μm to 4 μm.

[0039] Preferably, in some embodiments, step S4 includes: S41: An insulating layer is formed on the first intermediate; S42: A fourth hole is formed on the insulating layer on the bottom wall of the first hole to expose the N-type semiconductor layer; Specifically, the fourth hole 51 penetrates the insulating layer 5 and the current blocking layer 3 to expose the N-type semiconductor layer 21.

[0040] S43: Form an N-type conductive reflective layer and pattern it; Specifically, a photoresist layer can be formed on the insulating layer 5 first, followed by exposure and development to form an N-type conductive reflective layer 6, and then the photoresist layer can be removed using a photoresist peeling process. Alternatively, the N-type conductive reflective layer 6 can be formed first, and then patterned using a photolithography etching process.

[0041] Preferably, after the N-type conductive reflective layer 6 is patterned, in the finished vertical LED chip, the projection of the N-type conductive reflective layer 6 onto the conductive substrate at least partially overlaps with the projection of the P-type conductive reflective layer 41 onto the conductive substrate, which can further improve the reflectivity of light and increase the luminous brightness of the vertical LED chip. More preferably, the projection of the N-type conductive reflective layer 6 onto the conductive substrate overlaps with the projection of the first hole 24 onto the conductive substrate, or the projection of the N-type conductive reflective layer 6 onto the conductive substrate is slightly larger than the projection of the first hole 24 onto the conductive substrate. Moreover, the P-type conductive reflective layer 41 at least partially covers the sidewall of the first hole 24. Based on this embodiment, the luminous brightness can be further improved.

[0042] S44: A metal bonding layer is formed, resulting in the second intermediate.

[0043] S5: Bond the second intermediate to the conductive substrate and remove the patterned substrate; Specifically, after removing the patterned substrate 1, the protrusions 211 of the N-type semiconductor layer 21 are exposed.

[0044] S6: Thin the protrusion to obtain the third intermediate; Specifically, the protrusion 211 can be thinned using wet or dry etching to achieve a height ≤1.5μm. This significantly reduces etching damage to the current blocking layer 3 during subsequent step etching, improving reliability. Preferably, the height of the protrusion 211 after thinning is 0.6μm~1.2μm. Simultaneously, to avoid reducing light extraction efficiency, the sidewall tilt angle of the protrusion 211 should change by ≤10° before and after thinning, i.e., the difference between the sidewall tilt angle of the protrusion 211 after thinning and the sidewall tilt angle before thinning is ≤10°, more preferably 1°~5°.

[0045] Preferably, in some embodiments, step S6 includes: S61: A first photoresist layer is formed on one side of the N-type semiconductor layer of the third intermediate; Specifically, photoresist can be spin-coated onto the N-type semiconductor layer 21, and then baked and cured to form the first photoresist layer 400. The viscosity of the photoresist is <100 cP. See also Figure 7 (b) The thickness of the first photoresist layer 400 is 1 μm to 2 μm greater than the height of the protrusion 211 before thinning, in order to ensure etching uniformity and at the same time ensure high yield.

[0046] S62: Etch to thin the first photoresist layer to expose the top of the protrusion; Specifically, the first photoresist layer 400 can be thinned by wet etching or dry etching, but is not limited thereto. Preferably, in some embodiments, a second gas is used as the reactant gas for dry etching to thin the first photoresist layer 400; this process ensures that the N-type GaN layer is not damaged while thinning the first photoresist. Specifically, the process parameters for dry etching include: upper power of 100W~300W, lower power of 50W~200W, chamber pressure of 3mtorr~10mtorr, and flow rate of the second gas of 40sccm~80sccm.

[0047] Specifically, the second gas includes O2, and more specifically, the second gas is a mixture of O2 and C4F6, with a volume ratio of O2 to C4F6 of (2~3):1. The surface of the first photoresist layer 400 obtained after thinning is relatively rough due to the etching gas. When the protrusion 211 and the first photoresist layer 400 are etched simultaneously in the later stage, the sidewalls of the protrusion 211 can also be etched to different degrees, thereby increasing the roughening rate and further improving the light extraction efficiency.

[0048] S63: Using the first gas as the reaction gas, dry etching is used to thin the protrusion and simultaneously thin the first photoresist layer; Specifically, the process parameters for dry etching include: upper power of 100W~500W, lower power of 50W~200W, chamber pressure of 3mtorr~10mtorr, and flow rate of the first gas of 40sccm~80sccm.

[0049] Specifically, see Figure 7 (c) During the dry etching process, not only is the protrusion 211 thinned, but the surrounding first photoresist layer 400 is also thinned.

[0050] Specifically, the first gas is selected from one or more of Cl2, BCl3, Ar, and SF6, but is not limited thereto. Preferably, in some embodiments, the first gas is a mixture of Cl2, BCl3, and SF6, and the volume ratio of Cl2, BCl3, and SF6 is (3~5):(2~5):(0.1~1), so that the ratio of the etching rate of the first photoresist layer 400 to the etching rate of the protrusion 211 during dry etching is 1:(0.8~1.2). This ensures that while thinning the protrusion 211, the protrusion 211 is not flattened, thus ensuring that the light extraction efficiency is not reduced.

[0051] S64: Remove the remaining first photoresist layer; S7: A third hole is formed on the third intermediate to expose the current blocking layer, thus obtaining the fourth intermediate; Specifically, a mask layer (SiO2 layer or photoresist layer) can be formed on the third intermediate first, and then the third hole 26 can be formed by photolithography etching process, that is, the third hole 26 can be formed by step etching. Since the protrusion 211 is thinned in this technical solution, the etching of the current blocking layer 3 is small during the step etching process, and the thinning thickness is ≤0.3μm.

[0052] Preferably, in some embodiments, step S7 includes: S71: A second photoresist layer is formed on one side of the N-type semiconductor layer of the third intermediate; S72: Etch away the N-type semiconductor layer, multiple quantum well layer, and P-type semiconductor layer in the first preset area to form a third hole that exposes the current blocking layer; Specifically, see Figure 8 The third hole 26 is formed on one side of the first hole 24, and can be used later to form the P electrode 43.

[0053] Specifically, see Figure 9 During the formation of the third hole 26, the current blocking layer 3 at its bottom will inevitably be etched, forming a pyramid-like shape. This technical solution can control the thinning thickness to less than 0.3μm, effectively improving the reliability of the vertical LED chip.

[0054] More preferably, in some embodiments, the N-type semiconductor layer 21, the multiple quantum well layer 22, and the P-type semiconductor layer 23 above the first preset region 100 are removed to form a third hole 26; the first preset region 100 includes the second preset region 200. Based on this embodiment, the amount of Ag used in the P-type conductive reflective layer can be reduced, thereby reducing production costs.

[0055] S73: Remove the remaining second photoresist layer.

[0056] S8: A passivation protective layer and a P electrode are formed on the fourth intermediate.

[0057] The passivation layer 9 covers the hole walls (sidewalls + bottom wall) of the third hole 26, as well as the N-type semiconductor layer 21 and the sidewalls of the epitaxial layer formed by step etching. The passivation layer 9 effectively passivates dangling bonds, reduces leakage current, improves the luminous efficiency of the vertical LED chip, and enhances reliability. Specifically, the passivation layer 9 can be a SiO2 layer, an Al2O3 layer, or a SiN layer. x The layer may be a stacked structure consisting of one or at least two of the layers, but is not limited thereto. Preferably, in some embodiments, the passivation protective layer 9 is a SiO2 layer with a thickness of 60 nm to 500 nm.

[0058] Specifically, the P-electrode 43 is a common metal stacked structure in the art, such as a stacked structure composed of Au, Ti, Cr, Pt, Cu, etc. Preferably, it is a Pt layer or an Au layer. The thickness of the P-electrode 43 is 500 nm to 1500 nm. The P-electrode 43 is electrically connected to the P-type reflective layer. Preferably, the P-electrode 43 is electrically connected to the P-type metal extension layer 42.

[0059] Preferably, in some embodiments, step S8 includes: S81: A passivation protective layer is formed on the fourth intermediate; S82: Remove the passivation protection layer and current blocking layer of the third preset area to expose the P-type metal extension layer; Specifically, the third preset area is located inside the third hole and is positioned near the edge of the conductive substrate.

[0060] S83: Forms a P electrode.

[0061] In summary, based on the fabrication method of the vertical LED chip of the present invention, firstly, the N-type conductive reflective layer 6, the metal bonding layer 7, and the conductive substrate 8 within the first hole 24 jointly achieve current extraction from the N-type semiconductor layer 21. These layers have low resistivity, improving the uniformity of current spread and thus enhancing the uniformity of light emission. Secondly, after stripping the patterned substrate 1 to expose the N-type semiconductor layer 21, its protrusions 211 are thinned, such that the height of the thinned protrusions 211 is less than or equal to 1.5 μm, and the difference between the tilt angle of the sidewall of the thinned protrusions 211 and the tilt angle of the sidewall of the protrusions 211 before thinning is less than or equal to 10°. This significantly reduces etching damage to the current blocking layer 3 during subsequent step etching, optimizing reliability; and it also maintains the light extraction function of the protrusions 211, ensuring high brightness of the vertical LED chip. Thirdly, the current introduced by the P electrode 43 is distributed through the P-type conductive reflective layer 41 and injected into different positions of the P-type semiconductor layer 23 through the second hole 31, thereby optimizing the current distribution and improving the uniformity of light emission. Fourthly, by separately fabricating the N-type conductive reflective layer 6 and the P-type conductive reflective layer 41 to reflect the light emitted from the multi-quantum well layer 22, the light reflectivity is effectively improved, thus increasing the brightness.

[0062] Specifically, based on the fabrication method of this application, by controlling the height of different protrusions 211 and the sidewall tilt angle, a vertical LED chip with dimensions of 1235μm × 1060μm was fabricated, and the chip brightness and operating voltage were tested at 350mA. The specific experimental results are shown in the table below:

[0063] As can be seen from the table, by changing the tilt angle of the sidewall of the protrusion before and after thinning, and controlling the height of the protrusion after thinning, the etching loss of the current blocking layer can be effectively reduced, the brightness can be improved, and the reliability of the vertical LED chip can be enhanced.

[0064] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A method for fabricating a vertical LED chip, characterized in that, include: (1) An N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer are sequentially formed on a patterned substrate, and a first hole is formed to expose the N-type semiconductor layer to obtain an epitaxial wafer; wherein the N-type semiconductor layer includes a protrusion and a body portion that are in contact with the patterned substrate; (2) A current blocking layer is formed on the epitaxial wafer, the current blocking layer covering the P-type semiconductor layer and the hole wall of the first hole; (3) A P-type conductive reflective layer is formed on the current blocking layer to obtain a first intermediate; wherein the P-type conductive reflective layer is electrically connected to the P-type semiconductor layer through a second hole provided on the current blocking layer; (4) An insulating layer, an N-type conductive reflective layer and a metal bonding layer are sequentially formed on the first intermediate to obtain a second intermediate; (5) Bond the second intermediate to the conductive substrate and remove the patterned substrate; (6) Thinning the protrusion to obtain a third intermediate; wherein the height of the protrusion after thinning is less than or equal to 1.5 μm, and the difference between the inclination angle of the sidewall of the protrusion after thinning and the inclination angle of the sidewall of the protrusion before thinning is less than or equal to 10°. (7) A third hole is formed on the third intermediate to expose the current blocking layer, thereby obtaining a fourth intermediate; (8) A passivation protective layer and a P electrode are formed on the fourth intermediate to obtain the finished vertical LED chip; Step (4) includes: (4.1) An insulating layer is formed on the first intermediate; (4.2) A fourth hole is formed on the insulating layer on the bottom wall of the first hole to expose the N-type semiconductor layer; (4.3) An N-type conductive reflective layer is formed and patterned, wherein the N-type conductive reflective layer is electrically connected to the N-type semiconductor layer through the fourth hole; the projection of the N-type conductive reflective layer on the conductive substrate at least partially overlaps with the projection of the P-type conductive reflective layer on the conductive substrate. (4.4) A metal bonding layer is formed to obtain the second intermediate.

2. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The patterned substrate has multiple raised patterns, the height of which is 1μm~2.5μm; and / or The thickness of the N-type semiconductor layer is 2μm~5μm, the height of the protrusion before thinning is 1μm~2.5μm, and the height of the protrusion after thinning is 0.6μm~1.2μm.

3. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, Step (6) includes: (6.1) A first photoresist layer is formed on one side of the N-type semiconductor layer of the third intermediate; (6.2) Etch to thin the first photoresist layer to expose the top of the protrusion; (6.3) Using the first gas as the reaction gas, the protrusion is thinned by dry etching, and the first photoresist layer is thinned at the same time; (6.4) Remove the remaining first photoresist layer; The thickness of the first photoresist layer before thinning is 1 μm to 2 μm greater than the height of the protrusion before thinning.

4. The method for fabricating a vertical LED chip as described in claim 3, characterized in that, In step (6.2), the first photoresist layer is thinned by dry etching using a second gas as the reactant gas; wherein the second gas includes O2; the process parameters for dry etching include: upper power of 100W~300W, lower power of 50W~200W, chamber pressure of 3mtorr~10mtorr, and flow rate of the second gas of 40sccm~80sccm; and / or In step (6.3), the first gas is selected from one or more of Cl2, BCl3, Ar, and SF6; the dry etching process parameters include: upper power of 100W~500W, lower power of 50W~200W, chamber pressure of 3mtorr~10mtorr, and flow rate of the first gas of 40sccm~80sccm.

5. The method for fabricating a vertical LED chip as described in claim 3, characterized in that, In step (6.3), the first gas is a mixture of Cl2, BCl3 and SF6, and the volume ratio of Cl2, BCl3 and SF6 is (3~5):(2~5):(0.1~1), so that the ratio of the etching rate of the first photoresist layer to the etching rate of the protrusion during the dry etching process is 1:(0.8~1.2).

6. The method for fabricating a vertical LED chip as described in claim 4, characterized in that, In step (6.2), the second gas is a mixture of O2 and C4F6, and the volume ratio of O2 to C4F6 is (2~3):

1.

7. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, Step (7) includes: (7.1) A second photoresist layer is formed on one side of the N-type semiconductor layer of the third intermediate; (7.2) Etching away the N-type semiconductor layer, multiple quantum well layer, and P-type semiconductor layer in the first preset region to form a third hole exposing the current blocking layer; wherein the bottom current blocking layer of the third hole is etched and thinned, and a pyramid-like morphology is formed on the surface; the thinning thickness of the current blocking layer is ≤0.3μm; (7.3) Remove the remaining second photoresist layer.

8. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, Step (3) includes: (3.1) Etch the current blocking layer to form a second hole surrounding the first hole; (3.2) Form a P-type conductive reflective layer and pattern it to expose the current blocking layer of the second preset region; (3.3) A P-type metal extension layer is formed to obtain a first intermediate; wherein the P-type metal extension layer covers the P-type conductive reflective layer and the current blocking layer of the second preset region; Step (8) includes: (8.1) A passivation protective layer is formed on the fourth intermediate; (8.2) Remove the passivation protective layer and current blocking layer of the third preset area to expose the P-type metal extension layer; the third preset area is located in the third hole and is disposed near the edge of the conductive substrate; (8.3) A P electrode is formed, wherein the P electrode is electrically connected to the P-type metal extension layer.

9. A vertical LED chip, characterized in that, It is prepared by the method for preparing a vertical LED chip as described in any one of claims 1 to 8.

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