A harmonic analysis method based on double-buffer window function optimization

Abstract

This invention discloses a harmonic analysis method based on double-buffered window function optimization, relating to the field of power system harmonic analysis and signal processing technology. The method includes steps such as hardware initialization, double-buffered initialization, FFT module parameter configuration, data acquisition, buffer switching, data extraction, windowing, and FFT processing. It achieves parallel data acquisition and processing through a double-buffered ping-pong mechanism, applies the Hanning window function to suppress spectral leakage, and performs FFT calculations after recovering the signal amplitude using a compensation factor. This method improves the continuity and real-time performance of data acquisition, controls harmonic amplitude errors within ±0.5%, optimizes hardware resource utilization, and is suitable for power grid power quality monitoring.

Description

Technical Field

[0001] This invention relates to the field of power system harmonic analysis and signal processing technology, specifically a harmonic analysis method based on double-buffered window function optimization. Background Technology

[0002] With the widespread application of nonlinear loads in power systems, harmonic pollution of power grids is becoming increasingly prominent, making accurate harmonic analysis crucial for power quality assessment and fault diagnosis. Existing technologies mainly face the following bottlenecks:

[0003] Traditional single-buffering mechanisms employ a serial "acquisition-computation-wait" mode, which cannot synchronously acquire new data during FFT calculation. This results in the data of the preset number of sampling points matching the power frequency cycle within the power frequency cycle being overwritten or lost due to processing delays, causing sampling gaps and non-uniform sampling, ultimately leading to deviations in harmonic amplitude and phase estimation. Furthermore, the processor resource utilization rate is low in single-buffering mode, making it difficult to meet the requirements of real-time power grid monitoring for dynamic response capabilities.

[0004] The FFT algorithm is sensitive to non-integer period truncation. When the period of the power grid signal does not match the sampling window, the non-periodic extension of the time domain signal will lead to frequency domain energy diffusion (spectral leakage), which manifests as amplitude distortion at adjacent frequency points. Side lobe interference may cause the energy of strong harmonic components to diffuse to adjacent frequency points.

[0005] Traditional rectangular windows have low sidelobe attenuation (only -18dB / octave). In complex harmonic scenarios, the superposition of leakage effects can lead to amplitude estimation errors exceeding ±15%, which seriously affects the measurement accuracy of harmonic parameters. Summary of the Invention

[0006] The purpose of this invention is to provide a harmonic analysis method based on double-buffered window function optimization to solve the problems raised in the prior art.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A harmonic analysis method based on double-buffered window function optimization includes the following steps:

[0009] S1. After the system is powered on, hardware initialization is performed, and the parameters of the STM32F429 microcontroller, AD7606BADC sampling device and timer are configured.

[0010] S2. After the system hardware initialization is completed, perform dual buffer initialization, create two buffers A and B of the same size, and pre-set each buffer to store the number of sampling points that match the power frequency cycle and are matched with the FFT analysis; set buffer A as a write buffer and B as an idle state, and use a structure to mark the buffer read / write state, pointer position and data storage area to build the hardware foundation for alternating storage.

[0011] S3. After the double buffer initialization is completed, according to the preset sampling rules of the double buffer, the number of analysis points of the FFT module is configured to be the same as the number of sampling points and the number of sampling points that matches the power frequency cycle. The frequency resolution is calculated according to the relationship between the sampling frequency and the number of analysis points, and the calculation rules for frequency domain conversion are established.

[0012] After the S4 and FFT module parameters are configured, a conversion start signal is periodically sent to the AD7606B through a timer. After the AD7606B completes sampling, the STM32F429 interrupt is triggered by the falling edge of the BUSY pin, and the sampled data is written to the current write buffer in sequence to start the data acquisition process.

[0013] S5. When the write buffer is full of sampling point data matching the power frequency cycle, the data preparation status flag of the full buffer is set to 1 and switched to the read buffer through the dual buffer management structure. At the same time, the other buffer is switched to the write buffer, so that the acquisition of new data and the processing of existing data are carried out synchronously.

[0014] S6. After the buffer is switched to read mode, the main task periodically checks the data preparation status flag of the read buffer. When the flag is detected to be 1, all data in the buffer is read and the flag is cleared to zero.

[0015] S7. After extracting the buffer data, the Hanning window function is applied to the time domain data for windowing processing. The compensation factor is obtained by calculating the sum of the window function coefficients and the signal amplitude is recovered. Then, a fast Fourier transform is performed on the processed data to output the amplitude information of each frequency component, thus completing the harmonic analysis.

[0016] S1 further includes the following:

[0017] S1.1: After the system is powered on, the hardware resources of the STM32F429 microcontroller are initialized, including configuring the timer's working mode, counting period and interrupt parameters, so that the timer can periodically send the conversion start signal to the AD7606B ADC chip through the GPIO pin, providing a timing trigger mechanism for subsequent data acquisition;

[0018] S1.2: After completing the initialization of the STM32F429, initialize and configure the AD7606B ADC chip, including setting its sampling mode, conversion rate, data output format and pin levels, to ensure that the AD7606B is in a ready state and can respond to the sampling command triggered by the timer and complete the signal analog-to-digital conversion.

[0019] S2 further includes the following:

[0020] S2.1: The structure definition of a double buffer includes two parts: a single buffer structure and a double buffer management structure;

[0021] A single buffer structure describes a single storage unit and includes a status flag, a write position pointer, and a data storage array: the status flag uses an 8-bit unsigned integer to identify the buffer status, with 0 indicating that it is not full and can be written to, and 1 indicating that it is full and can be read from; the write position pointer is a 16-bit unsigned integer, starting from 0 to locate the data storage position; the data storage array is an 8-bit unsigned integer array of the number of sampling points matching the power frequency cycle, used to store the sampled data of the number of sampling points matching the power frequency cycle within the power frequency cycle;

[0022] The dual-buffer management structure is used to coordinate the control of two buffers, including a data readiness flag, the current read / write buffer index, and a buffer array: the data readiness flag uses an 8-bit unsigned integer to indicate the data readiness status, 0 for not ready and 1 for ready; the current write buffer index points to the buffer that is receiving data, and the current read buffer index points to the buffer that can extract data; the buffer array contains two single buffer instances, which are the physical carriers for implementing write-read ping-pong switching.

[0023] S2.2: Initialize the double buffer according to the double buffer structure; specifically: first, declare the double buffer management variable as an instance to carry the buffer state and data storage; then, set the data storage area of ​​the two buffers to 0 through memory zeroing operation; then initialize the status flag and pointer, set the data preparation flag to 0, indicating that there is no ready data; the current write buffer index is 0, indicating that the initial write buffer 0 is 0; the current read buffer index is -1, indicating that there is no read buffer; finally, by looping through the two buffers, set the status flag of each buffer to 0, indicating that it is writable, and set the write position pointer to 0, indicating that storage starts from the beginning of the array, establishing the initial state of writing to buffer 0 and waiting for buffer 1, providing the basis for the parallel mechanism of switching to the read buffer when it is full and activating the writing of the other buffer at the same time.

[0024] S3 further includes the following:

[0025] S3.1: After the double buffer initialization is completed, the number of analysis points of the FFT module is configured to be the same as the number of sampling points and matched with the power frequency cycle. This ensures that the FFT calculation covers the complete power frequency cycle sampling data and that the time domain signal is discretized at equal intervals to the number of sampling points that match the power frequency cycle, thus providing a complete time domain data foundation for frequency domain conversion.

[0026] S3.2: Based on the sampling frequency f s The relationship between the number of analysis points N and the frequency resolution of the FFT module is calculated and configured using the following formula:

[0027]

[0028] Where Δf is the frequency resolution, f s Where N is the sampling frequency, and N is the number of FFT analysis points, which is the same as the number of sampling points.

[0029] S4 further includes the following:

[0030] S4.1: After the FFT module parameters are configured, the STM32F429 microcontroller starts its internal timer and sends a periodic conversion start signal to the AD7606B ADC chip through the GPIO pin. The timer generates a pulse signal according to the preset sampling period, which is synchronized with the power frequency. This signal is transmitted to the trigger input of the AD7606B through hardware connection, driving it to start the analog-to-digital conversion process. After each trigger signal is sent, the AD7606B samples the input power grid analog signal, discretizing the continuous signal into digital quantities to provide the original sampled values ​​for subsequent data processing.

[0031] S4.2: After completing a single sampling, the AD7606B sends a conversion completion interrupt signal to the STM32F429 by changing the state of the BUSY pin from high to low. The microcontroller captures this falling edge event through the external interrupt interface and immediately executes the interrupt handler: it reads the current sampled value from the AD7606B's data output pin and writes the data to the data storage area of ​​the buffer according to the current write buffer index recorded in the dual buffer management structure, initially set to buffer 0. The write position is located by the write position pointer of the buffer. Each time data is written, the write position pointer automatically increments by 1 until the upper limit of the buffer capacity is reached, triggering the switching logic. The upper limit of the capacity is the number of sampling points matching the power frequency cycle.

[0032] S5 further includes the following:

[0033] S5.1: When the write position pointer of the current write buffer reaches the upper limit of the buffer capacity, it is determined that the buffer is full. At this time, the status flag of the buffer is set to 1 through the double buffer management structure, indicating that the data is ready for the main task to extract. At the same time, the status field of the buffer is updated from 0 to 1, completing the state transition from the write buffer to the read buffer.

[0034] S5.2: After completing the write-full mark, first switch the current write buffer index from 0 to 1, pointing to another free buffer, making it the new write buffer; at the same time, set the current read buffer index to the original write buffer index, establishing a parallel process of writing data to the new buffer and retrieving data from the original buffer; reset the write position pointer of the new write buffer to 0, and start receiving the sampling data of the next cycle.

[0035] S6 further includes the following:

[0036] S6.1: After the buffer switches to read mode, the main task polls the data preparation flag in the dual-buffer management structure at a fixed period. This flag is used to indicate whether the read buffer has completed data writing and is ready for retrieval: when the data preparation flag is 1, it indicates that the corresponding buffer has been filled with the number of sampling points matching the power frequency cycle and can be processed later; when the data preparation flag is 0, the main task continues to wait and does not perform data retrieval operation.

[0037] S6.2: When the main task detects that the data preparation status flag of a certain buffer is 1, it extracts all sample point data from the data storage area of ​​the buffer in sequence according to the current read buffer index in the double buffer management structure. After the data extraction is completed, the data preparation status flag is immediately set to 0 and the read buffer index is reset to -1, indicating that the buffer has completed data processing and can re-enter the write buffer queue.

[0038] S7 further includes the following:

[0039] S7.1: After extracting time-domain data from the buffer, the Hanning window function is applied to window the data to suppress spectral leakage. The Hanning window function calculates the window coefficient for each sampling point using a formula, and then multiplies the original data by the corresponding window coefficient to smooth the signal edges and reduce frequency domain energy diffusion caused by non-integer period truncation; the window coefficient w i The calculation formula is as follows:

[0040]

[0041] Where i is the sampling point index and N is the number of sampling points;

[0042] Since the Hanning window attenuates the signal amplitude, it is necessary to calculate the sum of the window function coefficients ∑w. i Obtain compensation factor Then, the windowed data is multiplied by a compensation factor to restore the true amplitude of the signal;

[0043] S7.2: Perform a Fast Fourier Transform (FFT) on the windowed and compensated time-domain data to convert the signal from the time domain to the frequency domain; the FFT calculation is based on the number of analysis points configured in the initialization phase, and the complex amplitude of each frequency component is efficiently calculated through the butterfly algorithm. After taking the modulus, the real amplitude of the corresponding frequency point is obtained; where the number of analysis points is consistent with the number of sampling points.

[0044] Then, based on the power frequency characteristics of the power grid signal, with the fundamental frequency being the fundamental frequency of the target signal, the amplitude information of the fundamental frequency and its harmonics is extracted to form the spectrum distribution result.

[0045] Compared with the prior art, the beneficial effects of the present invention are:

[0046] 1. Improved continuity and real-time performance of data acquisition: By using two buffers to alternately perform the roles of writing and reading, such as switching to reading when buffer A is full and simultaneously activating buffer B for writing, seamless acquisition of the preset number of sampling points matching the power frequency cycle is ensured, eliminating the risk of data loss during FFT calculation. In addition, the parallel acquisition-processing mode enables the system to complete the entire sampling-switching-analysis process within a 20ms power frequency cycle, meeting hard real-time requirements and improving the rapid response capability to power grid faults.

[0047] 2. Improved accuracy of harmonic analysis: The Hanning window function smoothly weights the time-domain signal using a formula, effectively suppressing spectral leakage caused by non-integer period truncation, concentrating frequency domain energy at the true frequency point, and reducing sidelobe interference by more than 90%. As experimental data shows, after windowing, the amplitude error of the third harmonic decreased from ±15% to ±0.5%. The true amplitude of the signal is restored by the compensation factor, ensuring the energy accuracy of the FFT results, and controlling the amplitude measurement error of the fundamental wave and each harmonic within ±0.5%.

[0048] 3. Optimized hardware resource utilization: The dual buffering mechanism enables the processor to perform FFT calculations synchronously during the data acquisition phase, avoiding the idle period of calculation in the single buffer mode. The hardware resource utilization is improved by more than 50%, reducing system power consumption while enhancing multi-tasking capabilities. Attached Figure Description

[0049] Figure 1 This is a flowchart of a harmonic analysis method based on double buffer window function optimization according to the present invention.

[0050] Figure 2This is a comparison of the spectrum of a harmonic analysis method based on double-buffered window function optimization according to the present invention, with and without windowing. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Example: Figures 1-2 As shown, the present invention provides a technical solution.

[0053] A harmonic analysis method based on double-buffered window function optimization includes the following steps:

[0054] S1. After the system is powered on, hardware initialization is performed, and the parameters of the STM32F429 microcontroller, AD7606BADC sampling device and timer are configured.

[0055] S2. After the system hardware initialization is completed, perform dual buffer initialization, create two buffers A and B of the same size, and pre-set each buffer to store the number of sampling points that match the power frequency cycle and are matched with the FFT analysis; set buffer A as a write buffer and B as an idle state, and use a structure to mark the buffer read / write state, pointer position and data storage area to build the hardware foundation for alternating storage.

[0056] S3. After the double buffer initialization is completed, according to the preset sampling rules of the double buffer, the number of analysis points of the FFT module is configured to be the same as the number of sampling points and the number of sampling points that matches the power frequency cycle. The frequency resolution is calculated according to the relationship between the sampling frequency and the number of analysis points, and the calculation rules for frequency domain conversion are established.

[0057] After the S4 and FFT module parameters are configured, a conversion start signal is periodically sent to the AD7606B through a timer. After the AD7606B completes sampling, the STM32F429 interrupt is triggered by the falling edge of the BUSY pin, and the sampled data is written to the current write buffer in sequence to start the data acquisition process.

[0058] S5. When the write buffer is full of sampling point data matching the power frequency cycle, the data preparation status flag of the full buffer is set to 1 and switched to the read buffer through the dual buffer management structure. At the same time, the other buffer is switched to the write buffer, so that the acquisition of new data and the processing of existing data are carried out synchronously.

[0059] S6. After the buffer is switched to read mode, the main task periodically checks the data preparation status flag of the read buffer. When the flag is detected to be 1, all data in the buffer is read and the flag is cleared to zero.

[0060] S7. After extracting the buffer data, the Hanning window function is applied to the time domain data for windowing processing. The compensation factor is obtained by calculating the sum of the window function coefficients and the signal amplitude is recovered. Then, a fast Fourier transform is performed on the processed data to output the amplitude information of each frequency component, thus completing the harmonic analysis.

[0061] S1 further includes the following:

[0062] S1.1: After the system is powered on, the hardware resources of the STM32F429 microcontroller are initialized, including configuring the timer's working mode, counting period and interrupt parameters, so that the timer can periodically send the conversion start signal to the AD7606B ADC chip through the GPIO pin, providing a timing trigger mechanism for subsequent data acquisition;

[0063] S1.2: After completing the initialization of the STM32F429, initialize and configure the AD7606B ADC chip, including setting its sampling mode, conversion rate, data output format and pin levels, to ensure that the AD7606B is in a ready state and can respond to the sampling command triggered by the timer and complete the signal analog-to-digital conversion.

[0064] S2 further includes the following:

[0065] S2.1: The structure definition of a double buffer includes two parts: a single buffer structure and a double buffer management structure;

[0066] A single buffer structure describes a single storage unit and includes a status flag, a write position pointer, and a data storage array: the status flag uses an 8-bit unsigned integer to identify the buffer status, with 0 indicating that it is not full and can be written to, and 1 indicating that it is full and can be read from; the write position pointer is a 16-bit unsigned integer, starting from 0 to locate the data storage position; the data storage array is an 8-bit unsigned integer array of the number of sampling points matching the power frequency cycle, used to store the sampled data of the number of sampling points matching the power frequency cycle within the power frequency cycle;

[0067] The dual-buffer management structure is used to coordinate the control of two buffers, including a data readiness flag, the current read / write buffer index, and a buffer array: the data readiness flag uses an 8-bit unsigned integer to indicate the data readiness status, 0 for not ready and 1 for ready; the current write buffer index points to the buffer that is receiving data, and the current read buffer index points to the buffer that can extract data; the buffer array contains two single buffer instances, which are the physical carriers for implementing write-read ping-pong switching.

[0068] S2.2: Initialize the double buffer according to the double buffer structure; specifically: first, declare the double buffer management variable as an instance to carry the buffer state and data storage; then, set the data storage area of ​​the two buffers to 0 through memory zeroing operation; then initialize the status flag and pointer, set the data preparation flag to 0, indicating that there is no ready data; the current write buffer index is 0, indicating that the initial write buffer 0 is 0; the current read buffer index is -1, indicating that there is no read buffer; finally, by looping through the two buffers, set the status flag of each buffer to 0, indicating that it is writable, and set the write position pointer to 0, indicating that storage starts from the beginning of the array, establishing the initial state of writing to buffer 0 and waiting for buffer 1, providing the basis for the parallel mechanism of switching to the read buffer when it is full and activating the writing of the other buffer at the same time.

[0069] S3 further includes the following:

[0070] S3.1: After the double buffer initialization is completed, the number of analysis points of the FFT module is configured to be the same as the number of sampling points and matched with the power frequency cycle. This ensures that the FFT calculation covers the complete power frequency cycle sampling data and that the time domain signal is discretized at equal intervals to the number of sampling points that match the power frequency cycle, thus providing a complete time domain data foundation for frequency domain conversion.

[0071] S3.2: Based on the sampling frequency f s The relationship between the number of analysis points N and the frequency resolution of the FFT module is calculated and configured using the following formula:

[0072]

[0073] Where Δf is the frequency resolution, f s Where N is the sampling frequency, and N is the number of FFT analysis points, which is the same as the number of sampling points;

[0074] The sampling frequency is 12.8kHz, which is determined by collecting 256 points within a 20ms power frequency cycle and is a fixed value. The frequency resolution is the sampling frequency divided by the number of analysis points, which is 50Hz. This value is consistent with the fundamental frequency of the power grid, so that the frequency scale of the FFT result accurately corresponds to the fundamental frequency of 50Hz and its harmonics, ensuring that the amplitude information of each frequency component can be accurately extracted during frequency domain analysis.

[0075] S4 further includes the following:

[0076] S4.1: After the FFT module parameters are configured, the STM32F429 microcontroller starts its internal timer and sends a periodic conversion start signal to the AD7606B ADC chip through the GPIO pin. The timer generates a pulse signal according to the preset sampling period, which is synchronized with the power frequency. This signal is transmitted to the trigger input of the AD7606B through hardware connection, driving it to start the analog-to-digital conversion process. After each trigger signal is sent, the AD7606B samples the input power grid analog signal, discretizing the continuous signal into digital quantities to provide the original sampled values ​​for subsequent data processing.

[0077] S4.2: After completing a single sampling, the AD7606B sends a conversion completion interrupt signal to the STM32F429 by changing the state of the BUSY pin from high to low. The microcontroller captures this falling edge event through the external interrupt interface and immediately executes the interrupt handler: it reads the current sampled value from the AD7606B's data output pin and writes the data to the data storage area of ​​the buffer according to the current write buffer index recorded in the dual buffer management structure, initially set to buffer 0. The write position is located by the write position pointer of the buffer. Each time data is written, the write position pointer automatically increments by 1 until the upper limit of the buffer capacity is reached, triggering the switching logic. The upper limit of the capacity is the number of sampling points matching the power frequency cycle.

[0078] S5 further includes the following:

[0079] S5.1: When the write position pointer of the current write buffer reaches the upper limit of the buffer capacity, it is determined that the buffer is full. At this time, the status flag of the buffer is set to 1 through the double buffer management structure, indicating that the data is ready for the main task to extract. At the same time, the status field of the buffer is updated from 0 to 1, completing the state transition from the write buffer to the read buffer.

[0080] S5.2: After completing the write-full mark, first switch the current write buffer index from 0 to 1, pointing to another free buffer, making it the new write buffer; at the same time, set the current read buffer index to the original write buffer index, establishing a parallel process of writing data to the new buffer and retrieving data from the original buffer; reset the write position pointer of the new write buffer to 0, and start receiving the sampling data of the next cycle.

[0081] S6 further includes the following:

[0082] S6.1: After the buffer switches to read mode, the main task polls the data preparation flag in the dual-buffer management structure at a fixed period. This flag is used to indicate whether the read buffer has completed data writing and is ready for retrieval: when the data preparation flag is 1, it indicates that the corresponding buffer has been filled with the number of sampling points matching the power frequency cycle and can be processed later; when the data preparation flag is 0, the main task continues to wait and does not perform data retrieval operation.

[0083] S6.2: When the main task detects that the data preparation status flag of a certain buffer is 1, it extracts all sample point data from the data storage area of ​​the buffer in sequence according to the current read buffer index in the double buffer management structure. After the data extraction is completed, the data preparation status flag is immediately set to 0 and the read buffer index is reset to -1, indicating that the buffer has completed data processing and can re-enter the write buffer queue.

[0084] S7 further includes the following:

[0085] S7.1: After extracting time-domain data from the buffer, the Hanning window function is applied to window the data to suppress spectral leakage. The Hanning window function calculates the window coefficient for each sampling point using a formula, and then multiplies the original data by the corresponding window coefficient to smooth the signal edges and reduce frequency domain energy diffusion caused by non-integer period truncation; the window coefficient w i The calculation formula is as follows:

[0086]

[0087] Where i is the sampling point index and N is the number of sampling points;

[0088] Since the Hanning window attenuates the signal amplitude, it is necessary to calculate the sum of the window function coefficients ∑w. i Obtain compensation factor Then, the windowed data is multiplied by a compensation factor to restore the true amplitude of the signal;

[0089] S7.2: Perform a Fast Fourier Transform (FFT) on the windowed and compensated time-domain data to convert the signal from the time domain to the frequency domain; the FFT calculation is based on the number of analysis points configured in the initialization phase, and the complex amplitude of each frequency component is efficiently calculated through the butterfly algorithm. After taking the modulus, the real amplitude of the corresponding frequency point is obtained; where the number of analysis points is consistent with the number of sampling points.

[0090] Then, based on the power frequency characteristics of the power grid signal, with the fundamental frequency being the fundamental frequency of the target signal, the amplitude information of the fundamental frequency and its harmonics is extracted to form the spectrum distribution result.

[0091] A power grid monitoring device needs to perform real-time analysis of harmonics generated by nonlinear loads in order to assess power quality;

[0092] 1. After the system powers on, the core hardware is initialized first:

[0093] 1. STM32F429 microcontroller and timer configuration:

[0094] The microcontroller's internal timer is configured via registers to generate a trigger signal with a 20-millisecond cycle (synchronized with the power grid frequency). This signal is periodically sent to the AD7606BADC chip via a GPIO pin, driving it to initiate the analog-to-digital conversion process. The timer interrupt priority is set to the highest level to ensure the accuracy and real-time performance of the trigger signal.

[0095] 2. AD7606B ADC chip initialization:

[0096] Configure the AD7606B to operate in single-channel continuous sampling mode, with a sampling rate of 12.8 kHz (i.e., acquiring 256 data points every 20 milliseconds), and the data output format as 16-bit binary two's complement. Simultaneously, connect the AD7606B's BUSY pin to the microcontroller's external interrupt interface to send an interrupt signal after sampling is complete.

[0097] 3. Definition and initialization of the double-buffer structure:

[0098] Define a management structure containing two buffers, each buffer including a status flag, a write position pointer, and a data storage area; specifically:

[0099] Status flags: 0 indicates that the buffer is writable, and 1 indicates that the buffer is full and can be read.

[0100] Write position pointer: It starts counting from 0 and automatically increments by 1 for each piece of data written, until the buffer capacity limit of 256 points is reached;

[0101] Data storage area: Used to store digital signals acquired by AD7606B in sequence (each buffer can store 256 points of 16-bit integer data).

[0102] During initialization, the first buffer is set as the current write buffer, the second buffer is set to the idle state, the status flags of all buffers are set to 0, the write position pointer is set to 0, and the data storage area is cleared.

[0103] II. Data Acquisition Process and Dual Buffer Switching Mechanism: Timed Triggering of Sampling and Interruption Response

[0104] The timer sends a conversion start signal to the AD7606B every 20 milliseconds. Upon receiving the signal, the AD7606B samples the analog grid signal and, after completing the conversion, triggers a microcontroller interrupt via the falling edge of the BUSY pin. In the interrupt handler, the microcontroller reads the sampled data from the AD7606B and writes the data to the specified position in the current write buffer (initially the first buffer) according to the current write buffer index (located by the write position pointer). The write position pointer automatically increments by 1 for each data entry. The buffer full detection and switching logic is as follows:

[0105] When the write position pointer of the current write buffer reaches 256, it is determined that the buffer is full. At this time: the status flag of the buffer is set to 1 (indicating that it is readable), and the global data ready flag is set; the current write buffer index is switched to another buffer (such as switching from 0 to 1), the write position pointer of the new write buffer is reset to 0, and the sampling data of the next cycle is received; the main task checks the global data ready flag by polling. When the flag is detected to be 1, all 256 data points of the full buffer are read according to the current read buffer index, the status flag of the buffer is reset to 0, the data ready flag is cleared, and preparation is made for the next cycle of writing.

[0106] III. Hanning Window Processing and Frequency Domain Analysis: Windowing and Amplitude Compensation for Time Domain Data

[0107] After extracting 256 points of time-domain data from the buffer, the Hanning window function is applied for windowing to suppress spectral leakage. The window coefficient for each sampling point is calculated using this function, and the original data is multiplied by the corresponding window coefficient to make the signal edges transition smoothly and reduce frequency domain energy diffusion caused by non-integer period truncation.

[0108] Since the Hanning window attenuates the signal amplitude, it is necessary to calculate the sum of the window function coefficients ∑w. i Obtain compensation factor The windowed data is multiplied by a compensation factor to recover the true amplitude of the signal. Specifically, the compensation factor equals the number of sampling points divided by the sum of the window function coefficients, ensuring the energy accuracy of subsequent frequency domain analysis. Fast Fourier Transform (FFT) and Harmonic Analysis:

[0109] A 256-point Fast Fourier Transform (FFT) is performed on the windowed and compensated time-domain data to convert the signal from the time domain to the frequency domain. The frequency resolution of the FFT calculation is 50 Hz (calculated from a sampling frequency of 12.8 kHz and 256 sampling points), consistent with the fundamental frequency of the power grid. The amplitude information of the fundamental frequency (50 Hz) and its harmonics (such as 150 Hz, 250 Hz, etc.) is extracted from the FFT results to form a spectral distribution result, thereby completing the accurate analysis of the harmonic content of the power grid. Through the above-mentioned double buffering mechanism and Hanning window optimization, the system realizes the parallel execution of data acquisition and processing. Experimental data shows that after windowing, the amplitude error of the third harmonic is reduced from ±15% to ±0.5%, effectively improving the real-time performance and accuracy of harmonic analysis and meeting the high requirements of the power system for power quality monitoring.

[0110] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A harmonic analysis method based on double-buffered window function optimization, characterized in that: Includes the following steps: S1. After the system is powered on, hardware initialization is performed to configure the parameters of the STM32F429 microcontroller, AD7606B ADC sampling device and timer. S2. After the system hardware initialization is completed, perform dual buffer initialization, create two buffers A and B of the same size, and pre-set each buffer to store the number of sampling points that match the power frequency cycle and are matched with the FFT analysis; set buffer A as a write buffer and B as an idle state, and use a structure to mark the buffer read / write state, pointer position and data storage area to build the hardware foundation for alternating storage. S3. After the double buffer initialization is completed, according to the preset sampling rules of the double buffer, the number of analysis points of the FFT module is configured to be the same as the number of sampling points and the number of sampling points that matches the power frequency cycle. The frequency resolution is calculated according to the relationship between the sampling frequency and the number of analysis points, and the calculation rules for frequency domain conversion are established. After the S4 and FFT module parameters are configured, a conversion start signal is periodically sent to the AD7606B through a timer. After the AD7606B completes sampling, the STM32F429 interrupt is triggered by the falling edge of the BUSY pin, and the sampled data is written to the current write buffer in sequence to start the data acquisition process. S5. When the write buffer is full of sampling point data matching the power frequency cycle, the data preparation status flag of the full buffer is set to 1 and switched to the read buffer through the dual buffer management structure. At the same time, the other buffer is switched to the write buffer, so that the acquisition of new data and the processing of existing data are carried out synchronously. S6. After the buffer is switched to read mode, the main task periodically checks the data preparation status flag of the read buffer. When the flag is detected to be 1, all data in the buffer is read and the flag is cleared to zero. S7. After extracting the buffer data, the Hanning window function is applied to the time domain data for windowing processing. The compensation factor is obtained by calculating the sum of the window function coefficients and the signal amplitude is restored. Then, a fast Fourier transform is performed on the processed data to output the amplitude information of each frequency component and complete the harmonic analysis. S2 further includes the following: S2.1: The structure definition of a double buffer includes two parts: a single buffer structure and a double buffer management structure; A single buffer structure describes a single storage unit and includes a status flag, a write position pointer, and a data storage array: the status flag uses an 8-bit unsigned integer to identify the buffer status, with 0 indicating that it is not full and can be written to, and 1 indicating that it is full and can be read from; the write position pointer is a 16-bit unsigned integer, starting from 0 to locate the data storage position; the data storage array is an 8-bit unsigned integer array of the number of sampling points matching the power frequency cycle, used to store the sampled data of the number of sampling points matching the power frequency cycle within the power frequency cycle; The dual-buffer management structure is used to coordinate the control of two buffers, including a data readiness flag, the current read / write buffer index, and a buffer array: the data readiness flag uses an 8-bit unsigned integer to indicate the data readiness status, 0 for not ready and 1 for ready; the current write buffer index points to the buffer that is receiving data, and the current read buffer index points to the buffer that can extract data; the buffer array contains two single buffer instances, which are the physical carriers for implementing write-read ping-pong switching. S2.2: Initialize the double buffer according to the double buffer structure; specifically: first, declare the double buffer management variable as an instance to carry the buffer state and data storage; then, set the data storage area of ​​the two buffers to 0 through memory zeroing operation; then initialize the status flag and pointer, set the data preparation flag to 0, indicating that there is no ready data; the current write buffer index is 0, indicating that the initial write buffer 0 is 0; the current read buffer index is -1, indicating that there is no read buffer; finally, by looping through the two buffers, set the status flag of each buffer to 0, indicating that it is writable, and set the write position pointer to 0, indicating that storage starts from the beginning of the array, establishing the initial state of writing to buffer 0 and waiting for buffer 1, providing the basis for the parallel mechanism of switching to the read buffer when it is full and activating the writing of the other buffer at the same time.

2. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: S1 further includes the following: S1.1: After the system is powered on, the hardware resources of the STM32F429 microcontroller are initialized, including configuring the timer's working mode, counting period and interrupt parameters, so that the timer can periodically send the conversion start signal to the AD7606B ADC chip through the GPIO pin, providing a timing trigger mechanism for subsequent data acquisition; S1.2: After completing the initialization of the STM32F429, initialize and configure the AD7606B ADC chip, including setting its sampling mode, conversion rate, data output format and pin levels, to ensure that the AD7606B is in a ready state and can respond to the sampling command triggered by the timer and complete the signal analog-to-digital conversion.

3. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: S3 further includes the following: S3.1: After the double buffer initialization is completed, the number of analysis points of the FFT module is configured to be the same as the number of sampling points and matched with the power frequency cycle. This ensures that the FFT calculation covers the complete power frequency cycle sampling data and that the time domain signal is discretized at equal intervals to the number of sampling points that match the power frequency cycle, thus providing a complete time domain data foundation for frequency domain conversion. S3.2: Based on the sampling frequency f s The relationship between the number of analysis points N and the frequency resolution of the FFT module is calculated and configured using the following formula: ； Where Δf is the frequency resolution, f s Where N is the sampling frequency, and N is the number of FFT analysis points, which is the same as the number of sampling points.

4. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: S4 further includes the following: S4.1: After the FFT module parameters are configured, the STM32F429 microcontroller starts its internal timer and sends a periodic conversion start signal to the AD7606B ADC chip through the GPIO pin. The timer generates a pulse signal according to the preset sampling period, which is synchronized with the power frequency. This signal is transmitted to the trigger input of the AD7606B through hardware connection, driving it to start the analog-to-digital conversion process. After each trigger signal is sent, the AD7606B samples the input power grid analog signal, discretizing the continuous signal into digital quantities to provide the original sampled values ​​for subsequent data processing. S4.2: After completing a single sampling, the AD7606B sends a conversion completion interrupt signal to the STM32F429 by changing the state of the BUSY pin from high to low. The microcontroller captures this falling edge event through the external interrupt interface and immediately executes the interrupt handler: it reads the current sampled value from the AD7606B's data output pin and writes the data to the data storage area of ​​the buffer according to the current write buffer index recorded in the dual buffer management structure, initially set to buffer 0. The write position is located by the write position pointer of the buffer. Each time data is written, the write position pointer automatically increments by 1 until the upper limit of the buffer capacity is reached, triggering the switching logic. The upper limit of the capacity is the number of sampling points matching the power frequency cycle.

5. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: S5 further includes the following: S5.1: When the write position pointer of the current write buffer reaches the upper limit of the buffer capacity, it is determined that the buffer is full. At this time, the status flag of the buffer is set to 1 through the double buffer management structure, indicating that the data is ready for the main task to extract. At the same time, the status field of the buffer is updated from 0 to 1, completing the state transition from the write buffer to the read buffer. S5.2: After completing the write-full mark, first switch the current write buffer index from 0 to 1, pointing to another free buffer, making it the new write buffer; at the same time, set the current read buffer index to the original write buffer index, establishing a parallel process of writing data to the new buffer and retrieving data from the original buffer; reset the write position pointer of the new write buffer to 0, and start receiving the sampling data of the next cycle.

6. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: S6 further includes the following: S6.1: After the buffer is switched to read mode, the main task polls and checks the data preparation flag in the double buffer management structure at a fixed period. This flag is used to indicate whether the read buffer has completed writing data and is ready for retrieval: when the data preparation status flag is 1, it indicates that the corresponding buffer has been filled with the number of sampling points matching the power frequency cycle and can be processed later; when the data preparation status flag is 0, the main task continues to wait and does not perform data retrieval operation. S6.2: When the main task detects that the data preparation status flag of a certain buffer is 1, it extracts all sample point data from the data storage area of ​​the buffer in sequence according to the current read buffer index in the double buffer management structure. After the data extraction is completed, the data preparation status flag is immediately set to 0 and the read buffer index is reset to -1, indicating that the buffer has completed data processing and can re-enter the write buffer queue.

7. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: S7 further includes the following: S7.1: After extracting time-domain data from the buffer, the Hanning window function is applied to window the data to suppress spectral leakage. The Hanning window function calculates the window coefficient for each sampling point using a formula, and then multiplies the original data by the corresponding window coefficient to smooth the signal edges and reduce frequency domain energy diffusion caused by non-integer period truncation; the window coefficient w i The calculation formula is as follows: ； Where i is the sampling point index and N is the number of sampling points; Since the Hanning window attenuates the signal amplitude, it is necessary to calculate the sum of the window function coefficients. Obtain compensation factor Then, the windowed data is multiplied by a compensation factor to restore the true amplitude of the signal; S7.2: Perform a Fast Fourier Transform (FFT) on the windowed and compensated time-domain data to convert the signal from the time domain to the frequency domain; the FFT calculation is based on the number of analysis points configured in the initialization phase, and the complex amplitude of each frequency component is efficiently calculated through the butterfly algorithm. After taking the modulus, the real amplitude of the corresponding frequency point is obtained; where the number of analysis points is consistent with the number of sampling points. Then, based on the power frequency characteristics of the power grid signal, with the fundamental frequency being the fundamental frequency of the target signal, the amplitude information of the fundamental frequency and its harmonics is extracted to form the spectrum distribution result.

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