Driving circuit, driving method and display panel

Abstract

The application relates to a driving circuit, a driving method and a display panel, wherein the driving circuit comprises a waveform recovery circuit and a voltage compensation circuit; an input end of the waveform recovery circuit is connected with a detection point in a target row gate line in the display panel, an output end of the waveform recovery circuit is connected with a non-inverting input end of an operational amplifier in the voltage compensation circuit, an inverting input end of the operational amplifier is connected with a gate line to be compensated, and an output end of the operational amplifier is connected with a compensation point in the gate line to be compensated; the waveform recovery circuit is used for recovering a waveform of the compensation point in the gate line to be compensated into a square wave, the voltage compensation circuit is used for compensating a high level of the square wave of the compensation point to a target high level and compensating a low level of the square wave of the compensation point to a target low level. Through the application, the problem of resistance-capacitance load effect existing in a circuit driven by a single-side chip-free gate driving circuit in the prior art is solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit, driving method and display panel. Background Technology

[0002] In existing display panels, the gate lines are driven in two ways: single-sided driving and double-sided driving. Currently, in monitor and television design, larger sizes are one of the most obvious development advantages to meet market demands. However, larger sizes often lead to a greater resistance-capacitance load effect on the in-plane gate lines. This greater resistance-capacitance load effect causes severe distortion of the clock signal waveform at the mid-to-far ends, resulting in uneven pixel charging times between the mid-to-far ends and the gate source ends, leading to a significant brightness difference and affecting display quality. Therefore, in large-size designs, double-sided driving is often used. This driving method effectively reduces the impact of the resistance-capacitance load effect and, combined with increasing the VGH voltage, solves the problem of uneven panel light emission.

[0003] However, dual-sided driving has disadvantages compared to single-sided driving: 1) More complex circuit design: Dual-sided driving requires chipless gate driver circuits (GDL) on both sides, increasing circuit complexity and the difficulty of wiring and manufacturing processes. 2) Higher cost: In applications using gate chips, dual-sided driving uses twice as many chips as single-sided driving. 3) Higher space occupation: Due to the chipless gate driver circuits on both sides, dual-sided driving results in more complex wiring and circuitry, and wider bezels, affecting the screen's visual effect and backlight utilization. These are also the advantages of single-sided driving compared to dual-sided driving; therefore, a single-sided chipless gate driver circuit is needed that can overcome the resistive-capacitive load effect problem of large-size display panels under single-sided driving. Summary of the Invention

[0004] This application provides a driving circuit, driving method, and display panel to solve the problem of resistive-capacitive load effect in the existing gate driving circuit without a chip on one side for large-size display panels.

[0005] In a first aspect, this application provides a driving circuit for driving a display panel, the driving circuit comprising: a waveform recovery circuit and a voltage compensation circuit; the input terminal of the waveform recovery circuit is connected to a detection point in a target row gate line in the display panel, the output terminal of the waveform recovery circuit is connected to the non-inverting input terminal of an operational amplifier in the voltage compensation circuit, the inverting input terminal of the operational amplifier is connected to the gate line to be compensated, and the output terminal of the operational amplifier is connected to a compensation point in the gate line to be compensated; the waveform recovery circuit is used to restore the waveform of the compensation point of the gate line to be compensated to a square wave, and the voltage compensation circuit is used to compensate the high level of the square wave of the compensation point to a target high level, and to compensate the low level of the square wave of the compensation point to a target low level.

[0006] Optionally, the waveform recovery circuit includes two transient voltage suppression diodes, which are oriented in opposite directions and are both connected in parallel with the capacitor in the target row gate line of the display panel.

[0007] Optionally, the voltage compensation circuit further includes a first capacitor, a first resistor, and a second resistor; one end of the first capacitor is connected to the compensated gate line, and the other end of the first capacitor is connected to one end of the first resistor; the other end of the first resistor is connected to the inverting input terminal of the operational amplifier and one end of the second resistor, respectively, and the other end of the second resistor is connected to the output terminal of the operational amplifier.

[0008] Optionally, the target row gate line and the gate line to be compensated are in the same group of gate lines; the same group of gate lines refers to gate lines with the same clock signal.

[0009] Optionally, the driving circuit further includes: a first MOS transistor and a second MOS transistor; the gate of the first MOS transistor is connected to the gate of the second MOS transistor; the source of the first MOS transistor is connected to the target row gate line of the display panel, and the drain of the first MOS transistor is connected to the output terminal; the source of the second MOS transistor is connected to the target row gate line of the display panel, and the drain of the second MOS transistor is connected to the non-inverting input terminal of the amplifier.

[0010] Optionally, the first MOSFET is a P-channel junction field-effect transistor, and the second MOSFET is an N-channel junction field-effect transistor.

[0011] Secondly, this application provides a driving method based on the driving circuit of the first aspect, comprising: the waveform recovery circuit restoring the waveform of the compensation point of the gate line to be compensated to a square wave; the voltage compensation circuit compensating the high level of the square wave at the compensation point to a target high level, and compensating the low level of the square wave at the compensation point to a target low level.

[0012] Optionally, the waveform recovery circuit includes a first transient voltage suppression diode and a second transient voltage suppression diode. The waveform recovery circuit restores the waveform at the compensation point of the gate line to be compensated to a square wave, including: the waveform recovery circuit limits the high level of the square wave to the clamping voltage of the first transient voltage suppression diode through the first transient voltage suppression diode; the waveform recovery circuit limits the low level of the square wave to the clamping voltage of the second transient voltage suppression diode through the second transient voltage suppression diode.

[0013] Optionally, the method further includes: controlling the first MOSFET to turn off and the second MOSFET to turn on to start the driving circuit; controlling the first MOSFET to turn on and the second MOSFET to turn off to disable the driving circuit.

[0014] Thirdly, this application provides a display panel, characterized in that it includes the driving circuit described in the first aspect.

[0015] Compared with the prior art, the technical solution provided in this application has the following advantages: In this application embodiment, the waveform is first restored by the waveform recovery circuit 110. After the waveform is restored to a square wave, the high and low levels of the currently restored waveform are compensated by the voltage compensation circuit 120, so that the high and low levels of the current waveform are compensated to the high and low levels before distortion, thereby restoring the distorted waveform to the state before distortion. Therefore, under the drive of the driving circuit provided in this application, for a display panel driven by a single-sided gate driving circuit without a chip, the waveform on the GATE line can still be a square wave and the high and low levels of the waveform still do not attenuate. Therefore, by driving the display panel with the driving circuit in this application embodiment, the problem of resistive-capacitive load effect of the single-sided gate driving circuit without a chip in the prior art for large-size display panels can be solved. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 A schematic diagram of a gate drive circuit without a chip on one side in a display panel in the prior art.

[0020] Figure 2 This is a schematic diagram of the gate drive circuit driving a dual-sided chipless display panel in the prior art;

[0021] Figure 3 This is a schematic diagram of the undistorted simulation waveform;

[0022] Figure 4 This is a schematic diagram of the circuit on the gate line in the display panel;

[0023] Figure 5 This is a schematic diagram of the simulated waveform distortion after driving one side of the display panel.

[0024] Figure 6 This is a schematic diagram showing the connection between the driving circuit and the display panel in an embodiment of this application;

[0025] Figure 7 This is a schematic diagram of the waveform recovery circuit of the driving circuit in the embodiments of this application;

[0026] Figure 8 This is a schematic diagram of the simulated waveform after being restored using a waveform restoration circuit.

[0027] Figure 9 This is a schematic diagram of the voltage compensation circuit of the driving circuit in the embodiments of this application;

[0028] Figure 10 This is an overall schematic diagram of the driving circuit after adding a TFT switch in the embodiments of this application;

[0029] Figure 11 This is a flowchart of the driving method based on the driving circuit in the embodiments of this application;

[0030] Figure 12 This is a schematic diagram of the gate compensation wiring in an embodiment of this application.

[0031] Explanation of the attached figures: 200 - Display panel, 100 - Driving circuit, 110 - Waveform recovery circuit, 120 - Voltage compensation circuit, 210 - Target row gate line, 211 - Detection point, 212 - Compensation point, D1 - TVS, D2 - TVS, C1 - First capacitor, R1 - First resistor, R2 - Second resistor, J1 - First MOSFET, J2 - Second MOSFET. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] Furthermore, in the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. Additionally, terms indicating orientation or positional relationships, such as "upper," "lower," "left," "right," "vertical," and "horizontal," are described based on the orientation or relative positional relationships shown in the accompanying drawings and are only for the purpose of simplifying the description of this application, not indicating that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0034] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0035] First, the single-sided drive gate signal and the double-sided drive gate signal will be explained with reference to the accompanying drawings, such as... Figure 1 As shown, the single-sided drive gate signal is transmitted laterally from the short side of the gate line to the other side, as follows: Figure 2As shown, the gate signal for dual-sided driving is simultaneously sent out from both gate lines and transmitted towards the center. Therefore, the disadvantages of dual-sided driving compared to single-sided driving include: 1) More complex circuit design: Dual-sided driving requires chipless gate driver circuits (GDL) on both sides, increasing circuit complexity and the difficulty of wiring and manufacturing processes. 2) Higher cost: In applications using gate chips, dual-sided driving requires twice the number of chips as single-sided driving. 3) Greater space occupation: Due to the chipless gate driver circuits on both sides, dual-sided driving results in more complex wiring and circuitry, and a wider bezel, affecting the screen's visual effect and backlight utilization. Therefore, a single-sided chipless gate driver circuit is needed that can overcome the resistive-capacitive load effect problem of large-size display panels under single-sided driving.

[0036] In a specific example, for the input gate signal V1, its high level is 30V, its low level is -10V, the high level time is 18.48us, and the period is 40.32us. The simulated waveform is as follows: Figure 3 As shown. It can be seen that, Figure 3 The simulated waveforms in the image are undistorted. If the current display panel is used in a large-size monitor, such as a 34-inch monitor, and the current monitor uses a chipless gate drive circuit in existing technology, and the resistance and capacitance (RC) values ​​on a single gate line are approximately: R = 4.704 ohms, C = 1.457 nF, the specific circuit diagram is as follows... Figure 4 As shown, the corresponding simulation waveform is as follows: Figure 5 As shown, the square wave is significantly distorted, becoming a sawtooth wave, with the high level almost disappearing in width, resulting in severely compressed charging time. This demonstrates that existing single-sided, chip-less gate drive circuits suffer from resistive-capacitive load effects for large-size display panels.

[0037] Based on this, this application provides a driving circuit for driving a display panel, such as... Figure 6 As shown, the driving circuit 100 is connected to the display panel 200, and the driving circuit 100 includes: a waveform recovery circuit 110 and a voltage compensation circuit 120.

[0038] The waveform recovery circuit 110 is connected to the detection point 211 in the target row gate line 210 in the display panel 200. The output of the waveform recovery circuit 110 is connected to the non-inverting input of the operational amplifier 121 in the voltage compensation circuit 120. The inverting input of the operational amplifier 121 is connected to the gate line 220 to be compensated. The output of the operational amplifier 121 is connected to the compensation point 212 in the gate line to be compensated.

[0039] The waveform recovery circuit 110 is used to restore the waveform of the compensation point 212 of the gate line to be compensated to a square wave, and the voltage compensation circuit 120 is used to compensate the high level of the square wave of the compensation point 212 to the target high level, and to compensate the low level of the square wave of the compensation point 212 to the target low level.

[0040] It should be noted that the detection points and compensation points in this application can be set at appropriate positions according to actual needs. For example, the three points of the first row clock signal, which are the near, middle, and far ends of the clock signal respectively for single-sided driving, will have different resistance-capacitance load effects. In this case, based on the actual display effect of the display panel, during the single-sided driving process, if the far end starts to darken, or the middle end starts to darken, or even the near end darkens, then feedback compensation can be started from one of the near, middle, or far ends to improve the display effect. That is, the detection points and compensation points in this application can each be one or more. For example, if there are three detection points and three compensation points, the compensation points and detection points are one-to-one corresponding, meaning that the three compensation points can be compensated by the three detection points respectively. In some cases, one detection point can compensate for multiple compensation points respectively, or one compensation point can require multiple detection points to compensate for it, to adapt to different needs.

[0041] Because existing display panels driven by a single-sided, chipless gate drive circuit produce a sawtooth waveform with almost no high-level amplitude, the waveform corresponding to the gate line is almost entirely composed of sawtooth waves. In this embodiment, the waveform is first restored using a waveform recovery circuit 110. After the waveform is restored to a square wave, a voltage compensation circuit 120 compensates for the high and low levels of the restored waveform, restoring them to their pre-distortion levels. Therefore, under the drive circuit provided in this application, for display panels driven by a single-sided, chipless gate drive circuit, the waveform on the gate line remains square, and the high and low levels are not attenuated. Thus, driving the display panel with the drive circuit in this embodiment solves the problem of resistive-capacitive load effects in existing single-sided GDL drive circuits for large-size display panels.

[0042] In this embodiment, the target row gate line and the gate line to be compensated are in the same group of gate lines; the same group of gate lines refers to gate lines with the same clock signal. Furthermore, it should be noted that the clock signal is typically a cyclic signal. Taking a full HD display panel with a resolution of 1920×1080 as an example, the clock signal (CLK) cycles from 1 to 12. That is, G1 = G13 = G25 = ... = G1069 = CLK1, G2 = G14 = G26 = ... G1070 = CLK2, and so on. Since gate lines with the same clock are grouped together, the target row gate line in this embodiment can be any gate line in the same group, preferably the first row gate line in the same group. Because detecting the first row means that the first row has already started displaying, and there needs to be a certain time difference between detection and compensation, it is impossible to simultaneously compensate the first row while it is being detected. In other words, to achieve compensation within the same frame, the first row must be sacrificed. Therefore, in this embodiment, the first row gate line is primarily used for feedback detection. Since the resistance-capacitance load effect of each row's clock is almost identical, detecting the first row and then compensating for other rows yields the same compensation effect (restoring the square wave and compensating for high and low levels). However, since there are many rows of GATE lines in the display panel, sacrificing the first row will not affect the human eye's perception.

[0043] Furthermore, in the embodiments of this application, such as Figure 7 As shown, the waveform recovery circuit 110 includes two transient voltage suppression diodes (TVS). The two transient voltage suppression diodes (D1 and D2) are in opposite directions and are both connected in parallel with the capacitor in the target row gate line of the display panel.

[0044] In this specific example, the high level of the gate square wave signal before distortion is VGH = 30V, and the low level is VGL = 10V. In the existing single-sided, chipless gate drive circuit, this square wave signal will be lost, meaning the high level will be less than 30V and the low level less than -10V. Simultaneously, the waveform will be delayed, with the DC portion of the voltage distorted. To address this, this application utilizes the clamping function of two parallel transient voltage suppressor diodes in opposite directions to restore the waveform to a square wave. For example, if one transient voltage suppressor diode has a clamping voltage of 20V and the other -5V, then when the clock signal waveform after the resistor-capacitor load effect arrives (originally as shown in the image), the waveform will be restored to a square wave. Figure 3 As shown, the effect of resistive-capacitive load is as follows: Figure 5As shown in the diagram, when the input voltage exceeds the breakdown voltage of the transient voltage suppressor diode (VTSD), the VTSD diode will quickly conduct, limiting the voltage to the clamping voltage. Excess voltage will then be grounded through the VTSD diode. In other words, the ratio of the positive and negative clamping voltages can be controlled by selecting the appropriate VTSD diode, such as VGH = 30V:VGL = 10V = 3:1, thereby restoring the square wave waveform as shown in the diagram. Figure 8 At this point, the waveform recovers, but the voltage value does not return to its previous value. Maintaining the high and low levels in this ratio is also beneficial for the subsequent recovery of the voltage value.

[0045] Furthermore, in addition to the voltage compensation circuit 121 for voltage amplification, the voltage compensation circuit 120 in this embodiment also includes a first capacitor C1, a first resistor R1, and a second resistor R2.

[0046] Specifically, such as Figure 9 As shown, one end of the first capacitor C1 is connected to the compensated gate line, and the other end of the first capacitor C1 is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the inverting input terminal of the operational amplifier 121 and one end of the second resistor R2, and the other end of the second resistor R2 is connected to the output terminal of the operational amplifier 121.

[0047] It should be noted that the compensated gate line here and the gate line to be compensated mentioned above are the same gate line. They are simply two different states. Before the driving circuit in this embodiment starts driving, all gate lines in the existing display panel can be referred to as gate lines to be compensated. Since this application uses one row of gate lines in a group as a detection line to compensate other gate lines in the same group, neither the gate line to be compensated nor the compensated gate line is the gate line used for detection, such as the first row of gate lines. After the driving circuit in this application starts performing waveform recovery and voltage compensation on the previous gate line to be compensated, the gate line to be compensated can also be referred to as the compensated gate line.

[0048] After the waveform restoration circuit restores the waveform to a square wave, the voltage value does not return to its previous value. Therefore, a voltage compensation circuit is needed to compensate for the voltage. Specifically, compensation is achieved through an amplifier in the voltage compensation circuit. Let the operational amplifier's amplification factor be Au, combined with... Figure 9 As shown in the circuit, V1 is sent to the positive input terminal of the op-amp, the negative input terminal potential is V3, and ΔV2 is the change in gate feedback. Since the current is the same on the same circuit, the calculation formula can be obtained from resistors R1 and R2:

[0049]

[0050] Transforming the above formula, we get Vout = (R1+R2) / R1V3-R2 / R1ΔV2;

[0051] At this point, the operational amplifier is operating in the linear region, so according to the virtual short, the voltages at the positive and negative input terminals are the same, i.e., V1 = V3; therefore, the above formula can be transformed into V out = (R1+R2) / R1V1-R2 / R1ΔV2, then when the gate feedback voltage V2 is in the constant current region, i.e., at the high and low level positions, V2 has no AC component, therefore, ΔV2=0. Based on this, the formula can be simplified to V out = (1+R2 / R1)V1, which is equivalent to a voltage input amplifier of V1. The amplifier's amplification factor Au = (1+R2 / R1), after which V is obtained. out = (1+R2 / R1)V1.

[0052] As can be seen, the required amplification factor can be controlled by the resistance values ​​of R2 and R1. Specifically, if the amplification factor is set very high, such as 100 times, the amplified voltage will not exceed the amplifier's bias voltage, i.e., forward bias VGH = 30V and negative bias VGL = -10V. Therefore, the voltage can only be restored to the voltage value before distortion. The larger the amplification factor, the faster the voltage amplification rate can be changed. That is, within the operating efficiency range of the operational amplifier (OP), the larger the Au, the faster the rise and fall edges of the restored clock signal voltage, and the better the effect.

[0053] Furthermore, in this application, such as Figure 10 As shown, the driving circuit 100 may further include a first MOS transistor J1 and a second MOS transistor J2; the gate of the first MOS transistor J1 is connected to the gate of the second MOS transistor J2; the source of the first MOS transistor J1 is connected to the target row gate line of the display panel, and the drain of the first MOS transistor J1 is connected to the output terminal; the source of the second MOS transistor J2 is connected to the target row gate line of the display panel, and the drain of the second MOS transistor J2 is connected to the non-inverting input terminal of the amplifier.

[0054] Furthermore, the first MOSFET is a P-channel junction field-effect transistor, and the second MOSFET is an N-channel junction field-effect transistor.

[0055] The first and second MOSFETs enable flexible switching between bilateral and single-sided driving. Furthermore, in this application, the gate is connected to the general-purpose input / output (TCON GPIO) port of the timing controller, allowing this function to be coded and controlled by the timing controller, making the switching control more flexible. Specifically, the switching process is as follows: when GPIO is high, J2 is on and J1 is off, enabling single-sided driving and the driving circuit in this application. This allows for the recovery of waveform distortion caused by the resistive-capacitive load effect and resulting in uneven charging during single-sided driving. When GPIO is low, J1 is on and J2 is off, disabling the driving circuit in this application. Compensation is not enabled during bilateral driving, or the compensation function can be selectively disabled under certain special single-sided driving conditions. Therefore, this application utilizes in-plane integrated thin-film transistors (TFTs) to set up a simple switch and leads the gate to the TCONIO port. The function of the driving circuit can be flexibly adjusted by the timing controller coding, making the compensation debugging process more digital.

[0056] As can be seen, based on the above-described driving circuit, the driving method in the embodiments of this application is as follows: Figure 11 As shown, it includes:

[0057] Step 1102: The waveform recovery circuit restores the waveform of the compensation point of the gate line to be compensated to a square wave;

[0058] The waveform recovery circuit limits the high level of the square wave to the clamping voltage of the first transient voltage suppression diode through the first transient voltage suppression diode; the waveform recovery circuit limits the low level of the square wave to the clamping voltage of the second transient voltage suppression diode through the second transient voltage suppression diode.

[0059] As can be seen, in this application, the gate square wave waveform can be recovered by using two reverse transient voltage suppression diodes.

[0060] Step 1104: The voltage compensation circuit compensates the high level of the square wave at the compensation point to the target high level, and compensates the low level of the square wave at the compensation point to the target low level.

[0061] As can be seen, the voltage parameters of the transient voltage suppression diode are first used to fix the high and low levels of the restored square wave at ideal values. Then, the voltage values ​​are restored by the OP amplifier circuit, and feedback is introduced to continuously follow the square wave after it is restored, thus stabilizing the waveform.

[0062] For steps 1102 to 1104 above, in a specific example, assuming the panel is FHD 1920×1080 and CLK cycles from 1 to 12, then G1 = G13 = G25 = ... = G1069 = CLK1, G2 = G14 = G26 = ... G1070 = CLK2, and so on; assuming the GATE lines with the same CLK are in the same group. Furthermore, the resistance-capacitance load effect at different points in the first row of CLK1 to 12 can be detected, and flexible compensation of varying degrees can be applied to the remaining rows.

[0063] Specifically, such as Figure 12 As shown, points A, B, and C are three points on the first row of gate lines of CLK1. The lines connected to points A, B, and C are the inputs of the compensation circuit. The resistive-capacitive load effect at points A, B, and C is different. By adjusting the circuit parameters according to the input at different positions, different degrees of compensation for the clock signal can be achieved. The lines connected to A' and B' are the gate outputs after compensation. They are connected to the same group of clock gate lines except for the first row, thereby realizing the effect of detecting and compensating the clock signal on the other gate lines based on the resistive-capacitive load effect of the first row of clock signals, and canceling the waveform distortion caused by the resistive-capacitive load effect.

[0064] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0065] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A driving circuit for driving a display panel, characterized in that, The driving circuit includes: a waveform recovery circuit and a voltage compensation circuit; The input terminal of the waveform recovery circuit is connected to the detection point in the target row gate line in the display panel, the output terminal of the waveform recovery circuit is connected to the non-inverting input terminal of the operational amplifier in the voltage compensation circuit, the inverting input terminal of the operational amplifier is connected to the gate line to be compensated, and the output terminal of the operational amplifier is connected to the compensation point in the gate line to be compensated. The waveform recovery circuit is used to restore the waveform of the compensation point of the gate line to be compensated to a square wave, and the voltage compensation circuit is used to compensate the high level of the square wave at the compensation point to the target high level, and to compensate the low level of the square wave at the compensation point to the target low level. The waveform recovery circuit includes two transient voltage suppression diodes, which are in opposite directions and are both connected in parallel with the capacitor in the target row gate line of the display panel; The voltage compensation circuit further includes a first capacitor, a first resistor, and a second resistor; one end of the first capacitor is connected to the compensated gate line, and the other end of the first capacitor is connected to one end of the first resistor; the other end of the first resistor is connected to the inverting input terminal of the operational amplifier and one end of the second resistor, respectively, and the other end of the second resistor is connected to the output terminal of the operational amplifier. The driving circuit further includes: a first MOS transistor and a second MOS transistor; the gate of the first MOS transistor is connected to the gate of the second MOS transistor; the source of the first MOS transistor is connected to the target row gate line of the display panel, and the drain of the first MOS transistor is connected to the output terminal; the source of the second MOS transistor is connected to the target row gate line of the display panel, and the drain of the second MOS transistor is connected to the non-inverting input terminal of the amplifier.

2. The driving circuit according to claim 1, characterized in that, The target row gate line and the gate line to be compensated are in the same group of gate lines; the same group of gate lines refers to gate lines with the same clock signal.

3. The driving circuit according to claim 1, characterized in that, The first MOSFET is a P-channel junction field-effect transistor, and the second MOSFET is an N-channel junction field-effect transistor.

4. A driving method based on the driving circuit of any one of claims 1 to 3, characterized in that, include: The waveform recovery circuit restores the waveform of the compensation point of the gate line to be compensated into a square wave. The voltage compensation circuit compensates the high level of the square wave at the compensation point to the target high level, and compensates the low level of the square wave at the compensation point to the target low level.

5. The driving method according to claim 4, characterized in that, The waveform recovery circuit includes a first transient voltage suppression diode and a second transient voltage suppression diode. The waveform recovery circuit restores the waveform at the compensation point of the gate line to be compensated to a square wave, including: The waveform recovery circuit limits the high level of the square wave to the clamping voltage of the first transient voltage suppression diode through the first transient voltage suppression diode; The waveform recovery circuit limits the low level of the square wave to the clamping voltage of the second transient voltage suppression diode through the second transient voltage suppression diode.

6. The driving method according to claim 5, characterized in that, The method further includes: The first MOSFET is turned off and the second MOSFET is turned on to start the drive circuit; Controlling the first MOSFET to turn on and the second MOSFET to turn off disables the drive circuit.

7. A display panel, characterized in that, The driving circuit includes any one of claims 1 to 3.

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