Hall device biasing circuit and bias current control method

Abstract

The embodiment of the application discloses a kind of Hall device bias circuit and bias current control method, Hall device bias circuit includes: channel selection module, operational amplifier module, first transistor, first switch, bias current control module, current mirror module and second switch;Hall device bias circuit is used when channel selection module selects a power signal end, control first switch and second switch conduction, to generate the bias current related to the equivalent impedance of Hall device;And for when channel selection module selects another power signal end, control first switch and second switch are turned off, to bias work according to bias current to Hall device.The technical scheme of the embodiment of the application solves the problem that traditional Hall device bias circuit cannot dynamically adjust bias current according to equivalent impedance change, and improves the sensitivity of Hall device.

Description

Technical Field

[0001] This invention relates to the field of Hall sensor technology, and in particular to a Hall device bias circuit and a bias current control method. Background Technology

[0002] With the rapid development of automotive electrification, various control systems are shifting from traditional mechanical control to electrical control, leading to a gradual increase in the application scenarios of motors. For motor applications, Hall effect sensors are an essential component. They can sense the position and speed of the motor rotor through the Hall effect, ensuring smoother and more reliable motor operation. Hall effect sensors mainly consist of Hall effect devices, Hall effect device biasing circuits, and amplification circuits.

[0003] Hall effect devices are passive devices that require a bias circuit to generate a voltage signal related to the magnetic field. This voltage signal detection allows the determination of the magnetic field strength and direction, thus providing the position and speed of the motor rotor. Traditional Hall effect device bias circuits have two implementation methods: voltage bias and current bias. Current bias is more effective at eliminating the Hall effect device's own offset voltage, so it is the more commonly chosen method.

[0004] However, the equivalent resistance of a Hall device varies with process technology and temperature. Especially at different temperatures, the resistance can differ by a factor of several. Design typically considers the case where the Hall device's equivalent resistance is at its maximum and selects an appropriate bias current, but this can lead to a decrease in the Hall device's sensitivity. Summary of the Invention

[0005] This invention provides a Hall effect device bias circuit and a bias current control method to solve the problem that traditional Hall effect device bias circuits cannot dynamically adjust the bias current according to changes in equivalent impedance.

[0006] According to one aspect of the present invention, a Hall device bias circuit is provided, comprising: a channel selection module, an operational amplifier module, a first transistor, a first switch, a bias current control module, a current mirror module, and a second switch;

[0007] The input terminal of the channel selection module is connected to at least two power signal terminals. The output terminal of the channel selection module is connected to the first input terminal of the operational amplifier module. The second input terminal of the operational amplifier module is connected to the second terminal and the fourth terminal of the Hall effect device. The output terminal of the operational amplifier module is connected to the gate of the first transistor and the first terminal of the first switch. The second terminal of the first switch is connected to the first terminal of the bias current control module. The second terminal of the bias current control module is connected to the ground terminal. The first electrode of the first transistor and the third terminal of the bias current control module are connected to the first power signal terminal. The second electrode of the first transistor is connected to the first terminal of the Hall effect device. The third terminal of the Hall effect device is connected to the first terminal of the current mirror module. The fourth terminal of the bias current control module is connected to the second terminal of the current mirror module. The first terminal of the second switch is connected to the third terminal of the Hall effect device. The second terminal of the second switch is connected to the third terminal of the current mirror module, and the third terminal of the current mirror module is connected to the ground terminal.

[0008] The channel selection module is used to select either input terminal or output terminal; the operational amplifier module is used to control the voltage of the second terminal and the fourth terminal of the Hall device to the voltage of the power signal terminal selected by the channel selection module; the bias current control module is used to control the bias current of the Hall device according to the on or off state of the first switch and the second switch; the Hall device bias circuit is used to control the first switch and the second switch to be turned on when the channel selection module selects a power signal terminal, so as to generate a bias current related to the equivalent impedance of the Hall device; and is used to control the first switch and the second switch to be turned off when the channel selection module selects another power signal terminal, so as to bias the Hall device according to the bias current.

[0009] Optionally, the bias current control module includes a first capacitor and a second transistor. The first terminal of the first capacitor is connected to the second terminal of the first switch and the gate of the second transistor. The second terminal of the first capacitor is connected to the ground terminal. The first electrode of the second transistor is connected to the first power signal terminal. The second electrode of the second transistor is connected to the second terminal of the current mirror module.

[0010] Optionally, the current mirror module includes a third transistor and a fourth transistor. The first terminals of the third transistor and the fourth transistor are connected to a ground terminal. The second terminal of the third transistor is connected to the fourth terminal of the bias current control module and the gate of the third transistor. The gate of the third transistor is connected to the gate of the fourth transistor. The second terminal of the fourth transistor is connected to the third terminal of the Hall device and the first terminal of the second switch. The second terminal of the second switch is connected to the first terminal of the fourth transistor.

[0011] Optionally, the third transistor and the fourth transistor include NMOS transistors.

[0012] Optionally, the operational amplifier module includes a first operational amplifier, the first input terminal of the first operational amplifier is connected to the output terminal of the channel selection module, the second input terminal of the first operational amplifier is connected to the second terminal and the fourth terminal of the Hall device, and the output terminal of the first operational amplifier is connected to the gate of the first transistor.

[0013] Optionally, the channel selection module includes at least a first gating switch and a second gating switch. The first end of the first gating switch is connected to a second power signal terminal, the first end of the second gating switch is connected to a third power signal terminal, and the second ends of the first gating switch and the second gating switch are connected to the first input terminal of the operational amplifier module.

[0014] Optionally, the first transistor and the second transistor include PMOS transistors.

[0015] According to another aspect of the present invention, a Hall device bias current control method is also provided, applied to any of the Hall device bias circuits described above, the Hall device bias current control method comprising:

[0016] When the channel selection module selects a power signal terminal, it controls the first switch and the second switch to be turned on to generate a bias current related to the equivalent impedance of the Hall device.

[0017] When the channel selection module selects another power signal terminal, it controls the first switch and the second switch to turn off so as to bias the Hall device according to the bias current.

[0018] Optionally, when the channel selection module selects a power signal terminal, controlling the first switch and the second switch to turn on to generate a bias current related to the equivalent impedance of the Hall device includes:

[0019] When the channel selection module selects a power signal terminal, it controls the first switch and the second switch to be turned on. The bias current control module generates a bias current related to the equivalent impedance of the Hall device and maintains the bias current.

[0020] Optionally, when the channel selection module selects another power signal terminal, controlling the first switch and the second switch to turn off, so as to bias the Hall device according to the bias current, includes:

[0021] When the channel selection module selects another power signal terminal, it controls the first switch and the second switch to turn off, and the bias current control module uses the maintained bias current to flow through the Hall device.

[0022] The technical solution of this invention, by setting a channel selection module, a first switch, a second switch, an operational amplifier module, and a bias current control module, ensures that the voltages at the second and fourth terminals of the Hall device signal are stable at the selected power supply voltage. By controlling the states of the channel selection module, the first switch, and the second switch, the Hall device bias circuit is divided into two stages. In the first stage, the Hall device bias current can be set appropriately based on the Hall device's equivalent resistance. In the second stage, the bias current from the first stage can be used to enable the Hall device to operate normally. This invention solves the problem that traditional Hall device bias circuits cannot dynamically adjust the bias current according to changes in equivalent impedance, thus improving the sensitivity of the Hall device.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the Hall effect device bias circuit in related technologies;

[0026] Figure 2 This is a schematic diagram of a Hall device bias circuit provided in an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of another Hall device bias circuit provided in an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of another Hall device bias circuit provided in an embodiment of the present invention;

[0029] Figure 5 This is a circuit schematic diagram of a Hall device bias circuit provided in an embodiment of the present invention;

[0030] Figure 6 This is a flowchart of a Hall device bias current control method provided in an embodiment of the present invention. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] A Hall effect device is equivalent to a four-resistor bridge model. Since it is a passive device, a bias circuit is needed to generate a voltage signal related to the magnetic field. This voltage signal can then be detected to determine the strength and direction of the magnetic field, thereby obtaining the position and speed of the motor rotor. The structure of the bias circuit for a Hall effect device in related technologies is as follows: Figure 1As shown, the negative terminal of the operational amplifier (OP) is connected to 0.5*VDD as a reference voltage. The two positive terminals of the OP are connected to the B and D terminals of the Hall effect sensor, respectively, to clamp the common-mode voltage of the Hall effect sensor's B and D terminals to 0.5*VDD. The output terminal of the OP is connected to the gate of transistor MP1. The source of transistor MP1 is connected to the power supply VDD, and the drain of transistor MP1 is connected to the A terminal of the Hall effect sensor. The first terminal of the bias current source Ibias is connected to the power supply VDD, and the other terminal of the bias current source Ibias is connected to the drain of transistor MN1. The drain of transistor MN1 is shorted to the gate of transistor MN2, and the drain of transistor MN2 is connected to the C terminal of the Hall effect sensor. The sources of transistors MN1 and MN2 are both connected to ground GND. Here, the power supply and power supply voltage are represented by VDD, and the bias current source and bias current are represented by Ibias.

[0034] Transistors MN1 and MN2 form a current mirror structure. The current flowing through transistor MN2 depends on the magnitude of the bias current Ibias and the size ratio of transistors MN2 and MN1. Here, transistors MN2 and MN1 are of equal size. Therefore, the current flowing through transistor MN2 is the bias current Ibias, which is also the current flowing through the Hall device. Assuming the equivalent resistance of the Hall device is R1 = R2 = R3 = R4 = 5KΩ, the voltage VDD = 5V, and the bias current Ibias = 0.5mA, due to the virtual short characteristic of the op-amp during normal operation, the voltages VB and VD at terminals B and D of the Hall device are both 0.5VDD, or 2.5V. The current flowing through transistor MN2 is generated by transistor MP1 and flows into transistor MN2 through resistors R1, R2, R3, and R4. Therefore, the voltage at terminal A of the Hall effect device is VA = VD + R1 * (0.5 * Ibias) = ​​3.75V, and the voltage at terminal C is VC = VD - R4 * (0.5 * Ibias) = ​​1.25V. At this time, the source-drain voltage of transistor MP1 is VDS1 = VDD - VA = 1.25V, and the source-drain voltage of transistor MN2 is VDS2 = VC = 1.25V. By selecting transistors MP1 and MN2 of appropriate sizes to ensure that their source-drain voltages are greater than the driving voltage, transistors MP1 and MN2 are kept in the saturation region, and the structure can operate reliably and normally.

[0035] In practice, the equivalent resistance of a Hall effect device varies with process technology and temperature. Especially at different temperatures, the resistance can differ by a factor of several. As calculated above, assuming the equivalent resistance of the Hall effect device at high temperature is R1 = R2 = R3 = R4 = 10KΩ, the power supply VDD = 5V, the bias current Ibias = 0.5mA, the voltage at terminal A of the Hall effect device VA = VD + R1 * (0.5 * Ibias) = ​​5V, and the voltage at terminal C VC = VD - R4 * (0.5 * Ibias) = ​​0V. At this time, the source-drain voltage VDS1 of transistor MP1 = VDD - VA = 0V, and the source-drain voltage VDS2 of transistor MN2 = VC = 0V. Both transistors MP1 and MN2 are in the linear region, which means the virtual short characteristic of the op-amp (OP) cannot be guaranteed. Furthermore, the current flowing through transistor MN2 is no longer equal to the bias current Ibias. All the above calculations are invalid, and the entire circuit is in an uncontrollable state. To avoid this problem, designs typically consider the case where the Hall device's equivalent resistance is at its maximum, selecting an appropriate bias current. For example, in this case, the bias current would be chosen to be 0.25mA to meet the requirement that the Hall device's equivalent resistance is 10KΩ at high temperatures. However, this leads to a decrease in the Hall device's sensitivity, which is generally expressed as uV / mT / mA, representing the voltage signal generated under a 1mA bias current and a 1mT magnetic field, measured in uV. When the bias current is halved, the voltage signal generated under a 1mT magnetic field also decreases by half. Simply to meet the bias requirements at high temperatures, the bias current needs to be reduced to half of the current required for room temperature bias, meaning the sensitivity at room temperature is halved. This introduces many limitations in practical applications. The fundamental drawback is that the bias current is generated by a bias current source and cannot change synchronously with the Hall device's equivalent resistance. When the resistance increases, the current cannot decrease, and when the resistance decreases, the current cannot increase, making dynamic adjustment impossible.

[0036] In view of this, Figure 2 This is a schematic diagram of a Hall effect device bias circuit provided in an embodiment of the present invention. This embodiment is applicable to scenarios requiring high-sensitivity Hall effect sensors, such as current detection, position sensing, and rotational speed measurement. Figure 1 As shown, the Hall device bias circuit includes: a channel selection module 101, an operational amplifier module 102, a first transistor 103, a first switch 104, a bias current control module 105, a current mirror module 106, and a second switch 107.

[0037] The input terminal of the channel selection module 101 is connected to at least two power signal terminals. The output terminal of the channel selection module 101 is connected to the first input terminal of the operational amplifier module 102. The second input terminal of the operational amplifier module 102 is connected to the second terminal and the fourth terminal of the Hall device 201. The output terminal of the operational amplifier module 102 is connected to the gate of the first transistor 103 and the first terminal of the first switch 104. The second terminal of the first switch 104 is connected to the first terminal of the bias current control module 105. The second terminal of the bias current control module 105 is connected to the ground terminal GND. The first transistor 103... The first terminal of transistor 103 and the third terminal of bias current control module 105 are connected to the first power signal terminal VDD. The second terminal of transistor 103 is connected to the first terminal of Hall device 201. The third terminal of Hall device 201 is connected to the first terminal of current mirror module 106. The fourth terminal of bias current control module 105 is connected to the second terminal of current mirror module 106. The first terminal of second switch 107 is connected to the third terminal of Hall device 201. The second terminal of second switch 107 is connected to the third terminal of current mirror module 106. The third terminal of current mirror module 106 is connected to ground terminal GND.

[0038] The channel selection module 101 is used to select either its input or output terminal; the operational amplifier module 102 is used to control the voltage of the second and fourth terminals of the Hall device 201 to the voltage of the power signal terminal selected by the channel selection module 101; the bias current control module 105 is used to control the bias current of the Hall device 201 according to the on or off state of the first switch 104 and the second switch 107; the Hall device bias circuit is used to control the first switch 104 and the second switch 107 to be turned on when the channel selection module selects a power signal terminal, so as to generate a bias current related to the equivalent impedance of the Hall device 201; and to control the first switch 104 and the second switch 107 to be turned off when the channel selection module selects another power signal terminal, so as to bias the Hall device 201 according to the bias current.

[0039] The channel selection module 101 may include multiple switches. The input terminal of the channel selection module 101 is connected to at least two power signal terminals, allowing it to select one power signal from at least two power signals and output the selected power signal to the operational amplifier module 102. The voltages of the two power signal terminals may be different; for example, one power signal terminal voltage may be 0.25 times the voltage of the first power signal terminal, and the other power signal terminal voltage may be 0.5 times the voltage of the first power signal terminal. The operational amplifier module 102 may be an operational amplifier. The operational amplifier module 102 can clamp the voltages of the second and fourth terminals of the Hall device 201 to the voltage of the power signal terminal selected by the channel selection module 101. The gate voltage of the first transistor 103 is controlled by the operational amplifier module 102. The first transistor 103 may be a PMOS transistor. The first terminal of the first transistor 103 may be the source, and the second terminal may be the drain. The first switch 104 can control the connection between the output terminal of the operational amplifier module 102 and the bias current control module 105. The bias current control module 105 can generate a bias current based on the equivalent impedance of the Hall device 201 when the first switch 104 and the second switch 107 are turned on, and maintain the bias current based on the equivalent impedance of the Hall device 201 when the first switch 104 and the second switch 107 are turned off. The current mirror module 106 may include two or more transistors, among which a reference transistor and a mirror transistor may be included. The current mirror module 106 can mirror the current flowing through its second terminal to its first terminal. The mirrored current is the bias current flowing through the Hall device 201. The third terminal of the current mirror module 106 is connected to the second terminal of the second switch 107, and is also connected to the ground terminal GND.

[0040] Specifically, in the first stage, the channel selection module 101 selects a power signal terminal to connect to. This power signal terminal can be a power signal terminal with a relatively low voltage. It controls the first switch 104 and the second switch 107 to be turned on. The operational amplifier module 102 clamps the voltage of the second and fourth terminals of the Hall device 201 to the voltage of the selected power signal terminal. Since the first switch 104 is turned on, the output terminal of the operational amplifier module 102 is also connected to the bias current control module 105. The first transistor 103 is turned on, and current flows into the first terminal of the Hall device 201 through the first transistor 103. The current flows through the internal resistance of the Hall device 201 and flows out from the third terminal. Since the second switch 107 is turned on, the third terminal of the Hall device 201 is connected to the third terminal of the current mirror module 106, that is, connected to the ground terminal GND. At this time, the current generated by the bias current control module 105 is the same as the bias current flowing into the Hall device 201 from the first transistor 103. The current generated by the bias current control module 105 flows into the current mirror module 105 and then into the ground terminal GND. In the second stage, the channel selection module 101 selects another power signal terminal, which can be a power signal terminal with a higher voltage, and controls the first switch 104 and the second switch 107 to turn off. The operational amplifier module 102 clamps the second and fourth terminals of the Hall device 201 to the voltage of the selected power signal terminal. Since the first switch 104 is off, the output terminal of the operational amplifier module 102 is no longer connected to the bias current control module 105, and at this time, the bias current control module 105 is no longer controlled by the voltage of the operational amplifier module 102. The second switch 107 is off, disconnecting the third terminal of the Hall device 201 from the third terminal of the current mirror module 106, that is, no longer connected to the ground terminal GND. At this time, the current mirror module 106 is in normal working condition. The bias current control module 105 uses the bias current generated in the first stage to flow through the second terminal of the current mirror module 106. The current mirror module 106 mirrors the bias current to its first terminal, thereby flowing into the Hall device 201, ensuring that the current flowing into the Hall device 201 is the bias current maintained in the first stage. At this point, sufficient margins are ensured for the source-drain voltage of the first transistor and the source-drain voltage of the mirror transistor in the current mirror module 105 to guarantee that they operate in the saturation region. This ensures that the bias current of the Hall device 201 is maintained at the current held in the first stage, while simultaneously maintaining the voltage at the second and fourth terminals of the Hall device 201 clamped to the selected power supply signal terminal. This stage is the normal operating mode of the Hall device 201, used to sense magnetic fields and output Hall voltage.

[0041] The technical solution of this invention, by setting a channel selection module, a first switch, a second switch, an operational amplifier module, and a bias current control module, ensures that the voltages at the second and fourth terminals of the Hall device signal are stable at the selected power supply voltage. By controlling the states of the channel selection module, the first switch, and the second switch, the Hall device bias circuit is divided into two stages. In the first stage, the Hall device bias current can be set appropriately based on the Hall device's equivalent resistance. In the second stage, the bias current from the first stage can be used to enable the Hall device to operate normally. This invention solves the problem that traditional Hall device bias circuits cannot dynamically adjust the bias current according to changes in equivalent impedance, thus improving the sensitivity of the Hall device.

[0042] Figure 3 This is a schematic diagram of another Hall device bias circuit provided in an embodiment of the present invention. In some optional embodiments of the present invention, such as... Figure 3 As shown, the bias current control module 105 includes a first capacitor C1 and a second transistor 1051. The first end of the first capacitor C1 is connected to the second end of the first switch 104 and the gate of the second transistor 1051. The second end of the first capacitor C1 is connected to the ground terminal. The first terminal of the second transistor 1051 is connected to the first power signal terminal VDD. The second terminal of the second transistor 1051 is connected to the second end of the current mirror module 106.

[0043] In this configuration, the first capacitor C1 can be a storage capacitor. The first terminal of the second transistor 1051 can be the source, and the second terminal can be the drain. When the first switch 104 is turned on, the voltage at the output terminal of the operational amplifier module 102 is transmitted through the turned-on first switch 104 to the first terminal of the first capacitor C1 and the gate of the second transistor 1051. At this time, the first capacitor C1 is charged, and the voltage across it reaches and remains at this voltage value. When the first switch 104 is turned off, the voltage stored in the first capacitor C1 continues to be applied to the gate of the second transistor 1051, and the current flowing through the second transistor 1051 remains unchanged.

[0044] In some alternative embodiments of the present invention, reference continues to be made. Figure 3 The current mirror module 106 includes a third transistor 1061 and a fourth transistor 1062. The first terminal of the third transistor 1061 and the first terminal of the fourth transistor 1062 are connected to the ground terminal GND. The second terminal of the third transistor 1061 is connected to the fourth terminal of the bias current control module 105 and the gate of the third transistor 1061. The gate of the third transistor 1061 is connected to the gate of the fourth transistor 1062. The second terminal of the fourth transistor 1062 is connected to the third terminal of the Hall device 201 and the first terminal of the second switch 107. The second terminal of the second switch 107 is connected to the first terminal of the fourth transistor 1062.

[0045] In this design, the current mirror module 106 can be an NMOS current mirror, and the third transistor 1061 and the fourth transistor 1062 can be NMOS transistors. The first terminal of the third transistor 1061 and the fourth transistor 1062 can be the source, and the second terminal can be the drain. The third transistor 1061 can be the reference transistor of the current mirror module 106. The gate and drain of the third transistor 1061 are shorted to set the reference current. The fourth transistor 1062 can be the mirror transistor of the current mirror module 106. The gate of the fourth transistor 1062 is connected to the gate of the third transistor 1061 to replicate the reference current and provide bias current for the Hall device 201.

[0046] In some alternative embodiments of the invention, the third and fourth transistors include NMOS transistors.

[0047] In this configuration, the sources of both the third and fourth transistors are connected to ground. The bias current of the Hall device needs to flow from its third terminal to ground.

[0048] Figure 4 This is a schematic diagram of another Hall device bias circuit provided in an embodiment of the present invention. In some optional embodiments of the present invention, such as... Figure 4 As shown, the operational amplifier module 102 includes a first operational amplifier 1021. The first input terminal of the first operational amplifier 1021 is connected to the output terminal of the channel selection module 101. The second input terminal of the first operational amplifier is connected to the second terminal and the fourth terminal of the Hall device 201. The output terminal of the first operational amplifier is connected to the gate of the first transistor 103.

[0049] The first operational amplifier 1021 differs from traditional operational amplifiers; its structure is similar to that of a common-mode feedback circuit. Utilizing the virtual short characteristic of the first operational amplifier 1021, the voltages at the second and fourth terminals of the Hall device 201 are clamped to the power signal voltage selected by the channel selection module 101, providing a stable common-mode operating point for the Hall device 201 and ensuring current control.

[0050] In some alternative embodiments of the present invention, reference continues to be made. Figure 4 The channel selection module 101 includes at least a first gating switch 1011 and a second gating switch 1012. The first end of the first gating switch 1011 is connected to the second power signal terminal VDD1, the first end of the second gating switch 1012 is connected to the third power signal terminal VDD2, and the second ends of the first gating switch 1011 and the second gating switch 1012 are connected to the first input terminal of the operational amplifier module 102.

[0051] The second terminals of the first gating switch 1011 and the second terminals of the second gating switch 1012 are connected in parallel and connected to the first input terminal of the operational amplifier module 102. The first gating switch 1011 controls the connection between the second power signal terminal VDD1 and the first input terminal of the operational amplifier module 102. The second gating switch 1012 controls the connection between the third power signal terminal VDD2 and the first input terminal of the operational amplifier module 102. The first gating switch 1011 and the second gating switch 1012 are mutually exclusive. For example, when the second power signal terminal VDD1 needs to be selected, the first gating switch 1011 is closed and the second gating switch 1012 is open. When the third power signal terminal VDD2 needs to be selected, the second gating switch 1012 is turned on and the first gating switch 1011 is turned off.

[0052] In some alternative embodiments of the present invention, the first transistor and the second transistor include PMOS transistors.

[0053] In this configuration, the sources of both the first and second transistors are connected to the first power supply terminal VDD, and current flows from VDD in both cases. The first transistor controls the current flowing from VDD to the first terminal of the Hall device. The second transistor generates a reference circuit that allows current to flow from VDD to the current mirror module. The PMOS transistor turns on when its gate voltage is lower than a threshold voltage below its source voltage. When on, current flows from the source to the drain. The inclusion of a PMOS transistor in both the first and second transistors ensures a current path for the Hall bias circuit.

[0054] Figure 5 This is a circuit schematic diagram of a Hall effect device bias circuit provided in an embodiment of the present invention, such as... Figure 5As shown, the negative terminal of the first operational amplifier 1021 is connected to the second power signal terminal VDD1 and the third power signal terminal VDD2 via the first gating switch 1011 and the second gating switch 1012, respectively. The two positive terminals of the first operational amplifier 1021 are connected to the B and D terminals of the Hall device 201, respectively, which can clamp the common-mode voltage of the B and D terminals of the Hall device to the voltage of the second power signal terminal VDD1 or the third power signal terminal VDD2. The output terminal of the first operational amplifier 1021 is connected to the gate of the first transistor 103, and is connected to the gate of the second transistor 1051 and one end of the first capacitor C1 via the first switch 104. The other end of the capacitor C1 is connected to the ground terminal GND. The source of the first transistor 103 is connected to the first power signal terminal VDD, and the drain is connected to the A terminal of the Hall device 201. The source of the second transistor 1051 is connected to the first power supply signal terminal VDD, and its drain is connected to the drain and gate of the third transistor 1061 and the gate of the fourth transistor 1062. The drain of the fourth transistor 1062 is connected to the C terminal of the Hall device 201 and one end of the second switch 107. The other end of the second switch 107 and the sources of the third transistor 1061 and the fourth transistor are all connected to the ground terminal GND. Here, the first transistor 103 and the second transistor 1051 are of equal size, and the third transistor 1061 and the fourth transistor 1062 are of equal size.

[0055] Assume the voltage of the second power signal terminal VDD1 is 0.25 times the voltage of the first power signal terminal VDD, the voltage of the third power signal terminal VDD2 is 0.5 times the voltage of the first power signal terminal VDD, the voltage of the first power signal terminal VDD is 5V, and at room temperature R1=R2=R3=R4=5KΩ, and at high temperature R1=R2=R3=R4=10KΩ.

[0056] At room temperature, in the first stage, the first selector switch 1011 is turned on, controlling the first switch 104 and the second switch 107 to turn on. Due to the virtual short characteristic of the first operational amplifier 1021 during normal operation, the voltages VB and VD at the B and D terminals of the Hall device are both 0.25VDD, VDD = 5V, and VB = VD = 1.25V. At this time, the C terminal of the Hall device is connected to the ground terminal GND through the second switch 107. The on-resistance of the second switch 107 is very small and can be ignored here. Therefore, the current flowing through the Hall device Ibias1 = VB / R3 + VD / R4 = 0.5mA, that is, the current flowing through the first transistor 103 is also 0.5mA. At this time, since the first switch 104 is turned on, the gate-source voltage VGS of the first transistor 103 and the second transistor 1051 are the same, and the dimensions of the first transistor 103 and the second transistor 1051 are equal, so the current flowing through the second transistor 1051 and the third transistor 1061 is also 0.5mA.

[0057] In the second stage, the second selector switch 1012 is turned on, controlling the first switch 104 and the second switch 107 to turn off. Due to the presence of the first capacitor C1, the gate voltage of the second transistor 1051 remains unchanged as it was when the first switch 104 and the second switch 107 were on, and its current also remains unchanged. Therefore, the current of the third transistor 1061 remains 0.5mA. Since the fourth transistor 1062 has the same size as the third transistor 1061 and the same gate-source power supply VGS, the current that can flow through the fourth transistor 1062 is also 0.5mA. The current Ibias2 flowing through the Hall device 201 and the fourth transistor 1062 are both 0.5mA. The negative terminal of the first operational amplifier 1021 is connected to 0.5VDD via the second selector switch 1012. Based on the virtual short characteristic of the first operational amplifier 1021, the voltages at terminals B and D of the Hall device 201 are: VB = VD = 0.5 * VDD = 2.5V; VA = VD + R1 * (0.5 * Ibias2) = 3.75V; and VC = VD - R4 * (0.5 * Ibias2) = 1.25V. At this time, the source-drain voltage VDS_1 of the first transistor 103 is VDD - VA = 1.25V, and the source-drain voltage VDS_2 of the fourth transistor 1062 is VC = 1.25V. By selecting appropriately sized first transistor 103 and fourth transistor 1062 to ensure their source-drain voltages are greater than the driving voltage, the first transistor 103 and fourth transistor 1062 are kept in the saturation region, allowing the structure to operate reliably and normally.

[0058] At high temperatures, in the first stage, the first selector switch 1011 is turned on, controlling the first switch 104 and the second switch 107 to turn on. Due to the virtual short characteristic of the first operational amplifier 1021 during normal operation, the voltages VB and VD at terminals B and D of the Hall device 201 are both 0.25VDD, VDD = 5V, and VB = VD = 1.25V. At this time, terminal C of the Hall device 201 is connected to GND through the second switch 107. The on-resistance of the second switch 107 is very small and can be ignored here. Therefore, the current flowing through the Hall device 201, Ibias3 = VB / R3 + VD / R4 = 0.25mA, which means the current flowing through the first transistor 103 is also 0.25mA. At this time, since the first switch 104 is turned on, the gate-source voltage VGS of the first transistor 103 and the second transistor 1051 are the same, and the dimensions of the first transistor 103 and the second transistor 1051 are equal, so the current flowing through the second transistor 1051MP2 and the third transistor 1061 is also 0.25mA.

[0059] In the second stage, the second selector switch 1012 is turned on, controlling the first switch 104 and the second switch 107 to turn off. Due to the presence of the first capacitor C1, the gate voltage of the second transistor 1051 remains unchanged as it was when the first switch 104 and the second switch 107 were on, and its current also remains unchanged. Therefore, the current of the third transistor 1061 remains 0.25mA. Since the fourth transistor 1062 has the same size as the third transistor 1061 and the same gate-source power supply VGS, the current that can flow through the fourth transistor 1062 is also 0.25mA. The current Ibias4 flowing through the Hall device 201 is the same as that of the fourth transistor 1062, which is 0.25mA. The negative terminal of the first operational amplifier 1021 is connected to 0.5VDD via the second selector switch 1012. Based on the virtual short characteristic of the first operational amplifier 1021, the voltages at terminals B and D of the Hall device 201 are: VB = VD = 0.5 * VDD = 2.5V; the voltage at terminal A is: VA = VD + R1 * (0.5 * Ibias4) = 3.75V; and the voltage at terminal C is: VC = VD - R4 * (0.5 * Ibias4) = 1.25V. At this time, the source-drain voltage VDS_1 of the first transistor 103 is: VDD - VA = 1.25V; and the source-drain voltage VDS_2 of the fourth transistor 1062 is: VC = 1.25V. By selecting appropriately sized first transistor 103 and fourth transistor 1062 to ensure their source-drain voltages are greater than the driving voltage, the first transistor 103 and fourth transistor 1062 are kept in the saturation region, ensuring the structure can operate reliably and normally.

[0060] As can be seen, regardless of the temperature or the change in the equivalent impedance of the Hall device 201, the source-drain voltage margin of the first transistor 103 and the fourth transistor 1062 can be guaranteed, thus ensuring the normal operation of the Hall device bias circuit. Furthermore, unlike traditional structures, it is not necessary to select a very small bias current to meet the maximum equivalent impedance of the Hall device 201, which would lead to a decrease in the sensitivity of the Hall device 201. The technical solution of this invention is applicable to all environments where the equivalent impedance of the Hall device 201 changes, including but not limited to temperature, process, and packaging stress.

[0061] Figure 6 This is a flowchart of a Hall device bias current control method provided in an embodiment of the present invention, which is applied to the Hall device bias circuit of any of the above embodiments. (Refer to...) Figure 5 and Figure 6 The bias current control method for this Hall device includes:

[0062] S301. When the channel selection module 101 selects a power signal terminal, it controls the first switch 105 and the second switch 107 to be turned on, so as to generate a bias current related to the equivalent impedance of the Hall device 201.

[0063] In this system, channel selection module 101 selects a power signal terminal, which can be a power signal terminal with a relatively low voltage, and controls the first switch 104 and the second switch 107 to be turned on. Operational amplifier module 102 clamps the voltage of the second and fourth terminals of Hall device 201 to the voltage of the selected power signal terminal. Since the first switch 104 is turned on, the output terminal of operational amplifier module 102 is also connected to bias current control module 105. The first transistor 103 is turned on, and current flows into the first terminal of Hall device 201 through the first transistor 103. The current flows through the internal resistance of Hall device 201 and flows out from the third terminal. Since the second switch 107 is turned on, the third terminal of Hall device 201 is connected to the third terminal of current mirror module 106, that is, connected to the ground terminal. At this time, the current generated by bias current control module 105 is the same as the bias current flowing into Hall device 201 by the first transistor 103. The current generated by bias current control module 105 flows into current mirror module 105 and then into ground terminal.

[0064] S302. When the channel selection module 101 selects another power signal terminal, it controls the first switch 104 and the second switch 107 to turn off so as to bias the Hall device 201 according to the bias current.

[0065] In this process, the channel selection module 101 selects another power signal terminal, which can be a power signal terminal with a higher voltage, and controls the first switch 104 and the second switch 107 to turn off. The operational amplifier module 102 clamps the second and fourth terminals of the Hall device 201 to the voltage of the selected power signal terminal. Since the first switch 104 is off, the output terminal of the operational amplifier module 102 is no longer connected to the bias current control module 105, and at this time, the bias current control module 105 is no longer controlled by the voltage of the operational amplifier module 102. The second switch 107 is off, disconnecting the third terminal of the Hall device from the third terminal of the current mirror module 106, that is, no longer connected to the ground terminal. At this time, the current mirror module 106 is in normal working condition. The bias current control module 105 uses the bias current stored in the first stage to flow through the second terminal of the current mirror module 106. The current mirror module 106 mirrors and copies the bias current to its first terminal, thereby flowing into the Hall device 201, ensuring that the current flowing into the Hall device 201 is the bias current maintained in the first stage. At this point, sufficient margins in the source-drain voltages of the first transistor 103 and the fourth transistor 1062 are ensured to operate in the saturation region. This guarantees that the bias current of the Hall device 201 remains the same as that maintained in the first stage, while simultaneously maintaining the voltages at the second and fourth terminals of the Hall device 201 clamped to the selected power supply signal terminals. This stage represents the normal operating mode of the Hall device 201, used to sense magnetic fields and output Hall voltages.

[0066] In some alternative embodiments of the present invention, reference continues to be made. Figure 5When the channel selection module 101 selects a power signal terminal, it controls the first switch 104 and the second switch 107 to turn on, so as to generate a bias current related to the equivalent impedance of the Hall device 201, including:

[0067] When the channel selection module 101 selects a power signal terminal, it controls the first switch 104 and the second switch 107 to be turned on, and the bias current control module 105 generates a bias current related to the equivalent impedance of the Hall device 201 and maintains the bias current.

[0068] In some alternative embodiments of the present invention, reference continues to be made. Figure 5 When the channel selection module 101 selects another power signal terminal, controlling the first switch 104 and the second switch 107 to turn off, so as to bias the Hall device 201 according to the bias current, includes:

[0069] When the channel selection module 101 selects another power signal terminal, it controls the first switch 104 and the second switch 107 to turn off, and the bias current control module 105 uses the maintained bias current to flow through the Hall device 201.

[0070] In some alternative embodiments of the present invention, reference continues to be made. Figure 5 The Hall device 201 includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The first end of the first resistor R1 is connected to the first end of the second resistor R2, and their common end is the first end A of the Hall device 201. The second end of the second resistor R2 is connected to the first end of the third resistor R3, and their common end is the second end B of the Hall device 201. The second end of the third resistor R3 is connected to the first end of the fourth resistor R4, and their common end is the third end C of the Hall device 201. The second end of the fourth resistor R4 is connected to the second end of the first resistor R1, and their common end is the fourth end D of the Hall device 201.

[0071] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0072] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A Hall effect device biasing circuit, characterized in that, include: Channel selection module, operational amplifier module, first transistor, first switch, bias current control module, current mirror module, and second switch; The input terminal of the channel selection module is connected to at least two power signal terminals. The output terminal of the channel selection module is connected to the first input terminal of the operational amplifier module. The second input terminal of the operational amplifier module is connected to the second terminal and the fourth terminal of the Hall effect device. The output terminal of the operational amplifier module is connected to the gate of the first transistor and the first terminal of the first switch. The second terminal of the first switch is connected to the first terminal of the bias current control module. The second terminal of the bias current control module is connected to the ground terminal. The first electrode of the first transistor and the third terminal of the bias current control module are connected to the first power signal terminal. The second electrode of the first transistor is connected to the first terminal of the Hall effect device. The third terminal of the Hall effect device is connected to the first terminal of the current mirror module. The fourth terminal of the bias current control module is connected to the second terminal of the current mirror module. The first terminal of the second switch is connected to the third terminal of the Hall effect device. The second terminal of the second switch is connected to the third terminal of the current mirror module, and the third terminal of the current mirror module is connected to the ground terminal. The channel selection module is used to select any input terminal and output terminal; the operational amplifier module is used to control the voltage of the second terminal and the fourth terminal of the Hall device to the voltage of the power signal terminal selected by the channel selection module; the bias current control module is used to control the bias current of the Hall device according to the on or off state of the first switch and the second switch; the Hall device bias circuit is used to control the first switch and the second switch to be turned on when the channel selection module selects a power signal terminal, so as to generate a bias current related to the equivalent impedance of the Hall device. And when the channel selection module selects another power signal terminal, it controls the first switch and the second switch to turn off, so as to bias the Hall device according to the bias current.

2. The Hall device biasing circuit according to claim 1, characterized in that, The bias current control module includes a first capacitor and a second transistor. The first terminal of the first capacitor is connected to the second terminal of the first switch and the gate of the second transistor. The second terminal of the first capacitor is connected to the ground terminal. The first electrode of the second transistor is connected to the first power signal terminal. The second electrode of the second transistor is connected to the second terminal of the current mirror module.

3. The Hall device biasing circuit according to claim 1, characterized in that, The current mirror module includes a third transistor and a fourth transistor. The first terminals of the third transistor and the fourth transistor are connected to a ground terminal. The second terminal of the third transistor is connected to the fourth terminal of the bias current control module and the gate of the third transistor. The gate of the third transistor is connected to the gate of the fourth transistor. The second terminal of the fourth transistor is connected to the third terminal of the Hall device and the first terminal of the second switch. The second terminal of the second switch is connected to the first terminal of the fourth transistor.

4. The Hall device biasing circuit according to claim 3, characterized in that, The third transistor and the fourth transistor include NMOS transistors.

5. The Hall device biasing circuit according to claim 1, characterized in that, The operational amplifier module includes a first operational amplifier, the first input terminal of the first operational amplifier is connected to the output terminal of the channel selection module, the second input terminal of the first operational amplifier is connected to the second terminal and the fourth terminal of the Hall device, and the output terminal of the first operational amplifier is connected to the gate of the first transistor.

6. The Hall device biasing circuit according to claim 1, characterized in that, The channel selection module includes at least a first gating switch and a second gating switch. The first end of the first gating switch is connected to a second power signal terminal, the first end of the second gating switch is connected to a third power signal terminal, and the second ends of the first gating switch and the second gating switch are connected to the first input terminal of the operational amplifier module.

7. The Hall device biasing circuit according to claim 2, characterized in that, The first transistor and the second transistor include PMOS transistors.

8. A method for controlling the bias current of a Hall effect device, characterized in that, The Hall device bias current control method, applied to the Hall device bias circuit according to any one of claims 1-7, comprises: When the channel selection module selects a power signal terminal, it controls the first switch and the second switch to be turned on to generate a bias current related to the equivalent impedance of the Hall device. When the channel selection module selects another power signal terminal, it controls the first switch and the second switch to turn off so as to bias the Hall device according to the bias current.

9. The Hall device bias current control method according to claim 8, characterized in that, When the channel selection module selects a power signal terminal, controlling the first switch and the second switch to turn on to generate a bias current related to the equivalent impedance of the Hall device includes: When the channel selection module selects a power signal terminal, it controls the first switch and the second switch to be turned on. The bias current control module generates a bias current related to the equivalent impedance of the Hall device and maintains the bias current.

10. The Hall device bias current control method according to claim 8, characterized in that, When the channel selection module selects another power signal terminal, controlling the first switch and the second switch to turn off, so as to bias the Hall device according to the bias current, includes: When the channel selection module selects another power signal terminal, it controls the first switch and the second switch to turn off, and the bias current control module uses the maintained bias current to flow through the Hall device.

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