Random number generation circuit, system thereof, memory device, and memory system

Abstract

Embodiments of the present application provide a random number generation circuit and system, a memory device and a memory system. The random number generation circuit comprises: a counter comprising m flip-flops; a clock terminal of a first flip-flop of the m flip-flops is coupled to a clock signal; an output terminal of a flip-flop of the m flip-flops is coupled to an input terminal of a first logic gate and a clock terminal of a next flip-flop through the first logic gate; a linear feedback shift register comprising (n-m) flip-flops; clock terminals of the (n-m) flip-flops are coupled to the clock signal; an input terminal of a first flip-flop of the (n-m) flip-flops and an output terminal of an (n-m) flip-flop are coupled to a first input terminal of each second logic gate; an output terminal of a flip-flop of the (n-m) flip-flops is coupled to an input terminal of a next flip-flop through a second input terminal of a second logic gate; m and n are both positive integers, and m is less than n.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a random number generation circuit and system thereof, a memory device and a memory system. Background Technology

[0002] A Line Feedback Shift Register (LFSR) is a special type of shift register where the current input depends on the previous output. LFSRs are widely used in random number generation, Cyclic Redundancy Checksum (CRC) calculation, encryption, decryption, and signal modulation. However, the performance of LFSRs in generating random numbers needs improvement. Summary of the Invention

[0003] In view of this, embodiments of this application provide a random number generation circuit and system thereof, a memory device, and a memory system.

[0004] In a first aspect, embodiments of this application disclose a random number generation circuit, comprising: a counter comprising m flip-flops; the clock terminal of the first flip-flop of the m flip-flops is coupled to a clock signal; the output terminal of one flip-flop of the m flip-flops is coupled to its input terminal through a first logic gate, and coupled to the clock terminal of the next flip-flop; a linear feedback shift register comprising (nm) flip-flops; the clock terminal of the (nm) flip-flops is coupled to a clock signal; the input terminal of the first flip-flop of the (nm) flip-flops and the output terminal of the (nm) flip-flops are coupled to the first input terminal of each second logic gate; the output terminal of one flip-flop of the (nm) flip-flops is coupled to the input terminal of the next flip-flop through the second input terminal of a second logic gate; m and n are both positive integers, and m is less than n; wherein, the output of the random number generation circuit comprises n bits from the least significant bit to the most significant bit; the least significant bit is based on the current clock cycle state of the m flip-flops of the counter; the most significant bit is based on the current clock cycle state of the (nm) flip-flops of the linear feedback shift register.

[0005] In some embodiments, the outputs of the first to the mth flip-flops of the counter output bits 0 to (m-1) of the least significant bit, respectively; the output of one of the m flip-flops is connected to the input of an inverter, and the output of the inverter is connected to the input of one flip-flop and to the clock of the next flip-flop.

[0006] In some embodiments, the outputs of the first to the (nm)th flip-flops of the linear feedback shift register output bits 0 to (nm-1) of the most significant bit, respectively; the input of the first flip-flop of the (nm)th flip-flops and the output of the (nm)th flip-flop are connected to the first input of each XOR gate; the output of one flip-flop of the (nm)th flip-flops is connected to the second input of an XOR gate, and the output of the XOR gate is connected to the input of the next flip-flop.

[0007] In some embodiments, the data generated by the m flip-flops of the counter and the data generated by the (nm) flip-flops of the linear feedback shift register have a greatest common divisor of 1.

[0008] In some embodiments, the random number generation circuit is configured to generate a target value after k clock cycles; where k is a positive integer less than or equal to 3; and the target value is less than a preset threshold.

[0009] In some embodiments, the data generated by the m flip-flops of the counter is repeatedly processed by 2... m There are several states.

[0010] In some embodiments, the data range generated by the m flip-flops of the counter is 0 to 2. m -1.

[0011] In some embodiments, the data generated by the (nm) flip-flops of the linear feedback shift register is repeatedly processed by 2 (n -m) -1 state.

[0012] In some embodiments, the (nm) flip-flops of the linear feedback shift register generate data ranging from 0 to 2. (n-m) -2.

[0013] In some embodiments, the trigger includes a D trigger.

[0014] Secondly, embodiments of this application provide a random number generation system, which includes: any of the random number generation circuits of the first aspect, configured to generate a target value based on a clock cycle state; a comparator, configured to determine whether the target value is less than a preset threshold; based on the target value being less than the preset threshold, using the target value as the output of the random number generation system; and based on the target value being greater than or equal to the preset threshold, enabling a pulse generation circuit, configured to generate an enable pulse; the enable pulse is used as the input of the random number generation system and configured to enable the random number generation circuit to generate the target value.

[0015] Thirdly, embodiments of this application provide a memory device including a memory cell array and peripheral circuitry coupled to the memory cell array; wherein the peripheral circuitry includes a random number generation system as described in the second aspect; the random number generation system is configured to generate addresses to detect and / or mitigate row hammering effects on the memory device.

[0016] In some embodiments, the memory device includes dynamic random access memory.

[0017] Fourthly, embodiments of this application provide a memory system comprising: a memory device including a memory cell array and peripheral circuitry coupled to the memory cell array; a memory controller coupled to the memory device, including a random number generation system according to the second aspect; the random number generation system being configured to generate addresses; and the memory device being configured to receive addresses to detect and / or mitigate row hammering effects on the memory device.

[0018] In various embodiments of this application, the random number generation circuit includes a counter and a linear feedback shift register. The counter and the linear feedback shift register are connected to a clock signal. The output of the counter constitutes the m least significant bits out of n bits, and the output of the linear feedback shift register constitutes the (nm) most significant bits out of n bits. The output of the counter and the output of the linear feedback shift register are combined to obtain n bits of output data. The random number generation circuit is configured to generate random numbers (or target values) that meet the requirements, which can reduce the number of triggers and obtain the required random numbers in a shorter time. The logic overhead of the counter is less than that of the linear feedback shift register, which can reduce the logic overhead of the random number generation circuit. Attached Figure Description

[0019] Figure 1 A schematic diagram of the first random number generation system provided in the embodiments of this application;

[0020] Figure 2 for Figure 1 The timing diagram corresponding to the circuit that generates random numbers;

[0021] Figure 3 for Figure 1 A schematic diagram of an exemplary random number generated by a circuit;

[0022] Figure 4 A schematic diagram of a first random number generation circuit provided in an embodiment of this application;

[0023] Figure 5 for Figure 4 A schematic diagram of a counter in a circuit;

[0024] Figure 6 for Figure 4A schematic diagram of a linear feedback shift register in a circuit;

[0025] Figure 7 for Figure 4 A schematic diagram of an exemplary random number generated by a circuit;

[0026] Figure 8 A schematic diagram illustrating all the data generated by the traversal counter (3 least significant bits) and the linear feedback shift register (3 most significant bits) provided in this embodiment of the application.

[0027] Figure 9 A schematic diagram of a second random number generation circuit provided in an embodiment of this application;

[0028] Figure 10 This is a schematic diagram illustrating all the data generated by traversing the 3 least significant bits of the linear feedback shift register and the 3 most significant bits of the counter, as provided in an embodiment of this application.

[0029] Figure 11 A schematic diagram of a third random number generation circuit provided in an embodiment of this application;

[0030] Figure 12 This is a schematic diagram of a second random number generation system provided in an embodiment of this application;

[0031] Figure 13 A schematic diagram of a memory cell in a DRAM memory cell array provided in an embodiment of this application;

[0032] Figure 14 A schematic diagram of the control circuit for a DRAM memory cell array provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0035] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0040] The behavior of an LFSR can be described by a characteristic polynomial, which is a binary polynomial whose degree equals the number of bits in the LFSR. Each term in the characteristic polynomial corresponds to a feedback point; a coefficient of 1 indicates the presence of feedback, while a coefficient of 0 indicates no feedback. The characteristic polynomial not only determines the period of the LFSR but can also be used to calculate the next vector sequence. LFSRs are used to generate random numbers; for example, an n-bit LFSR has 2^n... n -1 states, whose numerical sequence is determined by the characteristic polynomial used.

[0041] A row hammer is a security vulnerability discovered in memory (e.g., Dynamic Random Access Memory, DRAM). This vulnerability exploits unexpected electrical interactions caused by high-density memory cells, allowing frequent access to one row of memory to affect the contents of adjacent rows, or even change the data in adjacent rows—a form of unaddressed data tampering.

[0042] In memory products (such as DRAM), the row hammer phenomenon becomes increasingly pronounced as process dimensions shrink. For data security reasons, some algorithms are applied to repair row hammers (RHR). In this case, LFSR can be used in the algorithm for repairing row hammers.

[0043] The output of an LFSR is pseudo-random because the resulting sequence of values ​​is both deterministic and repeatable. Before the LFSR repeats, given a sufficiently large LFSR (i.e., an LFSR formed with a sufficient number of storage bits) and a sufficiently long sequence of values, the LFSR appears to be generating random numbers. For clarity, "pseudo-random" and "random" are used interchangeably in this document to refer to the output of the random number generation circuit.

[0044] Figure 1 This is a schematic diagram of a first random number generation system provided in an embodiment of this application. Figure 1 As shown, the random number generation system includes n bits (i.e., ... <n-1:0>) LFSR, a comparator, an OR gate, a flip-flop, and a delayer. The output end of the n-bit LFSR is connected to a first input end of the comparator, a second input end of the comparator is coupled to a reference signal (signal B), the output end of the comparator is connected to an input end of the flip-flop, the output end of the flip-flop is connected to an input end of the delayer and an input end of the n-bit LFSR, the output end of the delayer is connected to a second input end of the OR gate, a first input end of the OR gate is coupled to a clock signal (signal CLK), an output end of the OR gate is connected to a clock end of the flip-flop, and the output end of the n-bit LFSR outputs a signal A. A value of the signal A is a target random number, and the value of the signal A is required to be less than a value of the signal B, so that values meeting the requirement are selected from an original value sequence of the n-bit LFSR, and those values not meeting the requirement are filtered out; by continuously generating a plurality of pulses, a signal Y received by the input end of the n-bit LFSR performs continuous triggering for a plurality of times, so as to switch the value of the signal A until the value of the signal A is less than the value of the signal B.

[0045] However, a memory, such as a DRAM, is a high-speed product. If an n-bit LFSR is adopted, to obtain the signal A meeting the requirement, the number of continuous triggering times performed by the signal Y received by the input end of the n-bit LFSR is limited by time, for example, more triggering times or more time is required to obtain a random number meeting the requirement.

[0046] Figure 2 is Figure 1 is a timing diagram corresponding to random number generation by the circuit. As shown in Figure 1 and Figure 2 , the signal CLK is a start signal, and it is expected that a random number (a value of the signal A) corresponding to a value of the signal B can be obtained in each clock cycle. It can be seen that when the value of the signal A is greater than or equal to the value of the signal B (A1, A n-1 ≥ B, or C1, C2, C m-1 ≥ B), the signal Y will be triggered until the value of the signal A is less than the value of the signal B (A n < B, or C m < B), value A n or C m is an expected random number. In this case, the entire process takes a time length T2, while a period of the signal CLK is a time length T1, and the time length T1 is less than the time length T2 (T1 < T2). If the time length T2 is greater than the time length T1 (T2 > T1), this means that a problem will occur in a current operation and affect an operation of a next clock cycle.

[0047] Figure 3 is Figure 1 is a schematic diagram of an exemplary random number generated by the circuit. As shown in Figure 3 As shown, taking a 7-bit LFSR as an example, assuming the value of signal B is 70, the 7-bit LFSR needs to be triggered a maximum of six times consecutively to obtain a random number (the value "63" or "31"). After triggering the 7-bit LFSR a maximum of six times consecutively, generating the values ​​"126", "125", "123", "119", "111", and "95", we obtain the value "63", which is less than the value "70". After triggering it five times consecutively, generating the values ​​"124", "121", "115", "103", and "79", we obtain the value "31", which is less than the value "70".

[0048] In view of this, embodiments of this application provide a random number generation circuit and system thereof, a memory device, and a memory system. The random number generation circuit is configured to generate a random number (or target value) that meets the requirements, reducing the number of triggers and obtaining the required random number in a shorter time, achieving rapid output of the target random number with minimal logic overhead.

[0049] Figure 4 This is a schematic diagram of a first random number generation circuit provided in an embodiment of this application. Figure 5 for Figure 4 A schematic diagram of a counter in a circuit. Figure 6 for Figure 4 A schematic diagram of a linear feedback shift register in a circuit. Figure 7 for Figure 4 A schematic diagram of an exemplary random number generated by a circuit.

[0050] Firstly, according to an embodiment of this application, a random number generation circuit is provided, with reference to... Figure 4 , Figure 5 and Figure 6 The random number generation circuit 102 includes: a counter 202 comprising m flip-flops; the clock input of the first flip-flop of the m flip-flops is coupled to a clock signal CLK; the output of one flip-flop of the m flip-flops is coupled to its input through a first logic gate and to the clock input of the next flip-flop; a linear feedback shift register 302 comprising (nm) flip-flops; the clock input of the (nm) flip-flops is coupled to the clock signal CLK; the input of the first flip-flop of the (nm) flip-flops and the output of the (nm) flip-flops are coupled to the first input of each second logic gate; the output of one flip-flop of the (nm) flip-flops is coupled to the input of the next flip-flop through the second input of a second logic gate; m and n are both positive integers, and m is less than n; wherein, the output of the random number generation circuit includes n bits from the least significant bit to the most significant bit; the least significant bit is based on the current clock cycle state of the m flip-flops of the counter; the most significant bit is based on the current clock cycle state of the (nm) flip-flops of the linear feedback shift register. In this embodiment, the random number generation circuit includes a counter and a linear feedback shift register. The counter and the linear feedback shift register are connected to a clock signal. The output of the counter constitutes the m least significant bits out of n bits, and the output of the linear feedback shift register constitutes the (nm) most significant bits out of n bits. The outputs of the counter and the linear feedback shift register are combined to obtain n bits of output data. The random number generation circuit is configured to generate random numbers (or target values) that meet the requirements, which can reduce the number of triggers and obtain the required random numbers in a shorter time. The logic overhead of the counter is less than that of the linear feedback shift register, which can reduce the logic overhead of the random number generation circuit.

[0051] refer to Figure 5 In some embodiments, the outputs of the first to the mth flip-flops of the counter 202 output bits 0 to (m-1) of the least significant bit, respectively; the output of one of the m flip-flops is connected to the input of an inverter, and the output of the inverter is connected to the input of a flip-flop and to the clock of the next flip-flop.

[0052] like Figure 5 As shown, the outputs of the first flip-flop 204_1 to the m-th flip-flop 204_m are respectively connected to the inputs of NOT gates 206_1 to 206_m, and the outputs of NOT gates 206_1 to 206_m are respectively connected to the inputs of the first flip-flop 204_1 to the m-th flip-flop 204_m. The inputs of NOT gates 206_1 to 206_m-1 are respectively connected to the clock terminals of the second flip-flop 204_2 to the m-th flip-flop 204_m. The clock terminal of the first flip-flop 204_1 is coupled to the clock signal CLK. The outputs of the first flip-flop 204_1 to the m-th flip-flop 204_m respectively output signal P. <0> To signal P <m-1>Signal P <0> To signal P <m-1>The values ​​are respectively used as bits 0 to (m-1) of the least significant bit, that is... <m-1:0>.

[0053] In some embodiments, the data generated by the m flip-flops of counter 202 is repeatedly processed by 2... m There are several states.

[0054] In some embodiments, the data range generated by the m flip-flops of counter 202 is 0 to 2. m -1 or 1 to 2 m .

[0055] refer to Figure 6 In some embodiments, the outputs of the first to the (nm)th flip-flops of the linear feedback shift register 302 output bits 0 to (nm-1) of the most significant bit, respectively; the input of the first flip-flop of the (nm)th flip-flop and the output of the (nm)th flip-flop are connected to the first input of each XOR gate; the output of one flip-flop of the (nm)th flip-flop is connected to the second input of an XOR gate, and the output of the XOR gate is connected to the input of the next flip-flop.

[0056] like Figure 6 As shown, the outputs of the first flip-flop 304_1 to the (nm-1)th flip-flop 304_n-m-1 are respectively connected to the second inputs of XOR gates 306_1 to 306_n-m-1, and the outputs of XOR gates 306_1 to 306_n-m-1 are respectively connected to the inputs of the second flip-flop 304_2 to the (nm)th flip-flop 304_n-m; the input of the first flip-flop 304_1 and the output of the (nm)th flip-flop 304_n-m are both connected to the first inputs of XOR gates 306_1 to 306_n-m-1; the clock terminals of the first flip-flop 304_1 to the (nm)th flip-flop 304_n-m are all coupled to the clock signal CLK; the outputs of the first flip-flop 304_1 to the (nm)th flip-flop 304_n-m output signals P respectively. <m>To signal P <n-1>Signal P <m>To signal P <n-1>The values ​​are respectively used as bits 0 to (nm-1) of the most significant bit, that is... <n-m-1:0>.

[0057] In some embodiments, the data generated by the (nm) flip-flops of the linear feedback shift register 302 is repeatedly processed by 2 (n-m) -1 state.

[0058] In some embodiments, the data range generated by the (nm) flip-flops of the linear feedback shift register 302 is 0 to 2. (n-m) -2 or 1 to 2 m -1.

[0059] With the same number of flip-flops, the logic overhead of a counter is less than that of a linear feedback shift register because the logic overhead of an NOT gate is less than that of an XOR gate; compared to Figure 1 The random number generation circuit (n-bit LFSR) shown in this application embodiment can reduce logic overhead and achieve fast output of target random numbers with less logic overhead.

[0060] refer to Figure 7 In some embodiments, the random number generation circuit is configured to generate a target value after k clock cycles; where k is a positive integer less than or equal to 3; and the target value is less than a preset threshold.

[0061] like Figure 7 As shown, taking the output of the random number generation circuit 102, which includes 7 bits, as an example, with a preset threshold of 70, the random number generation circuit 102 needs to be triggered a maximum of three times consecutively (understood as going through three clock cycles) to obtain a random number that meets the requirements (the value "60" or "31"). After the random number generation circuit 102 is triggered a maximum of three times consecutively to generate the values ​​"113", "106", and "91", it obtains the value "60", which is less than the value "70". After being triggered twice consecutively to generate the values ​​"101" and "78", it obtains the value "31", which is less than the value "70".

[0062] Compared to Figure 1 The example random number generated by the random number generation circuit (n-bit LFSR) shown (reference) Figure 3 The random number generation circuit provided in this application embodiment (refer to...) Figure 4 This can reduce the number of triggers and obtain the required random number in a shorter time (see reference). Figure 7 ).

[0063] In some embodiments, the data generated by the m flip-flops of the counter and the data generated by the (nm) flip-flops of the linear feedback shift register have a greatest common divisor of 1.

[0064] Thus, the random number generation circuit is configured to traverse all the data, that is, to traverse the data range from 0 to [2]. (n-m) -1]x2 m -1 or 1 to [2] (n-m) -1]x2 m .

[0065] Figure 8 This is a schematic diagram of all the data generated by the traversal counter and the 3 most significant bits generated by the linear feedback shift register, as provided in the embodiments of this application. Figure 8 The data order shown is from left to right and from top to bottom. For example, the data generated by the counter or linear feedback shift register is in the order of the first row of data from left to right, the third row of data, ..., the fifteenth row of data from left to right, a total of 64 data.

[0066] refer to Figure 8 Taking the output of the random number generation circuit 102, which includes 6 bits, as an example, the counter generates 3 least significant bits of data, and the counter is called the low 3-bit counter (or 3-bit counter); the linear feedback shift register generates 3 most significant bits of data, and the linear feedback shift register is called the high 3-bit linear feedback shift register (or 3-bit linear feedback shift register). The data range generated by the low 3-bit counter is 0 to 7, that is, the data generated by the low 3-bit counter has a cycle of 8 data points; the data range generated by the high 3-bit linear feedback shift register is 0 to 6, that is, the data generated by the high 3-bit linear feedback shift register has a cycle of 7 data points. The random number generation circuit needs to be triggered 56 times to traverse the data range of 0 to 55, that is, to traverse all data in a cycle of 56 data points.

[0067] Figure 9 This is a schematic diagram of a second random number generation circuit provided in an embodiment of this application. Figure 9 The linear feedback shift register 602 in the random number generation circuit 502 shown can be referenced. Figure 6 The linear feedback shift register 302 is shown. Figure 9 The counter 702 in the random number generation circuit 502 shown can be referenced. Figure 5 The counter 202 shown.

[0068] Figure 10 This is a schematic diagram illustrating all the data generated by traversing the 3 least significant bits of the linear feedback shift register and the 3 most significant bits of the counter, as provided in an embodiment of this application. Figure 10 The data shown is in order from left to right and from top to bottom.

[0069] refer to Figure 9 and Figure 10 Taking a 6-bit system as an example, the 3 least significant bits of data generated by the linear feedback shift register are called the lower 3-bit linear feedback shift register (or 3-bit linear feedback shift register); the 3 most significant bits of data generated by the counter are called the higher 3-bit counter (or 3-bit counter). Figure 6 Based on the circuit shown, additional logic overhead is needed to increase the data range generated by the lower 3-bit linear feedback shift register from 0 to 6 to 0 to 7, with the lower 3-bit linear feedback shift register generating data in a cycle of 8 data points. Figure 5 Based on the circuit shown, the high 3-bit counter does not incur additional logic overhead, and the data generated by the high 3-bit counter cycles in groups of 8. For example... Figure 10 As shown, because the greatest common divisor between the data generated by the lower 3-bit linear feedback shift register and the data generated by the higher 3-bit counter is no longer 1, the random number generation circuit cannot traverse all the data.

[0070] If no additional logic overhead is applied to the lower 3 bits of the linear feedback shift register, the data range generated by the lower 3 bits of the linear feedback shift register will still be 0 to 6. This results in a 7-bit cycle for the data generated by the lower 3 bits of the linear feedback shift register and the 3 most significant bits generated by the higher 3 bits of the counter, leading to a discontinuous data range. This can result in missing data. Figure 10 (Not shown).

[0071] Figure 11 This is a schematic diagram of a third random number generation circuit provided in an embodiment of this application. Figure 11 The random number generation circuit shown can be understood as... Figure 9 An embodiment with additional logic overhead based on the random number generation circuit shown.

[0072] like Figure 11 As shown, in Figure 9 Based on the random number generation circuit shown, additional logic overhead is added to the counter, such as by adding a logic comparator and corresponding timing control circuitry. The input of logic comparator 704 is coupled to the output of counter 702, and the output of logic comparator 704 is coupled to the control terminal of counter 702. Logic comparator 704 is configured to output the Reset signal to control the timing of counter 702, so that the data range generated by counter 702 is 0 to 6, that is, the data generated by the counter has a cycle of 7 data points, so that the greatest common divisor between the data generated by the linear feedback shift register and the data generated by the counter is 1.

[0073] In some embodiments, the trigger includes a D trigger (Data Flip-Flop, DFF). In alternative embodiments, the trigger includes an RS trigger, a JK trigger, or a T trigger.

[0074] Figure 12 This is a schematic diagram of a second random number generation system provided in an embodiment of this application.

[0075] Secondly, embodiments of this application provide a random number generation system, referring to... Figure 12 The random number generation system 100 includes: a random number generation circuit 102 of any type in the first aspect, configured to generate a target value 102A based on a clock cycle state; a comparator 104, configured to determine whether the target value 102A is less than a preset threshold 102B; based on the target value 102A being less than the preset threshold 102B, to use the target value 102A as the output of the random number generation system; and based on the target value 102A being greater than or equal to the preset threshold 102B, to enable a pulse generation circuit 106, configured to generate an enable pulse 102Y; the enable pulse 102Y is used as the input of the random number generation circuit 102, and configured to enable the random number generation circuit 102 to generate the target value 102A.

[0076] For details regarding the random number generation circuit 102 in this application embodiment, please refer to the various implementations of the first aspect for understanding, and it will not be repeated here.

[0077] In this embodiment of the application, the value of the target value 102A is a target random number. The value of the target value 102A must be less than the value of the preset threshold 102B. By continuously generating several pulses, the input terminal of the random number generation circuit 102 receives the enable pulse 102Y and is continuously triggered several times, thereby switching the value of the target value 102A until the value of the target value 102A is less than the value of the preset threshold 102B.

[0078] Compared to Figure 1 The random number generation system shown in this application embodiment can reduce the number of triggers, obtain the required random number in a shorter time, and achieve rapid output of the target random number with less logic overhead.

[0079] like Figure 12 As shown, the random number generation circuit system 100 includes a random number generation circuit 102, a comparator 104, and an enable pulse generation circuit 106. The output terminal of the random number generation circuit 102 is connected to the first input terminal of the comparator 104, the second input terminal of the comparator 104 is coupled to a reference signal (preset threshold 102B), the output terminal of the comparator 104 is connected to the input terminal of the enable pulse generation circuit 106, and the output terminal of the enable pulse generation circuit 106 is connected to the input terminal of the random number generation circuit 102.

[0080] In some embodiments, the enable pulse generation circuit 106 includes an OR gate 1062, a flip-flop 1064, and a delay unit 1066. The output of the comparator 104 is connected to the input of the flip-flop 1064, the output of the flip-flop 1064 is connected to the input of the delay unit 1066 and the input of the random number generation circuit 102, the output of the delay unit 1066 is connected to the second input of the OR gate 1062, the first input of the OR gate 1062 is coupled to the clock signal CLK, and the output of the OR gate 1062 is connected to the clock terminal of the flip-flop 1064.

[0081] Thirdly, embodiments of this application provide a memory device including a memory cell array and peripheral circuitry coupled to the memory cell array; wherein the peripheral circuitry includes a random number generation system as described in the second aspect; the random number generation system is configured to generate addresses to detect and / or mitigate row hammering effects on the memory device.

[0082] In some embodiments, the peripheral circuitry includes a row decoder, which may include one or more random number generation systems to generate a random sampled signal. The memory device is configured to sample the row address to be used for detecting and / or mitigating row hammering effects using the random sampled signal.

[0083] In some embodiments, the memory device may be random access memory (RAM). Random access memory may include, for example, dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase-change RAM (PRAM), magnetic RAM (MRAM), or resistive RAM (RRAM). In some embodiments, multiple memory devices may constitute a high-bandwidth memory (HBM) DRAM. For example, four stacked memory devices constitute a high-bandwidth memory DRAM; alternatively, the number of memory devices in a high-bandwidth memory DRAM may be less than or more than four layers.

[0084] In some embodiments, the memory device includes DRAM. The control logic of the DRAM can independently access each memory cell in the DRAM's memory cell array and perform read, write, or refresh operations on the data stored therein.

[0085] Figure 13 This is a schematic diagram of a memory cell in a DRAM memory cell array provided in an embodiment of this application. Figure 13 As shown, the drain of transistor T is electrically connected to the bit line BL, the source of transistor T is electrically connected to one of the electrode plates of capacitor C, the other electrode plate of capacitor C is grounded through the ground terminal GND, and the gate of transistor T is connected to the word line WL. The voltage applied through the word line WL controls the transistor T to be turned on or off. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0086] Figure 14 This is a schematic diagram of the control circuit for a DRAM memory cell array provided in an embodiment of this application. Figure 14 As shown, the drains of multiple transistors T are electrically connected to the row address strobe (RAS), the sources of transistors T are electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C is grounded through ground terminal GND. The gates of the multiple transistors T are connected to the column address strobe (CAS). The voltage applied by the row address strobe (RAS) controls the transistors T to turn on or off, and the column address strobe (CAS) is used to perform read or write operations on transistor T when it is turned on. The address associated with RAS is a row address, and the address associated with CAS is a column address. In DRAM, a data bit is stored in the cell at the intersection of the column address and the row address, and CAS makes the column address valid.

[0087] Fourthly, embodiments of this application provide a memory system comprising: a memory device including a memory cell array and peripheral circuitry coupled to the memory cell array; a memory controller coupled to the memory device, including a random number generation system according to the second aspect; the random number generation system being configured to generate addresses; and the memory device being configured to receive addresses to detect and / or mitigate row hammering effects on the memory device.

[0088] In some embodiments, the random number generation system is configured to generate row addresses; the memory device is configured to receive the row addresses to detect and / or mitigate row hammering effects on the memory device.

[0089] In some embodiments, a memory controller is coupled to a memory device and configured to control the operation of the memory device, such as read or write operations. In some embodiments, the memory controller may include, for example, a central processing unit (CPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), a microcontroller unit (MCU), or an application-specific integrated circuit (ASIC).

[0090] In some embodiments, the memory device includes DRAM (e.g., LPDD DRAM). The control logic of the DRAM can independently access each memory cell in the DRAM's memory cell array and perform read, write, or refresh operations on the data stored therein.

[0091] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0092] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application. < / m> < / m>

Claims

1. A random number generation circuit, characterized in that, include: A counter comprising m flip-flops; the clock input of the first of the m flip-flops is coupled to a clock signal; The output of one of the m flip-flops is coupled to its input through a first logic gate, and is also coupled to the clock terminal of the next flip-flop. A linear feedback shift register includes (nm) flip-flops; the clock terminals of the (nm) flip-flops are coupled to a clock signal; the input terminal of the first flip-flop and the output terminal of the (nm)th flip-flop are coupled to the first input terminal of each second logic gate; the output terminal of one of the (nm) flip-flops is coupled to the input terminal of the next flip-flop through the second input terminal of the second logic gate; m and n are both positive integers, and m is less than n; The output of the random number generation circuit includes n bits from least significant bit to most significant bit; the least significant bit is based on the current clock cycle state of the m flip-flops of the counter; The most significant bit is based on the current clock cycle state of the (nm) flip-flops of the linear feedback shift register.

2. The random number generation circuit according to claim 1, characterized in that, The output terminals of the first to the mth flip-flops of the counter respectively output bits 0 to (m-1) of the least significant bit; The output of one of the m flip-flops is connected to the input of an inverter, and the output of the inverter is connected to the input of one of the flip-flops and to the clock terminal of the next flip-flop.

3. The random number generation circuit according to claim 1, characterized in that, The output terminals of the first to the (nm)th flip-flops of the linear feedback shift register respectively output bits 0 to (nm-1) of the most significant bit; The input terminal of the first of the (nm) flip-flops and the output terminal of the (nm)th flip-flop are connected to the first input terminal of each XOR gate; the output terminal of one of the (nm) flip-flops is connected to the second input terminal of one of the XOR gates, and the output terminal of one of the XOR gates is connected to the input terminal of the next flip-flop.

4. The random number generation circuit according to claim 1, characterized in that, The data generated by the m flip-flops of the counter and the data generated by the (nm) flip-flops of the linear feedback shift register have a greatest common divisor of 1.

5. The random number generation circuit according to claim 1, characterized in that, The random number generation circuit is configured to generate a target value after k clock cycles; wherein k is a positive integer less than or equal to 3; and the target value is less than a preset threshold.

6. The random number generation circuit according to claim 1, characterized in that, The data generated by the m flip-flops of the counter is repeatedly processed by 2... m There are several states.

7. The random number generation circuit according to claim 6, characterized in that, The data range generated by the m flip-flops of the counter is 0 to 2. m -1 or 1 to 2 m .

8. The random number generation circuit according to claim 1, characterized in that, The data generated by the (nm) flip-flops of the linear feedback shift register is repeatedly processed by 2 (n-m) -1 state.

9. The random number generation circuit according to claim 8, characterized in that, The data range generated by the (nm) flip-flops of the linear feedback shift register is 0 to 2. (n-m) -2 or 1 to 2 m -1.

10. The random number generation circuit according to claim 1, characterized in that, The trigger includes a D trigger.

11. A random number generation system, characterized in that, include: The random number generation circuit as described in any one of claims 1 to 10 is configured to generate a target value based on a clock cycle state; A comparator is configured to determine whether the target value is less than a preset threshold. Based on the fact that the target value is less than the preset threshold, the target value is used as the output of the system; as well as Based on the target value being greater than or equal to the preset threshold, the pulse generation circuit is activated and configured to generate an activation pulse. The enable pulse serves as input to the system and is configured to enable the random number generation circuit to generate the target value.

12. A memory device, characterized in that, It includes a memory cell array and peripheral circuitry coupled to the memory cell array; The peripheral circuitry includes the random number generation system as described in claim 11; the random number generation system is configured to generate addresses to detect and / or mitigate row hammering effects on the memory device.

13. The memory device according to claim 12, characterized in that, The memory device includes dynamic random access memory.

14. A memory system, characterized in that, include: A memory device, including a memory cell array and peripheral circuitry coupled to the memory cell array; A memory controller, coupled to the memory device, includes the random number generation system as described in claim 11; The random number generation system is configured to generate addresses; as well as The memory device is configured to receive the address to detect and / or mitigate row hammering effects on the memory device.

Images