PCIe BAR space mapping method, system, device and media for data stream processors

Abstract

The application relates to the technical field of servers, and specifically provides a PCIe BAR space mapping method, system and device of a data stream processor and a medium, which comprises the following steps: reading configuration space information of a PCIe device, determining the total size of memory space required by a data stream processor based on the configuration space information, obtaining the size of a special memory equipped by each computing core, determining the size of a DDR memory area used for task calculation according to the total size of the memory space and the size of the special memory, instantiating a static container for the special memory equipped by each computing core, instantiating a dynamic container for the DDR memory area, and allocating different BAR spaces to the static container and the dynamic container. Through the static container and dynamic container dual-mode address mapping mechanism, the key problem that 32-bit PCIe BAR space cannot support data stream processor over-4-GB memory access is solved.

Description

Technical Field

[0001] This invention belongs to the field of server technology, specifically relating to a PCIe BAR space mapping method, system, device, and medium for a data stream processor. Background Technology

[0002] A dataflow processor is a processor designed with a dataflow architecture. Unlike processors based on the von Neumann architecture, dataflow processors drive the computation process through the flow of data, rather than the conventional flow of instructions.

[0003] In traditional PCIe device designs, the BAR (Base Address Register) space is allocated using a 32-bit addressing mode. This design has certain drawbacks, namely that the 32-bit BAR space only supports a maximum physical address space of 4GB, which cannot meet the needs of dataflow processors for large-scale memory mapping (such as deep learning model parameters). Therefore, how to solve the problem of large-capacity memory access under the 32-bit BAR space without changing the hardware design has become a problem that needs to be studied. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a PCIe BAR space mapping method, system, device and medium for a data stream processor to solve the above-mentioned technical problems.

[0005] In a first aspect, the present invention provides a PCIe BAR space mapping method for a data stream processor, comprising:

[0006] Read the configuration space information of the PCIe device, and determine the total amount of memory space required by the data stream processor based on the configuration space information;

[0007] Obtain the size of the dedicated memory allocated to each computing core;

[0008] The size of the DDR memory region used for task computation is determined based on the total size of the memory space and the size of the dedicated memory.

[0009] Static containers are instantiated for the dedicated memory of each computing core, and dynamic containers are instantiated for the DDR memory region.

[0010] Assign different BAR spaces to static and dynamic containers.

[0011] In an optional implementation, the configuration space information of the PCIe device is read, and the total amount of memory space required by the data stream processor is determined based on the configuration space information, including:

[0012] During the PCIe device enumeration phase, the required memory space size is obtained by accessing the PCIe device's configuration space.

[0013] Sum the memory space required by all PCIe devices to obtain the total memory space size.

[0014] In an optional implementation, it further includes:

[0015] If the total size of the memory space is confirmed to exceed the set threshold, the dual-mode address mapping mechanism is enabled. The dual-mode address mapping mechanism is used to map the dedicated memory and DDR memory regions of the computing core to different BAR spaces respectively.

[0016] In one optional implementation, the size of the dedicated memory allocated to each computing core is obtained, including:

[0017] The hardware parameters of the data stream processor are read through the kernel driver interface;

[0018] The number of various computing cores and the size of dedicated memory for each computing core are analyzed from the hardware parameters.

[0019] In one optional implementation, the core parameters of the static container include:

[0020] The compute core base address is the starting address of the PCIe bus address space allocated to the dedicated memory region of the compute core at instantiation.

[0021] The size of the computational core's own dedicated memory.

[0022] In one alternative implementation, the dynamic container manages a variable number of memory blocks, each representing a contiguous area for storing task data;

[0023] The core parameters of a memory block include:

[0024] The base address of the memory block is used to indicate the starting address of the task data block in the PCIe bus address space;

[0025] Space size, used to indicate the length of the data block for this task.

[0026] In an optional implementation, it further includes:

[0027] During the execution of computational tasks, the dynamic container employs a prefetching strategy, which includes:

[0028] Based on the analysis of the task queue, predict the data blocks that need to be accessed in the next computation stage;

[0029] The dynamic container pre-defines the physical address mappings for these predicted data blocks.

[0030] In a second aspect, the present invention provides a PCIe BAR space mapping system for a data stream processor, comprising:

[0031] The first acquisition module is used to read the configuration space information of the PCIe device and determine the total size of the memory space required by the data stream processor based on the configuration space information.

[0032] The second acquisition module is used to acquire the size of the dedicated memory allocated to each computing core.

[0033] The memory computing module is used to determine the size of the DDR memory region used for task computing based on the total size of the memory space and the size of the dedicated memory.

[0034] The container building module is used to instantiate static containers for the dedicated memory provided by each computing core, and to instantiate dynamic containers for the DDR memory region.

[0035] The space mapping module is used to allocate different BAR spaces for static and dynamic containers.

[0036] Thirdly, a device is provided, comprising:

[0037] Memory used to store the PCIe BAR space mapping program of the data stream processor;

[0038] A processor, used to implement the steps of the PCIe BAR space mapping method for a data stream processor as provided in the first aspect when executing the PCIe BAR space mapping program of the data stream processor.

[0039] Fourthly, a computer-readable medium is provided, on which a PCIe BAR space mapping program for a data stream processor is stored, wherein when the PCIe BAR space mapping program for the data stream processor is executed by a processor, the PCIe BAR space mapping program for the data stream processor implements the steps of the PCIe BAR space mapping method for the data stream processor provided in the first aspect.

[0040] This invention solves the key problem that the 32-bit PCIe BAR space cannot support data stream processors accessing more than 4GB of memory through an innovative dual-mode address mapping mechanism of "static container + dynamic container". The specific effects are as follows:

[0041] 1) Breaking the 32-bit address space limit

[0042] Dynamic containers employ a block key-value pair management mechanism, breaking down a single large memory request into multiple dynamically mappable sub-blocks. By loading / unloading memory block mappings on demand, seamless expansion of the physical address space is achieved, supporting terabyte-level memory access without requiring hardware modifications.

[0043] 2) Optimization of resource utilization

[0044] Static containers: solidify the register / local memory mapping of the computing core (such as instruction cache and configuration registers) to ensure zero-latency access to core basic functions.

[0045] Dynamic containers: DDR data blocks (such as model parameters) are dynamically mapped only when the actual computing task is triggered, avoiding long-term occupation of BAR space.

[0046] 3) Significantly improved performance

[0047] Dynamic containers employ a prefetching strategy: based on the task queue, the data blocks required for the next computation stage are predicted, and mappings are established in advance to reduce mapping switching latency.

[0048] The key-value pair design supports O(1) complexity address translation, eliminating the lookup overhead of traditional paging mechanisms.

[0049] 4) Enhance system stability

[0050] Isolate core functional memory from task data memory: The crash of the computing core will not pollute the dynamic mapping area, and the failure of a task only requires resetting the corresponding dynamic container, reducing the system recovery time to the millisecond level. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic flowchart of a method according to an embodiment of the present invention.

[0053] Figure 2 This is a schematic block diagram of a system according to an embodiment of the present invention.

[0054] Figure 3 This is a schematic diagram of the structure of a device provided in an embodiment of the present invention. Detailed Implementation

[0055] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0057] The PCIe BAR space mapping method for a data stream processor provided in this embodiment of the invention is executed by a computer device, and correspondingly, the PCIe BAR space mapping system for the data stream processor runs in the computer device.

[0058] Figure 1 This is a schematic flowchart illustrating a method according to an embodiment of the present invention. Please refer to it. Figure 1 This invention proposes a PCIe BAR space mapping method for data stream processors. By using a dual-mode address mapping mechanism of "static container + dynamic container", it solves the key problem that the 32-bit PCIe BAR space cannot support data stream processors accessing more than 4GB of memory.

[0059] The main steps include:

[0060] (1) During the PCIe device enumeration phase, the host reads the configuration space information of the PCIe device to obtain the total size of the memory space required by the data stream processor. If the required memory space is greater than 4G, the dual-mode address mapping mechanism is used.

[0061] (2) Obtain detailed parameter information of the data stream processor through the kernel driver interface, and determine the configuration information such as the number of various computing cores of the data stream processor and the size of the memory of each processing core.

[0062] (3) Establish a data stream processor address mapping model. The address mapping model is constructed based on the information obtained in steps 1 and 2. The construction method is as follows: a static container class is used to instantiate a container for the memory space required by the computing core itself, and a dynamic container class is used to instantiate a container for the DDR memory area storing computing task data. Different BAR spaces are allocated for the static container and the dynamic container.

[0063] (4) The static container class contains two basic parameters: the base address of the computing core and the size of the space; the base address of the computing core is the starting address of the PCI address space allocated to the computing core when the static container is instantiated, and the size of the space is the memory space required by the computing core itself obtained in step 2.

[0064] (5) The dynamic container class contains a set of key-value pairs. The number of key-value pairs is determined by the scale of the data processed by the computing task. The key-value pairs also contain two basic parameters: the base address of the memory block and the size of the space. The base address of the memory block is the memory space required by the computing task is divided into blocks when the dynamic container is instantiated. The starting address of each block is used as the base address of the key-value pair, and the length of each block is used as the size of the key-value pair. The number of blocks is the number of key-value pairs instantiated in the dynamic container.

[0065] (6) When performing computation tasks, the dynamic container adopts a prefetching strategy, predicts the data blocks required for the next computation stage based on the task queue, establishes mappings in advance, and reduces mapping switching latency.

[0066] In one embodiment of the present invention, the order of the steps of the method can be changed, and some steps can be omitted, depending on different needs. The method includes:

[0067] S1. Read the configuration space information of the PCIe device, and determine the total size of the memory space required by the data stream processor based on the configuration space information;

[0068] S2. Obtain the size of the dedicated memory allocated to each computing core;

[0069] S3. Determine the size of the DDR memory region used for task computation based on the total size of the memory space and the size of the dedicated memory;

[0070] S4. Instantiate static containers for the dedicated memory provided by each computing core, and instantiate dynamic containers for the DDR memory region;

[0071] S5. Assign different BAR spaces to static and dynamic containers.

[0072] In one embodiment of the present invention, based on step S1, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0073] During the PCIe device enumeration phase at system startup, the host obtains the total memory space required by the target device by accessing its configuration space. If this space requirement exceeds 4GB, a dual-mode address mapping mechanism is enabled, and S2-S5 continue to execute under this mechanism. If the total memory space does not exceed 4GB, S2-S5 are not executed.

[0074] In one embodiment of the present invention, based on step S2, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0075] Through the kernel driver interface, the host further reads and parses the detailed hardware parameters of the data stream processor. These parameters include key configuration information such as the number of various computing cores and the size of dedicated memory (such as SRAM, L2 Cache, etc.) equipped on each computing core.

[0076] The kernel driver communicates with the data stream processor through the standard Device Control Interface (DevCtrl). This interface provides a standardized set of commands covering functions such as parameter reading, configuration updates, and status queries. During parameter acquisition, the driver first sends a parameter request command to the data stream processor, which includes a specific identifier to specify the required parameter type. Upon receiving the request, the data stream processor packages the hardware parameters stored in its internal registers or configuration memory into a parameter data packet according to a predefined data format.

[0077] The hardware parameters of a dataflow processor contain rich structural information, among which the number of computing cores and dedicated memory configuration are core parameters. As the execution unit for dataflow processing, the number of computing cores directly determines the system's parallel processing capability. The topology and interconnection method of each computing core are described by the core architecture field in the parameters, which includes information such as core type identifier, instruction set architecture (ISA) version number, and pipeline stage number. The dedicated memory configuration parameters define in detail the storage resources of each computing core, including key indicators such as the capacity, bit width, and access latency of static random access memory (SRAM) and secondary cache (L2 cache). SRAM, as the core carrier of near-memory computing, directly affects the data locality optimization strategy; the L2 cache configuration parameters relate to the performance balance of the multi-level storage system, and the driver needs to initialize the cache coherence protocol based on these parameters.

[0078] During the parameter parsing phase, the kernel driver adheres to a strict verification and conversion mechanism. First, the received parameter data packets undergo CRC verification to ensure data integrity. Then, the data packets are decapsulated according to the parameter format definition, converting the binary data into structured parameter objects. For critical parameters such as the number of computational cores and the size of dedicated memory, the driver performs boundary checks to verify compliance with hardware design specifications and system resource limitations. The parsed parameter information is stored in the Device Descriptor Table (DDS), available for use by the operating system's resource management modules (such as the task scheduler and memory allocator). Furthermore, the driver must establish a parameter change monitoring mechanism to monitor dynamic changes in hardware parameters in real time, enabling timely adjustments to system configuration strategies during device operation to achieve performance optimization and efficient resource utilization.

[0079] In one embodiment of the present invention, based on step S3, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0080] In heterogeneous computing systems, precise allocation of DDR memory regions is crucial for balancing the resource utilization of PCIe devices and computing cores. Step S3 achieves optimal partitioning of the DDR memory region by integrating the global memory requirements of PCIe devices with the local storage characteristics of computing cores. This process involves multi-level address mapping strategies and dynamic resource allocation algorithms, and must consider both hardware architecture constraints and system performance goals.

[0081] First, the system needs to establish a memory requirement model to quantify the DDR allocation benchmark. The total memory space of a PCIe device includes components such as device register space, DMA buffer, and data processing space. The size of dedicated memory for computing cores reflects near-memory computing capabilities, including SRAM for data temporary storage and L2 Cache for fast access. DDR allocation must satisfy the formula: Total DDR requirement = max(PCIe device peak bandwidth × processing latency, number of parallel tasks per computing core × data volume per task) - ∑(dedicated memory capacity for each computing core). This formula ensures that the DDR capacity can both cover the device's burst data transfer needs and compensate for insufficient local storage capacity.

[0082] Secondly, the DDR region partitioning follows a hierarchical address mapping strategy. The system divides the DDR space into fixed and flexible regions: the fixed region is used to map the base address space of PCIe devices, establishing a 1:1 physical address mapping through the IOMMU (Input / Output Memory Management Unit); the flexible region uses a dynamic page table mechanism to dynamically adjust page allocation based on the computing core load. For example, when the GPU core performs high-throughput computations, the flexible region can allocate more large pages (such as 2MB / 1GB pages) to reduce the TLB (Translation Look a Side Buffer) miss rate.

[0083] In one embodiment of the present invention, based on step S4, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0084] S401. A static container for instantiating dedicated memory for each computing core.

[0085] For each dedicated memory region of the computing core, instantiate a static container. This container manages a fixed-size, relatively stable memory mapping.

[0086] Static containers contain two core parameters:

[0087] Computation core base address: The starting address of the PCIe bus address space allocated to the dedicated memory region of this computation core at instantiation.

[0088] Space size: The size of the dedicated memory of the computing core itself, obtained from step S2.

[0089] S402. Instantiate a dynamic container for a DDR memory region.

[0090] Instantiate a dynamic container for an external DDR memory region used to store computational task input / output data. This container manages task data blocks that are variable in size and may change location frequently.

[0091] Dynamic containers manage a variable number of memory chunks, each representing a contiguous area for storing task data.

[0092] Each memory block is described by two core parameters:

[0093] Base address of memory block: The starting address of the task data block in the PCIe bus address space.

[0094] Space size: The length of the data block for this task.

[0095] Dynamic containers determine the number of memory blocks to allocate and manage based on the scale of data that the current computing task needs to process. Upon instantiation, it divides the total memory space required by the task data into one or more appropriately sized blocks and records the base address and size of each block.

[0096] In one embodiment of the present invention, based on step S5, a possible embodiment will be given below, and its specific implementation will be described in a non-limiting manner.

[0097] In PCIe system architecture, the address space mapping mechanism based on the BAR (Base Address Register) is a core technology for achieving memory resource isolation and efficient access. The process of mapping static and dynamic containers to different BAR spaces is essentially a key step in constructing a hierarchical memory access model through hardware address decoding and software driver collaborative configuration. This process involves the PCIe configuration space protocol, address translation mechanism, and dynamic management strategies for system resources.

[0098] A PCIe device's configuration space contains multiple BAR registers, each corresponding to an independent address space window used to map the memory or I / O resources required by the device. When executing S501 and S502, the system must first follow the standard procedure for BAR initialization in the PCIe specification. BAR register initialization is accomplished through the Configuration Access Mechanism (CAM), which defines two configuration cycles: Type 0 and Type 1, used to access the configuration spaces of functional devices and bridge devices, respectively.

[0099] S501. Map the static container to the first BAR space of the PCIe device.

[0100] First, the driver reads the metadata of the static container to obtain its base address and space size information. Then, it writes a specific probing value to the first BAR register of the PCIe device to identify the address space type (memory or I / O) supported by that BAR and its maximum capacity. Based on the probing result, the system aligns the physical address range of the static container with the address space of the BAR. This alignment process must meet the PCIe specification's address boundary requirements, typically 128-byte alignment, to ensure efficient data transfer. After address mapping is complete, the driver establishes a mapping relationship between the static container and the first BAR space in the system's Device Address Mapping Table, and configures the IOMMU (Input / Output Memory Management Unit) to implement virtual address to physical address translation, ensuring the security and transparency of memory access.

[0101] S502. Map the dynamic container to the second BAR space of the PCIe device.

[0102] Because the size and location of memory blocks managed by dynamic containers are variable and frequently change, the system needs to adopt a flexible address allocation strategy. Before mapping, the driver needs to calculate the total amount of address space required based on the number and size of memory blocks currently managed by the dynamic container. Considering the scalability requirements of dynamic memory, the system usually reserves a certain amount of address space margin. During the BAR initialization phase, in addition to performing probing operations similar to those for static containers, the prefetchable attribute of the BAR needs to be configured to optimize data transfer performance. For the mapping of dynamic memory blocks, the system adopts a segmented mapping strategy, allocating a contiguous address segment in the second BAR space for each memory block, and achieving address binding by updating the base address metadata of the memory block. In addition, the system needs to establish a Dynamic Memory Mapping Table to record the correspondence between each memory block and the BAR space address in real time, so as to quickly update the mapping information when memory blocks are dynamically adjusted.

[0103] The BAR space isolation design of the two containers achieves logical partitioning of memory resources, significantly improving system security and performance. From a security perspective, the isolation of physical address windows avoids illegal access between different types of memory regions, and together with the IOMMU access control mechanism, it can effectively prevent memory overflow attacks. From a performance perspective, the fixed mapping of static containers reduces address translation overhead and supports low-latency access to computing cores; the flexible mapping of dynamic containers adapts to the dynamic changes of task data, and improves the data transmission efficiency of the PCIe bus through prefetch optimization and address contiguous processing.

[0104] In one embodiment, the execution strategy for the dynamic container is also defined:

[0105] During the execution of computational tasks, dynamic containers employ a prefetching strategy.

[0106] This strategy is based on the analysis of the task queue to predict the data blocks that may be accessed in the next computation stage.

[0107] Once the prediction is complete, the dynamic container pre-builds the physical address mapping for these prediction data blocks (e.g., pre-loading the corresponding Scatter-Gather List entries into the device DMA engine).

[0108] This prefetch operation aims to reduce the latency (mapping delay) caused by waiting for data block address mappings to be established, thereby improving data throughput and task execution efficiency.

[0109] In some embodiments, the PCIe BAR space mapping system of the data stream processor may include multiple functional modules composed of computer program segments. The computer programs of each program segment in the PCIe BAR space mapping system of the data stream processor may be stored in the memory of a computer device and executed by at least one processor to perform (see details). Figure 1 (Description) Functionality of PCIe BAR space mapping for data stream processors.

[0110] In this embodiment, the PCIe BAR space mapping system of the data stream processor can be divided into multiple functional modules according to its functions, such as... Figure 2 As shown. The module referred to in this invention is a series of computer program segments that can be executed by at least one processor and perform a fixed function, and is stored in memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0111] The first acquisition module is used to read the configuration space information of the PCIe device and determine the total size of the memory space required by the data stream processor based on the configuration space information.

[0112] The second acquisition module is used to acquire the size of the dedicated memory allocated to each computing core.

[0113] The memory computing module is used to determine the size of the DDR memory region used for task computing based on the total size of the memory space and the size of the dedicated memory.

[0114] The container building module is used to instantiate static containers for the dedicated memory provided by each computing core, and to instantiate dynamic containers for the DDR memory region.

[0115] The space mapping module is used to allocate different BAR spaces for static and dynamic containers.

[0116] Figure 3The PCIe BAR space mapping method for the data stream processor provided in this application embodiment can be applied to a device. Those skilled in the art will understand that the device structure involved in the embodiments of this invention does not constitute a limitation on the device; a device may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. In the embodiments of this invention, the device includes, but is not limited to, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of this application described and / or claimed herein.

[0117] The device 300 may include a processor 310, a memory 320, and a communication unit 330. These components communicate via one or more buses. Those skilled in the art will understand that the server structure shown in the figure does not constitute a limitation of the present invention. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0118] The memory 320 can be used to store execution instructions of the processor 310. The memory 320 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. When the execution instructions in the memory 320 are executed by the processor 310, the device 300 is able to perform some or all of the steps in the above method embodiments.

[0119] The processor 310 serves as the control center of the storage device, connecting various parts of the electronic device via various interfaces and lines. It executes software programs and / or modules stored in the memory 320, and calls data stored in the memory to perform various functions of the electronic device and / or process data. The processor can be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 310 may consist only of a central processing unit (CPU). In this embodiment of the invention, the CPU may have a single processing core or include multiple processing cores.

[0120] The communication unit 330 is used to establish a communication channel, enabling the storage device to communicate with other devices. It can receive user data sent by other devices or send user data to other devices.

[0121] The present invention also provides a computer medium, wherein the computer medium may store a program, which, when executed, may include some or all of the steps provided in the embodiments of the present invention. The medium may be a magnetic disk, an optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0122] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a medium such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other medium capable of storing program code. It includes several instructions to cause a computer device (which may be a personal computer, a server, or a second device, network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0123] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

[0124] In the embodiments provided by this invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or modules may be electrical, mechanical, or other forms.

[0125] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0126] In addition, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0127] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the present invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should also be covered within the protection scope of the present invention.

Claims

1. A PCIe BAR space mapping method for a data stream processor, characterized in that, include: Read the configuration space information of the PCIe device, and determine the total amount of memory space required by the data stream processor based on the configuration space information; Obtain the size of the dedicated memory allocated to each computing core; The size of the DDR memory region used for task computation is determined based on the total size of the memory space and the size of the dedicated memory. Static containers are instantiated for the dedicated memory of each computing core, and dynamic containers are instantiated for the DDR memory region. Allocate different BAR spaces for static and dynamic containers; Also includes: During the execution of computational tasks, the dynamic container employs a prefetching strategy, which includes: Based on the analysis of the task queue, predict the data blocks that need to be accessed in the next computation stage; The dynamic container pre-defines the physical address mappings for these predicted data blocks.

2. The method according to claim 1, characterized in that, Read the configuration space information of the PCIe device, and determine the total amount of memory space required by the data stream processor based on the configuration space information, including: During the PCIe device enumeration phase, the required memory space size is obtained by accessing the PCIe device's configuration space. Sum the memory space required by all PCIe devices to obtain the total memory space size.

3. The method according to claim 2, characterized in that, After determining the total amount of memory space required by the data stream processor based on the configuration space information, the method further includes: If the total size of the memory space is confirmed to exceed the set threshold, the dual-mode address mapping mechanism is enabled. The dual-mode address mapping mechanism is used to map the dedicated memory and DDR memory regions of the computing core to different BAR spaces respectively.

4. The method according to claim 1, characterized in that, Obtain the size of the dedicated memory allocated to each computing core, including: The hardware parameters of the data stream processor are read through the kernel driver interface; The number of various computing cores and the size of dedicated memory for each computing core are analyzed from the hardware parameters.

5. The method according to claim 1, characterized in that, The core parameters of a static container include: The compute core base address is the starting address of the PCIe bus address space allocated to the dedicated memory region of the compute core at instantiation. The size of the computational core's own dedicated memory.

6. The method according to claim 1, characterized in that, The dynamic container manages a variable number of memory blocks, each block representing a contiguous area for storing task data. The core parameters of a memory block include: The memory block base address is used to indicate the starting address of the task data block in the PCIe bus address space; Space size, used to indicate the length of the data block for this task.

7. A PCIe BAR space mapping system for a data stream processor, characterized in that, include: The first acquisition module is used to read the configuration space information of the PCIe device and determine the total size of the memory space required by the data stream processor based on the configuration space information. The second acquisition module is used to acquire the size of the dedicated memory allocated to each computing core. The memory computing module is used to determine the size of the DDR memory region used for task computing based on the total size of the memory space and the size of the dedicated memory. The container building module is used to instantiate static containers for the dedicated memory provided by each computing core, and to instantiate dynamic containers for the DDR memory region. The space mapping module is used to allocate different BAR spaces for static and dynamic containers; Also includes: During the execution of computational tasks, the dynamic container employs a prefetching strategy, which includes: Based on the analysis of the task queue, predict the data blocks that need to be accessed in the next computation stage; The dynamic container pre-defines the physical address mappings for these predicted data blocks.

8. A PCIe BAR space mapping device for a data stream processor, characterized in that, include: Memory used to store the PCIe BAR space mapping program of the data stream processor; A processor, configured to implement the steps of the PCIe BAR space mapping method of the data stream processor as described in any one of claims 1-6 when executing the PCIe BAR space mapping program of the data stream processor.

9. A computer-readable medium storing a computer program, characterized in that, The readable medium stores a PCIe BAR space mapping program for a data stream processor, which, when executed by the processor, implements the steps of the PCIe BAR space mapping method for a data stream processor as described in any one of claims 1-6.

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