Superconducting quantum chip wiring path optimization method and device based on line-of-sight algorithm

Abstract

Embodiments of the present disclosure disclose a superconducting quantum chip wiring path optimization method and device based on a line-of-sight algorithm. A specific embodiment of the method includes: starting from a current path point, extending a straight line segment backward along an original path; determining the shortest distance between the straight line segment and each obstacle polygon, and determining whether the shortest distance is greater than or equal to a preset buffer distance; in response to determining that the shortest distance is greater than or equal to the preset buffer distance, determining that the straight line segment is safe; according to the preset buffer distance, expanding the obstacle polygon corresponding to the shortest distance outward to generate a buffer zone; using a forward jump greedy algorithm, starting from the current path point, simplifying the initial wiring path to generate a simplified wiring path; and according to a parameterized weight tuning function, performing multi-objective optimization processing on the simplified wiring path to generate an optimized wiring path. The embodiment improves the smoothness of the curvature change rate of the wiring path through iterative collinear point elimination, and meets the low impedance connection requirement between superconducting qubits.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of superconducting quantum chip wiring path optimization, specifically to a method and apparatus for superconducting quantum chip wiring path optimization based on a line segment line-of-sight algorithm. Background Technology

[0002] In the field of superconducting quantum chip wiring technology, existing research has not fully addressed the critical impact of path geometry on quantum device performance. Traditional wiring schemes largely follow the path planning approach of classical integrated circuits, focusing solely on physical connectivity and failing to establish dedicated optimization models for the unique electromagnetic susceptibility of superconducting quantum systems. This technological gap leads to unnecessary topological twists in the wiring paths, which cause parasitic inductance effects that significantly reduce the coherence time of qubits. Furthermore, local electromagnetic radiation interference at path inflection points is more likely to disrupt the stability of neighboring quantum states. Particularly in multi-qubit array wiring, unoptimized redundant path structures exacerbate microwave signal crosstalk, resulting in a decrease in quantum gate operation fidelity. Current technologies lack a systematic approach that couples path geometric smoothness, electromagnetic compatibility, and superconducting material properties, making it difficult to simultaneously meet the multidimensional requirements of low-loss transmission, enhanced anti-interference capabilities, and manufacturability under complex wiring constraints. This has become a core bottleneck restricting the performance improvement of large-scale superconducting quantum chips. Summary of the Invention

[0003] The summary portion of this disclosure is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description portion. This summary portion is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0004] Some embodiments of this disclosure propose a method, apparatus, electronic device, and computer-readable medium for optimizing wiring paths in superconducting quantum chips based on a line segment line-of-sight algorithm, in order to solve the technical problems mentioned in the background section above.

[0005] In a first aspect, some embodiments of this disclosure provide a method for optimizing the wiring path of a superconducting quantum chip based on a line segment line-of-sight algorithm. The method includes: converting a list of obstacle polygon vertices corresponding to the wiring diagram of the superconducting quantum chip into geometric objects in a target library; establishing a query mechanism for each converted obstacle polygon using spatial indexing results; constructing a straight line segment extending backward along the original path, starting from the current path point, where the original path is the initial wiring path corresponding to the wiring diagram of the superconducting quantum chip; determining the shortest distance between the aforementioned straight line segment and each obstacle polygon, and determining whether the shortest distance is greater than or equal to a preset buffer distance; determining the safety of the straight line segment in response to determining that the shortest distance is greater than or equal to the preset buffer distance; expanding the obstacle polygon corresponding to the shortest distance outward according to the preset buffer distance to generate a buffer zone; detecting whether there is an intersection between the straight line segment and the buffer zone, and in response to determining that there is no intersection between the straight line segment and the buffer zone, using a forward jump greedy algorithm to simplify the initial wiring path starting from the current path point to generate a simplified wiring path; and performing multi-objective optimization processing on the simplified wiring path according to a parameterized weight tuning function to generate an optimized wiring path.

[0006] Secondly, some embodiments of this disclosure provide a superconducting quantum chip wiring path optimization device based on a line segment line-of-sight algorithm. The device includes: a conversion unit configured to convert a list of obstacle polygon vertices corresponding to the superconducting quantum chip wiring diagram into geometric objects in a target library; an establishment unit configured to establish a query mechanism for each converted obstacle polygon using spatial indexing results; an extension unit configured to construct a straight line segment starting from the current path point and extending backward along the original path, wherein the original path is the initial wiring path corresponding to the superconducting quantum chip wiring diagram; and a first determination unit configured to determine the shortest distance between the aforementioned straight line segment and each obstacle polygon, and to determine whether the shortest distance is large. The system comprises: a first determination unit, a second determination unit, and a generation unit, configured to determine that the shortest distance is greater than or equal to the preset buffer distance and thus determine that the straight line segment is safe; a generation unit, configured to expand the obstacle polygon corresponding to the shortest distance outward according to the preset buffer distance to generate a buffer; a simplification unit, configured to detect whether there is an intersection between the straight line segment and the buffer, and, in response to determining that there is no intersection between the straight line segment and the buffer, to use a forward jump greedy algorithm to simplify the initial wiring path starting from the current path point to generate a simplified wiring path; and an optimization unit, configured to perform multi-objective optimization processing on the simplified wiring path according to a parameterized weight tuning function to generate an optimized wiring path.

[0007] Thirdly, some embodiments of this disclosure provide an electronic device, including: one or more processors; and a storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0008] Fourthly, some embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method described in any of the implementations of the first aspect above.

[0009] The various embodiments of this disclosure have the following beneficial effects: The superconducting quantum chip wiring path optimization method based on the line-segment line-of-sight algorithm of some embodiments of this disclosure reduces the number of path turning points while maintaining wiring spacing constraints through a multi-stage post-processing collaborative mechanism; it eliminates redundant turning points that induce parasitic inductance effects through dynamic angle threshold control, thereby reducing microwave signal transmission loss; and it dynamically eliminates near-collinear (angle close to 180 degrees) midpoints. Local security checks are performed on necessary retained turning points to ensure that the collinearity-optimized path still meets the full-segment obstacle avoidance constraints; and iterative collinearity point elimination improves the smoothness of the curvature change rate of the wiring path, meeting the low-impedance connection requirements between superconducting quantum bits. Attached Figure Description

[0010] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0011] Figure 1 This is a flowchart of some embodiments of the superconducting quantum chip wiring path optimization method based on the line segment line-of-sight algorithm according to the present disclosure; Figure 2 This is a schematic diagram of the initial wiring path in the wiring path optimization method for superconducting quantum chips based on the line segment line-line algorithm according to some embodiments of this disclosure; Figure 3 This is a schematic diagram of optimizing the wiring path in the wiring path optimization method for superconducting quantum chips based on the line segment line-line algorithm according to some embodiments of this disclosure; Figure 4 This is a schematic diagram of the structure of some embodiments of the superconducting quantum chip wiring path optimization device based on the line segment line-line algorithm according to the present disclosure; Figure 5 This is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of the present disclosure. Detailed Implementation

[0012] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0013] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0014] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0015] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0016] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0017] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0018] Figure 1 This is a flowchart 100 of some embodiments of a superconducting quantum chip wiring path optimization method based on the line segment line-line algorithm, which is one of the embodiments of this disclosure. The superconducting quantum chip wiring path optimization method based on the line segment line-line algorithm includes the following steps: Step 101: Convert the list of obstacle polygon vertices corresponding to the wiring diagram of the superconducting quantum chip into geometric objects of the target library.

[0019] In some embodiments, the execution subject (e.g., a computing device) of the superconducting quantum chip wiring path optimization method based on the line segment line-line algorithm can convert the list of obstacle polygon vertices corresponding to the superconducting quantum chip wiring diagram into geometric objects of the target library.

[0020] The parameter configurations for the path, obstacles, and safety distance after wiring of the superconducting quantum chip are shown in Table 1 below: Table 1 Field Name Data types illustrate path List Redundant polyline path, containing multiple intermediate points polygons List List of regions where obstacles are polygon vertices buffer_distance Float Safe distance to prevent interference with wiring signals The initial wiring path of the superconducting quantum chip before wiring path optimization is as follows: Figure 2 As shown, Figure 2 The blue line shown in the example represents the initial wiring path.

[0021] The target library can refer to the Shapely library. The geometric object can refer to a Polygon geometric object.

[0022] For invalid obstacle polygons that are self-intersecting or unclosed, topology repair is performed using polygon.buffer(0), and its mathematical expression is: .

[0023] The steps to convert the list of obstacle polygon vertices into Polygon objects from the Shapely library, while handling invalid polygons, are as follows: 1. First, check if the number of points is greater than or equal to 3 (a polygon needs at least 3 points); 2. Use Shapely's Polygon constructor to create geometry objects; 3. For invalid obstacle polygons (such as self-intersecting polygons), use the buffer(0) technique to fix topology errors; 4. If the repaired obstacle polygon is valid and not empty, add it to the processed list.

[0024] Step 102: Using the spatial index results, establish a query mechanism for each transformed obstacle polygon.

[0025] In some embodiments, the aforementioned execution entity can utilize the spatial index results to establish a query mechanism for each transformed obstacle polygon. For example, a spatial index structure (such as STRtree) can be used to establish a fast query mechanism for polygons. This index reduces the time complexity of collision detection from O(n) of linear search to logarithmic O(log n) by hierarchically organizing the minimum bounding rectangle (MBR) of polygons.

[0026] The relationship between spatial index and obstacle polygons is as follows: 1. Spatial indexes (such as STRtree) organize the minimum bounding rectangles (MBRs) of polygons into a tree structure; 2. When it is necessary to check whether a line segment intersects with a polygon, first check whether the line segment intersects with the polygon's MBR; 3. More complex and precise geometric calculations are only performed when MBRs intersect; 4. This reduces the time complexity of collision detection from O(n) (traversing all polygons) to O(log n).

[0027] Step 103: Starting from the current path point, extend the original path backward to construct a straight line segment.

[0028] In some embodiments, the aforementioned execution entity can construct a straight line segment starting from the current path point and extending backward along the original path. Here, the original path is the initial wiring path corresponding to the wiring diagram of the superconducting quantum chip. For example, dynamic gaze detection starts from the current path point P. i Starting from the beginning, extend the original path backward to construct a straight line segment L(P). i P j ).

[0029] Step 104: Determine the shortest distance between the above straight line segment and each obstacle polygon, and determine whether the shortest distance is greater than or equal to the preset buffer distance.

[0030] In some embodiments, the execution entity can determine the shortest distance between the line segment and each obstacle polygon, and determine whether the shortest distance is greater than or equal to a preset buffer distance. That is, it determines the perpendicular distance between the line segment and each obstacle polygon, and then determines the minimum distance among the perpendicular distances as the shortest distance. The preset buffer distance can be represented by buffer_distance.

[0031] For example, the shortest distance between the above straight line segment and each obstacle polygon can be determined using the following formula: .

[0032] in, This represents the k-th obstacle polygon.

[0033] Step 105: In response to determining that the shortest distance is greater than or equal to the preset buffer distance, the straight segment is determined to be safe.

[0034] In some embodiments, the aforementioned execution entity may determine the safety of a straight line segment in response to determining that the shortest distance is greater than or equal to a preset buffer distance. Starting from the current path node, the line string is extended point by point along the path sequence. The `distance` method of Shapely is used to calculate the shortest distance between the straight line segment and all obstacle polygons in real time; if the distance is greater than the buffer threshold throughout, it is marked as a visible point P. j Otherwise, the test will be terminated.

[0035] Step 106: Based on the preset buffer distance, expand the obstacle polygon corresponding to the shortest distance outward to generate a buffer zone.

[0036] In some embodiments, the aforementioned execution entity can expand the obstacle polygon corresponding to the shortest distance outward according to a preset buffer distance to generate a buffer zone.

[0037] For example, the buffer distance (buffer_distance) can be adaptively validated to check the obstacle polygon P. k Expand the generation buffer P outward k ' =P k ·buffer(buffer_distance).

[0038] Step 107: Detect whether there is an intersection between the line segment and the buffer. In response to determining that there is no intersection between the line segment and the buffer, a forward jump greedy algorithm is used to simplify the initial routing path starting from the current path point to generate a simplified routing path.

[0039] In some embodiments, the execution entity can detect whether there is an intersection between the line segment and the buffer, and in response to determining that there is no intersection between the line segment and the buffer, employ a forward jump greedy algorithm to simplify the initial routing path starting from the current path point to generate a simplified routing path. This is achieved by detecting whether the line segment L intersects with the buffer (L∩(⋃)). N k=1 P k ' The )=∅ mechanism dynamically avoids potential collision risks. This mechanism supports micrometer-level precision adjustment, such as allocating larger buffer distances for microwave signal lines in quantum chips to suppress electromagnetic crosstalk.

[0040] In practice, the path search strategy employs a forward jump greedy algorithm, starting from the current point P. i Start by sequentially checking P. (i+2) Point P (i+3) ..., point P (n-1) The visibility is improved by directly skipping intermediate redundant points (e.g., point P). (i+2) Point P (i+3) Once an invisible point is found, the current round of detection is terminated, and the farthest visible point P is selected. jmax As the next node.

[0041] In practice, the aforementioned implementing entity can simplify the initial wiring path through the following steps: The first step is to start from the original path starting point P0 and set the current point index i=0.

[0042] The second step is to use the current path point P. i Based on the baseline, detection point P is performed according to the reverse priority principle (from far end to near end). (i+2) Point P (i+3) ..., point P (n-1) Visibility.

[0043] The third step is in response to the detection of point P. jIf not visible, stop probing subsequent points and record the farthest visible point P that is currently reachable. jmax The farthest visible point P jmax Add a smooth path and update the current point index i=jmax.

[0044] Iterative loop: Repeat steps two and three until the end of the path is reached.

[0045] The fourth step is to check whether the end point P is included at the end of the smooth path. end To ensure the physical connectivity of the path, a mandatory endpoint inclusion mechanism checks whether the endpoint P is included at the end of the smooth path. end If a missing endpoint is detected, it is appended directly to the end of the path, i.e.: .

[0046] Step 5: If the endpoint P is detected end Missing, appended to the end of the smooth path.

[0047] This mechanism further eliminates the risk of path interruption caused by complex obstacle layouts through reverse collision detection (tracing back from the endpoint).

[0048] Step 108: Perform multi-objective optimization on the simplified routing path according to the parameterized weight tuning function to generate an optimized routing path.

[0049] In some embodiments, the aforementioned execution entity may perform multi-objective optimization processing on the simplified routing path according to the parameterized weight tuning function to generate an optimized routing path.

[0050] In practice, the aforementioned execution entity can perform multi-objective optimization of the simplified wiring path using the following parameterized weight tuning function: , in, Indicates the weight of the control path length. This represents the cost of adjusting for collision risk (the reciprocal of the distance from the point to the obstacle, 1 / d). min (Related), for highly sensitive signal lines (such as Flux lines), set ≫ Prioritize security; for paths with low latency requirements, increase... To shorten the total length, Indicates the current path point P i The corresponding shortest distance.

[0051] As an example, optimizing the wiring path is as follows: Figure 3 The example provided.

[0052] Further reference Figure 4 As an implementation of the methods shown in the above figures, this disclosure provides some embodiments of a superconducting quantum chip wiring path optimization device based on the line segment line-of-sight algorithm. These device embodiments are similar to... Figure 1 Corresponding to the method embodiments shown, this superconducting quantum chip wiring path optimization device based on the line segment line-of-sight algorithm can be specifically applied to various electronic devices.

[0053] like Figure 4 As shown, a superconducting quantum chip wiring path optimization device 400 based on a line segment line-line algorithm in some embodiments includes: a conversion unit 401, a building unit 402, an extension unit 403, a first determining unit 404, a second determining unit 405, a generation unit 406, a simplification unit 407, and an optimization unit 408. The conversion unit 401 is configured to convert the list of obstacle polygon vertices corresponding to the superconducting quantum chip wiring diagram into geometric objects in a target library; the building unit 402 is configured to establish a query mechanism for each converted obstacle polygon using spatial index results; the extension unit 403 is configured to construct straight line segments extending backward along the original path from the current path point, wherein the original path is the initial wiring path corresponding to the superconducting quantum chip wiring diagram; the first determining unit 404 is configured to determine the shortest distance between the aforementioned straight line segments and each obstacle polygon, and to determine whether the shortest distance is greater than or equal to a preset cache distance; the second determining unit 405 is configured to... In response to determining that the shortest distance is greater than or equal to a preset buffer distance, the line segment is determined to be safe. The generation unit 406 is configured to expand the obstacle polygon corresponding to the shortest distance outward according to the preset buffer distance to generate a buffer. The simplification unit 407 is configured to detect whether there is an intersection between the line segment and the buffer, and in response to determining that there is no intersection between the line segment and the buffer, adopt a forward jump greedy algorithm to simplify the initial wiring path starting from the current path point to generate a simplified wiring path. The optimization unit 408 is configured to perform multi-objective optimization processing on the above simplified wiring path according to the parameterized weight tuning function to generate an optimized wiring path.

[0054] It is understandable that the units and references described in the superconducting quantum chip wiring path optimization device 400 based on the line segment line-line algorithm are related. Figure 1 The steps in the described method correspond accordingly. Therefore, the operations, features, and beneficial effects described above for the method also apply to the superconducting quantum chip wiring path optimization device 400 based on the line segment line-of-sight algorithm and the units contained therein, and will not be repeated here.

[0055] The following is for reference. Figure 5 It illustrates a schematic diagram of the structure of an electronic device (such as a computing device) suitable for implementing some embodiments of the present disclosure. Figure 5The electronic device shown is merely an example and should not be construed as limiting the functionality or scope of the embodiments of this disclosure. Figure 5 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The memory may include a non-volatile storage medium and internal memory. The non-volatile storage medium may store an operating system and a computer program. The computer program includes program instructions that, when executed, cause the processor to execute any superconducting quantum chip wiring path optimization method based on the line-segment line-look algorithm. The processor provides computational and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the execution of the computer program in the non-volatile storage medium. When executed by the processor, this computer program causes the processor to execute any superconducting quantum chip wiring path optimization method based on the line-segment line-look algorithm. The network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the computer device to which the present disclosure is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0056] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0057] In one embodiment, the processor is configured to run a computer program stored in a memory to perform the following steps: converting the list of obstacle polygon vertices corresponding to the wiring diagram of the superconducting quantum chip into geometric objects of a target library; establishing a query mechanism for each converted obstacle polygon using spatial indexing results; constructing a straight line segment extending backward along the original path, starting from the current path point, wherein the original path is the initial wiring path corresponding to the wiring diagram of the superconducting quantum chip; determining the shortest distance between the straight line segment and each obstacle polygon, and determining whether the shortest distance is greater than or equal to a preset buffer distance; determining that the straight line segment is safe in response to determining that the shortest distance is greater than or equal to the preset buffer distance; expanding the obstacle polygon corresponding to the shortest distance outward according to the preset buffer distance to generate a buffer zone; detecting whether there is an intersection between the straight line segment and the buffer zone, and in response to determining that there is no intersection between the straight line segment and the buffer zone, using a forward jump greedy algorithm to simplify the initial wiring path starting from the current path point to generate a simplified wiring path; and performing multi-objective optimization processing on the simplified wiring path according to a parameterized weight tuning function to generate an optimized wiring path.

[0058] This disclosure also provides a computer-readable storage medium storing a computer program, which includes program instructions. When the program instructions are executed, the method implemented can be referred to various embodiments of the superconducting quantum chip wiring path optimization method based on the line segment line-line algorithm of this disclosure.

[0059] The aforementioned computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiments, such as a hard disk or memory of the computer device. Alternatively, the aforementioned computer-readable storage medium may be an external storage device of the computer device, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.

[0060] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0061] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. A method for optimizing wiring paths in superconducting quantum chips based on a line-segment line-of-sight algorithm, characterized in that, include: Convert the list of obstacle polygon vertices corresponding to the wiring diagram of the superconducting quantum chip into geometric objects from the target library; A query mechanism is established for each transformed obstacle polygon using the spatial index results; Starting from the current path point, construct a straight line segment by extending backward along the original path, where the original path is the initial wiring path corresponding to the wiring diagram of the superconducting quantum chip; Determine the shortest distance between the straight line segment and each obstacle polygon, and determine whether the shortest distance is greater than or equal to a preset buffer distance; In response to determining that the shortest distance is greater than or equal to the preset buffer distance, the safety of the straight line segment is determined. Based on the preset buffer distance, the obstacle polygon corresponding to the shortest distance is expanded outward to generate a buffer zone; To detect whether there is an intersection between the line segment and the buffer, and in response to determining that there is no intersection between the line segment and the buffer, a forward jump greedy algorithm is used to simplify the initial routing path starting from the current path point to generate a simplified routing path. Based on the parameterized weight tuning function, the simplified routing path is subjected to multi-objective optimization processing to generate an optimized routing path; The algorithm employs a forward-jump greedy approach, starting from the current path point, to simplify the initial routing path and generate a simplified routing path, including: Starting from the original path starting point P0, set the current point index i=0; With current path point P i Based on the baseline, point P is detected according to the reverse priority principle. (i+2) Point P (i+3) ..., point P (n-1) Visibility; In response to the detection of point P j If not visible, stop probing subsequent points and record the farthest visible point P that is currently reachable. jmax The farthest visible point P jmax Add a smooth path and update the current point index i = jmax; The step of performing multi-objective optimization processing on the simplified routing path according to the parameterized weight tuning function to generate an optimized routing path includes: The simplified routing path is optimized using the following parameterized weight tuning function, which performs multi-objective optimization: ， in, Indicates the weight of the control path length. This indicates the cost of adjusting collision risk; for highly sensitive signal lines, settings are... Prioritize security; for paths with low latency requirements, increase... To shorten the total length, Indicates the current path point P i The corresponding shortest distance.

2. The method according to claim 1, characterized in that, The method employs a forward-jump greedy algorithm to simplify the initial routing path starting from the current path point, thereby generating a simplified routing path. This also includes: Check at the end of the smooth path whether it contains the endpoint P. end ; If the endpoint P is detected end Missing, appended to the end of the smooth path.

3. A device for optimizing wiring paths in a superconducting quantum chip based on a line segment line-of-sight algorithm, characterized in that, include: The conversion unit is configured to convert a list of obstacle polygon vertices corresponding to the wiring diagram of a superconducting quantum chip into geometric objects of a target library; The unit is configured to use spatial indexing results to establish a query mechanism for each transformed obstacle polygon. The extension unit is configured to extend a straight line segment backward along the original path, starting from the current path point, where the original path is the initial wiring path corresponding to the wiring diagram of the superconducting quantum chip. The first determining unit is configured to determine the shortest distance between the straight line segment and each obstacle polygon, and to determine whether the shortest distance is greater than or equal to a preset buffer distance; The second determining unit is configured to determine the safety of the straight segment in response to determining that the shortest distance is greater than or equal to a preset buffer distance; The generation unit is configured to expand the obstacle polygon corresponding to the shortest distance outward according to the preset buffer distance to generate a buffer zone; The simplification unit is configured to detect whether there is an intersection between the line segment and the buffer, and in response to determining that there is no intersection between the line segment and the buffer, to use a forward jump greedy algorithm to simplify the initial routing path starting from the current path point to generate a simplified routing path, including: Starting from the original path starting point P0, set the current point index i=0; With current path point P i Based on the baseline, point P is detected according to the reverse priority principle. (i+2) Point P (i+3) ..., point P (n-1) Visibility; In response to the detection of point P j If not visible, stop probing subsequent points and record the farthest visible point P that is currently reachable. jmax The farthest visible point P jmax Add a smooth path and update the current point index i = jmax; An optimization unit is configured to perform multi-objective optimization processing on the simplified routing path according to a parameterized weight tuning function to generate an optimized routing path, including: The simplified routing path is optimized using the following parameterized weight tuning function, which performs multi-objective optimization: ， in, Indicates the weight of the control path length. This indicates the cost of adjusting collision risk; for highly sensitive signal lines, settings are... Prioritize security; for paths with low latency requirements, increase... To shorten the total length, Indicates the current path point P i The corresponding shortest distance.

4. An electronic device, characterized in that, include: One or more processors; A storage device on which one or more programs are stored; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 2.

5. A computer-readable medium, characterized in that, It stores a computer program thereon, wherein the computer program, when executed by a processor, implements the method as described in any one of claims 1 to 2.

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