Method of manufacturing a package substrate

Abstract

A method for manufacturing a package substrate includes pressing two substrates on a carrier, forming a circuit structure on the substrates, combining a support member and a reinforcing member on the circuit structure, and removing the carrier. The method can be used for any ultra-thin substrate, and the performance of existing processing equipment is sufficient to meet the process requirements, thereby achieving the ability to manufacture the minimum board thickness.

Description

Technical Field

[0001] This disclosure relates to a semiconductor packaging process, and more particularly to a method for manufacturing a packaging substrate that can improve reliability. Background Technology

[0002] With the booming development of the electronics industry, electronic products are becoming thinner and smaller in form, and are moving towards high performance, high functionality, and high speed in terms of function. Therefore, in order to meet the requirements of high integration and miniaturization of semiconductor devices, packaging substrates with designs such as thinness, low warpage, and high-density wiring are often used in packaging processes.

[0003] like Figure 1 As shown, the existing packaging substrate 1 includes a dielectric structure 10, a first circuit layer 11 and a second circuit layer 12 disposed on the dielectric structure 10, and the dielectric structure 10 has a core layer 100, a plurality of first insulating layers 101 and a plurality of second insulating layers 102 disposed on opposite sides of the core layer 100, and the core layer 100 has a plurality of conductive vias 120 for electrically connecting the first and second circuit layers 11, 12.

[0004] However, the existing packaging substrate 1 is extremely thin due to miniaturization requirements, so a temporary carrier plate needs to be configured in the process. Therefore, after the temporary carrier plate is removed, the thickness of the packaging substrate 1 often exceeds the process capability of the production equipment, which easily leads to board jamming.

[0005] Furthermore, the packaging substrate 1 is prone to warping during temperature cycling, such as... Figure 1 The dashed outline shown indicates poor package flatness.

[0006] Therefore, overcoming the various problems of the existing technologies has become a pressing issue that the industry urgently needs to address. Summary of the Invention

[0007] The purpose of this invention is to provide a method for manufacturing a packaging substrate to solve at least one of the above-mentioned problems.

[0008] In view of the deficiencies of the prior art, this disclosure provides a method for manufacturing a packaging substrate, comprising: disposing a substrate on opposite sides of a carrier; forming a circuit structure on the substrate; attaching a support member to the circuit structure and attaching a reinforcing member to the support member; removing the carrier member to expose the substrate; forming a wiring layer electrically connected to the circuit structure on the surface of the substrate after the carrier member has been removed; and removing the support member and the reinforcing member.

[0009] In the aforementioned manufacturing method, the substrate includes a core layer and a first metal layer and a second metal layer respectively formed on two opposite surfaces of the core layer. For example, the circuit structure includes a circuit layer made by means of the second metal layer and at least one conductive post disposed in the core layer and electrically connecting the circuit layer and the wiring layer.

[0010] In the aforementioned manufacturing method, the wiring layer is fabricated using the first metal layer. Furthermore, the circuit structure also includes an insulating layer formed on the core layer to cover the wiring layer.

[0011] The aforementioned manufacturing method further includes forming a solder resist layer on the surface of the substrate on which the wiring layer is formed, so that a portion of the wiring layer is exposed on the surface of the solder resist layer.

[0012] In the aforementioned manufacturing method, the hardness (pencil hardness) and modulus (Young's modulus) of the core layer are both greater than those of the solder resist layer.

[0013] In the aforementioned manufacturing method, the support is made of a thermally degradable membrane.

[0014] In the aforementioned manufacturing method, the reinforcing member is formed by coating an ink layer onto the support member and then baking and curing the ink layer. Furthermore, the viscosity of the ink layer before baking and curing is 35–50 Pa·s.

[0015] In the aforementioned manufacturing method, the reinforcing component is mainly composed of epoxy resin material.

[0016] In the aforementioned manufacturing method, the hardness (pencil hardness) of the reinforcing member is greater than or equal to 8H, and the hardness (pencil hardness) of the core layer is greater than or equal to 6H.

[0017] Furthermore, in one specific embodiment, the hardness (pencil hardness) of the reinforcing member is greater than the hardness (pencil hardness) of the core layer.

[0018] In one specific embodiment, the modulus (Young's modulus) of the reinforcing member is greater than 40 GPa, and the modulus (Young's modulus) of the core layer is 10 to 20 GPa.

[0019] As can be seen from the above, the method for manufacturing the packaging substrate disclosed herein mainly utilizes the configuration of the reinforcing member to allow existing processing equipment to continue subsequent processes (such as fabricating the wiring layer) after the carrier member is removed, without structural thickness limitations. Therefore, compared to the prior art, the method disclosed herein can be used for any ultra-thin substrate, and the performance of existing processing equipment is sufficient to meet process requirements without board jamming issues, thus achieving the ability to manufacture the minimum board thickness to improve reliability.

[0020] Furthermore, in order to ensure that the flatness of the thinned substrate structure meets the requirements and to avoid the problem of warping of the packaging substrate, the manufacturing method disclosed herein, by configuring the reinforcing member, ensures that the packaging substrate will not warp during temperature cycling (such as thermal curing of the solder resist layer), thereby ensuring that the flatness of the package meets the requirements and thus improving reliability. Attached Figure Description

[0021] Figure 1 This is a cross-sectional schematic diagram of an existing packaging substrate.

[0022] Figures 2A to 2H This is a cross-sectional schematic diagram of the manufacturing method of the packaging substrate disclosed herein.

[0023] The attached figures are labeled as follows:

[0024] 1,2 package substrate

[0025] 10 Dielectric Structure

[0026] 100, 80 core layers

[0027] 101 First Insulation Layer

[0028] 102 Second Insulation Layer

[0029] 11 First Line Layer

[0030] 12 Second Line Layer

[0031] 120 conductive via

[0032] 20. Circuit Structure

[0033] 201 Line Layer

[0034] 202 Conductive Post

[0035] 203 Electrical contact pad

[0036] 21 Wiring Layer

[0037] 210 Electrical contacts

[0038] 22. Solder resist layer

[0039] 220 opening

[0040] 23 Surface treatment layer

[0041] 24 Insulation layer

[0042] 240 opening

[0043] 6 Reinforcing components

[0044] 7 Support components

[0045] 8. Substrate

[0046] 81 First Metal Layer

[0047] 82 Second metal layer

[0048] 83 Third metal layer

[0049] 9. Bearing components

[0050] Thicknesses D, D0, D1, D2, D3, D4, D5, t1, t2

[0051] H0, H1, H2, H3 structural thicknesses. Detailed Implementation

[0052] The following specific embodiments illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification.

[0053] It should be understood that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," "third," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0054] Figures 2A to 2H This is a cross-sectional schematic diagram of the manufacturing method of the packaging substrate 2 disclosed herein.

[0055] like Figure 2A As shown, a plurality of substrates 8 are provided to be symmetrically bonded to opposite sides of a carrier 9 to form a symmetrical structure.

[0056] In this embodiment, the substrate 8 is a core plate with metal layers on opposite sides, such as a copper foil substrate. Its core layer 80 has a first metal layer 81 and a second metal layer 82, similar to copper, on opposite surfaces. A third metal layer 83, also similar to copper, is formed on the first metal layer 81 and the second metal layer 82, so that the third metal layer 83 on the first metal layer 81 is pressed onto the carrier 9. For example, the core layer 80 is an insulating material, such as bis(cis-butenediamide) triazine (BT) or other dielectric materials.

[0057] Furthermore, the core layer 80 has a thickness D0 of 40 micrometers (µm), and the thicknesses D1 and D2 of the first metal layer 81 and the second metal layer 82 are less than the thickness D3 of the third metal layer 83. For example, the thicknesses D1 and D2 of the first metal layer 81 and the second metal layer 82 are both 3 micrometers, and the thickness D3 of the third metal layer 83 is 18 micrometers, making the thickness D of the substrate 8 82 micrometers.

[0058] Furthermore, the support member 9 is a temporary carrier plate. For example, the thickness t1 of the support member 9 is 133 micrometers, making the structural thickness H0 297 micrometers. Figure 2A As shown.

[0059] like Figure 2B As shown, the third metal layer 83 on the second metal layer 82 is removed to expose the second metal layer 82, so that the structural thickness H1 becomes 261 micrometers.

[0060] like Figure 2C As shown, a patterned wiring process is performed using the second metal layer 82 to form a circuit layer 201 on each of the core layers 80.

[0061] In this embodiment, a plurality of conductive pillars 202 electrically connected to the circuit layer 201 can be formed in the core layer 80. For example, the thickness D4 of the circuit layer 201 is 15 micrometers, making the structural thickness H2 291 micrometers.

[0062] Furthermore, the circuit layer 201 and the conductive pillar 202 are fabricated using a build-up process by electroplating metal (such as copper) or other methods. For example, multiple vias are first formed on the core layer 80 using a laser, and then copper is electroplated on the core layer 80 and in the vias to integrally form the circuit layer 201 and the conductive pillar 202.

[0063] Furthermore, there are many ways to create through holes, and there are no particular restrictions. For example, the copper material may not completely fill the through hole; or, multiple interconnected double-conical through holes may be formed.

[0064] like Figure 2D As shown, an insulating layer 24 is formed on the core layer 80 to cover the circuit layer 201, thereby forming a circuit structure 20.

[0065] In this embodiment, the thickness D5 of the insulating layer 24 is 20 micrometers, making the structural thickness H3 331 micrometers.

[0066] Furthermore, the insulating layer 24 mainly comprises acrylic resin as a solder resist layer, and has an opening 240 that exposes the circuit layer 201 to serve as an electrical contact pad 203. For example, a surface treatment layer 23 of nickel, gold, or other metals may be formed on the electrical contact pad 203.

[0067] like Figure 2E As shown, a support member 7 is attached to each of the line structures 20 (or insulation layers 24), and a reinforcing member 6 is attached to the support member 7.

[0068] In this embodiment, the support member 7 can be made of any material with toughness and a glass transition temperature (Tg) higher than that of the substrate 8 and / or the core layer 80, such as glass fiber prepreg (PP), FR4, or thermal decomposition film. For example, the support member 7 is made of polyethylene terephthalate (PET) to form a thermal decomposition film with a thickness t2 greater than or equal to 140 micrometers (µm), and is bonded to the circuit structure 20 (or the insulating layer 24) by vacuum lamination.

[0069] Furthermore, the reinforcing component 6 is mainly composed of epoxy resin. For example, in the process, an ink layer with a viscosity of 35-50 Pa·s is first coated onto the support component 7, and then the ink is baked and cured after coating. In addition to solvents, the main components of the ink include epoxy resin and / or pigments. Other components may include dispersants, leveling agents, or anti-settling agents.

[0070] like Figure 2F As shown, the carrier 9 is removed, and then the third metal layer 83 is removed to expose the first metal layer 81.

[0071] In this embodiment, the carrier 9 is first removed by a slicing process to expose the third metal layer 83, and then the third metal layer 83 is etched or stripped away.

[0072] Furthermore, in this disclosure, the hardness (pencil hardness) of the reinforcing member is greater than or equal to 8H, and the hardness (pencil hardness) of the core layer is greater than or equal to 6H. In one specific embodiment, the hardness of the reinforcing member is greater than the hardness of the core layer.

[0073] In one specific embodiment, the modulus (Young's modulus) of the reinforcing member is greater than 40 GPa, and the modulus (Young's modulus) of the core layer is 10 to 20 GPa. Preferably, the modulus of the reinforcing member is greater than the modulus of the core layer.

[0074] like Figure 2GAs shown, a patterned wiring process is performed on the first metal layer 81 to form a wiring layer 21 that electrically connects to the conductive pillar 202 on each of the core layers 80.

[0075] In this embodiment, the wiring layer 21 is made of copper, such as using the redistribution layer (RDL) specification.

[0076] Furthermore, a solder resist layer 22 can be formed on each of the core layers 80 on which the wiring layer 21 is formed, so that a portion of the wiring layer 21 is exposed on the surface of the solder resist layer 22 to serve as an electrical contact 210. For example, the solder resist layer 22 can be formed with a plurality of openings 220 exposing the electrical contacts 210. In a specific embodiment, the pencil hardness and Young's modulus of the core layer are both greater than those of the solder resist layer.

[0077] Therefore, this disclosure uses the support member 7 as the first support body to avoid the depression on the surface of the substrate 8 due to the opening 240 of the insulating layer 24 after the carrier member 9 is removed. Since the thermally dissociative film (support member 7) has low rigidity, this disclosure forms an ink (reinforcing member 6) with better hardness and rigidity on it as the second support body to facilitate the fabrication of the wiring layer 21 and the solder resist layer 22.

[0078] like Figure 2H As shown, the reinforcing member 6 and the supporting member 7 are removed, and the solder resist layer 22 is thermally cured to obtain the encapsulation substrate 2.

[0079] In this embodiment, when the support member 7 is made of a thermally dissociable film, the temperature at which it decomposes from the circuit structure 20 (or the insulating layer 24) (i.e., the dissociation temperature) can be higher or lower than the post-cure temperature or curing temperature of the solder resist layer 22 as needed. Therefore, when the dissociation temperature of the support member 7 (e.g., 120°C) is lower than the curing temperature of the solder resist layer 22 (e.g., 160°C), the support member 7 is first heated (e.g., 120°C) to remove it, and then heated (e.g., 160°C) to cure the solder resist layer 22. In other embodiments, when the dissociation temperature of the support member 7 (e.g., 190°C) is higher than the curing temperature of the solder resist layer 22 (e.g., 160°C), the solder resist layer 22 is first cured by heating, and then the support member 7 is heated to remove it.

[0080] It should be understood that since the reinforcing member 6 is attached to the support member 7, the reinforcing member 6 will be removed together with the support member 7 when the support member 7 is removed.

[0081] In summary, the method for manufacturing the packaging substrate 2 disclosed herein mainly utilizes the configuration of the reinforcing member 6 to allow existing processing equipment to continue subsequent processes, such as fabricating the wiring layer 21 and the solder resist layer 22, after removing the carrier member 9, without structural thickness limitations. Therefore, compared to the prior art, the method disclosed herein can be used for any ultra-thin substrate 8, and the performance of existing processing equipment is sufficient to meet process requirements without board jamming issues, thus achieving the ability to manufacture the minimum board thickness and improving reliability.

[0082] Furthermore, by using the reinforcing member 6 and the supporting member 7, any ultra-thin core substrate 8 can be made into a packaging substrate 2.

[0083] In addition, in order to ensure that the flatness of the thinned substrate structure meets the requirements and to avoid the problem of warping of the packaging substrate 2, the manufacturing method disclosed herein, by means of the configuration of the reinforcing member 6, ensures that the packaging substrate 2 will not warp during temperature cycling (such as thermal curing of the solder resist layer 22), thereby ensuring that the flatness of the package meets the requirements and thus improving reliability.

[0084] The above embodiments are illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure should be as set forth in the claims.

Claims

1. A method for manufacturing a packaging substrate, characterized in that, include: Substrates are respectively provided on opposite sides of the bearing member; A circuit structure is formed on the substrate; A support member is attached to the line structure, and a reinforcing member is attached to the support member; Remove the carrier to expose the substrate; A wiring layer electrically connected to the circuit structure is formed on the surface of the substrate after the carrier has been removed; as well as Remove the support and the reinforcement.

2. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The substrate includes a core layer and a first metal layer and a second metal layer formed on opposite surfaces of the core layer.

3. The method for manufacturing the packaging substrate as described in claim 2, characterized in that, The circuit structure includes a circuit layer made by means of the second metal layer and at least one conductive post disposed in the core layer and electrically connecting the circuit layer and the wiring layer.

4. The method for manufacturing the packaging substrate as described in claim 2, characterized in that, The wiring layer is fabricated using the first metal layer.

5. The method for manufacturing the packaging substrate as described in claim 3, characterized in that, The circuit structure also includes an insulating layer formed on the core layer to cover the circuit layer.

6. The method for manufacturing the packaging substrate as described in claim 2, characterized in that, The manufacturing method also includes forming a solder resist layer on the surface of the substrate on which the wiring layer is formed, so that a portion of the wiring layer is exposed on the surface of the solder resist layer.

7. The method for manufacturing the packaging substrate as described in claim 6, characterized in that, The pencil hardness and Young's modulus of the core layer are both greater than those of the solder resist layer.

8. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The support is made of a thermally dissociable membrane.

9. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The reinforcing member is formed by coating the support member with an ink layer and then baking and curing the ink layer.

10. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The reinforcing component is mainly composed of epoxy resin.

11. The method for manufacturing the packaging substrate as described in claim 9, characterized in that, The viscosity of the ink layer before baking and curing is 35~50 Pa. s.

12. The method for manufacturing the packaging substrate as described in claim 2, characterized in that, The pencil hardness of the reinforcing component is greater than or equal to 8H, and the pencil hardness of the core layer is greater than or equal to 6H.

13. The method for manufacturing the packaging substrate as described in claim 12, characterized in that, The pencil hardness of this reinforcing component is greater than that of the core layer.

14. The method for manufacturing the packaging substrate as described in claim 2, characterized in that, The Young's modulus of the reinforcing component is greater than 40 GPa, and the Young's modulus of the core layer is 10 to 20 GPa.

15. The method for manufacturing the packaging substrate as described in claim 14, characterized in that, The Young's modulus of the reinforcing component is greater than that of the core layer.

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