Image sensor, solid-state imaging device, and control method for image sensor

Abstract

This application provides an image sensor, a solid-state imaging device, and a control method for the image sensor. The image sensor includes: a first pixel and a second pixel, each including a photodiode and a floating diffusion region, with the floating diffusion region connected in series with the photodiode; a first switching transistor, with its first and second terminals connected between the floating diffusion region and the photodiode in each pixel; and each of the first and second pixels further including an overflow transistor, with its first and second terminals connected to the photodiode and a power supply voltage, respectively. This application provides an image sensor, a solid-state imaging device, and a control method for the image sensor, capable of achieving a wide dynamic range.

Description

Technical Field

[0001] This application relates to the field of camera technology, and more specifically, to an image sensor, a solid-state imaging device, and a control method for the image sensor. Background Technology

[0002] Dynamic range (DR) is an important performance parameter of image sensors. DR refers to the ratio of the signal intensity of the brightest part of an image to that of the darkest part. A higher dynamic range means that more detail in both bright and dark areas of the image can be preserved in high-contrast scenes, resulting in a higher degree of fidelity to the real-world scene as seen by the naked eye.

[0003] Lateral overflow integration capacitor (LOFIC) technology is an effective method for achieving a wide dynamic range. It collects the charge overflowing from the photodiode (PD) by adding capacitance to the pixel structure, preventing signal loss. The larger the LOFIC capacitance value, the more charge it can store, and the wider the achievable dynamic range. However, large capacitance designs are easily limited by chip area, and current chip designs are trending towards miniaturization. Therefore, the problem of achieving a wide dynamic range in image sensors remains to be solved. Summary of the Invention

[0004] This application provides an image sensor, a solid-state imaging device, and a control method for the image sensor, which can achieve a wide dynamic range.

[0005] In a first aspect, an image sensor is provided, comprising: a first pixel, the first pixel including a first photodiode and a first floating diffusion region, the first floating diffusion region being connected in series with the first photodiode; a second pixel, the second pixel including a second photodiode and a second floating diffusion region, the second floating diffusion region being connected in series with the second photodiode; a first switching transistor, a first terminal of the first switching transistor being connected between the first floating diffusion region and the first photodiode, and a second terminal of the first switching transistor being connected between the second floating diffusion region and the second photodiode; the first pixel further comprising a first overflow transistor, a first terminal of the first overflow transistor being connected to the first photodiode, and a second terminal of the first overflow transistor being connected to a power supply voltage; and / or, the second pixel further comprising a second overflow transistor, a first terminal of the second overflow transistor being connected to the second photodiode, and a second terminal of the second overflow transistor being connected to the power supply voltage.

[0006] In the embodiments provided in this application, the image sensor includes a first switching transistor connected to a first pixel and a second pixel. When the first switching transistor is turned on, the circuit containing the first switching transistor can form a capacitor with other metal lines around the circuit. This capacitor, together with the first floating diffusion region and the second floating diffusion region, forms a combined capacitor. This combined capacitor has a high capacitance value, and the charge overflowed by the photodiode during the exposure time can be stored in this combined capacitor for subsequent readout, thereby achieving a wide dynamic range. The first pixel includes a first overflow transistor, and the second pixel includes a second overflow transistor, which can separate the overflow charge of different color pixels to obtain the correct color signal and improve the display quality of the image. In addition, the image sensor occupies a small area, which facilitates the implementation of small pixels. Connecting the first switching transistor between the first pixel and the second pixel allows for processing using existing CIS standard processes, which are simple and have high productivity.

[0007] In conjunction with the first aspect, in some implementations of the first aspect, the first floating diffusion region and the second floating diffusion region are floating diffusion regions arranged adjacent to each other.

[0008] In the embodiments provided in this application, the first floating diffusion region and the second floating diffusion region are adjacent floating diffusion regions, which facilitates the routing of the image sensor and reduces the area of ​​the image sensor.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the image sensor further includes a third pixel and a fourth pixel, and the image sensor further includes a second switching transistor, a third switching transistor, and a fourth switching transistor, wherein the second switching transistor is connected between the first pixel and the third pixel, the third switching transistor is connected between the second pixel and the fourth pixel, and the fourth switching transistor is connected between the third pixel and the fourth pixel.

[0010] In the embodiments provided in this application, multiple pixels are interconnected through switching transistors. By turning on more switching transistors, a larger capacitance can be achieved, thereby better realizing the effect of wide dynamic range.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the first switching transistor is connected in series with the second switching transistor; and / or, the third switching transistor is connected in series with the fourth switching transistor.

[0012] In the embodiments provided in this application, the first switching transistor and the second switching transistor are connected in series, and / or the third switching transistor and the fourth switching transistor are connected in series, which facilitates individual control of each pixel and individual switching of the conversion gain of each pixel.

[0013] In conjunction with the first aspect, in certain implementations of the first aspect, at least two of the gates of the first switching transistor, the second switching transistor, the third switching transistor, or the fourth switching transistor are connected to the same gate signal.

[0014] In the embodiments provided in this application, at least two of the gates of the first switching transistor, the second switching transistor, the third switching transistor, or the fourth switching transistor are connected to the same gate signal, which can reduce the structural space occupied by the signal lines.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, a plurality of first pixels share a first floating diffusion region; and / or, a plurality of second pixels share a second floating diffusion region.

[0016] In the embodiments provided in this application, multiple first pixels share a first floating diffusion region; and / or multiple second pixels share a second floating diffusion region, which can reduce the pixel size.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, a plurality of first pixels sharing the first floating diffusion region are jointly connected to the first switching transistor; and / or, a plurality of second pixels sharing the second floating diffusion region are jointly connected to the first switching transistor.

[0018] In the embodiments provided in this application, multiple first pixels sharing a first floating diffusion region are connected to a first switching transistor; and / or, multiple second pixels sharing a second floating diffusion region are connected to a first switching transistor, which can further reduce the pixel size.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the plurality of first pixels connected to the first switching transistor are of the same color; and / or, the plurality of second pixels connected to the first switching transistor are of the same color.

[0020] In the embodiments provided in this application, the multiple first pixels connected to the first switching transistor are of the same color; and / or, the multiple second pixels connected to the first switching transistor are of the same color, which can prevent the signals of pixels of different colors from mixing.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the first pixel further includes a first transmission transistor, a second transmission transistor, and a first memory node, wherein the first transmission transistor and the second transmission transistor are connected in series, and one end of the first memory node is connected between the first transmission transistor and the second transmission transistor; and / or, the second pixel further includes a third transmission transistor, a fourth transmission transistor, and a second memory node, wherein the third transmission transistor and the fourth transmission transistor are connected in series, and one end of the second memory node is connected between the third transmission transistor and the fourth transmission transistor.

[0022] In the embodiments provided in this application, one end of the first memory node is connected between the first transmission transistor and the second transmission transistor, and one end of the second memory node is connected between the third transmission transistor and the fourth transmission transistor, which facilitates the application of the image sensor in global shutter scenarios.

[0023] In a second aspect, a solid-state imaging device is provided, comprising an image sensor as described in the first aspect or any possible implementation thereof.

[0024] Thirdly, an electronic device is provided, including the solid-state imaging device described in the second aspect.

[0025] Fourthly, a control method for an image sensor is provided, applied to the image sensor as described in the first aspect or any possible implementation thereof, the method comprising: when the first pixel is a readout pixel, at a first moment, reading out a first voltage value, the first voltage value being the voltage value of the first floating diffusion region after a first reset process, and the first switching transistor being in a closed state at the first moment; at a second moment, reading out a second voltage value, the second voltage value being the voltage value of the first floating diffusion region after receiving overflow charge from the first photodiode, and the first switching transistor being in a closed state at the second moment; at a third moment, reading out a third voltage value, the third voltage value being the voltage value of the first floating diffusion region after a second reset process, and the first switching transistor being in a turned-on state at the third moment; at a fourth moment, reading out a fourth voltage value, the first switching transistor being in a turned-on state at the fourth moment, the circuit containing the first switching transistor and the first floating diffusion region forming a combined capacitor at the fourth moment, and the fourth voltage value being the voltage value of the combined capacitor after receiving overflow charge from the first photodiode.

[0026] In the embodiments provided in this application, two readouts are performed when the first switching transistor is on and off, and the reset signal and the signal after collecting the overflow charge are read out respectively. This makes it easy to obtain light intensity information based on the four readout signals and achieve a wide dynamic range.

[0027] In conjunction with the fourth aspect, in some implementations of the fourth aspect, when the second pixel and the first pixel are located in different pixel rows and the second pixel and the first pixel have different colors, at the fourth moment, the first overflow transistor is turned off and the second overflow transistor is turned on.

[0028] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the third moment occurs before the first moment.

[0029] In conjunction with the fourth aspect, in some implementations of the fourth aspect, at the fourth time, at least some of the transistors of the second switching transistor, the third switching transistor, and the fourth switching transistor are in the on state. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure and operation timing diagram of an image sensor;

[0031] Figure 2 and Figure 3 This is a schematic diagram of the node potential in an image sensor;

[0032] Figure 4 This is a schematic diagram of the structure of an image sensor provided in an embodiment of this application;

[0033] Figure 5 This is a schematic structural diagram and a node potential diagram of an image sensor provided in an embodiment of this application;

[0034] Figure 6 This is a schematic diagram of the structure of an image sensor provided in an embodiment of this application;

[0035] Figure 7 This is a schematic structural diagram and a node potential diagram of an image sensor provided in an embodiment of this application;

[0036] Figures 8 to 12 This is an operation timing diagram of the image sensor provided in the embodiments of this application;

[0037] Figures 13 to 15 This is a schematic diagram of the structure of the image sensor provided in the embodiments of this application;

[0038] Figures 16 to 18 This is a schematic structural diagram of the image sensor provided in the embodiments of this application;

[0039] Figure 19 and Figure 20 This is a schematic diagram of the structure of the image sensor provided in the embodiments of this application;

[0040] Figure 21and Figure 22 This is a schematic structural diagram of the image sensor provided in the embodiments of this application;

[0041] Figure 23 This is a schematic diagram of the structure of the image sensor provided in the embodiments of this application;

[0042] Figure 24 This is a schematic structural diagram of the image sensor provided in the embodiments of this application;

[0043] Figure 25 This is a schematic diagram of the structure of the image sensor provided in the embodiments of this application;

[0044] Figure 26 This is a schematic diagram of the solid-state imaging device provided in the embodiments of this application. Detailed Implementation

[0045] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0046] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0047] In the various embodiments of this application, the terms "first," "second," etc., are merely to indicate that multiple objects are different. For example, "first switching transistor" and "second switching transistor" are only to indicate different switching transistors. They should not have any effect on the switching transistors themselves or their number, and the aforementioned "first," "second," etc., should not impose any limitations on the embodiments of this application.

[0048] The terms “including,” “comprising,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized.

[0049] To facilitate understanding of this application, the technical terms used in this application will be introduced below:

[0050] (1) Lateral overflow integration capacitor (LOFIC)

[0051] LOFIC technology is an effective method to improve dynamic range. By adding capacitors within the pixel, it effectively collects the overflow charge of the photodiode, avoiding artifacts caused by direct charge overflow in the PD, and making the total full-well capacity of the pixel structure no longer limited by the full-well capacity of the PD.

[0052] (2) Full trap capacity

[0053] The full-well capacity of an image sensor refers to the maximum number of electrons that the pixel structure can collect and hold. A large full-well capacity can effectively improve the dynamic range of an image sensor.

[0054] (3) Floating diffusion (FD)

[0055] A floating diffusion region is a highly doped semiconductor region, typically composed of n-type material, formed on a p-type substrate. It is capable of temporarily storing charge overflowing from the PD.

[0056] (4) Conversion gain (CG)

[0057] Conversion gain is the rate at which charge accumulated in a floating diffusion node is converted into voltage; that is, the magnitude of the voltage change caused by an electron at the floating diffusion node. Conversion gain can be expressed as the ratio of the amount of charge to the node capacitance. Conversion gain modes are generally categorized into high conversion gain (HCG), low conversion gain (LCG), and dual conversion gain (DCG) modes for different illumination intensities. Dual conversion gain refers to implementing both high and low conversion gain modes within the same pixel, and these two modes can be switched.

[0058] Figure 1 (a) in the image is a schematic diagram of the pixel circuit of an image sensor. Figure 1 (b) in the diagram is the timing diagram of the pixel circuit. For example... Figure 1 As shown in (a), the pixel circuit may include a photodiode (PD), a transfer (TX) transistor, and a floating diffusion region (FD). One end of the PD is grounded, and the other end is connected to the first end of the TX transistor. The second end of the TX transistor is connected to the first end of the FD, and the third end of the TX transistor can be connected to the transfer gate (TG) signal. The second end of the FD can be grounded. When the TX transistor is in the on state, the connection between the PD and the FD is turned on, transferring charge from the PD to the FD.

[0059] As mentioned above, FD is a doped semiconductor that can be used to temporarily store charge, exhibiting capacitor-like characteristics. Therefore, FD is represented by the capacitor symbol in the figure.

[0060] The pixel circuit may also include a LFOIC and a reset (RST) transistor, the first terminal of which can be connected to V. LOFIC Voltage connection: the second terminal of the LOFIC can be connected to the first terminal of the RST transistor; the second terminal of the RST transistor can be connected to the power supply voltage V. DD The third terminal of the RST transistor can be connected to a reset signal (RST signal). This RST transistor can be used to reset LOFIC and FD.

[0061] The pixel circuit may also include a switching transistor, also known as a dual floating diffusion (DFD) transistor. The first terminal of the DFD transistor can be connected between the second terminal of the TX transistor and the first terminal of the FD transistor. The second terminal of the DFD transistor can be connected between the RST transistor and the LOFIC. The DFD transistor can be used to turn the connection between the FD and the LOFIC on or off.

[0062] The pixel circuit may also include a source follower (SF) transistor and a select (SEL) transistor. The first terminal of the SF transistor can be connected to the VDD voltage, the second terminal of the SF transistor can be connected to the first terminal of the SEL transistor, and the third terminal of the SF transistor can be connected between the first terminals of the DFD transistor and the first terminal of the FD. After exposure, the charge in the PD is transferred to the FD, causing a voltage change on the FD. The SF transistor converts this voltage change on the FD into a current change and provides a voltage signal proportional to the input voltage through its output terminal to amplify and stabilize the signal, ensuring that subsequent circuits can accurately read the signal. The second terminal of the SEL transistor can be connected to an analog signal (Vsig), and the third terminal of the SEL transistor can be connected to the SEL signal. The SEL transistor can be used to output a pixel signal based on the voltage of the SF follower. The SEL signal can be used to select which row of signals to read. When reading the signal of the current row of pixels, the SEL transistor of the current row of pixels can be in the on state; when not reading, it is in the off state.

[0063] The TX transistor, DFD transistor, RST transistor, SF transistor, and SEL transistor can be oxide transistors, which are in the on state under a positive voltage signal and in the off state under a negative voltage signal.

[0064] The first terminal of the transistor can be the source of the transistor, the second terminal can be the drain of the transistor, and the third terminal can be the gate of the transistor. The source and drain can also be interchanged.

[0065] The following is combined Figure 1 The timing pair shown in (b) Figure 1 The working process of the pixel circuit shown in (a) will be introduced.

[0066] At time t1, the DFD signal is high, the DFD transistor is on, and the connection between LOFIC and FD is established. TG is high, the TX transistor is on, and the connection between PD and FD is established. At time t1, LOFIC, PD, and FD are all connected to node N. The RST signal is high, the RST transistor is on, and the VDD voltage is written to node N, resetting PD, FD, and LOFIC to VDD. This process can be called the LOFIC reset process, which helps eliminate the influence of residual charge and ensures the consistency and accuracy of measurement results.

[0067] At time t2, the TG signal becomes a low voltage, the TX transistor is turned off, and the PD enters the exposure state. In the exposure state, the PD absorbs photons to generate electron-hole pairs. The generated electrons are collected inside the PD, forming a charge accumulation proportional to the incident light intensity.

[0068] At time t2, the RST signal goes low, the RST transistor turns off, and LOFIC and FD are connected to node N. The Vramp signal, used for analog-to-digital conversion, is a ramp signal that changes linearly with time. This Vramp signal, along with the Vsig signal, is input to a comparator for comparison with the analog signal Vsig. When the voltage value of the Vramp signal reaches or exceeds that of the Vsig signal, the corresponding signal value is read out. That is, the voltage value at the intersection of the Vsig and Vramp signals is read out. This read voltage value is an analog signal, which can be converted to a digital value through subsequent processing to determine the signal strength. The signal strength read out at time t2 can be considered the reset voltage value of the parallel capacitor between LOFIC and FD.

[0069] At time t3, the DFD signal is at a low voltage, the DFD transistor is turned off, and the connection between LOFIC and FD is broken.

[0070] At time t4, the voltage of node N is read out. Since the connection between LOFIC and FD is broken, the read signal strength is the voltage value of FD.

[0071] At time t5, the TG signal becomes high voltage, the TX transistor turns on, and the charge accumulated in the PD during the exposure time overflows into the FD.

[0072] At time t6, the voltage of node N is read out. Because the charge accumulated in PD overflows into FD, the voltage value read out at time t6 is different from the voltage value read out at time t4.

[0073] At time t7, the DFD signal becomes high voltage, the DFD transistor turns on, the connection between LOFIC and FD is turned on, and the charge accumulated in LOFIC during the exposure time is transferred to FD.

[0074] At time t8, the TG signal is at a high voltage, the TX transistor is turned on, and the charge accumulated in PD overflows into FD.

[0075] At time t9, the DFD transistor is still in the on state, and the voltage value of node N is read out, which is the voltage value of the combined capacitor of LOFIC and FD.

[0076] At time t10, PD, FD, and LOFIC are reset to prepare for the next exposure stage.

[0077] Figure 1 The double wavy line shown indicates that the exposure time of the image sensor can be extended, and the voltage of each signal can be maintained at the voltage corresponding to the time point of the wavy line during the extended period. The double wavy line in the timing diagrams discussed below has a similar meaning.

[0078] Figure 2 and Figure 3 These are potential diagrams from PD through FD and LOFIC to the drain node VDD of the RST transistor at times t1 to t10, respectively, in bright light and dark light scenarios.

[0079] like Figure 2 As shown, similar to the description of the timing sequence above, at time t1, PD is cleared by the TG signal, the RST transistor is turned on, and the potentials on FD and LOFIC are reset to VDD. The potentials on PD, FD, and LOFIC are the same.

[0080] At time t2, the DFD transistor turns on, and FD and LOFIC form a combined capacitor. The potentials of FD and LOFIC at all points on the line are the same. The reset voltage (reset 2) of this combined capacitor is latched, or in other words, the reset voltage of this combined capacitor is read out.

[0081] At time t3, the DFD transistor is turned off, and FD and LOFIC separate.

[0082] At time t4, due to the high-brightness exposure scene, the amount of charge generated in the PD is large, and the accumulated charge overflows. The overflowed charge can be transferred to the FD or to the LOFIC. The reset voltage (reset 1) of the FD is latched and read out.

[0083] At time t5, the TX transistor is turned on, and the charge in PD is transferred to FD.

[0084] At time t6, the TX transistor is turned off, latching the signal voltage (signal 1) of FD.

[0085] At time t7, the DFD transistor turns on, and the charge collected in the FD is deposited into the combined capacitance formed by the FD and LOFIC.

[0086] At time t8, the TX transistor turns on, and the charge in the PD is transferred to the combined capacitor.

[0087] At time t9, the TX transistor is turned off, and the voltage value of the combined capacitor FD and LOFIC (signal 2) is latched.

[0088] At time t10, PD, FD, and LOFIC are reset to VDD again.

[0089] Figure 3 The changes in the potential diagram in the low-light scene are shown. Figure 2 The changes in the potential diagram under bright light are similar. In low light, the amount of charge accumulated by the PD during exposure time is small, and it does not reach the PD's saturation state. At time t4, the charge is stored in the PD and does not overflow to the FD and LOFIC.

[0090] As mentioned above, a large LOFIC capacitor value is required to achieve a wide dynamic range, but the design of a large capacitor value is easily limited by the chip area. Therefore, embodiments of this application provide a solution for achieving a wide dynamic range, and this solution does not easily affect the chip area.

[0091] Figure 4 This is a schematic diagram of the pixel circuit of an image sensor provided in an embodiment of this application, such as... Figure 4 As shown, the image sensor includes a first pixel and a second pixel. The first pixel can be pixel PX1, which is marked by the dashed box on the left, and the second pixel can be pixel PX2, which is marked by the dashed box on the right.

[0092] The first pixel includes a first photodiode PD (hereinafter referred to as the first PD) and a first floating diffusion region (hereinafter referred to as the first FD), the first FD being connected in series with the first PD. The second pixel includes a second photodiode PD (hereinafter referred to as the second PD) and a second floating diffusion region (hereinafter referred to as the second FD), the second FD being connected in series with the second PD.

[0093] The image sensor may further include a first switching transistor, the first terminal of which may be connected between the first FD and the first PD, and the second terminal of which may be connected between the second FD and the second PD. This first switching transistor may also be referred to as a connection transistor or a floating diffusion connect (FDC) transistor.

[0094] When the first switching transistor is in the ON state, the circuit containing the first switching transistor is turned on. The connection line to which the first switching transistor is connected can form a capacitor with other connection lines nearby. For example, the connection line to which the first switching transistor is connected can form a capacitor with the connection line to which the first FD is connected. This capacitor can also be used to store the charge overflowed by the first PD and / or the second PD. The following is in conjunction with... Figure 5 The working principle of the first switching transistor will be introduced.

[0095] Figure 5 This application provides a schematic structural diagram of the image sensor and a schematic diagram of the charge changes corresponding to the pixel structure. Figure 5 (a) shows the structural diagram (left) and charge diagram (right) when there is no first switching transistor connection between the first pixel and the second pixel. Figure 5 Figure (b) shows a schematic diagram (left) and a charge diagram (right) of a structure where a first switching transistor is located between the first pixel and the second pixel and the first switching transistor is in the off state. Figure 5 (c) is a schematic diagram (left) and a charge diagram (right) of a structure when there is a first switching transistor between the first pixel and the second pixel and the first switching transistor is in the open state. Figure 5 The switch in the diagram represents the first switching transistor. When the switch is open, the first switching transistor is off; when the switch is on, the first switching transistor is on.

[0096] like Figure 5 As shown in (a), when there is no connection between the first and second pixels, the charge accumulated by the PD in each pixel during exposure overflows into the FD of that pixel. Figure 5As shown in (b), when the first pixel and the second pixel are connected by a first switching transistor, the first FD in the first pixel is connected to the second FD in the second pixel. When the first switching transistor is in the off state, the first FD, the first switching transistor, and the second FD can be used to store charge, respectively. Figure 5 As shown in (c), when the first switching transistor is in the on state, the first FD, the first switching transistor, and the second FD form a combined capacitor. The amount of charge that can be stored in this combined capacitor is greater than the amount of charge that a single FD can store. Therefore, this combined capacitor can collect more overflow charge from the PD, achieving a wide dynamic range and replacing the traditional LOFIC.

[0097] Furthermore, the first switching transistor and the connecting lines at both ends occupy a small area, which facilitates the implementation of small pixels. Moreover, connecting the first switching transistor between the first pixel and the second pixel allows for fabrication using existing standard processes for complementary metal-oxide-semiconductor (CIS) image sensors, resulting in a simple process and high productivity.

[0098] It should be understood that Figure 5 The simplified structural diagram shown is merely an example illustrating the structural elements contained in the image sensor and should not be construed as limiting the shape or position of the structural components in the image sensor. The circuit containing the first switching transistor can form a capacitor not only with the connecting line connected to the aforementioned FD, but also with the connecting lines surrounding the circuit containing the first switching transistor; this application does not impose any limitations on this.

[0099] See also Figure 4In some embodiments of the structure shown, the first pixel further includes a first transfer transistor (hereinafter referred to as the first TX transistor). The first TX transistor can be connected between the first PD and the first FD, and the first terminal of the first switching transistor can be connected between the first TX transistor and the first FD. The third terminal of the first TX transistor can be connected to a TG signal, which controls the on / off state of the first TX transistor. When the first TX transistor is on, the charge accumulated in the first PD during exposure can be transferred to the first FD through the first TX transistor. The second pixel may also include a second transfer transistor (hereinafter referred to as the second TX transistor). The second TX transistor can be connected between the second PD and the second FD, and the first terminal of the second switching transistor can be connected between the second TX transistor and the second FD. The third terminal of the second TX transistor can also be connected to a TG signal, which controls the on / off state of the second TX transistor. When the second TX transistor is on, the charge accumulated in the second PD during exposure can be transferred to the second FD through the second TX transistor.

[0100] The first pixel may further include a first reset transistor (hereinafter referred to as the first RST transistor). The first terminal of the first RST transistor is connected to the power supply voltage VDD, and the second terminal of the first RST transistor is connected to the second terminal of the first TX transistor and the first FD. Alternatively, the first FD, the first RST transistor, and the first PD can all be connected to node N1. The third terminal of the first RST transistor can be connected to an RST signal, which controls the on / off state of the first RST transistor. When the first RST transistor is on, the first FD is connected to the VDD voltage, and the VDD voltage can reset the first FD.

[0101] Similarly, the second pixel may also include a second reset transistor (hereinafter referred to as the second RST transistor). The first terminal of the second RST transistor is connected to the power supply voltage VDD, and the second terminal is connected to the second terminal of the second TX transistor and the second FD. Alternatively, the second FD, the second RST transistor, and the second PD can all be connected to node N2. The third terminal of the second RST transistor can also be connected to the RST signal, which controls the on / off state of the second RST transistor. When the second RST transistor is on, the second FD is connected to the VDD voltage, and the VDD voltage can reset the second FD.

[0102] The first pixel may further include a first source follower transistor (hereinafter referred to as the first SF transistor) and a first select transistor (hereinafter referred to as the first SEL transistor). The first terminal of the first SF transistor is connected to VDD, the second terminal of the first SF transistor is connected to the first terminal of the first SEL transistor, and the third terminal of the first SF transistor is connected to the second terminal of the first RST transistor. The second terminal of the first SEL transistor is connected to the Vsig signal, and the third terminal of the first SEL transistor is connected to the SEL signal. The SEL signal controls the on / off state of the first SEL transistor. When the first SEL transistor is on, the signal of the first pixel can be read out.

[0103] Similarly, the second pixel may also include a second source follower transistor (hereinafter referred to as the second SF transistor) and a second select transistor (hereinafter referred to as the second SEL transistor). The first terminal of the second SF transistor is connected to VDD, the second terminal of the second SF transistor is connected to the first terminal of the second SEL transistor, and the third terminal of the second SF transistor is connected to the second terminal of the second RST transistor. The second terminal of the second SEL transistor is connected to the Vsig signal, and the third terminal of the second SEL transistor is connected to the SEL signal, which controls the on / off state of the second SEL transistor. When the first SEL transistor is turned on, the signal of the first pixel can be read out.

[0104] The first pixel and the second pixel may be located in the same pixel row, or they may be located in the same pixel column, or they may be neither located in the same pixel row nor in the same pixel column. The first pixel and the second pixel may be adjacent pixels or they may not be adjacent pixels; this application does not limit this.

[0105] Figure 6 This is a schematic diagram of the pixel circuit of another image sensor provided in an embodiment of this application, as shown below. Figure 6 As shown, the first pixel may further include a first overflow (OF) transistor (hereinafter referred to as the first OF transistor). The first terminal of the first OF transistor may be connected between the first PD and the first TX transistors, and the second terminal of the first OF transistor may be connected to the power supply voltage. The third terminal of the first OF transistor may be connected to the overflow gate (OFG) signal, and the OFG signal controls the on / off state of the first OF transistor.

[0106] Similarly, the second pixel may also include a second overflow transistor (hereinafter referred to as the second OF transistor). The first terminal of the second OF transistor may be connected between the second PD and the second TX transistors, and the second terminal of the second OF transistor may be connected to the power supply voltage. The third terminal of the second OF transistor may be connected to the overflow gate (OFG) signal, which controls the on / off state of the second OF transistor.

[0107] The connection node between the first OFG and VDD can be called the first overflow drain (OFD), and the connection node between the second OFG and VDD can be called the second OFD. The first OFD and the second OFD can be used to store the charge from the first PD and the second PD, respectively.

[0108] Figure 7 This application provides a schematic structural diagram and a schematic diagram of charge change for another image sensor, wherein... Figure 7 (a) shows the architecture and charge diagram of the image sensor excluding OFD. Figure 7 (b) in the figure is a structural diagram and a charge diagram of the image sensor including OFD.

[0109] like Figure 7 As shown in (a), assuming the first pixel is a blue pixel and the second pixel is a green pixel, when the first switching transistor is turned on, the charge overflowing from the first PD and the charge overflowing from the second PD are both transferred to the combined capacitor formed by the first FD, the first switching transistor, and the second FD. Pixel signals of different colors are prone to mixing at the location of the combined capacitor. Figure 7 As shown in (b), when the image sensor includes a first OFD and a second OFD, the first OFD transistor is turned on when the first switching transistor is turned on. Due to the higher potential on the VDD side, when the first OFD transistor is turned on, the charge in the first PD transfers to the first OFD. The second OFD transistor can be in a closed state, and the charge in the second PD transfers to the combined capacitor location. Alternatively, when the first switching transistor is turned on, the second OFD transistor is turned on, while the first OFD transistor is turned off. In this case, the charge in the second PD transfers to the second OFD, and the charge in the first PD transfers to the combined capacitor location. Furthermore, the different colored charges flow to different areas, preventing the mixing of pixel signals of different colors. This allows the image sensor to obtain correct pixel signals, preventing problems such as color crosstalk, and thus improving the imaging quality of the image sensor.

[0110] It should be understood that the first pixel and the second pixel can also have the same color. When the first pixel and the second pixel have the same color, the first OF transistor and the second OF transistor can also be turned on or off at the same time.

[0111] In some embodiments, the voltage value of VDD can be 3V, and the voltage values ​​of the first OFD and the second OFD can also be 3V.

[0112] In some embodiments, the switching voltages of the OFG signal can be 3V and -1.6V, respectively. The switching voltages of the TG signal can be 3V and -1.6V, respectively. The switching voltages of the SEL signal can be 3V and -1.6V, respectively. The switching voltages of the FDCG signal can be 3V and -1.6V, respectively. The switching voltages of the RST signal are 3V and 0V, respectively.

[0113] Figures 8 to 11 for Figure 6 The image sensor operation timing diagram shown is as follows, in which, Figure 8 This is a timing diagram of the image sensor's operation in the first mode. Figure 9 This is a timing diagram showing the operation of the image sensor in the second mode. The first mode can be a high-brightness mode, and the second mode can be a normal light mode, also known as a normal mode. The following will first combine... Figure 8 and Figure 9 The operation process of the first and second modes will be introduced.

[0114] like Figure 8 As shown, in the first mode, the light intensity is strong, and the charge accumulated by the PD during the exposure time is large. To ensure that the PD remains unsaturated and prevent the accumulated charge from overflowing, the FDCG is maintained at a constant high voltage at different times, and the first switching transistor can be kept in the on state. Furthermore, in this first mode, with the first switching transistor in the on state, the combined capacitance formed by the floating diffusion region and the circuit containing the first switching transistor is large, and the voltage change caused by an electron at the location of the floating diffusion region is small. Therefore, the readout pixel can be in low-gain mode.

[0115] also, Figure 8 The operation timing diagram shown can be applied to rolling shutter scenarios, which refers to the exposure and readout of multiple rows of pixels in the image sensor line by line. That is, the exposure of the next row is performed after the current row is exposed, and the readout of the next row is performed after the current row is readout. Figure 8In this context, the `read` signal is the signal from the read-out pixel, and the `others` signals are the signals from other pixels besides the read-out pixel. For example, `OFG-read` is the OFG signal from the read-out pixel, and `OFG-others` is the OFG signal from other pixels besides the read-out pixel. `RST(common)` refers to the RST signals from both read-out and non-read-out pixels, and the timing of the RST signals from both read-out and non-read-out pixels is the same.

[0116] For example, Figure 8 Taking the first pixel in the image as an example, we will introduce the operation process of reading out pixels.

[0117] At time t1, the RST signal is high, the first RST transistor is turned on, the first FD is reset to VDD, and the first FD is reset. The OFG-read signal is high, the first OF transistor of the first pixel is turned on, the first PD is reset to VDD, and the first PD is reset.

[0118] At time t2, the Vramp signal has a slope, and the reset voltage value of the first FD is read out. (As described above...) Figure 1 Similar to the described embodiment, the readout process can be a numerical value read by comparing the Vramp signal with the Vsig signal. In this example, time t2 in the first mode can be referred to as the first time.

[0119] At time t3, the first OF transistor, the first TX transistor, and the first RST transistor are all in the off state, and the first PD is in the exposure time, continuously accumulating charge in the first PD. The exposure time of the first PD can start from the off time of the OFG-read signal and end from the on time of the TG-read signal.

[0120] At time t4, the TG-read signal is at a high voltage, the first TX transistor is in the on state, and the charge accumulated by the first PD during the exposure time begins to overflow. Since the first switching transistor is in the on state, the first FD, the first switching transistor, and the second FD form a combined capacitor, and the charge overflowing from the first PD overflows into this combined capacitor.

[0121] At time t5, the SEL-read signal is high, and the voltage value of the combined capacitor is read. In this example, time t5 in this first mode can be referred to as time 2. The reset signal value of the first FD and the voltage value at exposure are read at time t2 and time t5, respectively. Subtracting the two signal values ​​can be used to eliminate noise.

[0122] At time t6, the RST and OFG-read signals go high to initiate a new round of reset in order to start the next exposure stage.

[0123] For the second pixel, when it is a readout pixel, the actions performed by the second pixel can be the same as those performed by the first pixel when it is readout. When the first pixel is readout and the second pixel has a different color from the first pixel, at time t4, the second pixel can execute the OFG-others timing, that is, at time t4, the second OF transistor is turned on, so that the charge generated by the second PD flows to VDD, while the charge overflowing from the first PD flows to the combined capacitor, to prevent the pixel signals of different colors from mixing.

[0124] like Figure 9 As shown, in the second mode, the light intensity is lower, and the amount of charge accumulated by the PD during exposure time is less, allowing the PD to remain in a constant unsaturated state. At different times, the FDCG can maintain a constant low voltage, and the first switching transistor can remain constantly off. In this second mode, with the first switching transistor off, only the floating diffusion region is used to collect the overflow charge from the PD. At the location of the floating diffusion region, the voltage change caused by a single electron is significant, allowing the readout pixel to operate in a high-gain mode.

[0125] In this second mode, the timing of operations performed by readout pixels and non-readout pixels can be the same.

[0126] Taking the first pixel as the readout pixel as an example, at time t1, similar to the first mode, the RST signal is high, the first RST transistor is in the on state, the first FD is reset to VDD, and the first FD is reset. The OFG signal is high, the first OF transistor of the first pixel is in the on state, the first PD is reset to VDD, and the first PD is reset.

[0127] At time t2, the first PD enters the exposure time, and charge begins to accumulate in the first PD.

[0128] At time t3, the first OF transistor, the first TX transistor, and the first RST transistor are all off, the SEL signal is high, the first pixel is the readout pixel, and the reset voltage value of the first FD is read out. In this example, time t3 in this second mode can also be referred to as the third time.

[0129] At time t4, the TG signal is at a high voltage, the first TX transistor is turned on, and the charge accumulated in the first PD overflows into the first FD.

[0130] At time t5, the SEL signal is high voltage, the Vramp signal is ramp voltage, and the voltage value of the first FD is read again. In this example, time t5 in this second mode can be referred to as the fourth time. The reset signal value of the first FD and the voltage value at exposure are read at time t3 and time t5, respectively. Subtracting the two signal values ​​can be used to eliminate noise.

[0131] At time t6, the RST and OFG-read signals go high to initiate a new round of reset in order to start the next exposure stage.

[0132] In this second mode, the first switching transistor is in the off state, and the charge overflowed by the PD in each pixel is stored in the FD of each pixel, so there is no color mixing problem. Therefore, the OF transistors of each pixel can be in the off or on state at the same time.

[0133] Figure 10 This is an operational timing diagram of the image sensor in a dual-exposure mode combining first and second mode frames. The operational timing of the first mode and the operational timing of the second mode can be respectively compared with... Figure 8 and Figure 9 The operation timing shown is the same. In the first and second modes, the image sensor performs one exposure each, and reads out the reset signal and charge signal in high-brightness and low-brightness scenes, respectively. Based on the four readout signals, light intensity information under both bright and dark conditions can be obtained, achieving a wide dynamic range. Under high-brightness light, because the first switching transistor is turned on, the PD full-well capacity is large, resulting in low-sensitivity and unsaturated images. Under normal lighting, because the first switching transistor is turned off, it has high pixel conversion gain, resulting in high-sensitivity and low-noise images. By combining images from high-brightness and low-brightness scenes, a wide dynamic range (DR) image can be obtained.

[0134] Figure 10 The operation sequence shown achieves a wide dynamic range by acquiring brightness and darkness information through two exposures. This image sensor can also acquire brightness and darkness information through a single exposure, that is, acquire image data in both the first and second modes, as shown below. Figure 11 The operation timing diagram is shown.

[0135] like Figure 11 As shown, taking the first pixel as the readout pixel as an example, at time t1, the first RST transistor, the first switching transistor, and the first OF transistor are turned on, and the first PD and the first FD are reset. After the first OF transistor is turned off, the image sensor enters the exposure state.

[0136] At time t2, the first RST transistor and the first OF transistor are turned off, and the first switching transistor is turned on. The first pixel is in low-gain mode, and the reset voltage of the combined capacitor formed by the line containing the first switching transistor and the first FD is read out. In this example, time t2 can also be referred to as the third time.

[0137] At time t3, the first switching transistor is turned off. The charge accumulated in the first PD during the exposure time is transferred to the first FD.

[0138] At time t4, the first switching transistor is in the off state, the first pixel is in high gain mode, and the reset voltage of the first FD is read out.

[0139] At time t5, the first TX transistor turns on, and the overflow charge of the first PD flows to the first FD.

[0140] At time t6, the first switching transistor is in the off state, and the voltage value after the first FD collects the overflow charge is read out.

[0141] At time t7, the first switching transistor turns on, and the first pixel is in low-gain mode. The first TX transistor turns on, and the charge accumulated in the first PD overflows into the combined capacitor.

[0142] At time t8, the first switching transistor turns on, and the voltage value after the combined capacitor collects the overflow charge is read out.

[0143] By comparing the voltage values ​​read out four times, the brightness and darkness information of the image can be obtained, thus achieving a wide dynamic range.

[0144] Figure 6 In the image sensor shown, the first pixel and the second pixel each include a first OF transistor and a second OF transistor, and the gates of the first OF transistor and the second OF transistor are respectively connected to the OFG signal. During the reset phase, the OFG signal controls the first OF transistor and the second OF transistor to turn on, thereby resetting the first PD and the second PD, without needing to turn on the first TX transistor via the TG signal to reset the first PD, or turn on the second TX transistor to reset the second PD. When the first OF transistor is on, the charge in the first PD will overflow through the first OF transistor; when the first OF transistor is off, the charge in the first PD can be stored in the first PD for exposure, and the same applies to the second pixel. Furthermore, when the image sensor includes OF transistors, it is also convenient to control the exposure time of the image sensor, which can be the time interval between the falling edge of the OFG-read signal and the rising edge of the TG signal.

[0145] Furthermore, such as Figure 12 The operation timing diagram shown is relative to Figures 8 to 11 The timing diagram shown shows that the falling edge of the OFG-read signal can be brought closer to the rising edge of the TG signal to shorten the exposure time of the image sensor, for example, to a door opening speed of a few microseconds. The shortest exposure time of the image sensor is no longer limited by the rolling shutter, enabling the image sensor to be used for shooting fast-moving objects.

[0146] In the embodiments described above, two pixels are connected by a switching transistor, forming a combined capacitor when the switching transistor is turned on. In the embodiments provided in this application, more pixels may be connected by switching transistors. For example, in a pixel array consisting of four pixels, each pixel is connected by a switching transistor.

[0147] As an example, such as Figure 13 As shown, pixels PX1, PX2, PX3, and PX4 form a 2×2 pixel array. The structures of pixels PX1 to PX4 can be identical, for example, they can be the same as those described above. Figure 6 The structures of pixels PX1 and PX2 shown are the same.

[0148] Pixels PX1 and PX2 can be connected via a switching transistor FDC-1. The first terminal of FDC-1 can be connected between the TX transistor and the FD transistor in pixel PX1, and the second terminal of FDC-1 can be connected between the TX transistor and the FD transistor in pixel PX2. Similarly, pixels PX1 and PX3 can be connected via a switching transistor FDC-2. The first terminal of FDC-2 can be connected between the TX transistor and the FD transistor in pixel PX1, and the second terminal of FDC-2 can be connected between the TX transistor and the FD transistor in pixel PX3. Pixels PX2 and PX4 can be connected via a switching transistor FDC-3. The first terminal of FDC-3 can be connected between the TX transistor and the FD transistor in pixel PX2, and the second terminal of FDC-3 can be connected between the TX transistor and the FD transistor in pixel PX4. Pixels PX3 and PX4 can be connected by a switching transistor FDC-4. The first terminal of the switching transistor FDC-4 can be connected between the TX transistor and FD in pixel PX3, and the second terminal of the switching transistor FDC-4 can be connected between the TX transistor and FD in pixel PX4.

[0149] In this example, pixel PX3 can be referred to as the third pixel, and pixel PX4 can be referred to as the fourth pixel. Switching transistor FDC-2 can be referred to as the second switching transistor, switching transistor FDC-3 can be referred to as the third switching transistor, and switching transistor FDC-4 can be referred to as the fourth switching transistor.

[0150] In this example, Figure 8 At time t5 in the operation timing shown, or at... Figure 11At time t7 in the shown timing sequence, the switching transistors FDC-1 to FDC-4 can all be kept in the ON state. The FDs in these four pixels and the circuits containing the switching transistors FDC-1 to FDC-4 together form a combined capacitor, storing the charge overflowing from the PDs of the readout pixels in pixels PX1 to PX4. Alternatively, in Figure 8 The operation timing shown is at time t5 or at... Figure 11 At time t7 in the illustrated timing sequence, only some of the switching transistors FDC-1 to FDC-4 may be in the on state. For example, only switching transistors FDC-1 and FDC-2 may be on, while FDC-3 and FDC-4 may be off. In this example, the FD in pixels PX1 and PX2, together with switching transistors FDC-1 and FDC-2, form a combined capacitor. The charge accumulated by the PD of the readout pixels in pixels PX1 and PX2 can overflow into this combined capacitor.

[0151] As another example, such as Figure 14 As shown, pixels PX1 and PX3 can be connected via switching transistors FDC-1 and FDC-2, which can be connected in series. The first terminal of switching transistor FDC-1 can be connected between the TX transistor and the FD transistor in pixel PX1, and the second terminal of FDC-1 can be connected to the first terminal of switching transistor FDC-2. The second terminal of switching transistor FDC-2 can be connected between the TX transistor and the FD transistor in pixel PX3. Similarly, pixels PX2 and PX4 can be connected via switching transistors FDC-3 and FDC-4, which can be connected in series. The first terminal of switching transistor FDC-3 can be connected between the TX transistor and the FD transistor in pixel PX2, and the second terminal of FDC-3 can be connected to the first terminal of switching transistor FDC-4. The second terminal of switching transistor FDC-4 can be connected between the TX transistor and the FD transistor in pixel PX4. To enable the interconnection between pixels PX1 and PX2, and between pixels PX3 and PX4, via switching transistors, the second terminal of switching transistor FDC-1 can also be connected to the second terminal of switching transistor FDC-3 via a connecting line.

[0152] and Figure 13 The described example is similar, in Figure 8 At time t5 in the operation timing shown, or at... Figure 11 At time t7 in the operation timing shown, the switching transistors FDC-1 to FDC-4 can be fully or partially turned on to form a combined capacitor to receive the charge overflowed from the PD of the readout pixel.

[0153] As yet another example, such as Figure 15 As shown, the positions of the switching transistors FDC-1 to FDC-4 are similar to... Figure 14 The switching transistors FDC-1 to FDC-4 are positioned similarly. Furthermore, the image sensor may also include a switching transistor FDC-5. The first terminal of the switching transistor FDC-5 may be connected between the second terminal of the switching transistor FDC-1 and the first terminal of the switching transistor FDC-2. The second terminal of the switching transistor FDC-5 may be connected between the second terminal of the switching transistor FDC-3 and the first terminal of the switching transistor FDC-4.

[0154] Similar to the example described above, in Figure 8 At time t5 in the operation timing shown, or at... Figure 11 At time t7 in the operating timing sequence shown, the switching transistors FDC-1 to FDC-4 can be fully or partially turned on to form a combined capacitor to receive the charge overflowing from the PD.

[0155] Regarding the above Figures 13 to 15 The more switching transistors (FDCs) that are turned on, the larger the combined capacitance; conversely, the fewer the switching transistors (FDCs) that are turned on, the smaller the combined capacitance. For example, for Figure 13 When switching transistor FDC-1 is turned on, the combined capacitance formed is the size of the combined capacitance formed by the circuit where switching transistor FDC-1 is located, the FD in pixel PX1, and the FD in pixel PX2; when switching transistors FDC-1 and FDC-2 are turned on, the combined capacitance formed is the size of the combined capacitance formed by the circuit where switching transistor FDC-1 is located, the circuit where switching transistor FDC-2 is located, the FD in pixel PX1, and the FD in pixel PX2. For Figure 14 When the switching transistor FDC-1 is turned on, the combined capacitance formed is the capacitance formed by the circuit containing the switching transistor FDC-1 and the capacitance formed by the FD in the PX1 pixel. For Figure 15 When the switching transistor FDC-1 is turned on, the combined capacitance formed is the capacitance formed by the circuit where the switching transistor FDC-1 is located and the capacitance formed by the FD in the PX1 pixel.

[0156] The above Figures 13 to 15 In the described example, two pixels are interconnected via a switching transistor (FDC) to form a combined capacitance, thereby achieving a wide dynamic range. The interconnection of pixels via the switching transistor (FDC) also enables the image sensor to switch conversion gain (CG).

[0157] When the switching transistors are turned on to form a combined capacitor, the larger the combined capacitor, the stronger its charge collection capability. In this case, the combined capacitor needs to collect more charge to read out a high signal strength. However, in low-brightness scenarios, the PD generates less charge, and when the TX transistor is turned on, no charge overflows into the combined capacitor, or the amount of overflowing charge is small. In this case, if the capacitance value of the combined capacitor is large, the readout signal strength is low. Therefore, in low-brightness scenarios, the number of switched transistors (FDC) that are turned on can be smaller, for example, using... Figure 13 For example, in low-brightness scenes, the PX1 pixel is a readout pixel, and among the four switching transistors FDC, only switching transistor FDC-1 can be turned on.

[0158] Furthermore, in low-brightness scenarios, fewer switching transistors can be turned on to achieve high conversion gain (HCG) and provide higher signal amplification, thus reducing noise. In high-brightness scenarios, more switching transistors can be turned on, such as all of them, to achieve low conversion gain (LCG), preventing signal saturation and expanding the dynamic range.

[0159] It should be understood that the above Figures 13 to 15 This example illustrates how connecting pixel arrays via switching transistors (FDCs) to achieve combined capacitance and thus a wide dynamic range should not be construed as limiting the number of pixels interconnected via FDCs in an image sensor. For instance, Figure 16 This is a schematic structural diagram of the image sensor provided in the embodiments of this application, such as... Figure 16 As shown in (a), in this image sensor, adjacent pixels can be interconnected via switching transistors (FDCs), and multiple FDCs can be turned on or off according to the position of the readout pixel. For example... Figure 16 As shown in (b) above, Figures 13 to 15 The structure shown is similar. In a pixel array, every 4 pixels form a pixel array. When a pixel in the pixel array is read out, the corresponding switching transistor FDC of the pixel array can be turned on.

[0160] The above Figures 4 to 16 In the image sensor described, each pixel has a dedicated FD. In the embodiments provided in this application, an FD can also be shared by multiple pixels.

[0161] As an example, such as Figure 17The image sensor diagram shown illustrates that one FD can be shared by four pixels, which can form a 2×2 pixel array. The four FDs can be interconnected through a switching transistor FDC.

[0162] In this example, the four pixels sharing a common FD can all be referred to as the first pixel, or they can also be referred to as the second pixel, the third pixel, and the fourth pixel, as described above. Figures 13 to 15 Similar to the structure shown, the first pixel, second pixel, third pixel and fourth pixel can also be interconnected by switching transistors.

[0163] As another example, such as Figure 18 The image sensor diagram shown shows that one FD can be shared by four pixels, which can form a 2×2 pixel array. The 16 FDs can be interconnected through switching transistors FDC.

[0164] and Figure 17 Similarly, in the example described, each pixel in a pixel array sharing a single FD can be referred to as the first pixel, or the second pixel, the third pixel, the fourth pixel.

[0165] It should be understood that an FD can also be shared by other numbers of pixels. For example, an FD can be shared by 2×1 pixels, or by pixel arrays with multiple pixel numbers such as 2×2, 3×3, 4×4, etc. This application does not limit this.

[0166] Sharing a single FD (fingerprint detector) for multiple pixels simplifies the pixel structure, enables smaller pixels, and reduces the chip area occupied by each pixel.

[0167] See Figure 19 In some embodiments of the image sensor shown, the first pixel may further include a first switching transistor, the first terminal of which may be connected between the first transmission transistor and the first floating diffusion region, and the second terminal of which may be connected to the first terminal of the first switching transistor. Similarly, the second pixel may further include a second switching transistor, the first terminal of which may be connected between the second transmission transistor and the second floating diffusion region, and the second terminal of which may be connected to the second terminal of the first switching transistor.

[0168] The first switching transistor can also be called a first conversion gain switch (CGS) transistor, or a gain selection transistor. Similarly, the second switching transistor can also be called a second conversion gain switch transistor. The third terminals of the first and second switching transistors can be connected to a dual conversion gain (DCG) signal to switch the conversion gain mode of the image sensor.

[0169] The gates of the first switching transistor and the second switching transistor can be connected to a dual floating gate (DFG) signal.

[0170] Figure 19 In the image sensor shown, each pixel includes an FD. Similar to the example described above, multiple pixels can also share an FD in this image sensor. In this example, multiple pixels can also share a CGS transistor.

[0171] like Figure 20 The image sensor shown can have four pixels in a row sharing a single FD (Focus Function), and these four pixels can also share other pixel structures, such as a reset module and a readout module. The reset module can include the RST transistor shown in the figure, and the readout module can include the SEL transistor shown in the figure. Each of the four pixels can include a TX transistor, which can individually control the overflow charge flow of the PD (Power Discharge) in that pixel. The CGS transistor can be connected between the shared FD of the four pixels and the TX transistor of each pixel.

[0172] Sixteen pixels can be connected by a switching transistor FDC, which can be connected, for example, between the second and third rows of pixels shown in the figure.

[0173] In this example, pixels located in the same row and connected to the same CGS transistor can be referred to as the first pixel, or as the second, third, or fourth pixel.

[0174] It should be understood that Figure 19 and Figure 20 The gate of the CGS transistor shown is connected to the DCG signal. The gate of the CGS transistor can also be connected to the FDCG signal. When the gate of the CGS transistor is connected to the FDCG signal, it can also be called a switching transistor. It should be understood that in Figure 20, four pixels located in the same pixel row share the CGS transistor. In actual products, these four transistors may not be located in the same pixel row; for example, they could be a 2×2 pixel array.

[0175] Figure 21 and Figure 22 This is a simplified schematic diagram of an image sensor that includes CGS transistors.

[0176] like Figure 21 As shown, in this image sensor, the dual floating drain (DFD) can be a structure formed by the connection between the CGS transistor and the FDC switching transistor. One FD can be shared by four pixels, and two FDs can be connected to the same DFD. Adjacent DFDs can be connected through the FDC switching transistor; for example, DFDs located in the same pixel column can be connected through the FDC switching transistor.

[0177] like Figure 22 As shown, with Figure 21 Similar to the image sensor shown, one FD can be shared by four pixels, and two FDs can be connected to the same DFD. Multiple DFDs can be interconnected via switching transistors (FDCs), for example, DFDs located in the same pixel row can also be interconnected via switching transistors (FDCs).

[0178] To facilitate the use of this image sensor in global shutter scenarios, the image sensor can be a dual transmission grid architecture, and the image sensor can include a memory node (MEM). The global shutter refers to the simultaneous exposure and readout of all pixels in the image sensor.

[0179] For the first pixel, the first pixel may further include a third transmission transistor and a first memory node. The third transmission transistor may be connected in series with the first transmission transistor, and one end of the first memory node may be connected between the first transmission transistor and the third transmission transistor. For the second pixel, the second pixel may further include a fourth transmission transistor and a second memory node. The fourth transmission transistor may be connected in series with the second transmission transistor, and one end of the second memory node may be connected between the second transmission transistor and the fourth transmission transistor.

[0180] The memory node can be a capacitor, a doped semiconductor structure, or other storage structure. It can be used to store the overflow charge of the PD. If the memory node is a capacitor, it can consist of one or more capacitors.

[0181] See Figure 23In the structure shown, the first pixel can be a PX1 pixel, the transistor TX1 in the PX1 pixel can be a first transmission transistor, the transistor TX2 in the PX1 pixel can be a third transmission transistor, the second pixel can be a PX2 pixel, the transistor TX1 in the PX2 pixel can be a second transmission transistor, and the transistor TX2 in the PX2 pixel can be a fourth transmission transistor.

[0182] for Figure 23 The pixel structure shown, taking the PX1 pixel as an example, involves the following steps: After exposure, transistor TX1 turns on, transferring charge from the PD to the memory node. While the charge is being transferred, the PD can begin a new exposure cycle. When data needs to be read out, transistor TG2 turns on, transferring charge from the memory node to the FD. This ensures that the charge is converted into a voltage signal and read out at the appropriate time.

[0183] This pixel structure includes dual transfer gates, enabling simultaneous exposure and readout of all pixels. This avoids the "rolling shutter effect" and other motion artifacts common with rolling shutters. For example, in scenes with fast-moving subjects, this global shutter architecture can mitigate the tilting, stretching, or compression of moving objects in the captured image. The presence of memory nodes allows photodiodes to begin the next exposure immediately after completing one, while the previous charge is safely stored in the MEM (Mean Interaction Time) for readout, improving the overall efficiency of the image sensor. By incorporating memory nodes, the full-well capacity can also be increased, thereby expanding the dynamic range.

[0184] This dual-transmission-gate and memory-node structure can also be applied to the shared FD scenario described above.

[0185] For example, Figure 24 Here is a simplified diagram of the image sensor structure under this shared architecture, as follows: Figure 24 As shown, in this image sensor, the connections between structures such as the FD, the switching transistor FDC, and the CGS transistor can be... Figure 21 Similar to the described example, further, in this image sensor, a memory node can be connected to each pixel, so that the image sensor can be applied to a global shutter.

[0186] For example, Figure 25 This is a schematic diagram of the pixel structure of the image sensor under this shared architecture, as shown below. Figure 25 As shown, the connection structure of this image sensor can be connected to... Figure 20 Similar to the structure shown, further, in this image sensor, each pixel can include two transmission transistors and a memory node, and one end of the memory node can be connected between the two transmission transistors.

[0187] The image sensor provided in this application can also be used in applications such as phase detection autofocus (PDAF), by dividing each pixel or some pixels into two independent photodiodes to capture light information from different angles. This application does not limit the application scenarios of this image sensor.

[0188] This application also provides a solid-state imaging device, which may include any of the image sensors described in the above embodiments. Figure 26 This is a schematic diagram of the structure of a solid-state imaging device provided in an embodiment of this application.

[0189] like Figure 26 As shown, the solid-state imaging device may include a lens, which may include one or more lens groups, each lens group including one or more lenses. The lens can guide light from the subject onto the surface of an image sensor, forming an image on the surface of the image sensor. The lens can also perform autofocus movement in a direction parallel to the optical axis, or image stabilization movement in a plane perpendicular to the optical axis, under the action of a driving component.

[0190] The solid-state imaging device may also include a shutter, which may be positioned between the lens and the image sensor. Under the control of the control circuit, the shutter may also control the duration of light exposure on the image sensor, i.e., the exposure time of the image sensor.

[0191] The image sensor can receive light passing through the lens and shutter. During the exposure time, the image sensor can generate signal charge based on the received light, and convert the signal charge into a digital signal according to the drive signal provided by the drive circuit, which is then transmitted as raw data to the image signal processing (ISP) circuit.

[0192] The solid-state imaging device may also include the aforementioned control circuit, which can output a drive signal that can be used to drive shutter operation and image sensor operation.

[0193] The solid-state imaging device may also include an image signal processing circuit that can perform various types of image signal processing on the raw data output by the image sensor. The image data obtained by the image signal processing circuit can be provided to a memory for storage or to a display for display.

[0194] This application also provides an electronic device that may include the solid-state imaging device. This electronic device may be a mobile phone, tablet, laptop, television or other large-screen device with shooting and image processing capabilities, or a wearable device; this application does not limit its scope to these.

[0195] This application embodiment also provides a control device, which may include a processor and a memory. The memory may be used to store program code, and the processor may be used to execute the program code to cause the control device to perform the above-described actions. Figures 8 to 12 The described operating timing sequence of the image sensor.

[0196] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An image sensor, characterized in that, include: The first pixel includes a first photodiode and a first floating diffusion region, wherein the first floating diffusion region is connected in series with the first photodiode. The second pixel includes a second photodiode and a second floating diffusion region, wherein the second floating diffusion region is connected in series with the second photodiode. A first switching transistor, wherein a first terminal of the first switching transistor is connected between the first floating diffusion region and the first photodiode, and a second terminal of the first switching transistor is connected between the second floating diffusion region and the second photodiode; The first pixel further includes a first overflow transistor, a first terminal of which is connected to the first photodiode, and a second terminal of which is connected to a power supply voltage; and / or, The second pixel also includes a second overflow transistor, the first terminal of which is connected to the second photodiode, and the second terminal of which is connected to the power supply voltage; The image sensor further includes a third pixel and a fourth pixel, and also includes a second switching transistor, a third switching transistor, and a fourth switching transistor. The second switching transistor is connected between the first pixel and the third pixel, the third switching transistor is connected between the second pixel and the fourth pixel, and the fourth switching transistor is connected between the third pixel and the fourth pixel.

2. The image sensor according to claim 1, characterized in that, The first floating diffusion region and the second floating diffusion region are floating diffusion regions arranged adjacent to each other.

3. The image sensor according to claim 1, characterized in that, The first switching transistor and the second switching transistor are connected in series; and / or, The third switching transistor is connected in series with the fourth switching transistor.

4. The image sensor according to claim 3, characterized in that, At least two of the gates of the first switching transistor, the second switching transistor, the third switching transistor, or the fourth switching transistor are connected to the same gate signal.

5. The image sensor according to claim 1, characterized in that, Multiple first pixels share a single first floating diffusion region; and / or, Multiple second pixels share a second floating diffusion region.

6. The image sensor according to claim 5, characterized in that, Multiple first pixels sharing the first floating diffusion region are jointly connected to the first switching transistor; and / or, Multiple second pixels sharing the second floating diffusion region are connected together to the first switching transistor.

7. The image sensor according to claim 6, characterized in that, The plurality of first pixels connected to the first switching transistor are of the same color; and / or, The multiple second pixels connected to the first switching transistor have the same color.

8. The image sensor according to any one of claims 1 to 7, characterized in that, The first pixel further includes a first transmission transistor, a second transmission transistor, and a first memory node, wherein the first transmission transistor and the second transmission transistor are connected in series, and one end of the first memory node is connected between the first transmission transistor and the second transmission transistor; and / or, The second pixel further includes a third transmission transistor, a fourth transmission transistor, and a second memory node, wherein the third transmission transistor and the fourth transmission transistor are connected in series, and one end of the second memory node is connected between the third transmission transistor and the fourth transmission transistor.

9. A solid-state imaging device, characterized in that, The image sensor included in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the solid-state imaging device as described in claim 9.

11. A control method for an image sensor, characterized in that, The method, applied to the image sensor of any one of claims 1 to 8, comprises: When the first pixel is a readout pixel, at the first moment, the first voltage value is read out. The first voltage value is the voltage value of the first floating diffusion region after the first reset process. The first switching transistor is in the off state at the first moment. At the second moment, the second voltage value is read out. The second voltage value is the voltage value after the first floating diffusion region receives the overflow charge of the first photodiode. The first switching transistor is in the off state at the second moment. At the third moment, the third voltage value is read out. The third voltage value is the voltage value of the first floating diffusion region after the second reset process. The first switching transistor is in the on state at the third moment. At the fourth moment, the fourth voltage value is read out. The first switching transistor is in the open state at the fourth moment. The circuit where the first switching transistor is located and the first floating diffusion region form a combined capacitor at the fourth moment. The fourth voltage value is the voltage value after the combined capacitor receives the overflow charge of the first photodiode.

12. The method according to claim 11, characterized in that, When the second pixel and the first pixel are located in different pixel rows and the second pixel and the first pixel have different colors, at the fourth time, the first overflow transistor is turned off and the second overflow transistor is turned on.

13. The method according to claim 11, characterized in that, The third moment is before the first moment.

14. The method according to any one of claims 11 to 13, characterized in that, At the fourth moment, at least some of the second, third, and fourth switching transistors are in the on state.

Images