An instrument landing system signal processing method and system based on FPGA

By using FPGA-based signal processing methods, the problems of high complexity of traditional ILS circuits and low accuracy of DDM measurement are solved, and high-precision modulation difference calculation is achieved, which improves the navigation reliability and safety during aircraft approach and landing phases and simplifies system design.

CN120722792BActive Publication Date: 2026-11-06HWA CREATE CORP
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Patent Information

Application Number
CN202510816790.9
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-06-18
Publication Date
2026-11-06
Estimated Expiration
2045-06-18

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Abstract

The application relates to the technical field of air transportation, in particular to an instrument landing system signal processing method and system based on FPGA, which comprises the following steps: receiving a heading path signal and a glide path signal of an instrument landing system, and performing radio frequency processing on the signals respectively to obtain intermediate frequency signals; then performing analog-digital conversion on the intermediate frequency signals to obtain corresponding digital signals, and sequentially performing rectification processing, multi-stage extraction filtering processing, band-pass filtering processing, amplitude detection processing and modulation degree difference calculation on the digital signals to obtain a modulation degree difference; finally, judging the deviation state of an airplane relative to a runway center line and a glide path center line according to the modulation degree difference. The application improves the measurement precision of the modulation degree difference, simplifies the circuit complexity, effectively reduces the navigation error of the airplane in the approach and landing stage, and significantly improves the flight safety.
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Description

Technical Field

[0001] This invention relates to the field of aviation transportation technology, and specifically to a signal processing method and system for an instrument landing system based on FPGA. Background Technology

[0002] With the vigorous development of civil aviation, air transport has become one of the main modes of transportation. However, among all phases of flight, flight safety issues are particularly prominent during the approach and landing phase.

[0003] The Instrument Landing System (ILS) is a crucial aviation radio navigation system ensuring safe flight during approach and landing in civil aviation, and its importance is self-evident. The ILS consists of a Localizer (LOC) and a Glide Slope (GS) beacon, which provide horizontal and vertical guidance to the aircraft, ensuring a safe landing along the correct flight path and glide slope. Traditional ILS signal processing methods primarily rely on analog circuits, which have numerous drawbacks. For example, analog circuits are complex, increasing hardware costs and maintenance difficulty, and raising the probability of system failure. Furthermore, traditional analog methods have low accuracy when measuring modulation difference (DDM), making it difficult to meet the high-precision signal processing requirements of modern aviation navigation.

[0004] In the above scheme, the traditional Instrument Landing System (ILS) uses analog circuits to implement signal processing, which has the disadvantages of high circuit complexity and low modulation difference (DDM) measurement accuracy, resulting in insufficient navigation reliability during the aircraft approach and landing phases. Summary of the Invention

[0005] In view of this, the present invention provides an FPGA-based instrument landing system signal processing method and system to solve the problem that traditional instrument landing systems use analog circuits to implement signal processing, which has the disadvantages of high circuit complexity and low accuracy of modulation difference measurement, resulting in insufficient navigation reliability during aircraft approach and landing phases.

[0006] In a first aspect, the present invention provides a signal processing method for an instrument landing system based on an FPGA, the method comprising:

[0007] Receives the localizer and glide slope signals from the instrument landing system;

[0008] The localizer signal and the glide slope signal are subjected to radio frequency processing to obtain a first intermediate frequency signal corresponding to the localizer signal and a second intermediate frequency signal corresponding to the glide slope signal.

[0009] The first intermediate frequency signal and the second intermediate frequency signal are respectively converted from analog to digital to obtain the first digital signal corresponding to the heading signal and the second digital signal corresponding to the glide slope signal;

[0010] The first digital signal and the second digital signal are respectively subjected to rectification processing, multi-stage decimation filtering processing, bandpass filtering processing, amplitude detection processing and modulation difference calculation to obtain the first modulation difference corresponding to the heading signal and the second modulation difference corresponding to the glide slope signal.

[0011] Based on the first modulation difference and the second modulation difference, determine the deviation of the aircraft from the runway centerline and the glide slope centerline.

[0012] In one optional implementation, receiving the localizer and glide slope signals from the instrument landing system includes:

[0013] It receives the localizer signal in the first frequency range from the localizer beacon and the glide slope signal in the second frequency range from the glide slope beacon.

[0014] In one optional implementation, the step of performing radio frequency processing on the localizer signal and the glide slope signal respectively to obtain a first intermediate frequency signal corresponding to the localizer signal and a second intermediate frequency signal corresponding to the glide slope signal includes:

[0015] The localizer signal and the glide slope signal are sequentially amplified, mixed, and filtered to obtain a first intermediate frequency signal corresponding to the localizer signal and a second intermediate frequency signal corresponding to the glide slope signal; the center frequencies of the first intermediate frequency signal and the second intermediate frequency signal are equal.

[0016] In one optional implementation, the rectification process includes:

[0017] The sign of the corresponding digital signal is determined based on the sign bit of the corresponding digital signal. If the corresponding digital signal is positive, the original value of the corresponding digital signal is retained. If the corresponding digital signal is negative, a two's complement conversion operation is performed on the corresponding digital signal. The corresponding digital signal includes the first digital signal and the second digital signal.

[0018] In one optional implementation, the multi-stage decimation filtering process includes:

[0019] The first-stage decimation filter is performed on the corresponding digital signal after rectification, reducing the signal sampling rate of the corresponding digital signal after rectification from the first sampling rate to the second sampling rate.

[0020] The corresponding digital signal after the first-stage decimation filtering is subjected to a second-stage decimation filtering, which reduces the signal sampling rate of the corresponding digital signal after the first-stage decimation filtering from the second sampling rate to the third sampling rate.

[0021] The corresponding digital signal after the second-stage decimation filtering is subjected to a third-stage decimation filtering, which reduces the signal sampling rate of the corresponding digital signal after the second-stage decimation filtering from the third sampling rate to the fourth sampling rate; each decimation filtering stage uses a CIC decimation filter, and the number of cascaded CIC decimation filters is equal.

[0022] In one optional implementation, the bandpass filtering process includes:

[0023] The corresponding digital signal after the third-stage decimation filter is subjected to an FIR filter to extract the first frequency component of the first passband frequency range and the second frequency component of the second passband frequency range; the first passband frequency range is smaller than the second passband frequency range, and the frequency value of the first frequency component is smaller than the frequency value of the second frequency component.

[0024] In one optional implementation, the amplitude detection process includes:

[0025] The first frequency component and the second frequency component of the corresponding digital signal after bandpass filtering are averaged to obtain the first amplitude average value corresponding to the first frequency component and the second amplitude average value corresponding to the second frequency component.

[0026] In one optional implementation, the modulation difference of the first digital signal after amplitude detection processing is calculated using the following formula:

[0027] DDM1=(m190-m1150) / (m190+m1150)*0.4;

[0028] The modulation difference of the second digital signal after amplitude detection processing is calculated using the following formula:

[0029] DDM2=(m290-m2150) / (m290+m2150)*0.8;

[0030] Wherein, DDM1 represents the first modulation difference, DDM2 represents the second modulation difference, m190 represents the first average amplitude corresponding to the first digital signal after amplitude detection processing, m1150 represents the second average amplitude corresponding to the first digital signal after amplitude detection processing, m290 represents the first average amplitude corresponding to the second digital signal after amplitude detection processing, and m2150 represents the second average amplitude corresponding to the second digital signal after amplitude detection processing.

[0031] In one optional implementation, determining the aircraft's deviation from the runway centerline and glide slope centerline based on the first modulation difference and the second modulation difference includes:

[0032] If the first modulation difference is within a preset first threshold range and the second modulation difference is within a preset second threshold range, then the aircraft is determined to be located on the runway centerline and the glide slope centerline.

[0033] If the first modulation difference is greater than the maximum value of the first threshold range, the aircraft is determined to have deviated to the left of the runway centerline; if the second modulation difference is greater than the maximum value of the second threshold range, the aircraft is determined to have deviated to the upper side of the glide slope centerline.

[0034] If the first modulation difference is less than the minimum value of the first threshold range, the aircraft is determined to have deviated to the right of the runway centerline; if the second modulation difference is less than the minimum value of the second threshold range, the aircraft is determined to have deviated to the lower side of the glide slope centerline.

[0035] Secondly, the present invention provides an FPGA-based instrument landing system signal processing system, the system comprising an antenna, a radio frequency module, an ADC sampling module, an FPGA signal processing module, and a main control module;

[0036] The antenna is used to receive the localizer and glide slope signals from the instrument landing system.

[0037] The radio frequency module is used to perform radio frequency processing on the localizer signal and the glide slope signal respectively to obtain a first intermediate frequency signal corresponding to the localizer signal and a second intermediate frequency signal corresponding to the glide slope signal;

[0038] The ADC sampling module is used to perform analog-to-digital conversion on the first intermediate frequency signal and the second intermediate frequency signal respectively to obtain a first digital signal corresponding to the heading signal and a second digital signal corresponding to the glide slope signal.

[0039] The FPGA signal processing module is used to sequentially perform rectification processing, multi-stage decimation filtering processing, bandpass filtering processing, amplitude detection processing, and modulation difference calculation on the first digital signal and the second digital signal, respectively, to obtain the first modulation difference corresponding to the heading signal and the second modulation difference corresponding to the glide slope signal.

[0040] The main control module is used to control the signal transmission between the modules in the system, and to determine the deviation of the aircraft from the runway centerline and the glide slope centerline based on the first modulation difference and the second modulation difference.

[0041] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform a signal processing method for an instrument landing system based on FPGA as described in the first aspect or any corresponding embodiment.

[0042] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute a signal processing method for an instrument landing system based on an FPGA as described in the first aspect or any corresponding embodiment thereof.

[0043] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute an FPGA-based instrument landing system signal processing method according to the first aspect or any corresponding embodiment described above.

[0044] The technical solution provided by this invention may include the following beneficial effects:

[0045] This invention employs multi-stage decimation filtering and bandpass filtering, combined with amplitude mean calculation, to improve the accuracy of modulation difference calculation to ±0.001, effectively reducing navigation errors during aircraft approach and landing phases and significantly improving flight safety. Furthermore, based on the parallel processing capabilities of the FPGA signal processing module, the multi-stage decimation filtering significantly shortens signal processing link latency. The output frequency of the modulation difference can be flexibly configured to meet the real-time requirements of dynamic flight attitude adjustments. Secondly, this invention achieves a high degree of unification in the processing of localizer and glide slope signals, simplifying the system architecture, reducing development and maintenance difficulty and costs, and improving system reliability and scalability. Attached Figure Description

[0046] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the directional radiation field pattern according to an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of the glide radiation field pattern according to an embodiment of the present invention;

[0049] Figure 3This is a schematic diagram of the structure of an instrument landing system signal processing system based on FPGA according to an embodiment of the present invention;

[0050] Figure 4 This is a flowchart of a signal processing method for an instrument landing system based on FPGA according to an embodiment of the present invention;

[0051] Figure 5 This is a flowchart of another FPGA-based instrument landing system signal processing method according to an embodiment of the present invention;

[0052] Figure 6 This is a schematic diagram of the algorithm flow of the FPGA signal processing module according to an embodiment of the present invention;

[0053] Figure 7 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] It should be noted that the Instrument Landing System (ILS) consists of the Localizer (LOC) and the Glide Slope Beacon (GS). It guides the aircraft to land using signals emitted from the airport. These two signals correspond to two subsystems: one provides horizontal guidance (heading), and the other provides vertical guidance (glide slope guidance). The ILS receiver performs in-depth analysis of these two signals from the airport and adjusts the aircraft's landing attitude and speed through the autopilot system, providing flight path deviation guidance to the instruments and flight control system during the approach and landing phases. The signal providing horizontal guidance is provided by the localizer installed at the far end of the runway. The localizer emits two signals, 90Hz and 150Hz, with the beams positioned slightly to the left and right of the runway centerline, respectively. By analyzing the intensity difference between the two signal beams, the system determines whether the aircraft is on the extended line of the runway centerline. In the cockpit, the flight instruments also display the aircraft's position relative to the runway centerline.

[0056] The directional launcher is positioned along the extended centerline of the runway in the landing direction. It emits two identical beams that overlap on one side along the runway centerline. (See [link to relevant documentation]). Figure 1The diagram shows the directional radiation pattern. The beam to the left of the runway centerline uses 90Hz AM modulation, and the beam to the right uses 150Hz AM modulation, both with an amplitude modulation of 20%. The difference in modulation depth (DDM) varies depending on the relative field strength of the two beams. At the runway centerline, the DDM is zero; it gradually increases with increasing angle of deviation from the centerline. To the left of the runway centerline, the 90Hz audio component is greater than the 150Hz audio component, and vice versa to the right. Within a range of ±4° to ±6° centered on the runway centerline, the difference changes linearly with angle.

[0057] When the aircraft approaches the runway, the onboard equipment receives the signal transmitted by the ground station, detects the 90Hz and 150Hz signal components, compares them, and outputs a digital signal proportional to the modulation difference (that is, proportional to the angle of deviation from the runway center) to the deviation and warning indicators and other instruments.

[0058] The glide slope launcher is located on one side near the runway entrance. It emits two identical beams at a certain elevation angle, one side of which overlaps. Please refer to [link to relevant documentation]. Figure 2 The diagram shows the glide slope radiation pattern, with beams distributed vertically. The upper beam carrier uses 90Hz audio amplitude modulation (AAM), and the lower beam carrier uses 150Hz audio AAM, both with an amplitude modulation of 40%. The difference in amplitude modulation (DDM) between the two audio frequencies varies according to the field strength of the upper and lower beams. At the center of the glide slope, this difference is zero. Within a certain angular range on both sides of the glide slope, this difference gradually increases with the angle of deviation from the glide slope. The glide slope is a straight line located in the vertical plane of the runway centerline, with a horizontal elevation angle of approximately 2° to 4°.

[0059] When the aircraft approaches, the onboard equipment receives the signal transmitted by the glide slope, detects the 90Hz and 150Hz audio components, compares them, and outputs a digital or analog signal proportional to the difference in modulation amplitude of the two audio frequencies (that is, proportional to the angle of deviation from the glide slope) to the glide deviation and warning indicator and other instruments.

[0060] When the aircraft is to the left of the runway centerline, the heading deviation indicator needle deflects to the right, and vice versa. When the aircraft is above the glide slope centerline, the glide deviation indicator needle deflects downward, and vice versa. When the aircraft is on both the runway centerline (localizer) and the glide slope centerline, both the heading deviation and glide deviation indicators return to zero simultaneously. In case of equipment failure or unreliable signals, the corresponding heading and glide slope warnings will be displayed; otherwise, no warning indication will be displayed. By following the instructions of the indicators, the pilot can safely approach and land on the optimal flight path.

[0061] This embodiment provides a signal processing system for an instrument landing system based on an FPGA. Figure 3 This is a schematic diagram of the structure of an FPGA-based instrument landing system signal processing system according to an embodiment of the present invention, as shown below. Figure 3 As shown, the system includes an antenna, a radio frequency module, an ADC sampling module, an FPGA signal processing module, and a main control module;

[0062] This antenna is used to receive the localizer and glide slope signals from the instrument landing system.

[0063] The radio frequency module is used to perform radio frequency processing on the localizer signal and the glide slope signal respectively to obtain a first intermediate frequency signal corresponding to the localizer signal and a second intermediate frequency signal corresponding to the glide slope signal.

[0064] The ADC sampling module is used to perform analog-to-digital conversion on the first intermediate frequency signal and the second intermediate frequency signal respectively to obtain the first digital signal corresponding to the heading signal and the second digital signal corresponding to the glide slope signal.

[0065] The FPGA signal processing module is used to sequentially perform rectification processing, multi-stage decimation filtering processing, bandpass filtering processing, amplitude detection processing, and modulation difference calculation on the first digital signal and the second digital signal, respectively, to obtain the first modulation difference corresponding to the heading signal and the second modulation difference corresponding to the glide slope signal.

[0066] The main control module is used to control the signal transmission between the modules in the system, and to determine the deviation of the aircraft from the runway centerline and the glide slope centerline based on the first modulation difference and the second modulation difference.

[0067] Furthermore, the antenna is used to receive the localizer (LOC) and glide slope (GS) signals from the instrument landing system.

[0068] The radio frequency (RF) module is used to perform RF processing on the LOC signal and GS signal respectively, including amplification, mixing and filtering, and converts the signal into a first intermediate frequency (IF) signal (corresponding to the LOC signal) and a second IF signal (corresponding to the GS signal) with a center frequency of 21.4MHz.

[0069] The ADC sampling module is used to perform analog-to-digital conversion on the first and second intermediate frequency signals, respectively. An ADC chip module with a 65MHz sampling rate is used to sample the 21.4MHz intermediate frequency signal to obtain the first digital signal (21.4MHz@65Msps) corresponding to the localizer signal and the second digital signal (21.4MHz@65Msps) corresponding to the glide slope signal.

[0070] The FPGA signal processing module is used to perform the following processing on the first digital signal and the second digital signal respectively:

[0071] Rectification: The sign of the data is determined by the sign bit. Positive numbers retain their original value, while negative numbers are given their two's complement.

[0072] Multi-stage decimation filtering: A CIC decimation filter is used to perform multi-stage decimation filtering, gradually reducing the signal sampling rate to 1KHz.

[0073] Bandpass filtering: Use an FIR bandpass filter to extract the 90Hz and 150Hz signals respectively.

[0074] Amplitude detection processing: Calculate the average amplitude of the 90Hz and 150Hz signals.

[0075] Modulation difference calculation: Calculate the first modulation difference (DDM1) of the localizer signal and the second modulation difference (DDM2) of the glide slope signal according to the formula.

[0076] The main control module controls the signal transmission and timing between modules in the entire system, and determines the aircraft's deviation from the runway centerline and glide slope centerline based on DDM1 and DDM2.

[0077] The system achieves full-process processing from signal reception to aircraft deviation judgment through the division of labor and cooperation among its various modules, ensuring the accurate operation of the instrument landing system.

[0078] In summary, this embodiment employs multi-stage decimation filtering and bandpass filtering, combined with amplitude mean calculation, to improve the modulation difference calculation accuracy to ±0.001, effectively reducing navigation errors during aircraft approach and landing phases and significantly improving flight safety. Furthermore, this embodiment leverages the parallel processing capabilities of the FPGA signal processing module and employs multi-stage decimation filtering to substantially shorten signal processing link latency. The output frequency of the modulation difference can be flexibly configured to meet the real-time requirements of dynamic flight attitude adjustments. Secondly, this embodiment achieves a high degree of unification in the processing of localizer and glide slope signals, simplifying the system architecture, reducing development and maintenance difficulty and costs, and improving system reliability and scalability.

[0079] According to an embodiment of the present invention, an embodiment of an instrument landing system signal processing method based on FPGA is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0080] This embodiment provides a signal processing method for an instrument landing system based on FPGA, which can be applied to... Figure 3 The illustrated signal processing system for an instrument landing system based on an FPGA is shown. Figure 4 This is a flowchart of a signal processing method for an instrument landing system based on an FPGA according to an embodiment of the present invention, such as... Figure 4 As shown, the process includes the following steps:

[0081] Step S401: Receive the localizer signal and glide slope signal from the instrument landing system.

[0082] Furthermore, this embodiment utilizes an antenna to receive the localizer (LOC) and glide slope (GS) signals from the Instrument Landing System (ILS). The antenna serves as the interface between the system and external signal sources, responsible for capturing radio waves propagating in space and converting them into electrical signals for subsequent processing.

[0083] Step S402: Perform radio frequency processing on the localizer signal and the glide slope signal respectively to obtain the first intermediate frequency signal corresponding to the localizer signal and the second intermediate frequency signal corresponding to the glide slope signal.

[0084] Furthermore, this embodiment performs radio frequency (RF) processing on the captured localizer and glide slope signals. RF processing is the process of converting the received high-frequency signal into an intermediate frequency (IF) signal suitable for subsequent processing. This includes amplifying the signal to increase its power level, making it suitable for further processing; converting the signal frequency to a 21.4MHz IF through mixing for more efficient signal processing; and filtering to remove unwanted noise and interference components, ensuring signal purity. After processing, a first IF signal corresponding to the localizer signal and a second IF signal corresponding to the glide slope signal are obtained.

[0085] Step S403: Perform analog-to-digital conversion on the first intermediate frequency signal and the second intermediate frequency signal respectively to obtain the first digital signal corresponding to the heading signal and the second digital signal corresponding to the glide slope signal.

[0086] Furthermore, in this embodiment, the first intermediate frequency signal and the second intermediate frequency signal are converted from analog to digital. The ADC sampling module converts the analog signal into a digital signal, obtaining the first digital signal corresponding to the heading signal and the second digital signal corresponding to the glide slope signal, enabling the signals to undergo digital signal processing in the FPGA signal processing module.

[0087] Step S404: Rectification, multi-stage decimation filtering, bandpass filtering, amplitude detection, and modulation difference calculation are performed sequentially on the first digital signal and the second digital signal to obtain the first modulation difference corresponding to the heading signal and the second modulation difference corresponding to the glide slope signal.

[0088] Furthermore, in this embodiment, multiple processing steps are sequentially performed on the first digital signal and the second digital signal, including:

[0089] Rectification: Converting the negative half of a digital signal into the positive half, making the signal a unipolar signal, which is convenient for subsequent processing.

[0090] Multi-stage decimation filtering: The signal is decimated in multiple stages using a CIC decimation filter, which gradually reduces the sampling rate of the signal, reduces the amount of data, and retains the key information of the signal.

[0091] Bandpass filtering: FIR bandpass filters are used to extract the 90Hz and 150Hz frequency components from the signal. These specific frequency signals carry crucial information about the aircraft's position relative to the runway.

[0092] Amplitude detection processing: Calculate the average amplitude of the 90Hz and 150Hz frequency components to obtain the first and second average amplitude values, which reflect the relative intensity of the two frequency components.

[0093] Modulation difference calculation: Calculate the first modulation difference (DDM1) of the localizer signal and the second modulation difference (DDM2) of the glide slope signal according to the formula.

[0094] Step S405: Based on the first modulation difference and the second modulation difference, determine the deviation of the aircraft from the runway centerline and the glide slope centerline.

[0095] Furthermore, this embodiment determines the aircraft's deviation from the runway centerline and glide slope centerline based on the calculated first modulation difference (DDM1) of the localizer signal and the second modulation difference (DDM2) of the glide slope signal. If the first modulation difference (DDM1) is within a first threshold range, the aircraft is on the runway centerline; if the first modulation difference (DDM1) is greater than the maximum value of the first threshold range, the aircraft is to the left of the runway centerline; if the first modulation difference (DDM1) is less than the minimum value of the first threshold range, the aircraft is to the right of the runway centerline. If the second modulation difference (DDM2) is within a second threshold range, the aircraft is on the glide slope centerline; if the second modulation difference (DDM2) is greater than the maximum value of the second threshold range, the aircraft is above the glide slope centerline; if the second modulation difference (DDM2) is less than the minimum value of the second threshold range, the aircraft is below the glide slope centerline.

[0096] In summary, this embodiment employs multi-stage decimation filtering and bandpass filtering, combined with amplitude mean calculation, to improve the modulation difference calculation accuracy to ±0.001, effectively reducing navigation errors during aircraft approach and landing phases and significantly improving flight safety. Furthermore, this embodiment leverages the parallel processing capabilities of the FPGA signal processing module and employs multi-stage decimation filtering to substantially shorten signal processing link latency. The output frequency of the modulation difference can be flexibly configured to meet the real-time requirements of dynamic flight attitude adjustments. Secondly, this embodiment achieves a high degree of unification in the processing of localizer and glide slope signals, simplifying the system architecture, reducing development and maintenance difficulty and costs, and improving system reliability and scalability.

[0097] This embodiment provides a signal processing method for an instrument landing system based on FPGA, which can be applied to... Figure 3 The illustrated signal processing system for an instrument landing system based on an FPGA is shown. Figure 5 This is a flowchart of another FPGA-based instrument landing system signal processing method according to an embodiment of the present invention, such as... Figure 5 As shown, the process includes the following steps:

[0098] Step S501: Receive the localizer signal in the first frequency range emitted by the localizer beacon and the glide slope signal in the second frequency range emitted by the glide slope beacon; the number of channel points of the localizer signal and the number of channel points of the glide slope signal are equal, and the channels are assigned in pairs.

[0099] Furthermore, this embodiment receives localizer signals (within a specific first frequency range) from a localizer beacon and glide slope signals (within a specific second frequency range) from a glide slope beacon via an antenna. The localizer signal indicates the aircraft's lateral position, and the glide slope signal indicates its vertical position. Specifically, the number of channels for both signals is equal and they are paired, ensuring signal correspondence and coordination, providing a foundation for subsequent precise processing, and enabling the system to accurately match and analyze the navigation information carried by the two signals. The first frequency range is 108.1–111.95 MHz, with a total of 40 channels, used for horizontal guidance; the second frequency range is 329.15–335.10 MHz, with a total of 40 channels, used for vertical guidance. The channels for both are paired, as detailed in the table below:

[0100] Table 1

[0101]

[0102]

[0103] Step S502: Amplification, mixing and filtering are performed on the localizer signal and the glide slope signal respectively to obtain a first intermediate frequency signal corresponding to the localizer signal and a second intermediate frequency signal corresponding to the glide slope signal; the center frequencies of the first intermediate frequency signal and the second intermediate frequency signal are equal.

[0104] Furthermore, in this embodiment, the received localizer and glide slope signals are sequentially amplified, mixed, and filtered. Amplification enhances signal strength for subsequent stabilization; mixing converts the signal frequency to a uniform center frequency (the center frequencies of the first and second intermediate frequency signals are equal), facilitating standardization; filtering removes noise and interference, making the output first intermediate frequency signal (corresponding to the localizer) and second intermediate frequency signal (corresponding to the glide slope) cleaner and more stable, laying a good foundation for subsequent analog-to-digital conversion and digital processing. The center frequencies of the first and second intermediate frequency signals are 21.4 MHz.

[0105] Step S503: Perform analog-to-digital conversion on the first intermediate frequency signal and the second intermediate frequency signal respectively to obtain the first digital signal corresponding to the heading signal and the second digital signal corresponding to the glide slope signal.

[0106] Furthermore, this embodiment utilizes an ADC sampling module to convert the analog first and second intermediate frequency signals into digital signals. By sampling the 21.4MHz intermediate frequency signal at a 65MHz sampling rate, a first digital signal corresponding to the localizer signal and a second digital signal corresponding to the glide slope signal are generated, thus converting the signals from analog to a digital form suitable for processing by digital processing modules such as FPGAs.

[0107] Step S504: Rectification, multi-stage decimation filtering, bandpass filtering, amplitude detection, and modulation difference calculation are performed sequentially on the first digital signal and the second digital signal to obtain the first modulation difference corresponding to the heading signal and the second modulation difference corresponding to the glide slope signal.

[0108] In one alternative implementation, the rectification process includes:

[0109] The sign of the corresponding digital signal is determined by the sign bit of the corresponding digital signal. If the corresponding digital signal is positive, the original value of the corresponding digital signal is retained. If the corresponding digital signal is negative, a two's complement conversion operation is performed on the corresponding digital signal. The corresponding digital signal includes the first digital signal and the second digital signal.

[0110] Furthermore, this embodiment uses an FPGA signal processing module to decimate and filter the 21.4MHz intermediate frequency signal, calculates the modulation difference between the localizer and glide slope, and outputs it. The rectification processing in this embodiment targets the first and second digital signals, determining their sign based on the sign bit. If the sign is positive, the original value is retained; if negative, a two's complement conversion operation is performed (inverting the corresponding digital signal bit by bit and adding 1) to unify the first and second digital signals to positive values, eliminating the influence of signal polarity on subsequent processing and facilitating the analysis of signal amplitude characteristics.

[0111] In one optional implementation, the multi-stage decimation filtering process includes:

[0112] The first-stage decimation filter, which reduces the rectified digital signal by 65 times, decreases the signal sampling rate of the rectified digital signal from the first sampling rate to the second sampling rate.

[0113] The corresponding digital signal after the first-stage decimation filtering is subjected to a second-stage decimation filtering with a decimation factor of 100, and the signal sampling rate of the corresponding digital signal after the first-stage decimation filtering is reduced from the second sampling rate to the third sampling rate.

[0114] The digital signal after the second-stage decimation filtering is subjected to a third-stage decimation filtering with a 10x decimation, reducing the signal sampling rate of the digital signal after the second-stage decimation filtering from the third sampling rate to the fourth sampling rate; each decimation filtering stage uses a CIC decimation filter, and the number of cascaded CIC decimation filters (5 stages) is equal.

[0115] Furthermore, this embodiment employs a 5-stage CIC decimation filter to reduce the sampling rate in three stages. The first-stage decimation filter (65x decimation) reduces the rectified signal sampling rate from the first sampling rate (65MHz) to the second sampling rate (1MHz). The second stage (100x decimation) further reduces it to the third sampling rate (10kHz), and the third stage (10x decimation) further reduces it to the fourth sampling rate (1kHz). Each stage has an equal number of cascaded filters, reducing the amount of data while preserving key frequency components, improving processing efficiency, and reducing computational complexity.

[0116] In one alternative implementation, the bandpass filtering process includes:

[0117] The corresponding digital signal after the third-stage decimation filter is subjected to an FIR filter to extract the first frequency component of the first passband frequency range and the second frequency component of the second passband frequency range; the first passband frequency range is smaller than the second passband frequency range, and the frequency value of the first frequency component is smaller than the frequency value of the second frequency component.

[0118] Furthermore, this embodiment uses a 64th-order FIR filter to process the signal after the third-stage decimation filtering, extracting a first frequency component (90Hz) in the first passband frequency range (0.12π~0.24π) and a second frequency component (150Hz) in the second passband frequency range (0.24π~0.36π). The first passband frequency range is smaller than the second passband frequency range, and the first frequency component has a lower frequency value; both are key indicators for determining aircraft deviation.

[0119] In one optional implementation, the amplitude detection process includes:

[0120] The first frequency component and the second frequency component of the corresponding digital signal after bandpass filtering are averaged to obtain the first amplitude average value corresponding to the first frequency component and the second amplitude average value corresponding to the second frequency component.

[0121] Furthermore, in this embodiment, the first and second frequency components after bandpass filtering are averaged using 1024 data points to obtain the corresponding first amplitude average (e.g., m190, m290) and second amplitude average (e.g., m1150, m2150). By averaging, signal fluctuations are smoothed, accurately reflecting the amplitude characteristics of each frequency component, and providing reliable data for modulation calculation.

[0122] In one optional implementation, the modulation difference of the first digital signal after amplitude detection processing is calculated using the following formula:

[0123] DDM1=(m190-m1150) / (m190+m1150)*0.4;

[0124] The modulation difference of the second digital signal after amplitude detection processing is calculated using the following formula:

[0125] DDM2=(m290-m2150) / (m290+m2150)*0.8;

[0126] Wherein, DDM1 represents the first modulation difference, DDM2 represents the second modulation difference, m190 represents the first average amplitude corresponding to the first digital signal after amplitude detection processing, m1150 represents the second average amplitude corresponding to the first digital signal after amplitude detection processing, m290 represents the first average amplitude corresponding to the second digital signal after amplitude detection processing, and m2150 represents the second average amplitude corresponding to the second digital signal after amplitude detection processing.

[0127] Step S505: If the first modulation difference is within a preset first threshold range and the second modulation difference is within a preset second threshold range, then the aircraft is determined to be located on the runway centerline and the glide slope centerline.

[0128] Furthermore, if the first modulation difference (DDM1) is within a preset first threshold range (0 ± 0.004), and the second modulation difference (DDM2) is within a preset second threshold range (0 ± 0.004), it indicates that the modulation difference between the 90Hz first frequency component and the 150Hz second frequency component is within the ideal range. This means that the aircraft is in an ideal position in both the lateral (runway) and vertical (glide path) directions, i.e., located on the runway centerline and the glide path centerline, and the flight path is accurate. The first threshold range and the second threshold range can be equal.

[0129] In step S506, if the first modulation difference is greater than the maximum value of the first threshold range, it is determined that the aircraft has deviated to the left of the runway centerline; if the second modulation difference is greater than the maximum value of the second threshold range, it is determined that the aircraft has deviated to the upper side of the glide slope centerline.

[0130] Furthermore, when the first modulation difference (DDM1) is greater than the maximum value of the first threshold range (i.e., 0.004), it indicates that the modulation difference between the first frequency component of 90Hz and the second frequency component of 150Hz in the localizer signal exceeds the positive standard, and it is determined that the aircraft is deviating to the left of the runway centerline; if the second modulation difference (DDM2) is greater than the maximum value of the second threshold range (i.e., 0.004), it indicates that the corresponding modulation difference in the glide slope signal exceeds the positive standard, and it is determined that the aircraft is deviating above the glide slope centerline, prompting the pilot to adjust the lateral or vertical flight path.

[0131] In step S507, if the first modulation difference is less than the minimum value of the first threshold range, it is determined that the aircraft has deviated to the right of the runway centerline; if the second modulation difference is less than the minimum value of the second threshold range, it is determined that the aircraft has deviated to the lower side of the glide slope centerline.

[0132] Furthermore, if the first modulation difference (DDM1) is less than the minimum value of the first threshold range (i.e., -0.004), it indicates that the localizer signal modulation difference exceeds the negative standard, and the aircraft is determined to have deviated to the right of the runway centerline; when the second modulation difference (DDM2) is less than the minimum value of the second threshold range (i.e., -0.004), it indicates that the glide slope signal modulation difference exceeds the negative standard, and the aircraft is determined to have deviated to the lower side of the glide slope centerline, and the pilot is promptly alerted to make a reverse adjustment to ensure that the aircraft returns to the correct landing path.

[0133] For further details, please see Figure 6The illustrated flowchart of the FPGA signal processing module shows that, firstly, the heading signal processing flow based on the FPGA signal processing module includes:

[0134] (1) The first intermediate frequency signal of 21.4MHz after sampling by the ADC sampling module is rectified. The method is to judge the sign bit of the first digital signal. If it is positive, the rectified data is the first digital signal itself; if it is negative, the rectified signal is the complement of the first digital signal.

[0135] (2) The rectified signal is decimated by 65 times (first-stage decimation filtering). The decimation filter uses a CIC decimation filter, cascaded in 5 stages, with a decimation of 65 times. Since the main signals are 90Hz and 150Hz, flatness compensation is not required. After decimation by 65 times, the signal sampling rate is 1MHz (i.e., the second sampling rate).

[0136] (3) Perform a 100x decimation filter on the 1MHz sampling rate signal (second-stage decimation filter). The decimation filter uses a CIC decimation filter, cascaded in 5 stages, with a 100x decimation. Since the main signals are 90Hz and 150Hz, flatness compensation is not required. After 100x decimation, the signal sampling rate is 10kHz (i.e., the third sampling rate).

[0137] (4) Perform a 10x decimation filter on the 10kHz sampling rate signal (third-stage decimation filter). The decimation filter uses a CIC decimation filter, cascaded in 5 stages, with a 10x decimation. Since the main signals are 90Hz and 150Hz, flatness compensation is not required. After 10x decimation, the signal sampling rate is 1kHz (i.e., the fourth sampling rate).

[0138] (5) Perform bandpass filtering of 90Hz and 150Hz on the 1KHz sampling rate signal to obtain 90Hz and 150Hz signals respectively. See (6) and (7) for specific methods.

[0139] (6) Perform 90Hz bandpass filtering on the 1kHz sampling rate signal. Use an FIR bandpass filter with a filter order of 64 and a passband of 0.12π to 0.24π (i.e., the first passband frequency range); the output of the bandpass filter is the 90Hz localizer signal (i.e., the first frequency component).

[0140] (7) Perform 150Hz bandpass filtering on the 1kHz sampling rate signal. Use an FIR bandpass filter with a filter order of 64 and a passband of 0.24π to 0.36π (i.e., the second passband frequency range); the output of the bandpass filter is the 150Hz localizer signal (i.e., the second frequency component).

[0141] (8) Amplitude detection was performed on the 90Hz and 150Hz signals respectively. The detection method was to calculate the average of 1024 data points to obtain the average amplitude values ​​m190 and m1150 of the 90Hz and 150Hz signals.

[0142] (9) Calculate and output the DDM1 value.

[0143] The formula for calculating the DDM1 value is: DDM1 = (m190 - m1150) / (m190 + m1150) * 0.4;

[0144] If the DDM1 value is 0 ± 0.004 (i.e., the first threshold range), it indicates that the aircraft is on the centerline of the localizer; if the DDM1 value is greater than 0.004, it indicates that the aircraft is to the left of the centerline of the localizer, and the larger the value, the greater the deviation; if the DDM1 value is less than -0.004, it indicates that the aircraft is to the right of the centerline of the localizer, and the smaller the value, the greater the deviation.

[0145] Secondly, the down-slope signal processing flow based on the FPGA signal processing module includes:

[0146] (1) The second intermediate frequency signal of 21.4MHz after sampling by the ADC sampling module is rectified. The method is to judge the sign bit of the second digital signal. If it is positive, the rectified data is the second digital signal itself; if it is negative, the rectified signal is the complement of the second digital signal.

[0147] (2) The rectified signal is decimated by 65 times (first-stage decimation filtering). The decimation filter uses a CIC decimation filter, cascaded in 5 stages, with a decimation of 65 times. Since the main signals are 90Hz and 150Hz, flatness compensation is not required. After decimation by 65 times, the signal sampling rate is 1MHz (i.e., the second sampling rate).

[0148] (3) Perform a 100x decimation filter on the 1MHz sampling rate signal (second-stage decimation filter). The decimation filter uses a CIC decimation filter, cascaded in 5 stages, with a 100x decimation. Since the main signals are 90Hz and 150Hz, flatness compensation is not required. After 100x decimation, the signal sampling rate is 10kHz (i.e., the third sampling rate).

[0149] (4) Perform a 10x decimation filter on the 10kHz sampling rate signal (third-stage decimation filter). The decimation filter uses a CIC decimation filter, cascaded in 5 stages, with a 10x decimation. Since the main signals are 90Hz and 150Hz, flatness compensation is not required. After 10x decimation, the signal sampling rate is 1kHz (i.e., the fourth sampling rate).

[0150] (5) Perform bandpass filtering of 90Hz and 150Hz on the 1KHz sampling rate signal to obtain 90Hz and 150Hz signals respectively. See (6) and (7) for specific methods.

[0151] (6) Perform 90Hz bandpass filtering on the 1kHz sampling rate signal. Use an FIR bandpass filter with a filter order of 64 and a passband of 0.12π to 0.24π (i.e., the first passband frequency range); the output of the bandpass filter is the 90Hz localizer signal (i.e., the first frequency component).

[0152] (7) Perform 150Hz bandpass filtering on the 1kHz sampling rate signal. Use an FIR bandpass filter with a filter order of 64 and a passband of 0.24π to 0.36π (i.e., the second passband frequency range); the output of the bandpass filter is the 150Hz localizer signal (i.e., the second frequency component).

[0153] (8) Amplitude detection was performed on the 90Hz and 150Hz signals respectively. The detection method was to calculate the average of 1024 data points to obtain the average amplitude values ​​m190 and m1150 of the 90Hz and 150Hz signals.

[0154] (9) Calculate and output the DDM2 value.

[0155] The formula for calculating the DDM2 value is: DDM2=(m290-m2150) / (m290+m2150)*0.8;

[0156] If the DDM2 value is 0 ± 0.004 (i.e., the second threshold range), it indicates that the aircraft is on the centerline of the glide slope; if the DDM2 value is greater than 0.004, it indicates that the aircraft is slightly above the centerline of the glide slope, and the larger the value, the greater the deviation; if the DDM1 value is less than -0.004, it indicates that the aircraft is slightly below the centerline of the localizer, and the smaller the value, the greater the deviation. Therefore, this embodiment achieves a unified architecture and flexible method, with the localizer data processing method and the glide slope data processing method being basically the same, simplifying the signal processing difficulty.

[0157] In summary, this embodiment employs multi-stage decimation filtering and bandpass filtering, combined with amplitude mean calculation, to improve the modulation difference calculation accuracy to ±0.001, effectively reducing navigation errors during aircraft approach and landing phases and significantly improving flight safety. Furthermore, this embodiment leverages the parallel processing capabilities of the FPGA signal processing module and employs multi-stage decimation filtering to substantially shorten signal processing link latency. The output frequency of the modulation difference can be flexibly configured to meet the real-time requirements of dynamic flight attitude adjustments. Secondly, this embodiment achieves a high degree of unification in the processing of localizer and glide slope signals, simplifying the system architecture, reducing development and maintenance difficulty and costs, and improving system reliability and scalability.

[0158] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 7 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0159] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0160] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0161] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0162] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0163] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0164] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0165] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0166] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the defined scope.

Claims

1. A signal processing method for an instrument landing system based on FPGA, characterized in that, The method includes: Receives the localizer and glide slope signals from the instrument landing system; The localizer signal and the glide slope signal are subjected to radio frequency processing to obtain a first intermediate frequency signal corresponding to the localizer signal and a second intermediate frequency signal corresponding to the glide slope signal. The first intermediate frequency signal and the second intermediate frequency signal are respectively converted from analog to digital to obtain the first digital signal corresponding to the heading signal and the second digital signal corresponding to the glide slope signal; The first digital signal and the second digital signal are respectively subjected to rectification processing, multi-stage decimation filtering processing, bandpass filtering processing, amplitude detection processing and modulation difference calculation to obtain the first modulation difference corresponding to the heading signal and the second modulation difference corresponding to the glide slope signal. Based on the first modulation difference and the second modulation difference, determine the deviation of the aircraft from the runway centerline and the glide slope centerline; The rectification process includes: The sign of the corresponding digital signal is determined based on the sign bit of the corresponding digital signal. If the corresponding digital signal is positive, its original value is retained. If the corresponding digital signal is negative, a two's complement conversion operation is performed on the corresponding digital signal. The corresponding digital signal includes the first digital signal and the second digital signal. The multi-stage decimation filtering process includes: The first-stage decimation filter is performed on the corresponding digital signal after rectification, reducing the signal sampling rate of the corresponding digital signal after rectification from the first sampling rate to the second sampling rate. The corresponding digital signal after the first-stage decimation filtering is subjected to a second-stage decimation filtering, which reduces the signal sampling rate of the corresponding digital signal after the first-stage decimation filtering from the second sampling rate to the third sampling rate. The corresponding digital signal after the second-stage decimation filtering is subjected to a third-stage decimation filtering, which reduces the signal sampling rate of the corresponding digital signal after the second-stage decimation filtering from the third sampling rate to the fourth sampling rate; each decimation filtering stage uses a CIC decimation filter, and the number of cascaded CIC decimation filters is equal.

2. The method according to claim 1, characterized in that, The receiving instrument landing system's localizer and glide slope signals include: It receives the localizer signal in the first frequency range from the localizer beacon and the glide slope signal in the second frequency range from the glide slope beacon.

3. The method according to claim 1, characterized in that, The step of performing radio frequency processing on the localizer signal and the glide slope signal to obtain a first intermediate frequency signal corresponding to the localizer signal and a second intermediate frequency signal corresponding to the glide slope signal includes: The localizer signal and the glide slope signal are sequentially amplified, mixed, and filtered to obtain a first intermediate frequency signal corresponding to the localizer signal and a second intermediate frequency signal corresponding to the glide slope signal; the center frequencies of the first intermediate frequency signal and the second intermediate frequency signal are equal.

4. The method according to claim 1, characterized in that, The bandpass filtering process includes: The corresponding digital signal after the third-stage decimation filter is subjected to an FIR filter to extract the first frequency component of the first passband frequency range and the second frequency component of the second passband frequency range; the first passband frequency range is smaller than the second passband frequency range, and the frequency value of the first frequency component is smaller than the frequency value of the second frequency component.

5. The method according to claim 4, characterized in that, The amplitude detection process includes: The first frequency component and the second frequency component of the corresponding digital signal after bandpass filtering are averaged to obtain the first amplitude average value corresponding to the first frequency component and the second amplitude average value corresponding to the second frequency component.

6. The method according to claim 5, characterized in that, The modulation difference of the first digital signal after amplitude detection processing is calculated using the following formula: DDM1=(m190-m1150) / (m190+m1150) 0.4; The modulation difference of the second digital signal after amplitude detection processing is calculated using the following formula: DDM2=(m290-m2150) / (m290+m2150) 0.8; Wherein, DDM1 represents the first modulation difference, DDM2 represents the second modulation difference, m190 represents the first average amplitude corresponding to the first digital signal after amplitude detection processing, m1150 represents the second average amplitude corresponding to the first digital signal after amplitude detection processing, m290 represents the first average amplitude corresponding to the second digital signal after amplitude detection processing, and m2150 represents the second average amplitude corresponding to the second digital signal after amplitude detection processing.

7. The method according to any one of claims 1 to 6, characterized in that, The step of determining the aircraft's deviation from the runway centerline and glide slope centerline based on the first modulation difference and the second modulation difference includes: If the first modulation difference is within a preset first threshold range and the second modulation difference is within a preset second threshold range, then the aircraft is determined to be located on the runway centerline and the glide slope centerline. If the first modulation difference is greater than the maximum value of the first threshold range, the aircraft is determined to have deviated to the left of the runway centerline; if the second modulation difference is greater than the maximum value of the second threshold range, the aircraft is determined to have deviated to the upper side of the glide slope centerline. If the first modulation difference is less than the minimum value of the first threshold range, the aircraft is determined to have deviated to the right of the runway centerline; if the second modulation difference is less than the minimum value of the second threshold range, the aircraft is determined to have deviated to the lower side of the glide slope centerline.

8. A signal processing system for an instrument landing system based on FPGA, characterized in that, The system includes an antenna, a radio frequency module, an ADC sampling module, an FPGA signal processing module, and a main control module; The antenna is used to receive the localizer and glide slope signals from the instrument landing system. The radio frequency module is used to perform radio frequency processing on the localizer signal and the glide slope signal respectively to obtain a first intermediate frequency signal corresponding to the localizer signal and a second intermediate frequency signal corresponding to the glide slope signal; The ADC sampling module is used to perform analog-to-digital conversion on the first intermediate frequency signal and the second intermediate frequency signal respectively to obtain a first digital signal corresponding to the heading signal and a second digital signal corresponding to the glide slope signal. The FPGA signal processing module is used to sequentially perform rectification processing, multi-stage decimation filtering processing, bandpass filtering processing, amplitude detection processing, and modulation difference calculation on the first digital signal and the second digital signal, respectively, to obtain the first modulation difference corresponding to the heading signal and the second modulation difference corresponding to the glide slope signal. The main control module is used to control the signal transmission between the modules in the system, and to determine the deviation of the aircraft from the runway centerline and the glide slope centerline based on the first modulation difference and the second modulation difference. The rectification process includes: The sign of the corresponding digital signal is determined based on the sign bit of the corresponding digital signal. If the corresponding digital signal is positive, its original value is retained. If the corresponding digital signal is negative, a two's complement conversion operation is performed on the corresponding digital signal. The corresponding digital signal includes the first digital signal and the second digital signal. The multi-stage decimation filtering process includes: The first-stage decimation filter is performed on the corresponding digital signal after rectification, reducing the signal sampling rate of the corresponding digital signal after rectification from the first sampling rate to the second sampling rate. The corresponding digital signal after the first-stage decimation filtering is subjected to a second-stage decimation filtering, which reduces the signal sampling rate of the corresponding digital signal after the first-stage decimation filtering from the second sampling rate to the third sampling rate. The corresponding digital signal after the second-stage decimation filtering is subjected to a third-stage decimation filtering, which reduces the signal sampling rate of the corresponding digital signal after the second-stage decimation filtering from the third sampling rate to the fourth sampling rate; each decimation filtering stage uses a CIC decimation filter, and the number of cascaded CIC decimation filters is equal.

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