Dma transmission method, dma controller, computer device and storage medium

Abstract

The application relates to a DMA transmission method, a DMA controller, a computer device and a storage medium, wherein the DMA transmission method comprises the following steps: in response to a DMA transmission request signal, loading a configuration word in a configuration word storage module to a DMA control module; before DMA transmission starts, emptying the configuration word storage module and releasing the configuration word storage module as a data transmission cache area; and in the DMA transmission process, caching target data to the data transmission cache area. By emptying the configuration word storage module before DMA transmission starts and releasing the configuration word storage module as a data transmission cache area, the configuration word storage module is dynamically multiplexed as a data transmission cache area, time-sharing multiplexing of storage space is realized, the utilization rate of storage resources is improved, and waste of hardware resources is reduced.

Description

Technical Field

[0001] This application relates to the field of computers, and in particular to a DMA transfer method, a DMA controller, a computer device, and a storage medium. Background Technology

[0002] DMA (Direct Memory Access) is a data transfer technique that allows data to be transferred directly between memories without CPU intervention. The DMA controller takes over bus control during the transfer and returns control to the CPU upon completion. During DMA transfers, a DMA FIFO (First-In, First-Out) buffers the data to be transferred, while a DMA configuration word is loaded from a separate memory area into the DMA controller to configure the transfer information. However, this introduces data redundancy into the system, leading to low system memory utilization.

[0003] Currently, no effective solution has been proposed for the problem of low system storage utilization during DMA transfer in related technologies. Summary of the Invention

[0004] Therefore, it is necessary to provide a DMA transfer method, DMA controller, computer device, and storage medium that can improve system storage utilization in response to the above-mentioned technical problems.

[0005] Firstly, this application provides a DMA transfer method applied to a DMA controller. The method includes:

[0006] In response to the DMA transfer request signal, the configuration word in the configuration word storage module is loaded into the DMA control module;

[0007] Before DMA transfer begins, the configuration word storage module is cleared and released as a data transfer buffer area;

[0008] During the DMA transfer process, the target data is cached in the data transfer cache area.

[0009] In one embodiment, the method further includes:

[0010] After the DMA transfer is completed, the configuration word is written back to the configuration word storage module.

[0011] In one embodiment, after the DMA transfer is completed, writing the configuration word back to the configuration word storage module includes:

[0012] Send a write-back signal to the configuration word storage module to rewrite the configuration word from the DMA control module to the configuration word storage module and restore the configuration word storage function of the configuration word storage module.

[0013] In one embodiment, the configuration word includes a transfer control descriptor used to configure the source address, destination address, transfer length, and transfer mode of the DMA transfer.

[0014] In one embodiment, before the DMA transfer begins, the configuration word storage module is cleared and released as a data transfer buffer area, including:

[0015] Send a clear signal to the configuration word storage module to clear the data in the configuration word storage module;

[0016] Switch the access permissions of the configuration word storage module from configuration word storage mode to data transmission cache mode.

[0017] In one embodiment, during the DMA transfer process, buffering the target data into the data transfer buffer area includes:

[0018] Based on the burst length of the DMA transfer, the target data is written into the data transmission buffer area in batches;

[0019] During the target data transmission process, the water level of the data transmission buffer area is monitored in real time.

[0020] Secondly, this application provides a DMA controller, comprising:

[0021] Configuration word storage module, used to store configuration words;

[0022] A data transmission buffer area is used to cache target data;

[0023] The DMA control module is used to clear the configuration word storage module and release it as the data transmission buffer area before the DMA transfer begins.

[0024] The data transmission module is used to cache the target data to the data transmission cache area during DMA transmission.

[0025] In one embodiment, the DMA control module includes:

[0026] The clearing unit is used to send a clearing signal to the configuration word storage module to clear its data to zero;

[0027] The permission switching unit is used to switch the access permission of the configuration word storage module from configuration word storage mode to data transmission caching mode;

[0028] The control word write-back unit is used to rewrite the configuration word back to the configuration word storage module after the DMA transfer is completed.

[0029] Thirdly, this application provides a computer device, including: a memory, a processor, and a DMA controller as described in the second aspect above, wherein the memory, the processor, and the DMA controller are connected via a bus.

[0030] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect above.

[0031] The aforementioned DMA transfer method, DMA controller, computer device, and storage medium achieve time-sharing multiplexing of storage space by clearing the configuration word storage module before the DMA transfer begins and releasing it as a data transfer buffer area, and dynamically reusing the configuration word storage module as a data transfer buffer area. This improves the utilization rate of storage resources and reduces the waste of hardware resources. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the DMA controller in one embodiment;

[0033] Figure 2 To run in Figure 1 A flowchart of the DMA transfer method in the DMA controller;

[0034] Figure 3 This is a schematic diagram of the DMA control module in one embodiment;

[0035] Figure 4 Here is a flowchart of the DMA transfer method in another embodiment;

[0036] Figure 5 This is a schematic diagram of the data transmission module in one embodiment;

[0037] Figure 6 This is a schematic diagram of the structure of a computer device in one embodiment. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0039] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order of objects.

[0040] When a local device or peripheral sends a transfer request to the DMA controller, the DMA controller takes over bus control and transfers the data to be transferred from the source address to the destination address. After the transfer is complete, the DMA controller returns bus control to the CPU. Because the DMA FIFO is used to store the transferred data, while the DMA configuration word is stored in another area, most of the configuration word has already been loaded into the DMA circuit before the DMA transfer begins. This results in the area storing the configuration word not being fully utilized during the transfer, leading to wasted storage space. Therefore, in one embodiment… Figure 1 A schematic diagram of a DMA controller is provided, such as... Figure 1 As shown, the DMA controller includes: a configuration word storage module, a data transfer buffer area, a DMA control module, and a data transfer module. The configuration word storage module stores configuration words; the data transfer buffer area buffers target data; the DMA control module clears the configuration word storage module before DMA transfer begins and releases it as the data transfer buffer area; and the data transfer module buffers target data into the data transfer buffer area during DMA transfer.

[0041] Figure 2 A flowchart of a DMA transfer method running on this DMA controller is provided, such as... Figure 2As shown, the process includes the following steps:

[0042] In step S101, the DMA control module responds to the DMA transfer request signal by loading the configuration word from the configuration word storage module into the DMA control module.

[0043] When the system or peripheral device issues a DMA transfer request signal, the DMA control module begins to respond. The DMA control module first reads the pre-configured configuration words from the configuration word storage module. These configuration words contain all the necessary information about the upcoming data transfer, such as the source address, destination address, transfer size, transfer direction (read / write), and transfer mode. Then, the DMA control module loads these configuration words into its internal registers to determine the specific data transfer task to be performed.

[0044] In step S102, before the DMA transfer begins, the DMA control module clears the configuration word storage module and releases the configuration word storage module as a data transfer buffer area.

[0045] After confirming that all necessary configuration words have been successfully loaded into the DMA control module, the DMA control module will clear the configuration word storage module, that is, clear all data in the configuration word storage module. After clearing, the DMA control module will reconfigure the function of this area, changing it from a state dedicated to storing configuration words to a space that can be used to temporarily cache target data for data transfer. Specifically, the DMA control module will use the configuration word storage module as an additional data buffer during DMA transfers by changing the access permissions or logical functions of this memory area.

[0046] In step S103, during the DMA transfer process, the data transfer module caches the target data in the data transfer buffer area.

[0047] During DMA transfer, the data transfer module reads the target data from the specified source address and temporarily stores this target data in the data transfer buffer area. The data transfer buffer area acts as a FIFO buffer, smoothing out data rate differences between devices with different speeds and ensuring that data can be moved efficiently and stably from the source address to the target address. Once the target data has been successfully transferred to the target address, the corresponding data block can be removed from the data transfer buffer area to make room for the next data block, until the entire DMA transfer task is completed.

[0048] In this embodiment, by clearing the configuration word storage module before the DMA transfer begins and releasing it as a data transmission buffer area, the configuration word storage module is dynamically reused as a data transmission buffer area, thereby realizing time-sharing multiplexing of storage space, improving the utilization rate of storage resources, and reducing the waste of hardware resources.

[0049] In one embodiment, Figure 3 A schematic diagram of the DMA control module is provided, such as... Figure 3 As shown, the DMA control module includes a clear unit, a permission switching unit, and a control word write-back unit. The clear unit sends a clear signal to the configuration word storage module to clear its data; the permission switching unit switches the access permissions of the configuration word storage module from configuration word storage mode to data transfer buffer mode; and the control word write-back unit rewrites the configuration word back to the configuration word storage module after the DMA transfer is completed.

[0050] In this embodiment, before the DMA transfer begins, the DMA control module clears the configuration word storage module and releases it as a data transfer buffer. Specifically, this includes the following steps:

[0051] In step S201, the clearing unit sends a clear signal to the configuration word storage module to clear the data in the configuration word storage module.

[0052] Once the DMA transfer request is acknowledged and all necessary configuration words have been loaded into the DMA control module, the system prepares to begin the actual data transfer. The clear unit sends a clear signal to the configuration word storage module, instructing it to clear all currently stored data.

[0053] In step S202, the permission switching unit switches the access permission of the configuration word storage module from configuration word storage mode to data transmission cache mode.

[0054] The access control unit receives an instruction from the DMA control module indicating a need to switch the operating mode of the configuration word storage module. Specifically, the access control unit sends a series of control signals or commands to the configuration word storage module, instructing it to modify the access control list, enable / disable read / write permissions for certain address ranges, or change relevant settings in the memory management unit (MMU). Upon receiving these control signals, the configuration word storage module updates its internal state and enters data transfer buffer mode.

[0055] Figure 4 A flowchart of another DMA transfer method is provided, such as Figure 4 As shown, the process includes the following steps:

[0056] In step S101, the DMA control module responds to the DMA transfer request signal by loading the configuration word from the configuration word storage module into the DMA control module;

[0057] Step S102: Before the DMA transfer begins, the DMA control module clears the configuration word storage module and releases the configuration word storage module as a data transfer buffer area.

[0058] Step S103: During the DMA transfer process, the data transfer module buffers the target data into the data transfer buffer area;

[0059] In step S104, after the DMA transfer is completed, the DMA control module rewrites the configuration word back to the configuration word storage module.

[0060] This embodiment is in Figure 1 Based on the previous step, step S104 is added. In this step, the control word write-back unit sends a write-back signal to the configuration word storage module, rewrites the configuration word from the DMA control module to the configuration word storage module, and restores the configuration word storage function of the configuration word storage module. The configuration word includes a transfer control descriptor, which is used to configure the source address, destination address, transfer length, and transfer mode of the DMA transfer.

[0061] In this embodiment, the control word write-back unit sends a write signal to the configuration word storage module, instructing the configuration word storage module to be ready to receive new data (i.e., configuration words). The control word write-back unit writes the configuration words (including transfer control descriptors) stored in the DMA control module back to the configuration word storage module via the bus or other communication path. For example, assuming the starting address of the configuration word storage module is 0x1000, the DMA control module will sequentially write the configuration words into a continuous address space starting from 0x1000. Then, the access control unit sends a switching instruction to restore the access permissions of the configuration word storage module from "data transfer buffer mode" to "configuration word storage mode".

[0062] In this embodiment, by setting up a clearing unit, a permission switching unit, and a control word write-back unit in the DMA control module, the configuration word storage module is cleared before the DMA transfer begins and released as a data transmission buffer area. This ensures the availability of the data transmission buffer area and avoids data conflicts or errors. After the DMA transfer ends, the configuration word is written back to the configuration word storage module, realizing dynamic switching between the configuration word storage module and the data transmission buffer area. This ensures the integrity and reusability of the configuration word and prepares for the next DMA transfer.

[0063] In one embodiment, Figure 5 A schematic diagram of the data transmission module is provided, such as... Figure 5 As shown, the data transmission module includes: a batch transmission unit, used to write the target data into the data transmission buffer area in batches according to the burst length of the DMA transmission; and a water level monitoring unit, used to monitor the water level line of the data transmission buffer area in real time.

[0064] In this embodiment, during DMA transfer, the data transfer module buffers the target data into the data transfer buffer area. Specifically, this includes the following steps:

[0065] In step S301, the batch transmission unit writes the target data into the data transmission buffer area in batches according to the burst length of the DMA transmission.

[0066] The batch transfer unit reads the DMA transfer parameters from the configuration word, specifically the burst length. The burst length defines the size of the data transferred each time, typically in bytes or double words. Based on the burst length, the batch transfer unit reads data from the source address in batches. For example, if the burst length is set to 8 bytes, then each read operation will read 8 bytes of data. The data read in each batch is written to a data transfer buffer (such as a FIFO). This step ensures a smooth data transfer from the source address to the destination address even when there is a speed mismatch between the source and destination addresses.

[0067] In step S302, the water level monitoring unit monitors the water level in the data transmission buffer area in real time during the target data transmission process.

[0068] During system initialization, different watermark thresholds can be set according to application requirements. For example, a high watermark and a low watermark can be set. The high watermark indicates that the cache is close to full, while the low watermark indicates that the cache is close to empty.

[0069] The water level monitoring unit continuously monitors the current fill status of the data transmission buffer area and compares it with a preset water level line. When the buffer area's fill level reaches or exceeds the high water level line, the water level monitoring unit sends a signal to the batch transmission unit to temporarily stop new data reading operations to prevent buffer overflow. If the buffer area's fill level is below the low water level line, the water level monitoring unit sends a signal to the batch transmission unit to continue reading and writing new data to avoid transmission interruption due to an empty buffer. Furthermore, based on actual transmission conditions, the water level monitoring unit can dynamically adjust the transmission strategy to ensure the continuity and stability of data transmission. For example, in high-speed transmission scenarios, the high water level threshold can be increased to allow for greater buffer usage; while in low-speed transmission scenarios, the high water level threshold can be decreased to reduce the risk of buffer overflow.

[0070] In this embodiment, by writing data in batches and monitoring the water level in real time, the efficiency and reliability of data transmission are ensured, and data loss or transmission errors are avoided.

[0071] In one embodiment, Figure 6 A schematic diagram of the structure of a computer device is provided, such as... Figure 6As shown, it includes at least a memory, a processor, and a DMA controller according to any of the above embodiments. The memory, processor, and DMA controller are connected via a bus. During the transfer process, the DMA controller takes over bus control and returns control to the processor after the transfer is completed. The DMA controller stores a computer program, which, when executed, implements the steps of the DMA transfer method according to any of the above embodiments.

[0072] The computer device may be a server, and its processing includes memory, a processor, and a DMA controller connected via a system bus, and may also include a network interface. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and other computer programs stored in the non-volatile storage media. The database stores data. The network interface communicates with external terminals via a network connection. The computer programs, when executed by the processor, implement other methods.

[0073] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated in this embodiment.

[0074] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0075] In one embodiment, the DMA controller performs the following steps when executing a computer program:

[0076] In response to the DMA transfer request signal, the configuration word in the configuration word storage module is loaded into the DMA control module; before the DMA transfer begins, the configuration word storage module is cleared and released as a data transfer buffer area; during the DMA transfer, the target data is cached in the data transfer buffer area.

[0077] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0078] After the DMA transfer is completed, the configuration word is written back to the configuration word storage module.

[0079] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0080] After the DMA transfer is completed, a write-back signal is sent to the configuration word storage module to rewrite the configuration word from the DMA control module to the configuration word storage module and restore the configuration word storage function of the configuration word storage module.

[0081] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0082] Before the DMA transfer begins, a clear signal is sent to the configuration word storage module to clear the data in the configuration word storage module; the access permissions of the configuration word storage module are switched from configuration word storage mode to data transfer buffer mode.

[0083] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0084] During DMA transfer, the target data is written to the data transfer buffer in batches according to the burst length of the DMA transfer; during the target data transfer, the water level of the data transfer buffer is monitored in real time.

[0085] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0086] In response to the DMA transfer request signal, the configuration word in the configuration word storage module is loaded into the DMA control module; before the DMA transfer begins, the configuration word storage module is cleared and released as a data transfer buffer area; during the DMA transfer, the target data is cached in the data transfer buffer area.

[0087] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0088] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A DMA transfer method, characterized in that, Applied to a DMA controller, the method includes: In response to the DMA transfer request signal, the configuration word in the configuration word storage module is loaded into the DMA control module; Before the DMA transfer begins, the configuration word storage module is cleared and released as a data transmission buffer area, including: sending a clear signal to the configuration word storage module to clear the data in the configuration word storage module; and switching the access permission of the configuration word storage module from configuration word storage mode to data transmission buffer mode. During the DMA transfer process, the target data is cached in the data transfer buffer area; After the DMA transfer is completed, a write-back signal is sent to the configuration word storage module to rewrite the configuration word from the DMA control module to the configuration word storage module and restore the configuration word storage function of the configuration word storage module; the access permissions of the configuration word storage module are restored from the data transmission buffer mode to the configuration word storage mode.

2. The DMA transfer method according to claim 1, characterized in that, The configuration word includes a transfer control descriptor, which is used to configure the source address, destination address, transfer length, and transfer mode of the DMA transfer.

3. The DMA transfer method according to claim 1, characterized in that, During the DMA transfer process, buffering the target data into the data transfer buffer area includes: Based on the burst length of the DMA transfer, the target data is written into the data transmission buffer area in batches; During the target data transmission process, the water level of the data transmission buffer area is monitored in real time.

4. A DMA controller, characterized in that, include: Configuration word storage module, used to store configuration words; A data transmission buffer area is used to cache target data; The DMA control module is used to clear the configuration word storage module and release it as the data transmission buffer area before the DMA transfer begins. A data transmission module is used to cache the target data into the data transmission cache area during DMA transmission; The DMA control module includes a clear unit, a permission switching unit, and a control word write-back unit. The clearing unit is used to send a clearing signal to the configuration word storage module to clear its data to zero; The permission switching unit is used to switch the access permission of the configuration word storage module from configuration word storage mode to data transmission caching mode; The control word write-back unit is used to rewrite the configuration word back to the configuration word storage module after the DMA transfer is completed; The permission switching unit is further configured to restore the access permissions of the configuration word storage module from the data transmission cache mode to the configuration word storage mode after the DMA transmission is completed.

5. A computer device, characterized in that, include: The memory, the processor, and the DMA controller of claim 4 are connected via a bus.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 3.

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