LVDS communication method, line card, electronic device and apparatus

Abstract

The embodiment of the application provides a kind of LVDS communication method, line card, electronic equipment and device, it is related to chip technology field, it is applied to line card, the corresponding relationship between the identification of LVDS component and the phase difference of the LVDS component is stored in line card, method includes: determine whether the first phase difference of target LVDS component is stored;If yes, then send the first start frame carrying check data to target LVDS component, so that target LVDS component feeds back check data to line card, determine whether check data can be correctly collected from the received data according to the first phase difference;If check data can be correctly collected, then communicate with target LVDS component according to the first phase difference.Application embodiment of the application can save the time consumed by LVDS training before line card carries out LVDS communication.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to an LVDS communication method, line card, electronic device and apparatus. Background Technology

[0002] In current circuit board designs, line cards and daughter cards on the circuit board typically use LVDS (Low-Voltage Differential Signaling) as the management channel. When a line card sends data to the LVDS component configured on the daughter card via LVDS, it transmits both TX (Transmit) and CLK (Clock) signals. The CLK and TX signals transmitted by the line card maintain a fixed timing relationship. Therefore, the LVDS component directly determines the phase and extracts data from the TX signal. However, when the LVDS component sends the RX (Receive) signal to the line card, it does not send the CLK signal. Therefore, the line card cannot determine the phase of the RX signal and cannot directly extract data from it. To determine the phase difference between the RX signal and the line card's clock, the line card needs to undergo LVDS training.

[0003] However, if the line card is connected to multiple LVDS components via different LVDS modules, the different hardware links between each LVDS component and the line card will result in different signal delays. Consequently, the phase difference between the RX signal sent by each LVDS component to the line card and the line card's clock will be different. Therefore, LVDS training needs to be performed again every time the LVDS component accessed by the line card changes, which will waste a lot of time on LVDS training during LVDS communication between the line card and the LVDS components. Summary of the Invention

[0004] The purpose of this application is to provide an LVDS communication method, line card, electronic device, and apparatus to save the time spent on LVDS training before the line card can perform LVDS communication. The specific technical solution is as follows:

[0005] In a first aspect, embodiments of this application provide an LVDS communication method applied to a line card, wherein the line card stores a correspondence between the identifier of a Low Voltage Differential Signaling (LVDS) component and the phase difference of the LVDS component, the LVDS component being configured on a daughter card, and the method includes:

[0006] Determine whether the first phase difference corresponding to the target identifier of the target LVDS component to be accessed is stored;

[0007] If the first phase difference is stored, a first start frame carrying verification data is sent to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference;

[0008] If the verification data can be correctly acquired, then communication is established with the target LVDS component according to the first phase difference.

[0009] In one embodiment of this application, the method further includes:

[0010] If the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, then low voltage differential signal LVDS training is performed on the target LVDS component to determine the second phase difference corresponding to the target LVDS component, and communication is performed with the target LVDS component according to the second phase difference, and the phase difference corresponding to the target identifier is recorded as the second phase difference.

[0011] In one embodiment of this application, the step of performing LVDS training on the target LVDS component to determine the second phase difference corresponding to the target LVDS component includes:

[0012] Send a second start frame to the target LVDS component so that the target LVDS component sends a receive RX signal to the line card;

[0013] The phase of the RX signal is determined according to the training phase difference and the phase of the frequency multiplier clock of the line card. The RX signal is sampled at the clock frequency of the frequency multiplier clock according to the phase of the RX signal to obtain the frequency multiplier sequence. The initial value of the training phase difference is a preset value. The clock frequency of the frequency multiplier clock is a preset multiple of the clock frequency of the original clock in the line card. Each frequency multiplier sequence contains the preset multiple of consecutive sub-data.

[0014] If the number of consecutive frequency-multiply sequences containing the same sub-data with the same value reaches the second preset number, then the current training phase difference is determined to be the second phase difference, and the second preset number is less than or equal to the preset multiple.

[0015] Otherwise, adjust the training phase difference and return to the step of determining the phase of the RX signal according to the training phase difference and the phase of the multiplied clock of the line card, sampling the RX signal according to the clock frequency of the multiplied clock, and obtaining the multiplied sequence.

[0016] In one embodiment of this application, the second start frame includes at least one of the following fields: first idle code, start flag, first training flag, first operation instruction, start address of the target LVDS component, first checksum, and second idle code;

[0017] The value of the start flag is a preset value, so that the target LVDS component can determine whether the data frame containing the start flag is the first start frame or the second start frame after receiving the data frame.

[0018] The first training flag is used to indicate that the data frame in which the first training flag is located is the second starting frame;

[0019] The first operation instruction is used to instruct the target LVDS component to perform the operation after receiving the second start frame.

[0020] In one embodiment of this application, the first start frame includes at least one of the following fields: first idle code, start flag, second training flag, second operation instruction, start address of the target LVDS component, verification data, second verification code, and second idle code;

[0021] The value of the start flag is a preset value, so that the target LVDS component determines the data frame as the first start frame after receiving the data frame containing the start flag and the second training flag;

[0022] The second operation instruction is used to instruct the target LVDS component to perform the operation after receiving the first start frame.

[0023] In one embodiment of this application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, with different correspondences corresponding to different numbers.

[0024] Secondly, embodiments of this application provide a line card that stores a correspondence between the identifier of a Low Voltage Differential Signaling (LVDS) component and the phase difference of the LVDS component. The LVDS component is configured on a sub-card. The line card performs the following steps:

[0025] Determine whether the first phase difference corresponding to the target identifier of the target LVDS component to be accessed is stored;

[0026] If the first phase difference is stored, a first start frame carrying verification data is sent to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference;

[0027] If the verification data can be correctly acquired, then communication is established with the target LVDS component according to the first phase difference.

[0028] In one embodiment of this application, the line card further performs the following steps:

[0029] If the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, then low voltage differential signal LVDS training is performed on the target LVDS component to determine the second phase difference corresponding to the target LVDS component, and communication is performed with the target LVDS component according to the second phase difference, and the phase difference corresponding to the target identifier is recorded as the second phase difference.

[0030] In one embodiment of this application, the step of performing LVDS training on the target LVDS component to determine the second phase difference corresponding to the target LVDS component includes:

[0031] Send a second start frame to the target LVDS component so that the target LVDS component sends a receive RX signal to the line card;

[0032] The phase of the RX signal is determined according to the training phase difference and the phase of the frequency multiplier clock of the line card. The RX signal is sampled at the clock frequency of the frequency multiplier clock according to the phase of the RX signal to obtain the frequency multiplier sequence. The initial value of the training phase difference is a preset value. The clock frequency of the frequency multiplier clock is a preset multiple of the clock frequency of the original clock in the line card. Each frequency multiplier sequence contains the preset multiple of consecutive sub-data.

[0033] If the number of consecutive frequency-multiply sequences containing the same sub-data with the same value reaches the second preset number, then the current training phase difference is determined to be the second phase difference, and the second preset number is less than or equal to the preset multiple.

[0034] Otherwise, adjust the training phase difference and return to the step of determining the phase of the RX signal according to the training phase difference and the phase of the multiplied clock of the line card, sampling the RX signal according to the clock frequency of the multiplied clock, and obtaining the multiplied sequence.

[0035] In one embodiment of this application, the second start frame includes at least one of the following fields: first idle code, start flag, first training flag, first operation instruction, start address of the target LVDS component, first checksum, and second idle code;

[0036] The value of the start flag is a preset value, so that the target LVDS component can determine whether the data frame containing the start flag is the first start frame or the second start frame after receiving the data frame.

[0037] The first training flag is used to indicate that the data frame in which the first training flag is located is the second starting frame;

[0038] The first operation instruction is used to instruct the target LVDS component to perform the operation after receiving the second start frame.

[0039] In one embodiment of this application, the first start frame includes at least one of the following fields: first idle code, start flag, second training flag, second operation instruction, start address of the target LVDS component, verification data, second verification code, and second idle code;

[0040] The value of the start flag is a preset value, so that the target LVDS component determines the data frame as the first start frame after receiving the data frame containing the start flag and the second training flag;

[0041] The second operation instruction is used to instruct the target LVDS component to perform the operation after receiving the first start frame.

[0042] In one embodiment of this application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, with different correspondences corresponding to different numbers.

[0043] Thirdly, embodiments of this application provide an electronic device, the electronic device comprising:

[0044] processor;

[0045] transceiver;

[0046] A line card that stores the correspondence between the identifier of a Low Voltage Differential Signaling (LVDS) component and the phase difference of that LVDS component;

[0047] Daughter card, wherein the daughter card is configured with an LVDS component;

[0048] A machine-readable storage medium storing machine-executable instructions that can be executed by the processor;

[0049] The line card implements any of the steps described in the first aspect.

[0050] Fourthly, embodiments of this application provide an LVDS communication device applied to a line card, wherein the line card stores a correspondence between the identifier of a Low Voltage Differential Signaling (LVDS) component and the phase difference of the LVDS component, the LVDS component being configured on a daughter card, and the device comprising:

[0051] The first phase difference determination module is used to determine whether the first phase difference corresponding to the target identifier of the target LVDS component to be accessed is stored.

[0052] The first start frame sending module is used to send a first start frame carrying verification data to the target LVDS component if the first phase difference is stored, so that the target LVDS component can feed back the verification data to the line card and determine whether the verification data can be correctly collected from the received data according to the first phase difference.

[0053] The first communication module is used to communicate with the target LVDS component according to the first phase difference if the verification data can be correctly acquired.

[0054] In one embodiment of this application, the apparatus further includes:

[0055] The second communication module is used to perform low-voltage differential signal LVDS training on the target LVDS component if the first phase difference is not stored, or if the verification data cannot be correctly extracted from the received data according to the first phase difference, determine the second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

[0056] In one embodiment of this application, the second phase difference is determined by the following module:

[0057] The second start frame sending module is used to send a second start frame to the target LVDS component so that the target LVDS component sends a receive RX signal to the line card;

[0058] The sequence extraction module is used to determine the phase of the RX signal according to the training phase difference and the phase of the frequency multiplier clock of the line card, and to sample the RX signal at the clock frequency of the frequency multiplier clock according to the phase of the RX signal to obtain a frequency multiplier sequence. The initial value of the training phase difference is a preset value, the clock frequency of the frequency multiplier clock is a preset multiple of the clock frequency of the original clock in the line card, and each frequency multiplier sequence contains the preset multiple of consecutive sub-data.

[0059] The second phase difference determination module is used to determine the current training phase difference as the second phase difference if the sub-data with the same value contained in a first preset number of consecutive frequency harmonic sequences all reach a second preset number, and the second preset number is less than or equal to the preset multiple.

[0060] The phase difference adjustment module is used to adjust the training phase difference and return to trigger the execution of the sequence extraction module if there are no consecutive first preset number of frequency harmonic sequences containing sub-data with the same value that have reached the second preset number.

[0061] In one embodiment of this application, the second start frame includes at least one of the following fields: first idle code, start flag, first training flag, first operation instruction, start address of the target LVDS component, first checksum, and second idle code;

[0062] The value of the start flag is a preset value, so that the target LVDS component can determine whether the data frame containing the start flag is the first start frame or the second start frame after receiving the data frame.

[0063] The first training flag is used to indicate that the data frame in which the first training flag is located is the second starting frame;

[0064] The first operation instruction is used to instruct the target LVDS component to perform the operation after receiving the second start frame.

[0065] In one embodiment of this application, the first start frame includes at least one of the following fields: first idle code, start flag, second training flag, second operation instruction, start address of the target LVDS component, verification data, second verification code, and second idle code;

[0066] The value of the start flag is a preset value, so that the target LVDS component determines the data frame as the first start frame after receiving the data frame containing the start flag and the second training flag;

[0067] The second operation instruction is used to instruct the target LVDS component to perform the operation after receiving the first start frame.

[0068] In one embodiment of this application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, with different correspondences corresponding to different numbers.

[0069] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the methods described in the first aspect.

[0070] In a sixth aspect, embodiments of this application also provide a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the methods described in the first aspect above.

[0071] Beneficial effects of the embodiments in this application:

[0072] In the solution provided in this application embodiment, before communication between the line card and the target LVDS component to be accessed, it is first determined whether the line card has already stored the first phase difference corresponding to the target LVDS component. If it exists, a first start frame is sent to the target LVDS component, causing the target LVDS component to return the verification data in the first start frame. If the line card can correctly collect the verification data, it indicates that the first phase difference has passed verification, and therefore communication can be directly based on the first phase difference. In this case, before communicating with the target LVDS component, only the sending of the first start frame, the receiving of the verification data, and the extraction of the verification data need to be completed, which takes much less time than the time required for LVDS training. Furthermore, verifying the first phase difference can ensure normal communication in most cases. Therefore, this application embodiment can save the time consumed by the line card in LVDS training before LVDS communication. Attached Figure Description

[0073] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0074] Figure 1 This is a schematic diagram illustrating the connection relationship between a line card and a daughter card, provided as an embodiment of this application.

[0075] Figure 2 A flowchart illustrating the first LVDS communication method provided in this application embodiment;

[0076] Figure 3 A flowchart illustrating the second LVDS communication method provided in this application embodiment;

[0077] Figure 4 A flowchart illustrating the third LVDS communication method provided in this application embodiment;

[0078] Figure 5 This is a schematic diagram of the first LVDS training process provided in the embodiments of this application;

[0079] Figure 6 This is a schematic diagram of a second LVDS training process provided in an embodiment of this application;

[0080] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0081] Figure 8This is a schematic diagram of the structure of an LVDS communication device provided in an embodiment of this application. Detailed Implementation

[0082] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0083] In related technologies, the line card is connected to multiple daughter cards, and each daughter card can be configured with one or more LVDS components. When communicating with different LVDS components, LVDS training is required to determine the phase difference of each LVDS component before communication, which wastes a considerable amount of time. To solve the above problems, embodiments of this application provide an LVDS communication method, line card, electronic device, and apparatus.

[0084] First, the application scenarios of the embodiments of this application will be described.

[0085] See Figure 1 This is a schematic diagram illustrating the connection relationship between a line card and a sub-card, provided in an embodiment of this application.

[0086] In the diagram, the Field-Programmable Gate Array (FPGA) on the left side of the Complex Programmable Logic Device (CPLD) is a line card, and the N FPGAs on the right side of the CPLD are daughter cards, which are configured with LVDS components. The CPLD is part of the daughter card. It should be noted that the CPLD is not a necessary part; it is only one of the common designs.

[0087] The FPGA, acting as a line card, transmits transmit and clock signals to the CPLD. The gating module in the CPLD determines whether the received transmit and clock signals are intended for itself or for the FPGA. If they are intended for itself, the signal is transmitted to the low-voltage differential signal module in the CPLD. If they are intended for the FPGA, the signal is transmitted to the corresponding FPGA.

[0088] In the CPLD, the low-voltage differential signal module transmits the received signal to the FPGA (which acts as a line card) via a gating module after receiving a signal. Similarly, the LVDS component on the FPGA (acting as a daughter card) also transmits the received signal to the FPGA via a gating module after receiving a signal.

[0089] It should be noted that this application does not limit the specific type of chip used for the line card and daughter card. As long as the line card and daughter card communicate using LVDS as the channel, the solution provided in the embodiments of this application can be applied.

[0090] See Figure 2 This is a flowchart illustrating the first LVDS communication method provided in this application embodiment, used for a line card, including steps S201-S203. The line card stores the correspondence between the identifier of the LVDS component and the phase difference of the LVDS component, and the LVDS component is configured on a daughter card.

[0091] In one embodiment of this application, the identifier of the LVDS component can be the number, name, or starting address of the storage space of the LVDS component. The starting address of each LVDS component is unique in the link, and the line card only records the correspondence between the identifier of the LVDS component and the phase difference of the LVDS component.

[0092] In another embodiment of this application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, with different numbers corresponding to different correspondences. This number can be referred to as the X phase. For example, the correspondence between the identifier of the first completed LVDS training and the phase difference of the LVDS component is numbered 0, i.e., phase 0; the correspondence between the identifier of the second completed LVDS training and the phase difference of the LVDS component is numbered 1, i.e., phase 1, and so on.

[0093] Referring to Table 1, which is a phase difference storage format table provided in the embodiments of this application, the identifier of the LVDS component stored in this storage format is the starting address of the LVDS component, and the corresponding relationship number is X phase.

[0094] Table 1

[0095]

[0096] The starting address is 24 bits long, the X-phase is 3 bits long, and the phase result (i.e., phase difference) is 5 bits long. It should be noted that the length of the X-phase is related to the number of LVDS components. The number of possible values ​​for the X-phase must be greater than or equal to the number of LVDS components. If there are 2 LVDS components, the X-phase length only needs to be greater than or equal to 1 bit; if there are 3-4 LVDS components, the X-phase length only needs to be greater than or equal to 2 bits. In this embodiment, the X-phase is 3 bits, so it can have 8 different values, which can be used to distinguish the correspondence between up to 8 different LVDS components and the phase difference.

[0097] S201: Determine whether the first phase difference corresponding to the target identifier of the target LVDS component to be accessed is stored.

[0098] Specifically, after the line card obtains the target identifier of the target LVDS component to be accessed, it searches for a corresponding relationship containing the target identifier in its own stored correspondence. If a corresponding relationship containing the target identifier is found, the first phase difference corresponding to the target identifier is determined, and step S202 is executed.

[0099] S202: Send a first start frame carrying verification data to the target LVDS component, so that the target LVDS component can feed back the verification data to the line card and determine whether the verification data can be correctly collected from the received data according to the first phase difference.

[0100] The line card sends a first start frame to the target LVDS component via the TX signal and also sends a CLK signal, enabling the target LVDS component to determine the phase of the TX signal based on the CLK signal. Furthermore, the first start frame contains a field with fixed values. By recognizing this field, the target LVDS component can determine the position of the first start frame within the TX signal, and then extract the check data from the TX signal based on the bits of the check data in the first start frame.

[0101] In one embodiment of this application, the first start frame includes at least one of the following fields: first idle code, start flag, second training flag, second operation instruction, start address of the target LVDS component, verification data, second verification code, and second idle code.

[0102] The value of the aforementioned start flag is a preset value, so that the aforementioned target LVDS component determines the data frame as the aforementioned first start frame after receiving the data frame containing the aforementioned start flag and the aforementioned second training flag;

[0103] The second operation instruction is used to instruct the target LVDS component to perform the operation after receiving the first start frame.

[0104] See Table 2, which is a first start frame format table provided in the embodiments of this application.

[0105] Table 2

[0106]

[0107] The length of each field recorded in the table is only an example, and this application embodiment does not limit it.

[0108] The first and second idle codes are fixed codes, sent when the line card is idle. Their codes can be the same or different; for example, the first and second idle codes could be 0x5c.

[0109] The start flag is set to a preset value, such as 0xbc. When the target LVDS component detects this preset value, it can determine that the data here is the start flag, thus identifying this data segment as the first start frame. It then determines that the 32-bit data following the start flag, with a length of 1+8+24=33 bits, is the checksum data. Based on this, the target LVDS component can extract the checksum data.

[0110] The target LVDS component can determine that the received start frame is the first start frame based on the second training flag.

[0111] Different values ​​of the aforementioned second operation instruction instruct the target LVDS component to perform different operations, including an FPGA write operation to control the FPGA as a daughter card to write data, an FPGA read operation to control the FPGA as a daughter card to read data, a CPLD read response to control the CPLD as a daughter card to read data, and a daughter card FPGA load operation to control the FPGA as a daughter card to load data. The value of the second operation instruction controlling the FPGA write operation can be 0x00, the value of the second operation instruction controlling the FPGA read operation can be 0x80, the value of the second operation instruction controlling the CPLD read response can be 0xb0, and the value of the second operation instruction controlling the daughter card FPGA load operation can be 0xcb.

[0112] The second check code can be a CRC (Cyclic Redundancy Check) code or other check codes; there are no restrictions on this.

[0113] Furthermore, after extracting the verification data, the target LVDS component encapsulates the verification data into a normal frame and sends it to the line card. The normal frame also contains a start flag, and the value of the start flag in the normal frame is a fixed value, different from the value of the start flag in the first start frame. Therefore, the line card can determine the phase of the RX signal sent by the target LVDS component based on the first phase difference and the phase of its own multiplied clock, and then identify the start flag contained in the normal frame from the RX signal, thereby determining the position of the start flag. The 32 bits of data following the start flag in the normal frame are then determined to be the verification data. If the verification data extracted by the line card is the same as the transmitted verification data, it indicates that there was no problem in extracting the verification data, the first phase difference is correct, and communication with the target LVDS component can proceed according to the first phase difference, executing step S203.

[0114] S203: Communicate with the target LVDS component according to the first phase difference mentioned above.

[0115] As can be seen from the above, the process first determines whether the line card already stores the first phase difference corresponding to the target LVDS component. If it does, a first start frame is sent to the target LVDS component, causing the target LVDS component to return the verification data in the first start frame. If the line card can correctly acquire the verification data, it indicates that the first phase difference has passed verification, and therefore communication can be directly based on the first phase difference. In this case, before communicating with the target LVDS component, only the sending of the first start frame, the reception of the verification data, and the extraction of the verification data need to be completed, which takes much less time than the time required for LVDS training. Furthermore, verifying the first phase difference can ensure normal communication in most cases. Therefore, the embodiments of this application can save the time consumed by the line card in LVDS training before LVDS communication.

[0116] See Figure 3 This is a flowchart illustrating the second LVDS communication method provided in this application embodiment, which is consistent with the aforementioned... Figure 2 Compared to the illustrated embodiment, if the line card cannot correctly extract the verification data from the received data according to the first phase difference, it indicates that the recorded first phase difference is incorrect, or that the delay between the line card and the target LVDS component has changed, causing a change in the phase difference. Therefore, the originally recorded first phase difference is no longer applicable to the current environment, and it is necessary to redetermine the phase difference between the line card and the target LVDS component. Thus, step S204 is executed. Alternatively, if the line card does not store the first phase difference, step S204 is executed.

[0117] S204: Perform LVDS training on the target LVDS component, determine the second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

[0118] In this application embodiment, LVDS training can be performed using any of the related technologies, or using the following methods. Figure 4 The embodiments shown are used for LVDS training, but this application does not limit the scope of the application.

[0119] Additionally, if the line card has not pre-stored the first phase difference corresponding to the target LVDS component, the correspondence between the target LVDS component's identifier and the second phase difference is directly recorded. If the line card has pre-stored the first phase difference corresponding to the target LVDS component, but the verification data is not correctly extracted according to the first phase difference, the stored first phase difference corresponding to the target LVDS component's identifier is updated to the second phase difference.

[0120] As can be seen from the above, in this embodiment of the application, LVDS training is only required to determine the second phase difference when the first phase difference fails verification or is not stored. Furthermore, after determining the second phase difference, the correspondence between the target LVDS component's identifier and the second phase difference is stored, so that the second phase difference can be used in the next communication with the target LVDS component, saving time consumed in the next communication with the target LVDS component.

[0121] See Figure 4 This is a flowchart illustrating the second LVDS communication method provided in this application embodiment, including the following steps S401-S410.

[0122] S401: The line card is ready to initiate communication with the target LVDS component.

[0123] S402: The line card determines whether it can find the first phase difference corresponding to the target LVDS component based on the starting address of the target LVDS component.

[0124] If the first phase difference can be found, proceed to step S403; if the first phase difference is not found, proceed to step S408.

[0125] S403: The line card adjusts the phase of the frequency multiplier clock inside the line card according to the first phase difference.

[0126] S404: The line card sends the first start frame to the target LVDS component.

[0127] S405: The target LVDS component receives the verification data in the first start frame.

[0128] S406: The target LVDS component sends verification data to the line card.

[0129] S407: Line card checks whether the verification was successful.

[0130] If the verification is successful, proceed to step S410; if the verification fails, proceed to step S408.

[0131] S408: The line card performs LVDS training to obtain the second phase difference.

[0132] S409: The line card records the correspondence between the starting address, X phase, and second phase difference of the target LVDS component.

[0133] S410: The line card and the target LVDS component communicate normally.

[0134] Figure 4 The illustrated embodiments and Figure 2 and Figure 3 The embodiments shown are similar and will not be described again here.

[0135] See Figure 5 This is a schematic diagram of the first LVDS training process provided in the embodiment of this application. The step of performing LVDS training on the target LVDS component and determining the second phase difference corresponding to the target LVDS component is implemented by the following steps S501-S504.

[0136] S501: Send a second start frame to the target LVDS component so that the target LVDS component sends an RX signal to the line card.

[0137] The line card sends a TX signal and a CLK signal carrying a second start frame to the target LVDS component. Since the TX and CLK signals have a fixed timing sequence, the target LVDS component can directly determine the phase and extract data from the TX signal. The second start frame, like the first start frame, contains a start flag with a fixed value. After extracting the start flag from the TX signal, the target LVDS component can determine whether the current frame is the first or second start frame. If it also identifies a second training flag, it determines that the current frame is the second start frame, and then determines to send an RX signal to the line card via the RX signal. The value of the RX signal is a preset fixed value.

[0138] In one embodiment of this application, the second start frame includes at least one of the following fields: first idle code, start flag, first training flag, first operation instruction, start address of the target LVDS component, first checksum, and second idle code;

[0139] The value of the aforementioned start flag is a preset value, so that the target LVDS component can determine the data frame as the first start frame or the second start frame after receiving the data frame containing the aforementioned start flag.

[0140] The aforementioned first training flag is used to indicate that the data frame containing the first training flag is the second starting frame;

[0141] The first operation instruction is used to instruct the target LVDS component to perform the operation after receiving the second start frame.

[0142] The first and second idle codes in the second start frame are the same as those in the first start frame. The first operation instruction in the second start frame is the same as the second operation instruction in the first start frame. Further details will not be provided here.

[0143] The start flag in the second start frame is the same as the start flag in the first start frame. The first training flag in the second start frame is different from the second training flag in the first start frame. Therefore, when the target LVDS component receives a data frame containing a start flag, it can determine whether the data frame is the first start frame or the second start frame. Furthermore, if it carries the first training flag, the data frame is the second start frame, and if it carries the second training flag, the data frame is the first start frame.

[0144] See Table 3, which is a second start frame format table provided in an embodiment of this application.

[0145] Table 3

[0146]

[0147] The length of each field recorded in the table is only an example, and this application embodiment does not limit it.

[0148] S502: Determine the phase of the RX signal according to the training phase difference and the phase of the frequency multiplication clock of the above-mentioned line card. Sample the RX signal at the clock frequency of the frequency multiplication clock according to the phase of the RX signal to obtain the frequency multiplication sequence.

[0149] The initial value of the aforementioned training phase difference is a preset value.

[0150] The clock frequency of the aforementioned frequency-multiplied clock is a preset multiple of the clock frequency of the original clock in the aforementioned line card. Therefore, one original clock cycle of the original clock contains a preset multiple of the frequency-multiplied clock cycles. Since the RX signal sent by the target LVDS component should theoretically remain high or low throughout one original clock cycle, the RX signal level should theoretically remain consistent within a preset number of frequency-multiplied clock cycles belonging to the same original clock cycle, assuming the edges of the CLK signal and RX signal of the line card are aligned.

[0151] Each frequency multiplication sequence contains a preset number of consecutive sub-data points. That is, each sub-data point is the sub-data collected within one frequency multiplication clock cycle. If all sub-data points in a frequency multiplication sequence come from the same original clock cycle, then theoretically, with the edges of the CLK and RX signals of the line card aligned, the values ​​of all sub-data points in the same frequency multiplication sequence should be the same, either all 1 or all 0. Conversely, if there are sub-data points with different values ​​in the same frequency multiplication sequence, then theoretically, the sub-data points with different values ​​will not come from the same original clock cycle. In this case, it indicates that the current training phase difference is not the phase difference between the RX signal of the target LVDS component and the frequency multiplication clock of the line card. The training phase difference needs to be adjusted until the number of sub-data points with the same value in the first preset number of consecutive frequency multiplication sequences reaches the second preset number. Then it can be determined that each of the first preset number of consecutive frequency multiplication sequences theoretically corresponds exactly to one original clock cycle. Therefore, the current training phase difference should be the second phase difference corresponding to the target LVDS component, and step S503 is executed; otherwise, step S504 is executed.

[0152] It should be noted that although theoretically the level of the RX signal will not change within a single original clock cycle, if the level of the RX signal flips between two adjacent original clock cycles, the flip actually takes a relatively short time. Therefore, the level of the RX signal within a single original clock cycle will not remain completely consistent. After dividing a single original clock cycle into a preset number of frequency-multiplying clock cycles, the level within the first frequency-multiplying clock cycle where the level flip occurs within the same original clock cycle may differ from the level within other second frequency-multiplying clock cycles. Consequently, the values ​​of the sub-data corresponding to the first frequency-multiplying clock cycle will differ from those corresponding to the second frequency-multiplying clock cycle. Considering the above, in determining the second phase difference, this application embodiment does not require all sub-data in the frequency multiplication sequence to have the same value; it only requires ensuring that the number of sub-data with the same value reaches a second preset number. For example, if the frequency multiplication clock is 8 times the frequency multiplication clock and the preset multiplication factor is 8, then the second preset number can be 8, 7, 6, etc.

[0153] Furthermore, to ensure the accuracy of the second phase difference detection, the number of consecutive harmonic sequences containing sub-data with the same value that all reach a second preset number must reach a first preset number. For example, the first preset number can be 256, 512, etc. To shorten the LVDS training time, it is not necessary to detect the first preset number of harmonic sequences every time step S502 is executed. Instead, step S504 can be executed directly whenever any harmonic sequence containing sub-data with the same value that is less than the second preset number is detected.

[0154] S503: Determine the current training phase difference as the second phase difference.

[0155] S504: Adjust training phase difference.

[0156] Return to step S502 and continue execution.

[0157] Specifically, the value of the training phase difference can be adjusted randomly, or the value of the training phase difference can be adjusted to the preset candidate values ​​in a fixed order.

[0158] As can be seen from the above, the embodiments of this application acquire a frequency multiplication sequence based on the phase and clock frequency of the frequency multiplication clock, and determine the second phase difference of the target LVDS component according to the value of the sub-data in the frequency multiplication sequence. Based on the determined second phase difference, subsequent communication with the target LVDS component can be carried out.

[0159] See Figure 6 This is a schematic diagram of the second LVDS training process provided in the embodiments of this application. Taking the frequency multiplier clock in the line card as an 8-fold frequency multiplier clock as an example, it includes the following steps S601-S605.

[0160] After training begins, proceed to step S601.

[0161] S601: Samples the RX signal at a clock frequency multiplied by 8.

[0162] S602: Determine whether [7:0] is all 0 or all 1.

[0163] [7:0] represents the sampled frequency harmonic sequence, which contains 8 bits of data, from 0bit to 7bit. In this embodiment, it is required that all sub-data in the frequency harmonic sequence have the same value, that is, the second preset quantity is equal to the preset multiple.

[0164] If yes, proceed to step S603; otherwise, proceed to step S604.

[0165] S603: Increment the counter by 1.

[0166] After executing step S603, continue to execute step S605.

[0167] S604: Count is cleared to zero, and bit sliding signal is adjusted.

[0168] Bitslip, also known as bit sliding, can adjust the training phase difference by adjusting the bit sliding signal.

[0169] After executing step S604, return to execute step S601.

[0170] S605: Has the count reached 256?

[0171] In this embodiment, the first preset quantity is 256.

[0172] If the value reaches 256, the training ends; otherwise, the process returns to step S601.

[0173] Corresponding to the aforementioned LVDS communication method applied to line cards, this application also provides a line card.

[0174] The line card stores the correspondence between the identifier of the Low Voltage Differential Signaling (LVDS) component and the phase difference of the LVDS component. The LVDS component is configured on the daughter card. The line card performs the following steps:

[0175] Determine whether the first phase difference corresponding to the target identifier of the target LVDS component to be accessed is stored;

[0176] If the first phase difference is stored, a first start frame carrying verification data is sent to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference;

[0177] If the verification data can be correctly acquired, then communication is established with the target LVDS component according to the first phase difference.

[0178] As can be seen from the above, the process first determines whether the line card already stores the first phase difference corresponding to the target LVDS component. If it does, a first start frame is sent to the target LVDS component, causing the target LVDS component to return the verification data in the first start frame. If the line card can correctly acquire the verification data, it indicates that the first phase difference has passed verification, and therefore communication can be directly based on the first phase difference. In this case, before communicating with the target LVDS component, only the sending of the first start frame, the reception of the verification data, and the extraction of the verification data need to be completed, which takes much less time than the time required for LVDS training. Furthermore, verifying the first phase difference can ensure normal communication in most cases. Therefore, the embodiments of this application can save the time consumed by the line card in LVDS training before LVDS communication.

[0179] In one embodiment of this application, the line card further performs the following steps:

[0180] If the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, then low voltage differential signal LVDS training is performed on the target LVDS component to determine the second phase difference corresponding to the target LVDS component, and communication is performed with the target LVDS component according to the second phase difference, and the phase difference corresponding to the target identifier is recorded as the second phase difference.

[0181] As can be seen from the above, in this embodiment of the application, LVDS training is only required to determine the second phase difference when the first phase difference fails verification or is not stored. Furthermore, after determining the second phase difference, the correspondence between the target LVDS component's identifier and the second phase difference is stored, so that the second phase difference can be used in the next communication with the target LVDS component, saving time consumed in the next communication with the target LVDS component.

[0182] In one embodiment of this application, the step of performing LVDS training on the target LVDS component to determine the second phase difference corresponding to the target LVDS component includes:

[0183] Send a second start frame to the target LVDS component so that the target LVDS component sends a receive RX signal to the line card;

[0184] The phase of the RX signal is determined according to the training phase difference and the phase of the frequency multiplier clock of the line card. The RX signal is sampled at the clock frequency of the frequency multiplier clock according to the phase of the RX signal to obtain the frequency multiplier sequence. The initial value of the training phase difference is a preset value. The clock frequency of the frequency multiplier clock is a preset multiple of the clock frequency of the original clock in the line card. Each frequency multiplier sequence contains the preset multiple of consecutive sub-data.

[0185] If the number of consecutive frequency-multiply sequences containing the same sub-data with the same value reaches the second preset number, then the current training phase difference is determined to be the second phase difference, and the second preset number is less than or equal to the preset multiple.

[0186] Otherwise, adjust the training phase difference and return to the step of determining the phase of the RX signal according to the training phase difference and the phase of the multiplied clock of the line card, sampling the RX signal according to the clock frequency of the multiplied clock, and obtaining the multiplied sequence.

[0187] As can be seen from the above, the embodiments of this application acquire a frequency multiplication sequence based on the phase and clock frequency of the frequency multiplication clock, and determine the second phase difference of the target LVDS component according to the value of the sub-data in the frequency multiplication sequence. Based on the determined second phase difference, subsequent communication with the target LVDS component can be carried out.

[0188] In one embodiment of this application, the second start frame includes at least one of the following fields: first idle code, start flag, first training flag, first operation instruction, start address of the target LVDS component, first checksum, and second idle code;

[0189] The value of the start flag is a preset value, so that the target LVDS component can determine whether the data frame containing the start flag is the first start frame or the second start frame after receiving the data frame.

[0190] The first training flag is used to indicate that the data frame in which the first training flag is located is the second starting frame;

[0191] The first operation instruction is used to instruct the target LVDS component to perform the operation after receiving the second start frame.

[0192] In one embodiment of this application, the first start frame includes at least one of the following fields: first idle code, start flag, second training flag, second operation instruction, start address of the target LVDS component, verification data, second verification code, and second idle code;

[0193] The value of the start flag is a preset value, so that the target LVDS component determines the data frame as the first start frame after receiving the data frame containing the start flag and the second training flag;

[0194] The second operation instruction is used to instruct the target LVDS component to perform the operation after receiving the first start frame.

[0195] In one embodiment of this application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, with different correspondences corresponding to different numbers.

[0196] Corresponding to the aforementioned LVDS communication method applied to line cards, this application also provides an electronic device.

[0197] See Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device includes:

[0198] Processor 701;

[0199] Transceiver 704;

[0200] Line card 705, wherein the line card 705 stores the correspondence between the identifier of the low voltage differential signal LVDS component and the phase difference of the LVDS component;

[0201] Daughter card 706, wherein an LVDS component is configured on the daughter card 706;

[0202] A machine-readable storage medium 702 stores machine-executable instructions that can be executed by the processor 701;

[0203] The line card 705 implements any of the steps described in the LVDS communication method.

[0204] like Figure 7 As shown, the network device may also include a communication bus 703. The processor 701, machine-readable storage medium 702, and transceiver 704 communicate with each other via the communication bus 703. The communication bus 703 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus 703 can be divided into an address bus, a data bus, a control bus, etc.

[0205] The transceiver 704 can be a wireless communication module. Under the control of the processor 701, the transceiver 704 interacts with other devices for data exchange.

[0206] Machine-readable storage medium 702 may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Alternatively, machine-readable storage medium 702 may also be at least one storage device located remotely from the aforementioned processor.

[0207] The processor 701 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0208] The 705 line card can be used for FPGAs.

[0209] Corresponding to the aforementioned LVDS communication method, this application also provides an LVDS communication device.

[0210] See Figure 8This is a schematic diagram of an LVDS communication device provided in an embodiment of this application, applied to a line card. The line card stores the correspondence between the identifier of a low-voltage differential signal LVDS component and the phase difference of the LVDS component. The LVDS component is configured on a daughter card. The device includes:

[0211] The first phase difference determination module 801 is used to determine whether the first phase difference corresponding to the target identifier of the target LVDS component to be accessed is stored.

[0212] The first start frame sending module 802 is used to send a first start frame carrying verification data to the target LVDS component if the first phase difference is stored, so that the target LVDS component can feed back the verification data to the line card and determine whether the verification data can be correctly collected from the received data according to the first phase difference.

[0213] The first communication module 803 is used to communicate with the target LVDS component according to the first phase difference if the verification data can be correctly acquired.

[0214] As can be seen from the above, the process first determines whether the line card already stores the first phase difference corresponding to the target LVDS component. If it does, a first start frame is sent to the target LVDS component, causing the target LVDS component to return the verification data in the first start frame. If the line card can correctly acquire the verification data, it indicates that the first phase difference has passed verification, and therefore communication can be directly based on the first phase difference. In this case, before communicating with the target LVDS component, only the sending of the first start frame, the reception of the verification data, and the extraction of the verification data need to be completed, which takes much less time than the time required for LVDS training. Furthermore, verifying the first phase difference can ensure normal communication in most cases. Therefore, the embodiments of this application can save the time consumed by the line card in LVDS training before LVDS communication.

[0215] In one embodiment of this application, the apparatus further includes:

[0216] The second communication module is used to perform low-voltage differential signal LVDS training on the target LVDS component if the first phase difference is not stored, or if the verification data cannot be correctly extracted from the received data according to the first phase difference, determine the second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

[0217] As can be seen from the above, in this embodiment of the application, LVDS training is only required to determine the second phase difference when the first phase difference fails verification or is not stored. Furthermore, after determining the second phase difference, the correspondence between the target LVDS component's identifier and the second phase difference is stored, so that the second phase difference can be used in the next communication with the target LVDS component, saving time consumed in the next communication with the target LVDS component.

[0218] In one embodiment of this application, the second phase difference is determined by the following module:

[0219] The second start frame sending module is used to send a second start frame to the target LVDS component so that the target LVDS component sends a receive RX signal to the line card;

[0220] The sequence extraction module is used to determine the phase of the RX signal according to the training phase difference and the phase of the frequency multiplier clock of the line card, and to sample the RX signal at the clock frequency of the frequency multiplier clock according to the phase of the RX signal to obtain a frequency multiplier sequence. The initial value of the training phase difference is a preset value, the clock frequency of the frequency multiplier clock is a preset multiple of the clock frequency of the original clock in the line card, and each frequency multiplier sequence contains the preset multiple of consecutive sub-data.

[0221] The second phase difference determination module is used to determine the current training phase difference as the second phase difference if the sub-data with the same value contained in a first preset number of consecutive frequency harmonic sequences all reach a second preset number, and the second preset number is less than or equal to the preset multiple.

[0222] The phase difference adjustment module is used to adjust the training phase difference and return to trigger the execution of the sequence extraction module if there are no consecutive first preset number of frequency harmonic sequences containing sub-data with the same value that have reached the second preset number.

[0223] As can be seen from the above, the embodiments of this application acquire a frequency multiplication sequence based on the phase and clock frequency of the frequency multiplication clock, and determine the second phase difference of the target LVDS component according to the value of the sub-data in the frequency multiplication sequence. Based on the determined second phase difference, subsequent communication with the target LVDS component can be carried out.

[0224] In one embodiment of this application, the second start frame includes at least one of the following fields: first idle code, start flag, first training flag, first operation instruction, start address of the target LVDS component, first checksum, and second idle code;

[0225] The value of the start flag is a preset value, so that the target LVDS component can determine whether the data frame containing the start flag is the first start frame or the second start frame after receiving the data frame.

[0226] The first training flag is used to indicate that the data frame in which the first training flag is located is the second starting frame;

[0227] The first operation instruction is used to instruct the target LVDS component to perform the operation after receiving the second start frame.

[0228] In one embodiment of this application, the first start frame includes at least one of the following fields: first idle code, start flag, second training flag, second operation instruction, start address of the target LVDS component, verification data, second verification code, and second idle code;

[0229] The value of the start flag is a preset value, so that the target LVDS component determines the data frame as the first start frame after receiving the data frame containing the start flag and the second training flag;

[0230] The second operation instruction is used to instruct the target LVDS component to perform the operation after receiving the first start frame.

[0231] In one embodiment of this application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, with different correspondences corresponding to different numbers.

[0232] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of any of the above-described LVDS communication methods.

[0233] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the LVDS communication methods described above.

[0234] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0235] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0236] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments for line cards, electronic devices, apparatuses, computer-readable storage media, and computer program products are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0237] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. An LVDS communication method, characterized in that, The method, applied to a line card, stores a correspondence between the identifier of a Low Voltage Differential Signaling (LVDS) component and the phase difference of that LVDS component, wherein the LVDS component is configured on a daughter card, includes: Determine whether the first phase difference corresponding to the target identifier of the target LVDS component to be accessed is stored; If the first phase difference is stored, a first start frame carrying verification data is sent to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference; If the verification data can be correctly acquired, then communication is performed with the target LVDS component according to the first phase difference; If the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, then low voltage differential signal LVDS training is performed on the target LVDS component to determine the second phase difference corresponding to the target LVDS component, and communication is performed with the target LVDS component according to the second phase difference, and the phase difference corresponding to the target identifier is recorded as the second phase difference.

2. The method according to claim 1, characterized in that, The step of performing LVDS training on the target LVDS component to determine the second phase difference corresponding to the target LVDS component includes: Send a second start frame to the target LVDS component so that the target LVDS component sends a receive RX signal to the line card; The phase of the RX signal is determined according to the training phase difference and the phase of the frequency multiplier clock of the line card. The RX signal is sampled at the clock frequency of the frequency multiplier clock according to the phase of the RX signal to obtain the frequency multiplier sequence. The initial value of the training phase difference is a preset value. The clock frequency of the frequency multiplier clock is a preset multiple of the clock frequency of the original clock in the line card. Each frequency multiplier sequence contains the preset multiple of consecutive sub-data. If the number of consecutive frequency-multiply sequences containing the same sub-data with the same value reaches the second preset number, then the current training phase difference is determined to be the second phase difference, and the second preset number is less than or equal to the preset multiple. Otherwise, adjust the training phase difference and return to the step of determining the phase of the RX signal according to the training phase difference and the phase of the multiplied clock of the line card, sampling the RX signal according to the clock frequency of the multiplied clock, and obtaining the multiplied sequence.

3. The method according to claim 2, characterized in that, The second start frame contains at least one of the following fields: first idle code, start flag, first training flag, first operation instruction, start address of the target LVDS component, first check code, and second idle code; The value of the start flag is a preset value, so that the target LVDS component can determine whether the data frame containing the start flag is the first start frame or the second start frame after receiving the data frame. The first training flag is used to indicate that the data frame in which the first training flag is located is the second starting frame; The first operation instruction is used to instruct the target LVDS component to perform the operation after receiving the second start frame.

4. The method according to claim 1, characterized in that, The first start frame contains at least one of the following fields: first idle code, start flag, second training flag, second operation instruction, start address of the target LVDS component, verification data, second verification code, and second idle code; The value of the start flag is a preset value, so that the target LVDS component determines the data frame as the first start frame after receiving the data frame containing the start flag and the second training flag; The second operation instruction is used to instruct the target LVDS component to perform the operation after receiving the first start frame.

5. A line card, characterized in that, The line card stores the correspondence between the identifier of the Low Voltage Differential Signaling (LVDS) component and the phase difference of the LVDS component. The LVDS component is configured on the daughter card. The line card performs the following steps: Determine whether the first phase difference corresponding to the target identifier of the target LVDS component to be accessed is stored; If the first phase difference is stored, a first start frame carrying verification data is sent to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference; If the verification data can be correctly acquired, then communication is performed with the target LVDS component according to the first phase difference; If the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, then low voltage differential signal LVDS training is performed on the target LVDS component to determine the second phase difference corresponding to the target LVDS component, and communication is performed with the target LVDS component according to the second phase difference, and the phase difference corresponding to the target identifier is recorded as the second phase difference.

6. An electronic device, characterized in that, The electronic device includes: processor; transceiver; A line card that stores the correspondence between the identifier of a Low Voltage Differential Signaling (LVDS) component and the phase difference of that LVDS component; Daughter card, wherein the daughter card is configured with an LVDS component; A machine-readable storage medium storing machine-executable instructions that can be executed by the processor; The line card implements the steps of the method described in any one of claims 1-4.

7. An LVDS communication device, characterized in that, An application for line cards, wherein the line card stores a correspondence between the identifier of a Low Voltage Differential Signaling (LVDS) component and the phase difference of the LVDS component, the LVDS component being configured on a daughter card, the device comprising: The first phase difference determination module is used to determine whether the first phase difference corresponding to the target identifier of the target LVDS component to be accessed is stored. The first start frame sending module is used to send a first start frame carrying verification data to the target LVDS component if the first phase difference is stored, so that the target LVDS component can feed back the verification data to the line card and determine whether the verification data can be correctly collected from the received data according to the first phase difference. The first communication module is used to communicate with the target LVDS component according to the first phase difference if the verification data can be correctly acquired. The second communication module is used to perform low-voltage differential signal LVDS training on the target LVDS component if the first phase difference is not stored, or if the verification data cannot be correctly extracted from the received data according to the first phase difference, determine the second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-4.

Images