A SiC MOSFET active gate driving method with parallel current sharing function

Abstract

The application relates to a SiC MOSFET active gate driving method with a parallel current sharing function, and relates to the technical field of power electronics. A main-aid double-branch driving structure is adopted, two basic driving modes of main-branch separate enabling and main-aid double-branch simultaneous enabling are provided, the enabling time sequence of the two modes is distributed during the switching process of the device to realize dynamic adjustment of the device, the main device and the controlled device are selected, the device current information sampling moment is obtained, whether the switching delay and the current slope deviation between the main device and the controlled device meet the set threshold value is calculated, the driving is adjusted through the mode of adjusting the simultaneous action time of the main-aid double branch until the deviation is stabilized in the set threshold value range, and the switching delay and the current slope are synchronized. The active gate driving mode effectively adjusts the current balance effect among the parallel SiC MOSFETs, prolongs the service life of the device, and has simple structure and strong adaptability.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically a SiC MOSFET active gate driving method with parallel current sharing function. Background Technology

[0002] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have become a replacement for Si MOSFETs in the field of power electronics due to their higher switching frequency, lower loss and higher voltage withstand capability compared to Si MOSFETs.

[0003] In power electronic devices, multiple SiC MOSFETs are typically connected in parallel to increase the product's power rating. However, when SiC MOSFETs are used in parallel, current imbalance occurs, primarily due to the differences in SiC MOSFET device parameters (V... th C iss g m V miller Dispersion, PCB parasitic parameters (L) s This is caused by asymmetry and inconsistency in the driving signal.

[0004] Traditional solutions focus on pre-screening and selecting devices with good consistency for parallel use, and optimizing PCB layout to improve circuit structure symmetry. However, these methods offer limited improvement and are costly. Active Gate Drive (AGD) technology can address this issue by dynamically adjusting parameters such as drive voltage, current, and gate resistance to regulate the current of each parallel device during switching, providing a new approach to solving current sharing problems. However, existing technologies still face bottlenecks in practical applications due to their complex control architecture and insufficient current imbalance suppression. Summary of the Invention

[0005] To address the problem of poor passive current sharing in existing SiC MOSFET parallel applications, this invention provides an active gate driving method for SiC MOSFETs with parallel current sharing function. Based on active gate driving, it effectively adjusts the current balance between parallel SiC MOSFETs, extends device lifespan, and has a simple structure and strong adaptability.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a SiCMOSFET active gate driving method with parallel current sharing function, comprising the following steps:

[0007] S1. Initialize the simultaneous operation time of the main and auxiliary dual branches.

[0008] Each SiC MOSFET adopts a main-auxiliary dual-branch drive structure, with the drive resistors of the main branch and auxiliary branch respectively expressed as R. main and R aux It indicates that it has two basic driving modes: single main branch enable and simultaneous main-auxiliary dual branch enable. By dynamically allocating the enable timing of the two basic driving modes during the device's turn-on or turn-off process, dynamic adjustment of the device's turn-on or turn-off process can be achieved.

[0009] S2, Extraction of current information from controlled devices

[0010] A SiC MOSFET in one branch of a parallel structure is selected as the master device, and the SiC MOSFET in any other parallel branch is the controlled device. The turn-on times t1 and t2 of the master and controlled devices during the turn-on process, as well as the rise of the drain-source current to the same specified reference value V, are sampled. refe At times t3 and t4, the turn-off times t5 and t6 of the master device and the controlled device during the turn-off process are sampled, and the drain-source current sample value drops to the same specified reference value V. refo The times t7 and t8;

[0011] S3. Synchronization determination of switching delay between master device and controlled device

[0012] Calculate whether the switching delay deviation between the master device and the controlled device meets the set threshold. If it does, the switching delay is considered to be synchronized, and the current slope is determined in S4. Otherwise, the drive is adjusted by adjusting the simultaneous action time of the master and auxiliary dual branches until the deviation is stable within the set threshold range, thus achieving switching delay synchronization.

[0013] S4. Synchronous determination of current slope between master device and controlled device

[0014] Calculate whether the current slope deviation between the master device and the controlled device meets the set threshold. If it does, the current slope is considered to be synchronized and the driving method ends. Otherwise, adjust the driving by adjusting the simultaneous action time of the master and auxiliary dual branches until the deviation stabilizes within the set threshold range to achieve current slope synchronization.

[0015] Furthermore, in step S1, the driving resistor R main and R aux The design steps are as follows:

[0016] The device parameters are determined according to the SiC MOSFET device datasheet, including the threshold voltage V. th Range of variation [V] th +ΔV th1 V th +ΔV th2 Miller voltage V miller Range of variation [V]miller +ΔV miller1 V miller +ΔV miller2 Input capacitor C iss Range of variation [C] iss +ΔC iss1 C iss +ΔC iss2 ] and transconductance g m Range of variation [g] m +Δg m1 ,g m +Δg m2 Define the equivalent drive resistance R during the switching process;

[0017] Calculate the maximum and minimum values ​​ΔR1 and ΔR2 of the equivalent drive resistance R that need to be adjusted during device turn-on delay synchronization, the maximum and minimum values ​​ΔR3 and ΔR4 during device rise current slope synchronization, the maximum and minimum values ​​ΔR5 and ΔR6 during device turn-off delay synchronization, and the maximum and minimum values ​​ΔR7 and ΔR8 during device fall current slope synchronization, when device parameters change. Based on the calculation results, the maximum value among ΔR1, ΔR3, ΔR5, and ΔR7 is taken as the maximum value ΔR that the equivalent drive resistance R needs to be adjusted to. max The minimum value among ΔR2, ΔR4, ΔR6, and ΔR8 is taken as the minimum value ΔR that the equivalent drive resistance R needs to be adjusted to. min Therefore, the driving resistance R is determined. main and R aux The calculation formula is as follows:

[0018]

[0019] Among them, R g The driving resistor value of the main device, ΔR min <0, ΔR max >0.

[0020] Furthermore, the maximum value ΔR1 and minimum value ΔR2 of the equivalent drive resistor R that need to be adjusted during the device turn-on delay synchronization process are calculated using the following formulas:

[0021]

[0022]

[0023] In the formula, V CC To activate the drive voltage value, V EE This is the value of the shut-off drive voltage.

[0024] Furthermore, the maximum value ΔR3 and minimum value ΔR4 of the equivalent drive resistor R that need to be adjusted during the synchronization of the device's rising current slope are calculated using the following formula:

[0025]

[0026]

[0027] In the formula, V CC To enable the drive voltage value, I L L is the total load current. s This is the source parasitic inductance.

[0028] Furthermore, the maximum value ΔR5 and minimum value ΔR6 of the equivalent drive resistor R that need to be adjusted during the device turn-off delay synchronization process are calculated using the following formula:

[0029]

[0030]

[0031] In the formula, V CC To activate the drive voltage value, V EE This is the value of the shut-off drive voltage.

[0032] Furthermore, the maximum value ΔR7 and minimum value ΔR8 of the equivalent drive resistor R that need to be adjusted during the synchronization of the device's current drop slope are calculated using the following formula:

[0033]

[0034]

[0035] In the formula, V EE To turn off the drive voltage value, I L L is the total load current. s This is the source parasitic inductance.

[0036] Furthermore, the method for adjusting the simultaneous operation time of the main and auxiliary branches in step S3 specifically includes:

[0037] When the activation signal arrives, the main and auxiliary branches are simultaneously enabled for a time T. s1 Then, the main branch is enabled independently until the controlled device turns on at time t2; simultaneously, the controller calculates the turn-on delay difference ΔT between the main device and the controlled device. on =t1-t2, if ΔT on If T > T, then the controlled device's turn-on delay phase in the next switching cycle is increased by the PI algorithm. s1 Reduce the turn-on delay of the controlled device; if ΔT onIf T <-T, then the PI algorithm is used to reduce the T of the controlled device during the turn-on delay phase in the next switching cycle. s1 Increase the turn-on delay of the controlled device; otherwise, assume that the turn-on delays of the master device and the controlled device are synchronized.

[0038] When the shutdown signal arrives, the main and auxiliary branches are simultaneously enabled for a time T. s2 Then, the main branch is enabled independently until the controlled device turns off at time t6; simultaneously, the controller calculates the turn-off delay difference ΔT between the main device and the controlled device. off =t5-t6, if ΔT off If T > T, then the controlled device's T is increased during the turn-off delay phase in the next switching cycle using the PI algorithm. s2 Reduce the turn-off delay of the controlled device; if ΔT off If T <-T, then the PI algorithm is used to reduce the T of the controlled device during the turn-off delay phase in the next switching cycle. s2 Increase the turn-off delay of the controlled device; otherwise, assume that the turn-off delays of the master device and the controlled device are synchronized.

[0039] Where T is the control clock period, T s1 The adjustment time of the next switching cycle is satisfied k pon and k ion These are the corresponding P parameters and I parameters, T. s2 The adjustment time of the next switching cycle is satisfied k poff and k ioff These are the corresponding P parameters and I parameters, respectively.

[0040] Furthermore, the method for adjusting the simultaneous operation time of the main and auxiliary branches in step S4 specifically includes:

[0041] At time t2, the simultaneous enabling time T of the main and auxiliary branches is... s3 Then, the main branch enables the controlled device independently until the next shutdown signal arrives. During the turn-on delay synchronization process, T... s3 No adjustments are made until the controller determines that the turn-on delay synchronization is complete. Only then does the controller begin calculating the rise of the sampled drain current values ​​of the master and controlled devices to V. refe Time difference ΔT rise =t3-t4, if ΔT rise If T > T, then the controlled device's T is increased during the current rise phase in the next switching cycle using the PI algorithm. s3 Increase the current rise slope of the controlled device; if ΔT rise If the current is less than or equal to T, then the PI algorithm is used to reduce the T value of the controlled device during the current rise phase in the next switching cycle. s3Reduce the current rise slope of the controlled device; otherwise, assume that the turn-on currents of the master device and the controlled device are synchronized.

[0042] At time t6, the simultaneous enabling time T of the main and auxiliary branches is... s4 Then, the main branch enables the controlled device to turn off until the next turn-on signal arrives. During the turn-off delay synchronization process, T... s4 No adjustments are made until the controller determines that the turn-off delay synchronization is complete. Only then does the controller begin calculating the drain current sampling values ​​of the master and controlled devices as they decrease to V. refo Time difference ΔT fall =t7-t8, if ΔT fall If T > T, then the controlled device's T is increased during the current decrease phase in the next switching cycle using the PI algorithm. s4 Increase the slope of the current drop in the controlled device; if ΔT fall If the current decreases by less than -T, then the PI algorithm is used to reduce the T value of the controlled device during the current decrease phase in the next switching cycle. s4 Reduce the current drop slope of the controlled device; otherwise, it is assumed that the master device and the controlled device have achieved current synchronization during shutdown.

[0043] Where T is the control clock period, T s3 The adjustment time of the next switching cycle is satisfied k prise and k irise These are the corresponding P parameters and I parameters, T. s4 The adjustment time in the next cycle will be satisfied. k pfall and k ifall These are the corresponding P parameters and I parameters, respectively.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows: During the transient process of parallel SiC MOSFET switching, the present invention automatically synchronizes the current of multiple parallel SiC MOSFETs by dynamically adjusting the driving resistor value of the controlled device in segments based on the comparison results of the current information of the master device and the controlled device. This solves the problem of current imbalance caused by inconsistent device parameters, parasitic parameter differences, and changes in driving circuit parameters, and achieves parallel current sharing between the master device and the controlled device. It effectively avoids the risk of device burnout due to overcurrent and extends the service life of the device. It has the advantages of simple structure and strong adaptability, and is suitable for high power density and high efficiency power electronics applications, providing a guarantee for improving the reliability of SiC MOSFETs. Attached Figure Description

[0045] Figure 1 This is a flowchart of the method of the present invention;

[0046] Figure 2 This is a test result diagram of an example. Detailed Implementation

[0047] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0048] A method for driving the active gate of a SiC MOSFET with parallel current sharing function, the process of which is combined with Figure 1 As shown, it includes the following steps:

[0049] S1. Initialize the simultaneous operation time of the main and auxiliary dual branches.

[0050] Each SiC MOSFET adopts a main-auxiliary dual-branch drive structure, with the drive resistors of the main branch and auxiliary branch respectively expressed as R. main and R aux It indicates that it has two basic driving modes: single main branch enable and simultaneous main-auxiliary dual branch enable. By dynamically allocating the enable timing of the two basic driving modes during the device's turn-on or turn-off process, dynamic adjustment of the device's turn-on or turn-off process is achieved, and an equivalent driving resistance R is defined during the switching process.

[0051] Among them, the driving resistor R main and R aux The design steps are as follows:

[0052] The device parameters are determined according to the SiC MOSFET device datasheet, including the threshold voltage V. th Miller voltage V miller Input capacitor C iss and transconductance g m The range of variation of the threshold voltage, wherein the range of variation of the threshold voltage satisfies [V th +ΔV th1 V th +ΔV th2 The Miller voltage variation range satisfies [V miller +ΔV miller1 V miller +ΔV miller2 The range of variation of the input capacitance satisfies [C]. iss +ΔC iss1 C iss +ΔC iss2 The range of transconductance variation satisfies [g] m +Δg m1 ,g m +Δg m2 ];

[0053] The maximum value ΔR1 and minimum value ΔR2 of the equivalent drive resistance R that need to be adjusted during the device turn-on delay synchronization process when the device parameters change are calculated using the following formula:

[0054]

[0055]

[0056] The maximum and minimum values ​​ΔR3 and ΔR4 of the equivalent drive resistance R that need to be adjusted during the synchronization of the device's rising current slope when the device parameters change are calculated using the following formula:

[0057]

[0058]

[0059] The maximum value ΔR5 and minimum value ΔR6 of the equivalent drive resistance R that need to be adjusted during the device turn-off delay synchronization process when the device parameters change are calculated using the following formula:

[0060]

[0061]

[0062] Calculate the maximum value ΔR7 and minimum value ΔR8 of the equivalent drive resistance R that need to be adjusted during the synchronization of the device's current drop slope when the device parameters change. The calculation formula is as follows:

[0063]

[0064]

[0065] In the formula, R g The driving resistor value of the main device, V CC To activate the drive voltage value, V EE To turn off the drive voltage value, I L L is the total load current. s This is the source parasitic inductance.

[0066] Based on the calculation results, the maximum value among ΔR1, ΔR3, ΔR5, and ΔR7 is taken as the maximum value ΔR that the equivalent drive resistance R needs to be adjusted to. max The minimum value among ΔR2, ΔR4, ΔR6, and ΔR8 is taken as the minimum value ΔR that the equivalent drive resistance R needs to be adjusted to. min Therefore, the driving resistance R is determined. main and R aux The calculation formula is as follows:

[0067]

[0068] Where, ΔR min <0, ΔR max >0.

[0069] S2, Extraction of current information from controlled devices

[0070] A SiC MOSFET in one branch of a parallel structure is selected as the master device, and the SiC MOSFETs in any other parallel branch are the controlled devices. During the turn-on process, the turn-on times t1 and t2 of the master and controlled devices are obtained by sampling, and the drain-source current sample value rises to the same specified reference value V. refe At times t3 and t4; similarly, during the turn-off process, the turn-off times t5 and t6 of the master device and the controlled device are obtained through sampling, and the drain-source current sample value drops to the same specified reference value V. refo At times t7 and t8, a total of eight sampling times were acquired.

[0071] S3. Synchronization determination of switching delay between master device and controlled device

[0072] Calculate whether the switching delay deviation between the master device and the controlled device meets the set threshold. If yes, the switching delay is considered synchronized, and proceed to S4 to determine the current slope. Otherwise, adjust the drive by adjusting the simultaneous action time of the master and auxiliary branches until the deviation stabilizes within the set threshold range, thus achieving switching delay synchronization. Specifically:

[0073] Define the control clock period as T. When the enable signal arrives, the main and auxiliary branches are simultaneously enabled for a time T. s1 Then, the main branch is enabled independently until the controlled device turns on at time t2; simultaneously, the controller calculates the turn-on delay difference ΔT between the main device and the controlled device. on =t1-t2, if ΔT on If T >, then the PI algorithm is used to increase the simultaneous enable time T of the main and auxiliary branches of the controlled device during the turn-on delay phase in the next switching cycle. s1 This reduces the turn-on delay of the controlled device; if ΔT on If the value is less than or equal to T, then the PI algorithm is used to reduce the simultaneous enable time T of the main and auxiliary branches of the controlled device during the turn-on delay phase in the next switching cycle. s1 This increases the turn-on delay of the controlled device; otherwise, it is assumed that the master device and the controlled device have achieved turn-on delay synchronization. Wherein, T... s1 The adjustment time of the next switching cycle satisfies the following formula:

[0074]

[0075] In the formula, k pon and k ionThese are the corresponding P parameters and I parameters, respectively;

[0076] When the shutdown signal arrives, the main and auxiliary branches are simultaneously enabled for a time T. s2 Then, the main branch is enabled independently until the controlled device turns off at time t6; simultaneously, the controller calculates the turn-off delay difference ΔT between the main device and the controlled device. off =t5-t6, if ΔT off If T > T, then the PI algorithm is used to increase the simultaneous enable time T of the main and auxiliary branches of the controlled device during the turn-off delay phase in the next switching cycle. s2 This reduces the turn-off delay of the controlled device; if ΔT off If the value is less than or equal to T, then the PI algorithm is used to reduce the simultaneous enable time T of the main and auxiliary branches of the controlled device during the turn-off delay phase in the next switching cycle. s2 This increases the turn-off delay of the controlled device; otherwise, it is assumed that the master device and the controlled device have achieved turn-off delay synchronization. Wherein, T... s2 The adjustment time of the next switching cycle satisfies the following formula:

[0077]

[0078] In the formula, k poff and k ioff These are the corresponding P parameters and I parameters, respectively.

[0079] S4. Synchronous determination of current slope between master device and controlled device

[0080] Calculate whether the current slope deviation between the master device and the controlled device meets the set threshold. If yes, the current slope is considered synchronized, and the driving method ends. Otherwise, adjust the driving by adjusting the simultaneous action time of the master and auxiliary branches until the deviation stabilizes within the set threshold range, thus achieving current slope synchronization. Specifically:

[0081] At time t2, the simultaneous enabling time T of the main and auxiliary branches is... s3 Then, the main branch enables the controlled device independently to ensure reliable turn-on, awaiting the next turn-off signal. During the turn-on delay synchronization process, T s3 No adjustments are made until the controller determines that the turn-on delay synchronization is complete. Only then does the controller begin calculating the rise of the sampled drain current values ​​of the master and controlled devices to V. refe Time difference ΔT rise =t3-t4, if ΔT rise If T >, then the PI algorithm is used to increase the simultaneous enable time T of the main and auxiliary branches of the controlled device during the current rise phase in the next switching cycle. s3 This increases the current rise slope of the controlled device; if ΔT riseIf the current rise time is less than -T, then the PI algorithm is used to reduce the simultaneous enable time T of the main and auxiliary branches of the controlled device during the current rise phase in the next switching cycle. s3 This reduces the current rise slope of the controlled device; otherwise, it is assumed that the master device and the controlled device have achieved current synchronization. Wherein, T... s3 The adjustment time of the next switching cycle satisfies the following formula:

[0082]

[0083] In the formula, k prise and k irise These are the corresponding P parameters and I parameters, respectively;

[0084] At time t6, the simultaneous enabling time T of the main and auxiliary branches is... s4 Then, the main branch enables the controlled device independently to ensure reliable shutdown, awaiting the next turn-on signal. During the shutdown delay synchronization process, T s4 No adjustments are made until the controller determines that the turn-off delay synchronization is complete. Only then does the controller begin calculating the drain current sampling values ​​of the master and controlled devices as they decrease to V. refo Time difference ΔT fall =t7-t8, if ΔT fall If T >, then the PI algorithm is used to increase the simultaneous enable time T of the main and auxiliary branches of the controlled device during the current decrease phase in the next switching cycle. s4 This increases the slope of the current drop in the controlled device; if ΔT fall If the current decreases by less than -T, the PI algorithm is used to reduce the simultaneous enable time T of the main and auxiliary branches of the controlled device during the current decrease phase in the next switching cycle. s4 This reduces the current drop slope of the controlled device; otherwise, it is assumed that the master device and the controlled device have achieved current synchronization during shutdown. Wherein, T... s4 The adjustment time in the next cycle satisfies the following formula:

[0085]

[0086] In the formula, k pfall and k ifall These are the corresponding P parameters and I parameters, respectively.

[0087] Example

[0088] This embodiment uses two SiC MOSFETs connected in parallel to verify the effectiveness of the proposed AGD, with a load inductance L. load =200μH, test conditions were 400V / 40A, test results combined Figure 2 As shown in the figure, I L1 The current flowing through the main branch, I L2 For the current flowing through the controlled branch, U dsThe drain-source voltage of the SiC MOSFET is represented, where a) and b) are the turn-on current waveforms with and without AGD, respectively, and c) and d) are the corresponding turn-off current waveforms.

[0089] To more intuitively illustrate the effectiveness of the proposed AGD, a current sharing factor λ is introduced. The smaller the value, the better the current sharing effect. The formula is as follows:

[0090]

[0091] In the formula, I di I represents the peak current of the i-th branch. davg This represents the average peak current of n branches, where n represents the total number of parallel branches.

[0092] To demonstrate the effectiveness of the proposed AGD under different load conditions, tests were conducted at 400V / 20A, 400V / 40A, and 400V / 60A. The test results are shown in Table 1.

[0093] Table 1. Test results of current sharing factor under different load conditions

[0094]

[0095] The test results above show that the proposed AGD can improve the current sharing capability of parallel SiC MOSFETs under different load conditions.

[0096] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0097] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for driving the active gate of a SiC MOSFET with parallel current sharing function, characterized in that: Includes the following steps: S1. Initialize the simultaneous operation time of the main and auxiliary dual branches. Each SiC MOSFET adopts a main-auxiliary dual-branch drive structure, with the drive resistors of the main branch and auxiliary branch respectively expressed as R. main and R aux It indicates that it has two basic driving modes: single main branch enable and simultaneous main-auxiliary dual branch enable. By dynamically allocating the enable timing of the two basic driving modes during the device's turn-on or turn-off process, dynamic adjustment of the device's turn-on or turn-off process can be achieved. S2, Extraction of current information from controlled devices A SiC MOSFET in one branch of a parallel structure is selected as the master device, and the SiC MOSFET in any other parallel branch is the controlled device. The turn-on times t1 and t2 of the master and controlled devices during the turn-on process, as well as the rise of the drain-source current to the same specified reference value V, are sampled. refe At times t3 and t4, the turn-off times t5 and t6 of the master device and the controlled device during the turn-off process are sampled, and the drain-source current sample value drops to the same specified reference value V. refo The times t7 and t8; S3. Synchronization determination of switching delay between master device and controlled device Calculate whether the switching delay deviation between the master device and the controlled device meets the set threshold. If it does, the switching delay is considered to be synchronized, and the current slope is determined in S4. Otherwise, the drive is adjusted by adjusting the simultaneous action time of the master and auxiliary dual branches until the deviation is stable within the set threshold range, thus achieving switching delay synchronization. S4. Synchronous determination of current slope between master device and controlled device Calculate whether the current slope deviation between the master device and the controlled device meets the set threshold. If it does, the current slope is considered to be synchronized and the driving method ends. Otherwise, adjust the driving by adjusting the simultaneous action time of the master and auxiliary dual branches until the deviation stabilizes within the set threshold range to achieve current slope synchronization.

2. The SiC MOSFET active gate driving method with parallel current sharing function according to claim 1, characterized in that: In step S1, the driving resistor R main and R aux The design steps are as follows: The device parameters are determined according to the SiC MOSFET device datasheet, including the threshold voltage V. th Range of variation [V] th +ΔV th1 V th +ΔV th2 Miller voltage V miller Range of variation [V] miller +ΔV miller1 V miller +ΔV miller2 Input capacitor C iss Range of variation [C] iss +ΔC iss1 C iss +ΔC iss2 ] and transconductance g m Range of variation [g] m +Δg m1 ,g m +Δg m2 Define the equivalent drive resistance R during the switching process; Calculate the maximum and minimum values ​​ΔR1 and ΔR2 of the equivalent drive resistance R that need to be adjusted during device turn-on delay synchronization, during device rise current slope synchronization, during device turn-off delay synchronization, and during device fall current slope synchronization, when device parameters change. Based on the calculation results, the maximum value among ΔR1, ΔR3, ΔR5, and ΔR7 is taken as the maximum value ΔR that the equivalent drive resistance R needs to be adjusted to. max The minimum value among ΔR2, ΔR4, ΔR6, and ΔR8 is taken as the minimum value ΔR that the equivalent drive resistance R needs to be adjusted to. min Therefore, the driving resistance R is determined. main and R aux The calculation formula is as follows: Among them, R g The driving resistor value of the main device, ΔR min <0, ΔR max >0.

3. The SiC MOSFET active gate driving method with parallel current sharing function according to claim 2, characterized in that: The maximum value ΔR1 and minimum value ΔR2 of the equivalent drive resistor R that need to be adjusted during the device turn-on delay synchronization process are calculated using the following formula: In the formula, V CC To activate the drive voltage value, V EE This is the value of the drive voltage to be turned off.

4. The SiC MOSFET active gate driving method with parallel current sharing function according to claim 2, characterized in that: The maximum value ΔR3 and minimum value ΔR4 of the equivalent drive resistor R that need to be adjusted during the synchronization of the device's rising current slope are calculated using the following formula: In the formula, V CC To enable the drive voltage value, I L L is the total load current. s This is the source parasitic inductance.

5. A SiC MOSFET active gate driving method with parallel current sharing function according to claim 2, characterized in that: The maximum value ΔR5 and minimum value ΔR6 of the equivalent drive resistor R that need to be adjusted during the device turn-off delay synchronization process are calculated using the following formula: In the formula, V CC To activate the drive voltage value, V EE This is the value of the drive voltage to be turned off.

6. The SiC MOSFET active gate driving method with parallel current sharing function according to claim 2, characterized in that: The maximum value ΔR7 and minimum value ΔR8 of the equivalent drive resistor R that need to be adjusted during the synchronization of the device's current drop slope are calculated using the following formula: In the formula, V EE To turn off the drive voltage value, I L L is the total load current. s This is the source parasitic inductance.

7. The SiC MOSFET active gate driving method with parallel current sharing function according to claim 1, characterized in that: The specific methods for adjusting the simultaneous operation time of the main and auxiliary dual branches in step S3 include: When the activation signal arrives, the main and auxiliary branches are simultaneously enabled for a time T. s1 Then, the main branch is enabled independently until the controlled device turns on at time t2; simultaneously, the controller calculates the turn-on delay difference ΔT between the main device and the controlled device. on =t1-t2, if ΔT on If T > T, then the controlled device's turn-on delay phase in the next switching cycle is increased by the PI algorithm. s1 Reduce the turn-on delay of the controlled device; if ΔT on If T <-T, then the PI algorithm is used to reduce the T of the controlled device during the turn-on delay phase in the next switching cycle. s1 Increase the turn-on delay of the controlled device; otherwise, assume that the turn-on delays of the master device and the controlled device are synchronized. When the shutdown signal arrives, the main and auxiliary branches are simultaneously enabled for a time T. s2 Then, the main branch is enabled independently until the controlled device turns off at time t6; simultaneously, the controller calculates the turn-off delay difference ΔT between the main device and the controlled device. off =t5-t6, if ΔT off If T > T, then the controlled device's T is increased during the turn-off delay phase in the next switching cycle using the PI algorithm. s2 Reduce the turn-off delay of the controlled device; if ΔT off If T <-T, then the PI algorithm is used to reduce the T of the controlled device during the turn-off delay phase in the next switching cycle. s2 Increase the turn-off delay of the controlled device; otherwise, assume that the turn-off delays of the master device and the controlled device are synchronized. Where T is the control clock period, T s1 The adjustment time of the next switching cycle is satisfied k pon and k ion These are the corresponding P parameters and I parameters, T. s2 The adjustment time of the next switching cycle is satisfied k poff and k ioff These are the corresponding P parameters and I parameters, respectively.

8. A SiC MOSFET active gate driving method with parallel current sharing function according to claim 1, characterized in that: The specific methods for adjusting the simultaneous operation time of the main and auxiliary dual branches in step S4 include: At time t2, the simultaneous enabling time T of the main and auxiliary branches is... s3 Then, the main branch enables the controlled device independently until the next shutdown signal arrives. During the turn-on delay synchronization process, T... s3 No adjustments are made until the controller determines that the turn-on delay synchronization is complete. Only then does the controller begin calculating the rise of the sampled drain current values ​​of the master and controlled devices to V. refe Time difference ΔT rise =t3-t4, if ΔT rise If T > T, then the controlled device's T is increased during the current rise phase in the next switching cycle using the PI algorithm. s3 Increase the current rise slope of the controlled device; if ΔT rise If the current is less than or equal to T, then the PI algorithm is used to reduce the T value of the controlled device during the current rise phase in the next switching cycle. s3 Reduce the current rise slope of the controlled device; otherwise, assume that the turn-on currents of the master device and the controlled device are synchronized. At time t6, the simultaneous enabling time T of the main and auxiliary branches is... s4 Then, the main branch enables the controlled device to turn off until the next turn-on signal arrives. During the turn-off delay synchronization process, T... s4 No adjustments are made until the controller determines that the turn-off delay synchronization is complete. Only then does the controller begin calculating the drain current sampling values ​​of the master and controlled devices as they decrease to V. refo Time difference ΔT fall =t7-t8, if ΔT fall If T > T, then the controlled device's T is increased during the current decrease phase in the next switching cycle using the PI algorithm. s4 Increase the slope of the current drop in the controlled device; if ΔT fall If the current decreases by less than -T, then the PI algorithm is used to reduce the T value of the controlled device during the current decrease phase in the next switching cycle. s4 Reduce the current drop slope of the controlled device; otherwise, it is assumed that the master device and the controlled device have achieved current synchronization during shutdown. Where T is the control clock period, T s3 The adjustment time of the next switching cycle is satisfied k prise and k irise These are the corresponding P parameters and I parameters, T. s4 The adjustment time in the next cycle will be satisfied. k pfall and k ifall These are the corresponding P parameters and I parameters, respectively.

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