A data processing method and a data processing apparatus

Abstract

Embodiments of the present application disclose a data processing method and a data processing device. The method comprises the following steps. n channel data streams are respectively subjected to convolution interleaving to obtain n first data streams. Wherein, n>1, and the n channel data streams all undergo first FEC encoding. Each a code word after the first FEC encoding is distributed in b channel data streams, a≤b≤n, a≥1. z consecutive symbols in each first data stream come from z different code words, z>1. Then, each K first data stream in the n first data streams is multiplexed to obtain one second data stream, to obtain m second data streams in total. Wherein, the n first data streams comprise G first data stream subsets, the symbols in different first data stream subsets come from different code words, m=n / K, K>1, G>1. y consecutive symbols in each second data stream come from y different code words, y>z.

Description

[0001] This application is a divisional application. The original application, application number 202310610144.8, was filed on May 26, 2023. The entire contents of the original application are incorporated herein by reference.

[0002] This application claims priority to Chinese Patent Application No. 202211065772.4, filed on September 1, 2022, entitled "A Data Processing Method and Data Processing Apparatus"; Chinese Patent Application No. 202211305113.3, filed on October 24, 2022, entitled "A Data Processing Method and Data Processing Apparatus"; and Chinese Patent Application No. 202211448533.7, filed on November 18, 2022, entitled "A Data Processing Method and Data Processing Apparatus", the entire contents of which are incorporated herein by application. Technical Field

[0003] This application relates to the field of communications, and more particularly to a data processing method and a data processing apparatus. Background Technology

[0004] Driven by 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTNs) are developing towards higher capacity and ultra-high speed. Using forward error correction (FEC) to correct errors in transmitted data can resolve transmission errors and recover the original data sent by the transmitter from the received data.

[0005] A cascaded FEC transmission scheme is proposed, where the transmitting device and the transmitting processing module are connected via an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data and transmits the second FEC-encoded data to the data receiving end through the channel. Specifically, the transmitting processing module receives multiple data streams and first performs convolutional interleaving on each of the multiple data streams, then performs a second FEC encoding on each of the convolutionally interleaved data streams. It should be understood that to improve performance, the data stream participating in the second FEC encoding should come from multiple codewords after the first FEC encoding; however, this requires the use of convolutional interleaving with a longer latency, which is not ideal for scenarios requiring low latency. Summary of the Invention

[0006] This application provides a data processing method and a data processing apparatus. It can achieve better performance of the cascaded FEC scheme in scenarios requiring low latency.

[0007] Firstly, this application provides a data processing method, which includes the following steps. First, n channel data streams are convolved and interleaved to obtain n first data streams. Here, n is an integer greater than 1, and all n channel data streams undergo first FEC encoding. Each 'a' codeword after first FEC encoding is distributed across b channel data streams, where a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. In each first data stream, z consecutive symbols come from z different codewords, where z is an integer greater than 1. Next, every K first data streams from the n first data streams are multiplexed to obtain one second data stream, resulting in a total of m second data streams. Here, the n first data streams include G subsets of first data streams, where symbols in different subsets come from different codewords, m = n / K, K is an integer greater than 1, and G is an integer greater than 1. In each second data stream, y consecutive symbols come from y different codewords, where y > z. If K ≤ G, then the K first data streams each come from a subset of the K first data streams. If K > G, then the K first data streams include K / G first data streams from each subset of the first data streams.

[0008] In this embodiment, all n-channel data streams are codeword streams encoded with external codes. Convolutional interleaving is then performed on each of the n data streams, and the convolutionally interleaved n data streams are multiplexed into m second data streams, which are then encoded with internal codes. Using the data interleaving and multiplexing processing scheme provided in this application, multiple symbols continuously output from multiple different external codewords in the multiplexed m data streams can be achieved with a shorter latency. This allows the cascaded FEC scheme to reduce data interleaving latency while maintaining good performance. In other words, the combination of convolutional interleaving and data multiplexing in this application results in a lower overall latency for the cascaded FEC scheme, making it more suitable for applications requiring low latency.

[0009] In some possible implementations, convolutionally interleaving a single channel data stream to obtain a first data stream includes: delaying the single channel data stream according to p delay lines to obtain a first data stream. Here, p is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d symbols, z = p * d. The symbols in each channel data stream are sequentially input to the p delay lines according to their sequence numbers. Each delay line inputs d symbols at a time and outputs d symbols at a time. The consecutive p * d symbols in a first data stream include the d symbols output by each delay line. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. This implementation provides a specific method for implementing convolutional interleaving, improving the practicality of this solution.

[0010] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 memory units. Here, d(p*Q+1)≥a*N / b, d≤a, and N is the length of the codeword, thus enabling each first data stream to have z consecutive symbols originating from z different codewords.

[0011] In some possible implementations, the delay line with the smallest sequence number among the p delay lines includes 0 memory units. Here, d(p*Q-1)≥a*N / b, d≤a, and N is the length of the codeword, thus enabling each first data stream to have z consecutive symbols originating from z different codewords.

[0012] In some possible implementations, if K≤G, then y=K*z; if K>G, then y=G*z. This multiplexing approach ensures that y>z can be achieved in multiple different application scenarios, resulting in good performance of the cascaded FEC scheme with low latency.

[0013] In some possible implementations, each second data stream includes multiple subsets of second data stream symbols, each subset comprising K groups of symbols, and each group comprising Δ symbols. Adjacent groups of symbols within each subset of second data stream symbols originate from different subsets of the first data stream. If K ≤ G, then Δ is a divisor of z; if K > G, then Δ = z.

[0014] In this implementation, since adjacent groups of symbols in each second data stream symbol subset come from different first data stream subsets, consecutive y symbols in the multiplexed second data stream come from different y codewords, where y > z (y = K*z or y = G*z). It should be understood that obtaining consecutive y symbols from different y codewords in the output data stream solely through convolutional interleaving requires high latency. However, this solution achieves comparable performance by reducing the time occupied by convolutional interleaving while combining multiplexing. Furthermore, the multiplexing process is shorter, and combining convolutional interleaving and multiplexing allows for comparable performance with even shorter latency.

[0015] In some possible implementations, the j-th group of symbols in each subset of second data stream symbols comes from the j-th first data stream among the K first data streams participating in the multiplexing, where 0 ≤ j ≤ K-1. This provides a rule for selecting the K first data streams participating in the multiplexing, ensuring that adjacent groups of symbols in each subset of second data stream symbols come from different subsets of first data streams.

[0016] In some possible implementations, if K > G, two adjacent first data streams among the K first data streams participating in multiplexing come from different subsets of the first data streams. Through the above method, in the scenario where K > G, a rule for selecting the K first data streams participating in multiplexing is provided, ensuring that y = G*z.

[0017] In some possible implementations, if K > G, each of the G consecutive first data streams participating in the multiplexing comes from a different subset of the first data streams. In the above manner, a rule for selecting the K first data streams participating in the multiplexing is provided in the scenario where K > G, further ensuring y = G*z.

[0018] In some possible implementations, n = 32, and K = 2, 4, or 8. The above approach provides several specific types of multiplexers, expanding the application scenarios of this solution.

[0019] In some possible implementations, n = 32, p = 2, 3, 4, 6 or 8, and d = 1 or 2. The above approach provides several specific types of convolutional interleavers, expanding the application scenarios of this solution.

[0020] In some possible implementations, a = 1 or 2, and b = 4, 8, or 16. The above methods provide several distribution schemes for the channel data stream, expanding the application scenarios of this solution.

[0021] In some possible implementations, before performing convolutional interleaving on the n channel data streams to obtain n first data streams, the method further includes: reordering the n channel data streams so that the n channel data streams are arranged in a preset order.

[0022] In some possible implementations, before convolving and interleaving the n channel data streams to obtain the n first data streams, the method further includes: performing channel skew correction on the n channel data streams. This implementation provides a specific method for channel data alignment, enhancing the feasibility of this solution.

[0023] In some possible implementations, before convolving and interleaving the n channel data streams to obtain n first data streams, the method further includes aligning the n channel data streams to align the symbols within them. This implementation provides another specific method for channel data alignment, enhancing the flexibility of the proposed solution.

[0024] In some possible implementations, after obtaining a total of m second data streams, the method further includes: performing second FEC encoding on each of the m second data streams. The information bit length of the second FEC encoding is less than or equal to y symbols.

[0025] Secondly, this application provides a data processing apparatus. The data processing apparatus includes a convolutional interleaver and a multiplexer. The convolutional interleaver is used to: convolutionally interleave n channel data streams to obtain n first data streams. Here, n is an integer greater than 1, and all n channel data streams are encoded using first FEC. Each 'a' codeword after first FEC encoding is distributed across b channel data streams, where a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. Each first data stream contains z consecutive symbols from z different codewords, where z is an integer greater than 1. The multiplexer is used to: multiplex every K first data streams from the n first data streams to obtain one second data stream, resulting in a total of m second data streams. Here, the n first data streams include G subsets of first data streams, where symbols in different subsets come from different codewords, m = n / K, K is an integer greater than 1, and G is an integer greater than 1. Each second data stream contains y consecutive symbols from y different codewords, where y > z. If K ≤ G, then the K first data streams each come from a subset of the K first data streams. If K > G, then the K first data streams include K / G first data streams from each subset of the first data streams.

[0026] In some possible implementations, the convolutional interleaver is specifically used to: delay one channel data stream according to p delay lines to obtain one first data stream. Here, p is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit is used to store d symbols, z = p * d. The symbols in each channel data stream are sequentially input to the p delay lines according to their sequence numbers. Each delay line inputs d symbols at a time and outputs d symbols at a time. The consecutive p * d symbols in one first data stream include the d symbols output by each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0027] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 memory units, where d(p*Q+1)≥a*N / b, N is the length of the codeword, and d≤a.

[0028] In some possible implementations, the delay line with the smallest sequence number among the p delay lines includes 0 memory units, where d(p*Q-1)≥a*N / b, N is the length of the codeword, and d≤a.

[0029] In some possible implementations, if K≤G, then y=K*z; if K>G, then y=G*z.

[0030] In some possible implementations, each second data stream includes multiple subsets of second data stream symbols, each subset comprising K groups of symbols, and each group comprising Δ symbols. Adjacent groups of symbols within each subset of second data stream symbols originate from different subsets of the first data stream. If K ≤ G, then Δ is a divisor of z; if K > G, then Δ = z.

[0031] In some possible implementations, the j-th group of symbols in each subset of second data stream symbols comes from the j-th first data stream among the K first data streams participating in the multiplexing, where 0 ≤ j ≤ K-1.

[0032] In some possible implementations, if K > G, two adjacent first data streams among the K first data streams participating in the multiplexing come from different subsets of the first data streams.

[0033] In some possible implementations, if K > G, each of the G consecutive first data streams participating in the multiplexing comes from a different subset of the first data streams.

[0034] In some possible implementations, n = 32, K = 2, 4, or 8.

[0035] In some possible implementations, n = 32, p = 2, 3, 4, 6 or 8, and d = 1 or 2.

[0036] In some possible implementations, a = 1 or 2, b = 4, 8, or 16.

[0037] In some possible implementations, the data processing apparatus further includes a channel reordering unit. Before convolving and interleaving the n channel data streams to obtain n first data streams, the channel reordering unit is used to: reorder the n channel data streams so that the n channel data streams are arranged in a preset order.

[0038] In some possible implementations, the data processing apparatus further includes a channel data alignment unit, which is used to perform channel correction on the n channel data streams before convolutionally interleaving the n channel data streams to obtain n first data streams.

[0039] In some possible implementations, the data processing apparatus further includes a channel data alignment unit. Before convolving and interleaving the n channel data streams to obtain n first data streams, the channel data alignment unit is used to: align the n channel data streams so that the symbols in the n channel data streams are aligned.

[0040] In some possible implementations, the data processing apparatus further includes an encoder, which, after obtaining a total of m second data streams, performs second FEC encoding on each of the m second data streams, wherein the information bit length of the second FEC encoding is less than or equal to y symbols.

[0041] Thirdly, this application provides a data processing method, which includes the following steps: Interleaving n channel data streams to obtain m target data streams, where n is a multiple of 4. All n channel data streams undergo first forward error correction (FEC) coding. Each 'a' codeword after the first FEC coding is distributed across b channel data streams, where a ≤ b ≤ n, and n is divisible by b. In each target data stream, F consecutive symbols come from F different codewords, where F > a. In each target data stream, the F consecutive symbols come from at least K1 different channel data streams. In each target data stream, the F consecutive symbols come from at most K2 symbols among the n symbols aligned with the n channel data streams, where K1 and K2 are divisors of n, and K2 is a divisor of K1. In each target data stream, at most K3 symbols among the F consecutive symbols come from the same channel data stream. It represents the integer obtained by rounding up the quotient of F / K1. Any two symbols in the K3 symbols are separated by at least K4 symbols on the same channel data stream, where K4≥a*N*K2 / n, and N is the codeword length.

[0042] In some possible implementations, K1 = n / 4, K2 = n / 16.

[0043] In some possible implementations, interleaving n channel data streams to obtain m target data streams includes: performing convolutional interleaving on the n channel data streams to obtain n first data streams. In each first data stream, z consecutive symbols come from at least e different codewords, where z is an integer greater than 1, a ≤ e ≤ F, and e*k2 ≥ F. In each first data stream, at most k1 / k2 consecutive symbols come from the same codeword. Each K1 first data stream in the n first data streams is grouped and interleaved to obtain S target data streams, resulting in a total of m target data streams. Here, S is an integer greater than or equal to 1, m = S*n / K1, S ≥ k1 / k2, and the n first data streams include K1 first data stream groups. Within the same first data stream group, the symbols of every two first data streams come from the same codeword, and the K1 first data streams each come from one of the K1 first data stream groups.

[0044] In some possible implementations, convolutionally interleaving a single channel data stream to obtain a first data stream includes: delaying the single channel data stream according to p delay lines to obtain a first data stream. p is an integer greater than 1, p*a ≥ F / k², each delay line includes a different number of storage units, the delay line with the fewest storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit stores d symbols, z = p*d. The symbols in each channel data stream are sequentially input to the p delay lines according to their sequence numbers. Each delay line inputs d symbols at a time and outputs d symbols at a time. The consecutive p*d symbols in a first data stream include the d symbols output by each delay line, Q is an integer greater than or equal to 1, d is an integer greater than or equal to 1, and d ≤ a.

[0045] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 memory cells, where d(p*Q+1)≥K4.

[0046] In some possible implementations, the delay line with the smallest index among the p delay lines includes 0 memory cells, where d(p*Q-1)≥K4.

[0047] In some possible implementations, the K first data streams participating in the packet interleaving include a first symbol matrix, which comprises K rows and B columns of symbols, where B = R * p * d, and R is an integer greater than or equal to 1. The S target data streams after the packet interleaving include a second symbol matrix, which comprises S rows and F columns of symbols, where K * B = S * F. The symbols in the first symbol matrix come from at least F different codewords, and at most R * K1 / K2 symbols in the first symbol matrix come from the same codeword.

[0048] In some possible implementations, the F symbols in each row of the second symbol matrix are drawn from at least the first symbol matrix. column, and Each column can contain at most K2 symbols. This represents the integer obtained by rounding up the quotient of F / K2. The F symbols in each row of the second symbol matrix include at least the symbols in each row of the first symbol matrix. A symbol, Let F represent the integer obtained by rounding down the quotient of F / K1, where the F symbols in each row of the second symbol matrix include at most the symbols in each row of the first symbol matrix. A symbol, This represents the integer obtained by rounding up the quotient of F / K.

[0049] In some possible implementations, symbols from odd-numbered columns of the first symbol matrix in each row of the second symbol matrix are located in different rows of the first symbol matrix. Symbols from even-numbered columns of the first symbol matrix in each row of the second symbol matrix are located in different rows of the first symbol matrix.

[0050] In some possible implementations, the symbols output by delay lines with the same delay value in each row of the second symbol matrix come from different rows of the first symbol matrix.

[0051] In some possible implementations, at most K3 symbols in each row of the second symbol matrix come from the same row of the first symbol matrix, and any two of the K3 symbols are output by two delay lines with a delay difference greater than or equal to 2*Q*d.

[0052] In some possible implementations, interleaving n channel data streams to obtain m target data streams includes: performing a first group interleaving on the n channel data streams to obtain T first data streams, where each first data stream contains C consecutive symbols from at least E different codewords, T = n / K1, C is a multiple of a, and E ≥ K2 * a. Performing convolutional interleaving on the T first data streams to obtain T second data streams, where each second data stream contains H consecutive symbols from at least F different codewords, F ≥ E, and at most K1 / K2 consecutive symbols from the same codeword in each second data stream. Performing a second group interleaving on each of the T second data streams to obtain S target data streams, resulting in a total of m target data streams, m = T * S, and S ≥ k1 / K2.

[0053] In some possible implementations, the n channel data streams participating in the first group interleaving include a third symbol matrix, which comprises n rows and A columns of symbols, where A is a multiple of a. The T first data streams after the first group interleaving include a fourth symbol matrix, which comprises T rows and C columns of symbols, where T is a divisor of n, and n*A = T*C. Every T consecutive symbols in a column of the third symbol matrix constitutes a symbol submatrix, and the T symbols in each column of the fourth symbol matrix correspond one-to-one with each symbol submatrix in the third symbol matrix.

[0054] In some possible implementations, the symbol submatrices in the third symbol matrix are arranged in a first order. The first row to the nth row of each column in the third symbol matrix includes the first to the n / Tth symbol submatrices arranged in the first order. The n / Tth symbol submatrices in the first column to the first symbol submatrices in the next column of the third symbol matrix are two consecutive symbol submatrices arranged in the first order. The T symbols in the first column of the fourth symbol matrix come from the first symbol submatrice arranged in the first order in the third symbol matrix, and so on, until the T symbols in the Cth column of the fourth symbol matrix come from the last symbol submatrice arranged in the first order in the third symbol matrix. Alternatively, the symbolic submatrices in the third symbolic matrix are arranged in the second order. The first column to the Ath row of each T row in the third symbolic matrix includes the first to the Ath symbolic submatrices arranged in the second order. The first to the first symbolic submatrices of the first T rows of two consecutive T rows of the third symbolic matrix are two consecutive symbolic submatrices arranged in the second order. The T symbols in the first column of the fourth symbolic matrix come from the first symbolic submatrices arranged in the second order in the third symbolic matrix, and so on, until the T symbols in the Cth column of the fourth symbolic matrix come from the last symbolic submatrices arranged in the second order in the third symbolic matrix.

[0055] In some possible implementations, convolving and interleaving a first data stream to obtain a second data stream includes: delaying a first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, p*E≥F, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store C symbols, p*C=H, the symbols in each first data stream are sequentially input to p delay lines according to the sequence number of the p delay lines, each delay line inputs C symbols at a time and outputs C symbols at a time, and the consecutive p*C symbols in a second data stream include the C symbols output by each delay line, where Q is an integer greater than or equal to 1.

[0056] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 memory cells, where C(p*Q+1)≥K1*K4.

[0057] In some possible implementations, the delay line with the smallest sequence number among the p delay lines includes 0 memory cells, where C(p*Q-1)≥K1*K4.

[0058] In some possible implementations, each second data stream includes R symbol sets, each symbol set includes p symbol subsets, each symbol subset includes C symbols, the p symbol subsets are output by p delay lines respectively, the symbols in each symbol set come from at least F different codewords, each target data stream includes F symbols, R*p*C = S*F, where R is an integer greater than or equal to an integer. The F symbols in the target data stream come from at least... A distinct subset of symbols, and Each of the three distinct symbol subsets contains at most K²*a symbols. This represents the integer obtained by rounding up the quotient of F / (K2*a).

[0059] In some possible implementations, the F symbols in the target data stream include a first set of symbols from a first subset of symbols and a second set of symbols from a second subset of symbols. The first and second subsets of symbols belong to the same symbol set. The first and second subsets of symbols are output from two adjacent delay lines, respectively. The symbols in the first and second subsets of symbols are arranged in order, and the order of the first set of symbols in the first subset is different from the order of the second set of symbols in the second subset. The F symbols in the target data stream also include a third set of symbols from a third subset of symbols and a fourth set of symbols from a fourth subset of symbols. The third and fourth subsets of symbols belong to different symbol sets. The third and fourth subsets of symbols are output from the same delay line, and the symbols in the third and fourth subsets of symbols are arranged in order, respectively. The order of the third set of symbols in the third subset is different from the order of the fourth set of symbols in the fourth subset.

[0060] In some possible implementations, each target data stream contains at most F symbols. The symbols come from the same set of symbols. This represents the integer obtained by rounding up the quotient of F / R.

[0061] In some possible implementations, after obtaining a total of m target data streams, the method further includes: performing a second FEC encoding on each of the m target data streams, wherein the information bit length of the second FEC encoding is equal to F symbols.

[0062] Fourthly, this application provides a data processing apparatus, which includes an interleaving module. The interleaving module is used to: interleave n channel data streams to obtain m target data streams, where n is a multiple of 4. All n channel data streams undergo first forward error correction (FEC) coding. Each 'a' codeword after the first FEC coding is distributed across b channel data streams, where a ≤ b ≤ n, and n is divisible by b. In each target data stream, F consecutive symbols come from F different codewords, where F > a. In each target data stream, the F consecutive symbols come from at least K1 different channel data streams. In each target data stream, the F consecutive symbols come from at most K2 symbols among the n symbols aligned with the n channel data streams, where K1 and K2 are divisors of n, and K2 is a divisor of K1. In each target data stream, at most K3 symbols among the F consecutive symbols come from the same channel data stream. It represents the integer obtained by rounding up the quotient of F / K1. Any two symbols in the K3 symbols are separated by at least K4 symbols on the same channel data stream, where K4≥a*N*K2 / n, and N is the codeword length.

[0063] In some possible implementations, K1 = n / 4, K2 = n / 16.

[0064] In some possible implementations, the interleaving module includes a convolutional interleaver and a group interleaver. The convolutional interleaver is used to: convolutionally interleave n channel data streams to obtain n first data streams, where each first data stream contains z consecutive symbols from at least e different codewords, where z is an integer greater than 1, a ≤ e ≤ F, e*k2 ≥ F, and at most k1 / k2 symbols in each first data stream come from the same codeword. The group interleaver is used to: group and interleave every K1 first data streams from the n first data streams to obtain S target data streams, resulting in a total of m target data streams, where S is an integer greater than or equal to 1, m = S*n / K1, S ≥ k1 / k2, the n first data streams include K1 first data stream groups, and the symbols of every two first data streams within the same first data stream group come from the same codeword; the K1 first data streams each come from K1 first data stream groups.

[0065] In some possible implementations, the convolutional interleaver is specifically used to: delay one channel data stream according to p delay lines to obtain one first data stream, where p is an integer greater than 1, p*a≥F / k2, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store d symbols, z=p*d. The symbols in each channel data stream are sequentially input into p delay lines according to the sequence number of the p delay lines, each delay line inputs d symbols at a time and outputs d symbols at a time, and the consecutive p*d symbols in one first data stream include the d symbols output by each delay line, where Q is an integer greater than or equal to 1, d is an integer greater than or equal to 1, and d≤a.

[0066] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 memory cells, where d(p*Q+1)≥K4.

[0067] In some possible implementations, the delay line with the smallest index among the p delay lines includes 0 memory cells, where d(p*Q-1)≥K4.

[0068] In some possible implementations, the K first data streams participating in the packet interleaving include a first symbol matrix, which comprises K rows and B columns of symbols, where B = R * p * d, and R is an integer greater than or equal to 1. The S target data streams after the packet interleaving include a second symbol matrix, which comprises S rows and F columns of symbols, where K * B = S * F. The symbols in the first symbol matrix come from at least F different codewords, and at most R * K1 / K2 symbols in the first symbol matrix come from the same codeword.

[0069] In some possible implementations, the F symbols in each row of the second symbol matrix are drawn from at least the first symbol matrix. column, and Each column can contain at most K2 symbols. This represents the integer obtained by rounding up the quotient of F / K2. The F symbols in each row of the second symbol matrix include at least the symbols in each row of the first symbol matrix. A symbol, Let F represent the integer obtained by rounding down the quotient of F / K1, where the F symbols in each row of the second symbol matrix include at most the symbols in each row of the first symbol matrix. A symbol, This represents the integer obtained by rounding up the quotient of F / K.

[0070] In some possible implementations, symbols from odd-numbered columns of the first symbol matrix in each row of the second symbol matrix are located in different rows of the first symbol matrix, and symbols from even-numbered columns of the first symbol matrix in each row of the second symbol matrix are located in different rows of the first symbol matrix.

[0071] In some possible implementations, the symbols output by delay lines with the same delay value in each row of the second symbol matrix come from different rows of the first symbol matrix.

[0072] In some possible implementations, at most K3 symbols in each row of the second symbol matrix come from the same row of the first symbol matrix, and any two of the K3 symbols are output by two delay lines with a delay difference greater than or equal to 2*Q*d.

[0073] In some possible implementations, the convolutional interleaving module includes a first group interleaver, a convolutional interleaver, and a second group interleaver. The first group interleaver is used to: perform first group interleaving on n channel data streams to obtain T first data streams, where each first data stream contains C consecutive symbols from at least E different codewords, T = n / K1, C is a multiple of a, and E ≥ K2 * a. The convolutional interleaver is used to: perform convolutional interleaving on the T first data streams to obtain T second data streams, where each second data stream contains H consecutive symbols from at least F different codewords, F ≥ E, and at most K1 / K2 consecutive symbols from the same codeword in each second data stream. The second group interleaver is used to: perform second group interleaving on each of the T second data streams to obtain S target data streams, resulting in a total of m target data streams, m = T * S, and S ≥ k1 / K2.

[0074] In some possible implementations, the n channel data streams participating in the first group interleaving include a third symbol matrix, which comprises n rows and A columns of symbols, where A is a multiple of a. The T first data streams after the first group interleaving include a fourth symbol matrix, which comprises T rows and C columns of symbols, where T is a divisor of n, and n*A = T*C. Every T consecutive symbols in a column of the third symbol matrix constitutes a symbol submatrix, and the T symbols in each column of the fourth symbol matrix correspond one-to-one with each symbol submatrix in the third symbol matrix.

[0075] In some possible implementations, the symbol submatrices in the third symbol matrix are arranged in a first order. The first row to the nth row of each column in the third symbol matrix includes the first to the n / Tth symbol submatrices arranged in the first order. The n / Tth symbol submatrices in the first column to the first symbol submatrices in the next column of the third symbol matrix are two consecutive symbol submatrices arranged in the first order. The T symbols in the first column of the fourth symbol matrix come from the first symbol submatrice arranged in the first order in the third symbol matrix, and so on, until the T symbols in the Cth column of the fourth symbol matrix come from the last symbol submatrice arranged in the first order in the third symbol matrix. Alternatively, the symbolic submatrices in the third symbolic matrix are arranged in the second order. The first column to the Ath row of each T row in the third symbolic matrix includes the first to the Ath symbolic submatrices arranged in the second order. The first to the first symbolic submatrices of the first T rows of two consecutive T rows of the third symbolic matrix are two consecutive symbolic submatrices arranged in the second order. The T symbols in the first column of the fourth symbolic matrix come from the first symbolic submatrices arranged in the second order in the third symbolic matrix, and so on, until the T symbols in the Cth column of the fourth symbolic matrix come from the last symbolic submatrices arranged in the second order in the third symbolic matrix.

[0076] In some possible implementations, the convolutional interleaver is specifically used to: delay a first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, p*E≥F, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store C symbols, p*C=H. The symbols in each first data stream are sequentially input into p delay lines according to the sequence number of the p delay lines, each delay line inputs C symbols at a time and outputs C symbols at a time, and the consecutive p*C symbols in a second data stream include the C symbols output by each delay line, where Q is an integer greater than or equal to 1.

[0077] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 memory cells, where C(p*Q+1)≥K1*K4.

[0078] In some possible implementations, the delay line with the smallest sequence number among the p delay lines includes 0 memory cells, where C(p*Q-1)≥K1*K4.

[0079] In some possible implementations, each second data stream includes R symbol sets, each symbol set includes p symbol subsets, each symbol subset includes C symbols, the p symbol subsets are output by p delay lines respectively, the symbols in each symbol set come from at least F different codewords, each target data stream includes F symbols, R*p*C = S*F, where R is an integer greater than or equal to an integer. The F symbols in the target data stream come from at least... A distinct subset of symbols, and Each of the three distinct symbol subsets contains at most K²*a symbols. This represents the integer obtained by rounding up the quotient of F / (K2*a).

[0080] In some possible implementations, the F symbols in the target data stream include a first set of symbols from a first subset of symbols and a second set of symbols from a second subset of symbols. The first and second subsets of symbols belong to the same symbol set. The first and second subsets of symbols are output from two adjacent delay lines, respectively. The symbols in the first and second subsets of symbols are arranged in order, and the order of the first set of symbols in the first subset is different from the order of the second set of symbols in the second subset. The F symbols in the target data stream also include a third set of symbols from a third subset of symbols and a fourth set of symbols from a fourth subset of symbols. The third and fourth subsets of symbols belong to different symbol sets. The third and fourth subsets of symbols are output from the same delay line, and the symbols in the third and fourth subsets of symbols are arranged in order, respectively. The order of the third set of symbols in the third subset is different from the order of the fourth set of symbols in the fourth subset.

[0081] In some possible implementations, each target data stream contains at most F symbols. The symbols come from the same set of symbols. This represents the integer obtained by rounding up the quotient of F / R.

[0082] In some possible implementations, the data processing apparatus further includes an encoder, which, after obtaining a total of m target data streams, performs a second FEC encoding on each of the m target data streams, wherein the information bit length of the second FEC encoding is equal to F symbols.

[0083] Fifthly, this application provides a data processing method, which includes the following steps. First, each t channel data stream in n channel data streams is grouped and interleaved to obtain s first data streams, resulting in a total of m first data streams. n = q * t, m = q * s, where n is an integer greater than 1, n is divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. All n channel data streams undergo first forward error correction (FEC) coding. Each a codeword after the first FEC coding is distributed in b channel data streams, where a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. Each consecutive a symbols in each channel data stream come from a different codeword, and each consecutive L1 symbols in each channel data stream come from at least a different codeword, L1 = N * a / b, where N represents the length of the codeword. The t-channel data streams each consist of 'a' consecutive symbols, totaling t*a symbols. Each t*a symbol contains Δ bits, totaling D bits, where D = Δ*t*a. These D bits are consecutive in any one of the s first data streams, and Δ = M / s, where M represents the number of bits in a symbol. Then, the m first data streams are convolved and interleaved to obtain m second data streams.

[0084] In some possible implementations, each consecutive d symbols in each of the first data streams comes from v different codewords, and each consecutive L2 symbols in each of the first data streams comes from at least v different codewords, where v is divisible by a, L2 = t / s * L1, and d = D / M.

[0085] In some possible implementations, n = 32, the 16 odd-numbered data streams in the n-channel data streams come from the same codeword, the 16 even-numbered data streams in the n-channel data streams come from the same codeword, and the data streams in the odd-numbered channels and the data streams in the even-numbered channels in the n-channel data streams come from different codewords.

[0086] In some possible implementations, where t = 2 and s = 1, grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving the 2*i-th channel data stream and the 2*i+1-th channel data stream to obtain 1 first data stream, where 0 ≤ i < 16. Two consecutive symbols in the 2*i-th channel data stream and two consecutive symbols in the 2*i+1-th channel data stream are consecutive in the 1 first data stream obtained by grouping and interleaving, and every four consecutive symbols in the 1 first data stream obtained by grouping and interleaving come from four different codewords.

[0087] In some possible implementations, the j-th bit in a first data stream resulting from the packet interleaving comes from the first bit. The first of 20 consecutive bits in the channel data stream bits, the This indicates rounding down, where 0 ≤ j < 40, and β is 1, 2, 4, 5, 10, or 20.

[0088] In some possible implementations, t=2, s=1, and grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving the 2*i-th channel data stream and the 2*i+1-th channel data stream to obtain 1 first data stream, where 0≤i<16. The j-th group of consecutive β bits in the 2*i-th channel data stream and the j-th group of consecutive β bits in the 2*i+1-th channel data stream are consecutive in the 1 first data stream obtained by grouping and interleaving, where j≥0, and β is 1, 2, 4, 5, 10, or 20. Each consecutive 4 symbols in the 1 first data stream obtained by grouping and interleaving come from 4 different codewords.

[0089] In some possible implementations, t=2, s=2, and grouping and interleaving each t channel data stream in the n channel data streams to obtain s first data streams includes: grouping and interleaving the 2*i channel data stream and the 2*i+1 channel data stream to obtain the 2*i first data stream and the 2*i+1 first data stream, where 0≤i<16. Two consecutive symbols from the 2*i channel data stream and two consecutive symbols from the 2*i+1 channel data stream, totaling 20 bits, are consecutive in the 2*i first data stream. Each consecutive 20 bits in the 2*i first data stream comes from 4 different codewords. The other 5 bits from each of the four symbols (two consecutive symbols from the 2*i channel data stream and two consecutive symbols from the 2*i+1 channel data stream), totaling 20 bits, are consecutive in the 2*i+1 first data stream. Each consecutive 20 bits in the 2*i+1 first data stream comes from 4 different codewords.

[0090] In some possible implementations, the f-th bit in the 20 consecutive bits of the first data stream of the 2*i+g-th bit comes from the first... The first of 20 consecutive bits in the channel data stream 10 bits, 0≤f<20, 0≤g<2.

[0091] In some possible implementations, the f-th bit in the 20 consecutive bits of the first data stream of the 2*i+g-th bit comes from the first... The first of 20 consecutive bits in the channel data stream 10 bits, 0≤f<20, 0≤g<2.

[0092] In some possible implementations, t = 4, s = 1, and grouping and interleaving each t channel data stream in the n channel data streams to obtain s first data streams includes: grouping and interleaving the 4*i, 4*i+1, 4*i+2, and 4*i+3 channel data streams (a total of 4 channel data streams) to obtain 1 first data stream, where 0 ≤ i ≤ 7, and each of the 4 channel data streams includes 8 consecutive symbols (2 symbols in total) in the grouped and interleaved first data stream. In the first data stream obtained by the group interleaving, every consecutive 8 symbols come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords, and the 4th, 5th, 6th, and 7th symbols in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords.

[0093] In some possible implementations, t=4, s=1, and grouping and interleaving each t channel data stream in the n channel data streams to obtain s first data streams includes: grouping and interleaving the 4*i, 4*i+1, 4*i+2, and 4*i+3 channel data streams (a total of 4 channel data streams) to obtain 1 first data stream, where 0≤i≤7. In each of the 4 channel data streams, the j-th group of 2 consecutive symbols (a total of 8 symbols) is consecutive in the 1 first data stream obtained by grouping and interleaving. Each of the 4 channel data streams includes... The j-th group of two consecutive symbols are consecutive in the first data stream obtained by the group interleaving, j≥0. In the first data stream obtained by the group interleaving, every 8 consecutive symbols come from at least 4 different codewords, and every 272 consecutive symbols come from at least 4 different codewords. In the first data stream obtained by the group interleaving, the 0th, 1st, 2nd, and 3rd symbols in every 8 consecutive symbols come from different codewords. In the first data stream obtained by the group interleaving, the 4th, 5th, 6th, and 7th symbols in every 8 consecutive symbols come from different codewords.

[0094] In some possible implementations, t=4, s=1, and grouping and interleaving each t channel data stream in the n channel data streams to obtain s first data streams includes: grouping and interleaving the 4th*i channel data stream, the 4th*i+1 channel data stream, the 4th*i+2 channel data stream, and the 4th*i+3 channel data stream to obtain 1 first data stream, 0≤i≤7, where the j-th symbol in each of the 4 channel data streams is consecutive in the 1 first data stream obtained by grouping and interleaving, j≥0, and every 4 consecutive symbols in the 1 first data stream obtained by grouping and interleaving come from 4 different codewords.

[0095] In some possible implementations, t = 8, s = 1, and grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving 8 channel data streams (8*i, 8*i+1, 8*i+2, 8*i+3, 8*i+4, 8*i+5, 8*i+6, and 8*i+7) to obtain 1 first data stream, where 0 ≤ i ≤ 3. Each of the 8 channel data streams includes 16 consecutive symbols (2 symbols each) that are consecutive in the grouped and interleaved first data stream. Each consecutive 16 symbols in the grouped and interleaved first data stream comes from at least 4... The first data stream obtained by the group interleaving consists of 544 consecutive symbols from at least 4 different codewords. Specifically, the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving are from different codewords.

[0096] In some possible implementations, where t = 8 and s = 1, grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes:

[0097] Eight data streams (channels 8*i, 8*i+1, 8*i+2, 8*i+3, 8*i+4, 8*i+5, 8*i+6, and 8*i+7) are grouped and interleaved to obtain a first data stream, where 0 ≤ i ≤ 3. In the first data stream, the j-th group of two consecutive symbols (a total of 16 symbols) from each of the eight data streams are consecutive. Also, j ≥ 0. Each consecutive 16 symbols in the first data stream comes from at least four... The first data stream obtained by the group interleaving consists of 544 consecutive symbols from at least 4 different codewords. Specifically, the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving are from different codewords.

[0098] In some possible implementations, t = 8, s = 1, and grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving 8 channel data streams (8*i, 8*i+1, 8*i+2, 8*i+3, 8*i+4, 8*i+5, 8*i+6, and 8*i+7) to obtain 1 first data stream, where 0 ≤ i ≤ 3. Each channel data stream includes a j-th symbol and a total of 8 symbols that are consecutive in the first data stream obtained by the packet interleaving, where j≥0. In the first data stream obtained by the packet interleaving, every consecutive 8 symbols come from 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols in every consecutive 8 symbols in the first data stream obtained by the packet interleaving come from different codewords. The 4th, 5th, 6th, and 7th symbols in every consecutive 8 symbols in the first data stream obtained by the packet interleaving come from different codewords.

[0099] In some possible implementations, n = 32, the first 16 consecutive channel data streams in the n channel data streams come from the same codeword, the last 16 consecutive channel data streams in the n channel data streams come from the same codeword, and the first 16 consecutive channel data streams and the last 16 consecutive channel data streams in the n channel data streams come from different codewords.

[0100] In some possible implementations, where t = 2 and s = 1, grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving the i-th channel data stream and the (i+16)-th channel data stream to obtain 1 first data stream, where 0 ≤ i < 16. Two consecutive symbols in the i-th channel data stream and two consecutive symbols in the (i+16)-th channel data stream are consecutive in the grouped and interleaved first data stream, and every four consecutive symbols in the grouped and interleaved first data stream come from four different codewords.

[0101] In some possible implementations, the j-th bit in a first data stream resulting from the packet interleaving comes from the first bit. The first of 20 consecutive bits in the channel data stream bits, the This indicates rounding down, where 0 ≤ j < 40, and β is 1, 2, 4, 5, 10, or 20.

[0102] In some possible implementations, t=2, s=1, and grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving the i-th channel data stream and the (i+16)-th channel data stream to obtain 1 first data stream, where 0≤i<16. The j-th group of consecutive β bits in the i-th channel data stream and the j-th group of consecutive β bits in the (i+16)-th channel data stream are consecutive in the 1 first data stream obtained by grouping and interleaving, where j≥0, and β is 1, 2, 4, 5, 10, or 20. Each consecutive 4 symbols in the 1 first data stream obtained by grouping and interleaving come from 4 different codewords.

[0103] In some possible implementations, t=2, s=2, and grouping and interleaving each t channel data stream in the n channel data streams to obtain s first data streams includes: grouping and interleaving the i-th channel data stream and the i+16-th channel data stream to obtain the 2*i-th first data stream and the 2*i+1-th first data stream, where 0≤i<16. Two consecutive symbols from the i-th channel data stream and two consecutive symbols from the (i+16)-th channel data stream, totaling 20 bits, are consecutive in the 2*i-th first data stream. Each consecutive 20 bits in the 2*i-th first data stream comes from four different codewords. The other five bits from each of the four symbols (two consecutive symbols from the i-th channel data stream and two consecutive symbols from the (i+16)-th channel data stream, totaling 20 bits, are consecutive in the 2*i+1-th first data stream. Each consecutive 20 bits in the 2*i+1-th first data stream comes from four different codewords.

[0104] In some possible implementations, the f-th bit in the 20 consecutive bits of the first data stream of the 2*i+g-th bit comes from the first... The first of 20 consecutive bits in the channel data stream 10 bits, 0≤f<20, 0≤g<2.

[0105] In some possible implementations, the f-th bit in the 20 consecutive bits of the first data stream of the 2*i+g-th bit comes from the first... The first of 20 consecutive bits in the channel data stream 10 bits, 0≤f<20, 0≤g<2.

[0106] In some possible implementations, t = 4, s = 1, and grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving the 2*i, 2*i+1, 2*i+16, and 2*i+17 channel data streams (a total of 4 channels) to obtain 1 first data stream, where 0 ≤ i ≤ 7, and each of the 4 channel data streams includes 8 consecutive symbols (2 symbols in total) in the grouped and interleaved first data stream. In the continuous data stream, every consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords, and the 4th, 5th, 6th, and 7th symbols in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords.

[0107] In some possible implementations, t=4, s=1, and grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving the 2*i-th channel data stream, the 2*i+1-th channel data stream, the 2*i+16-th channel data stream, and the 2*i+17-th channel data stream (a total of 4 channels) to obtain 1 first data stream, where 0≤i≤7. In each of the 4 channel data streams, the j-th group of 2 consecutive symbols (a total of 8 symbols) is consecutive in the first data stream obtained by the grouping and interleaving. Each of the 4 channel data streams contains... The j-th group of two consecutive symbols are consecutive in the first data stream obtained by the packet interleaving, j≥0. In the first data stream obtained by the packet interleaving, every 8 consecutive symbols come from at least 4 different codewords, and every 272 consecutive symbols come from at least 4 different codewords. In the first data stream obtained by the packet interleaving, the 0th, 1st, 2nd, and 3rd symbols in every 8 consecutive symbols come from different codewords. In the first data stream obtained by the packet interleaving, the 4th, 5th, 6th, and 7th symbols in every 8 consecutive symbols come from different codewords.

[0108] In some possible implementations, t=4, s=1, and grouping and interleaving each t channel data stream in the n channel data streams to obtain s first data streams includes: grouping and interleaving the 2*i channel data stream, the 2*i+1 channel data stream, the 2*i+16 channel data stream, and the 2*i+17 channel data stream to obtain 1 first data stream, 0≤i≤7, where the j-th symbol in each of the 4 channel data streams is consecutive in the 1 first data stream obtained by grouping and interleaving, j≥0, and every 4 consecutive symbols in the 1 first data stream obtained by grouping and interleaving come from 4 different codewords.

[0109] In some possible implementations, t = 8, s = 1, and grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving 8 channel data streams (4*i, 4*i+1, 4*i+2, 4*i+3, 4*i+16, 4*i+17, 4*i+18, and 4*i+19) to obtain 1 first data stream, where 0 ≤ i ≤ 3. Each of the 8 channel data streams includes 16 consecutive symbols (2 symbols each) that are consecutive in the grouped and interleaved first data stream. Each consecutive 16 symbols in the grouped and interleaved first data stream originates from... The first data stream obtained by the group interleaving has at least 4 different codewords, and each consecutive 544 symbols comes from at least 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols of each consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords. The 4th, 5th, 6th, and 7th symbols of each consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords. The 8th, 9th, 10th, and 11th symbols of each consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords. The 12th, 13th, 14th, and 15th symbols of each consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords.

[0110] In some possible implementations, t = 8, s = 1, and grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving 8 channel data streams (4*i, 4*i+1, 4*i+2, 4*i+3, 4*i+16, 4*i+17, 4*i+18, and 4*i+19) to obtain 1 first data stream, where 0 ≤ i ≤ 3. In the 8 channel data streams, the j-th group of two consecutive symbols (a total of 16 symbols) is consecutive in the grouped and interleaved first data stream, and j ≥ 0. In the first data stream obtained by the group interleaving, every 16 consecutive symbols come from at least 4 different codewords, and every 544 consecutive symbols come from at least 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving come from different codewords. The 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving come from different codewords. The 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving come from different codewords. The 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving come from different codewords.

[0111] In some possible implementations, t = 8, s = 1, and grouping and interleaving each t channel data stream from the n channel data streams to obtain s first data streams includes: grouping and interleaving the 4*i, 4*i+1, 4*i+2, 4*i+3, 4*i+16, 4*i+17, 4*i+18, and 4*i+19 channel data streams (a total of 8 channels) to obtain 1 first data stream, where 0 ≤ i ≤ 3. Each channel data stream in the stream includes a j-th symbol, which consists of 8 consecutive symbols in the first data stream obtained by the packet interleaving, where j ≥ 0. In the first data stream obtained by the packet interleaving, each of the 8 consecutive symbols comes from at least 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols in each of the 8 consecutive symbols in the first data stream obtained by the packet interleaving come from different codewords. The 4th, 5th, 6th, and 7th symbols in each of the 8 consecutive symbols in the first data stream obtained by the packet interleaving come from different codewords.

[0112] In some possible implementations, convolutionally interleaving a first data stream to obtain a second data stream includes: delaying a first data stream according to p delay lines to obtain a second data stream. Here, p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the fewest storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit stores d symbols, the symbols in each channel data stream are sequentially input to the p delay lines according to their sequence numbers, each delay line inputs d symbols at a time and outputs d symbols at a time, and the consecutive p*d symbols in a second data stream include the d symbols output by each delay line, where Q is an integer greater than or equal to 1.

[0113] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 memory cells, d(p*Q+1)≥L2, and L2=t / s*L1. Alternatively, the delay line with the smallest sequence number among the p delay lines includes 0 memory cells, d(p*Q-1)≥L2, and L2=t / s*L1.

[0114] In some possible implementations, after convolutionally interleaving the m first data streams to obtain m second data streams, the method further includes: performing second FEC encoding on the m second data streams to obtain m encoded data streams. In each encoded data stream, information data of length K symbols comes from at most K different codewords, where K ≥ p*d.

[0115] In some possible implementations, convolutionally interleaving a first data stream to obtain a second data stream includes: delaying a first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store 4 symbols, the symbols in each channel data stream are sequentially input into the p delay lines according to the sequence number of the p delay lines, each delay line inputs 4 symbols at a time and outputs 4 symbols at a time, the consecutive p*4 symbols in a second data stream include the 4 symbols output by each delay line, and Q satisfies 4(p*Q-1)≥272 or 4(p*Q+1)≥272 or 4(p*Q-1)≥544 or 4(p*Q+1)≥544.

[0116] In some possible implementations, after convolutionally interleaving the m first data streams to obtain m second data streams, the method further includes: performing second FEC encoding on the m second data streams to obtain m encoded data streams, wherein the information data of length K symbols in each encoded data stream comes from at most K different codewords, where K ≥ p * 4.

[0117] In some possible implementations, convolutionally interleaving a first data stream to obtain a second data stream includes: delaying the first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the fewest storage units includes 0 storage units, and the difference in the number of storage units between any two adjacent delay lines is Q; each storage unit is used to store 34 bits, and the bits in each channel data stream are input sequentially according to the sequence number of the p delay lines. The second data stream has p delay lines, each inputting 34 bits and outputting 34 bits at a time. A continuous p*34 bits in one second data stream includes the 34 bits output by each delay line. Alternatively, each storage unit stores 68 bits, and the bits in each channel data stream are sequentially input to the p delay lines according to their sequence numbers. Each delay line inputs 68 bits and outputs 68 bits at a time. A continuous p*68 bits in one second data stream includes the 68 bits output by each delay line.

[0118] In some possible implementations, p = 2, with each storage unit used to store 68 bits, or p = 4, with each storage unit used to store 34 bits.

[0119] Sixthly, this application provides a data processing apparatus. The data processing apparatus includes a group interleaver and a convolutional interleaver. The group interleaver is used to: interleave each t channel data stream from n channel data streams to obtain s first data streams, resulting in a total of m first data streams. n = q * t, m = q * s, where n is an integer greater than 1, n is divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. All n channel data streams undergo first forward error correction (FEC) coding. Each a codeword after the first FEC coding is distributed across b channel data streams, where a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. Each consecutive a symbols in each channel data stream come from a different codeword, and each consecutive L1 symbols in each channel data stream come from at least a different codeword, L1 = N * a / b, where N represents the length of the codeword. The t-channel data streams each consist of 'a' consecutive symbols, totaling t*a symbols. Each t*a symbol contains Δ bits, totaling D bits, where D = Δ*t*a. These D bits are consecutive in any one of the s first data streams, and Δ = M / s, where M represents the number of bits in a symbol. The convolutional interleaver is used to convolve and interleave the m first data streams to obtain m second data streams.

[0120] In some possible implementations, each consecutive d symbols in each of the first data streams comes from v different codewords, and each consecutive L2 symbols in each of the first data streams comes from at least v different codewords, where v is divisible by a, L2 = t / s * L1, and d = D / M.

[0121] In some possible implementations, n = 32, the 16 odd-numbered data streams in the n-channel data streams come from the same codeword, the 16 even-numbered data streams in the n-channel data streams come from the same codeword, and the data streams in the odd-numbered channels and the data streams in the even-numbered channels in the n-channel data streams come from different codewords.

[0122] In some possible implementations, t = 2, s = 1, and the group interleaver is specifically used to: group-interleave the 2*i-th channel data stream and the 2*i+1-th channel data stream to obtain a first data stream, where 0 ≤ i < 16. Two consecutive symbols in the 2*i-th channel data stream and two consecutive symbols in the 2*i+1-th channel data stream are consecutive in the first data stream obtained by the group interleaver, and every four consecutive symbols in the first data stream obtained by the group interleaver come from four different codewords.

[0123] In some possible implementations, the j-th bit in a first data stream resulting from the packet interleaving comes from the first bit. The first of 20 consecutive bits in the channel data stream bits, the This indicates rounding down, where 0 ≤ j < 40, and β is 1, 2, 4, 5, 10, or 20.

[0124] In some possible implementations, t = 2, s = 1, and the group interleaver is specifically used to: interleave the 2*i-th channel data stream and the 2*i+1-th channel data stream to obtain a first data stream, where 0 ≤ i < 16. The j-th group of consecutive β bits in the 2*i-th channel data stream and the j-th group of consecutive β bits in the 2*i+1-th channel data stream are consecutive in the first data stream obtained by the group interleaver, where j ≥ 0, and β is 1, 2, 4, 5, 10, or 20. Each consecutive 4 symbols in the first data stream obtained by the group interleaver come from 4 different codewords.

[0125] In some possible implementations, t=2, s=2, and the group interleaver is specifically used to: group and interleave the 2*i channel data stream and the 2*i+1 channel data stream to obtain the 2*i first data stream and the 2*i+1 first data stream, where 0≤i<16. Two consecutive symbols from the 2*i channel data stream and two consecutive symbols from the 2*i+1 channel data stream, totaling 20 bits, are consecutive in the 2*i first data stream. Each consecutive 20 bits in the 2*i first data stream comes from 4 different codewords. The other 5 bits from each of the four symbols (two consecutive symbols from the 2*i channel data stream and two consecutive symbols from the 2*i+1 channel data stream), totaling 20 bits, are consecutive in the 2*i+1 first data stream. Each consecutive 20 bits in the 2*i+1 first data stream comes from 4 different codewords.

[0126] In some possible implementations, the f-th bit in the 20 consecutive bits of the first data stream of the 2*i+g-th bit comes from the first... The first of 20 consecutive bits in the channel data stream 10 bits, 0≤f<20, 0≤g<2.

[0127] In some possible implementations, the f-th bit in the 20 consecutive bits of the first data stream of the 2*i+g-th bit comes from the first... The first of 20 consecutive bits in the channel data stream 10 bits, 0≤f<20, 0≤g<2.

[0128] In some possible implementations, t = 4, s = 1, and the group interleaver is specifically used to: group interleave four channel data streams—the 4*i channel data stream, the 4*i+1 channel data stream, the 4*i+2 channel data stream, and the 4*i+3 channel data stream—to obtain one first data stream, where 0 ≤ i ≤ 7. Each of the four channel data streams includes eight consecutive symbols (two symbols in total) that are consecutive in the first data stream obtained by the group interleave. Each consecutive group of eight symbols in the first data stream comes from at least four different codewords, and each consecutive group of 272 symbols comes from at least four different codewords. The 0th, 1st, 2nd, and 3rd symbols in each consecutive group of eight symbols in the first data stream come from different codewords. The 4th, 5th, 6th, and 7th symbols in each consecutive group of eight symbols in the first data stream come from different codewords.

[0129] In some possible implementations, t = 4, s = 1, and the group interleaver is specifically used to: group and interleave four channel data streams—the 4*i channel data stream, the 4*i+1 channel data stream, the 4*i+2 channel data stream, and the 4*i+3 channel data stream—to obtain one first data stream, where 0 ≤ i ≤ 7. Each of the four channel data streams includes a j-th group of two consecutive symbols, totaling eight symbols, which are consecutive in the first data stream obtained by the group interleaver. The j-th group of two consecutive symbols in each of the four channel data streams... In the first data stream obtained by the group interleaving, j≥0, every consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords. The 4th, 5th, 6th, and 7th symbols in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords.

[0130] In some possible implementations, t = 4, s = 1, and the group interleaver is specifically used to: group interleave the 4*i channel data stream, the 4*i+1 channel data stream, the 4*i+2 channel data stream, and the 4*i+3 channel data stream to obtain a first data stream, 0 ≤ i ≤ 7, where the j-th symbol of each of the 4 channel data streams is consecutive in the first data stream obtained by the group interleave, j ≥ 0, and every consecutive 4 symbols in the first data stream obtained by the group interleave come from 4 different codewords.

[0131] In some possible implementations, t = 8, s = 1, and the group interleaver is specifically used to: group and interleave eight channel data streams (8*i, 8*i+1, 8*i+2, 8*i+3, 8*i+4, 8*i+5, 8*i+6, and 8*i+7) to obtain one first data stream, where 0 ≤ i ≤ 3. Each of the eight channel data streams includes 16 consecutive symbols (2 consecutive symbols each) that are consecutive in the first data stream obtained by the group interleaver. Each consecutive 16 symbols in the first data stream obtained by the group interleaver comes from at least four different codewords, and each consecutive... The 544 symbols come from at least 4 different codewords. In the first data stream obtained by the group interleaving, the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols come from different codewords. The 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving come from different codewords. The 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving come from different codewords. The 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving come from different codewords.

[0132] In some possible implementations, t = 8, s = 1, and the group interleaver is specifically used to: group and interleave 8 channel data streams (8*i+1, 8*i+2, 8*i+3, 8*i+4, 8*i+5, 8*i+6, and 8*i+7) to obtain 1 first data stream, 0 ≤ i ≤ 3, where each of the 8 channel data streams includes 16 consecutive symbols in the j-th group, and j ≥ 0. In the data stream, every consecutive 16 symbols come from at least 4 different codewords, and every consecutive 544 symbols come from at least 4 different codewords. In the first data stream obtained by the group interleaving, the 0th, 1st, 2nd, and 3rd symbols of every consecutive 16 symbols come from different codewords. In the first data stream obtained by the group interleaving, the 4th, 5th, 6th, and 7th symbols of every consecutive 16 symbols come from different codewords. In the first data stream obtained by the group interleaving, the 8th, 9th, 10th, and 11th symbols of every consecutive 16 symbols come from different codewords. In the first data stream obtained by the group interleaving, the 12th, 13th, 14th, and 15th symbols of every consecutive 16 symbols come from different codewords.

[0133] In some possible implementations, t = 8, s = 1, and the group interleaver is specifically used to: group and interleave eight channel data streams (8*i+1, 8*i+2, 8*i+3, 8*i+4, 8*i+5, 8*i+6, and 8*i+7) to obtain one first data stream, where 0 ≤ i ≤ 3. Each of the eight channel data streams includes the first... j symbols, a total of 8 symbols, are consecutive in the first data stream obtained by the packet interleaving, j≥0. In the first data stream obtained by the packet interleaving, every consecutive 8 symbols come from 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols in every consecutive 8 symbols in the first data stream obtained by the packet interleaving come from different codewords. The 4th, 5th, 6th, and 7th symbols in every consecutive 8 symbols in the first data stream obtained by the packet interleaving come from different codewords.

[0134] In some possible implementations, n = 32, the first 16 consecutive channel data streams in the n channel data streams come from the same codeword, the last 16 consecutive channel data streams in the n channel data streams come from the same codeword, and the first 16 consecutive channel data streams and the last 16 consecutive channel data streams in the n channel data streams come from different codewords.

[0135] In some possible implementations, t = 2, s = 1, and the group interleaver is specifically used to: group-interleave the i-th channel data stream and the (i+16)-th channel data stream to obtain a first data stream, where 0 ≤ i < 16. Two consecutive symbols in the i-th channel data stream and two consecutive symbols in the (i+16)-th channel data stream are consecutive in the first data stream obtained by the group interleaver, and every four consecutive symbols in the first data stream obtained by the group interleaver come from four different codewords.

[0136] In some possible implementations, the j-th bit in a first data stream resulting from the packet interleaving comes from the first bit. The first of 20 consecutive bits in the channel data stream bits, the This indicates rounding down, where 0 ≤ j < 40, and β is 1, 2, 4, 5, 10, or 20.

[0137] In some possible implementations, t = 2, s = 1, and the group interleaver is specifically used to: interleave the i-th channel data stream and the (i+16)-th channel data stream to obtain a first data stream, where 0 ≤ i < 16. The j-th group of consecutive β bits in the i-th channel data stream and the j-th group of consecutive β bits in the (i+16)-th channel data stream are consecutive in the first data stream obtained by the group interleaver, where j ≥ 0, and β is 1, 2, 4, 5, 10, or 20. Each consecutive 4 symbols in the first data stream obtained by the group interleaver come from 4 different codewords.

[0138] In some possible implementations, t = 2, s = 2, and the group interleaver is specifically used to: group and interleave the i-th channel data stream and the (i+16)-th channel data stream to obtain the 2*i-th first data stream and the 2*i+1-th first data stream, where 0 ≤ i < 16. Two consecutive symbols from the i-th channel data stream and two consecutive symbols from the (i+16)-th channel data stream, totaling 20 bits, are consecutive in the 2*i-th first data stream. Each consecutive 20 bits in the 2*i-th first data stream comes from four different codewords. The remaining five bits from each of the four consecutive symbols from the i-th channel data stream and the (i+16)-th channel data stream, totaling 20 bits, are consecutive in the 2*i+1-th first data stream. Each consecutive 20 bits in the 2*i+1-th first data stream comes from four different codewords.

[0139] In some possible implementations, the f-th bit in the 20 consecutive bits of the first data stream of the 2*i+g-th bit comes from the first... The first of 20 consecutive bits in the channel data stream 10 bits, 0≤f<20, 0≤g<2.

[0140] In some possible implementations, the f-th bit in the 20 consecutive bits of the first data stream of the 2*i+g-th bit comes from the first... The first of 20 consecutive bits in the channel data stream 10 bits, 0≤f<20, 0≤g<2.

[0141] In some possible implementations, t = 4, s = 1, and the group interleaver is specifically used to: group interleave four channel data streams—the 2*i channel data stream, the 2*i+1 channel data stream, the 2*i+16 channel data stream, and the 2*i+17 channel data stream—to obtain one first data stream, where 0 ≤ i ≤ 7. Each of the four channel data streams includes eight consecutive symbols (two symbols in total) that are consecutive in the first data stream obtained by the group interleave. Each consecutive group of eight symbols in the first data stream comes from at least four different codewords, and each consecutive group of 272 symbols comes from at least four different codewords. The 0th, 1st, 2nd, and 3rd symbols in each consecutive group of eight symbols in the first data stream come from different codewords, and the 4th, 5th, 6th, and 7th symbols in each consecutive group of eight symbols in the first data stream come from different codewords.

[0142] In some possible implementations, t = 4, s = 1, and the group interleaver is specifically used to: group and interleave four data streams—the 2*i-th channel data stream, the 2*i+1-th channel data stream, the 2*i+16-th channel data stream, and the 2*i+17-th channel data stream—to obtain one first data stream, where 0 ≤ i ≤ 7. Each of the four channel data streams includes a j-th group of two consecutive symbols, totaling eight symbols, which are consecutive in the first data stream obtained by the group interleaver. In the first data stream obtained by the group interleaving, j≥0, every consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords. The 4th, 5th, 6th, and 7th symbols in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords.

[0143] In some possible implementations, t = 4, s = 1, and the group interleaver is specifically used to: group interleave the 2*i channel data stream, the 2*i+1 channel data stream, the 2*i+16 channel data stream, and the 2*i+17 channel data stream, a total of 4 channel data streams, to obtain a first data stream, 0 ≤ i ≤ 7, wherein the j-th symbol of each of the 4 channel data streams is consecutive in the first data stream obtained by the group interleave, j ≥ 0, and every consecutive 4 symbols in the first data stream obtained by the group interleave come from 4 different codewords.

[0144] In some possible implementations, t = 8, s = 1, and the group interleaver is specifically used to: group and interleave eight channel data streams—the 4*i+1, 4*i+2, 4*i+3, 4*i+16, 4*i+17, 4*i+18, and 4*i+19—to obtain one first data stream, where 0 ≤ i ≤ 3. Each of the eight channel data streams includes 16 consecutive symbols (2 consecutive symbols each) that are consecutive in the first data stream obtained by the group interleaver. Each consecutive 16 symbols in the first data stream obtained by the group interleaver comes from at least four different codewords, and each consecutive... The 544 consecutive symbols come from at least 4 different codewords. In the first data stream obtained by the group interleaving, the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols come from different codewords. The 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving come from different codewords. The 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving come from different codewords. The 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by the group interleaving come from different codewords.

[0145] In some possible implementations, t = 8, s = 1, and the group interleaver is specifically used to: group and interleave eight channel data streams—the 4*i channel data stream, the 4*i+1 channel data stream, the 4*i+2 channel data stream, the 4*i+3 channel data stream, the 4*i+16 channel data stream, the 4*i+17 channel data stream, the 4*i+18 channel data stream, and the 4*i+19 channel data stream—to obtain one first data stream, 0 ≤ i ≤ 3. The j-th group of two consecutive symbols (a total of 16 symbols) included in each of the eight channel data streams are consecutive in the first data stream obtained by the group interleaver, and j ≥ 0. In the first data stream, every consecutive 16 symbols come from at least 4 different codewords, and every consecutive 544 symbols come from at least 4 different codewords. In the first data stream obtained by group interleaving, the 0th, 1st, 2nd, and 3rd symbols of every consecutive 16 symbols come from different codewords. In the first data stream obtained by group interleaving, the 4th, 5th, 6th, and 7th symbols of every consecutive 16 symbols come from different codewords. In the first data stream obtained by group interleaving, the 8th, 9th, 10th, and 11th symbols of every consecutive 16 symbols come from different codewords. In the first data stream obtained by group interleaving, the 12th, 13th, 14th, and 15th symbols of every consecutive 16 symbols come from different codewords.

[0146] In some possible implementations, t = 8, s = 1, and the group interleaver is specifically used to: group and interleave eight channel data streams—the 4*i+1, 4*i+2, 4*i+3, 4*i+16, 4*i+17, 4*i+18, and 4*i+19—to obtain one first data stream, where 0 ≤ i ≤ 3. Each of the eight channel data streams includes… The j-th symbol and a total of 8 symbols are consecutive in the first data stream obtained by the packet interleaving, j≥0. In the first data stream obtained by the packet interleaving, each consecutive 8 symbols comes from at least 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols in each consecutive 8 symbols in the first data stream obtained by the packet interleaving come from different codewords. The 4th, 5th, 6th, and 7th symbols in each consecutive 8 symbols in the first data stream obtained by the packet interleaving come from different codewords.

[0147] In some possible implementations, the convolutional interleaver is specifically used to: delay a first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store d symbols, the symbols in each channel data stream are sequentially input into the p delay lines according to the sequence number of the p delay lines, each delay line inputs d symbols at a time and outputs d symbols at a time, and the consecutive p*d symbols in a second data stream include the d symbols output by each delay line, where Q is an integer greater than or equal to 1.

[0148] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 memory cells, d(p*Q+1)≥L2, and L2=t / s*L1. Alternatively, the delay line with the smallest sequence number among the p delay lines includes 0 memory cells, d(p*Q-1)≥L2, and L2=t / s*L1.

[0149] In some possible implementations, the data processing apparatus further includes an encoder. After obtaining m second data streams, the encoder is used to: perform second FEC encoding on each of the m second data streams to obtain m encoded data streams. Information data of length K symbols in each encoded data stream comes from at most K different codewords, where K ≥ p*d.

[0150] In some possible implementations, the convolutional interleaver is specifically used to: delay a first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store 4 symbols, the symbols in each channel data stream are sequentially input into the p delay lines according to the sequence number of the p delay lines, each delay line inputs 4 symbols at a time and outputs 4 symbols at a time, the consecutive p*4 symbols in a second data stream include the 4 symbols output by each delay line, and Q satisfies 4(p*Q-1)≥272 or 4(p*Q+1)≥272 or 4(p*Q-1)≥544 or 4(p*Q+1)≥544.

[0151] In some possible implementations, the data processing apparatus further includes an encoder. After obtaining m second data streams, the encoder is used to: perform second FEC encoding on the m second data streams respectively to obtain m encoded data streams, wherein the information data of length K symbols in each encoded data stream comes from at most K different codewords, where K ≥ p * 4.

[0152] In some possible implementations, the convolutional interleaver is specifically used to: delay a first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit is used to store 34 bits, the bits in each channel data stream are sequentially input into the p delay lines according to their sequence numbers, each delay line inputs 34 bits at a time and outputs 34 bits at a time, and the consecutive p*34 bits in a second data stream include the 34 bits output by each delay line; or, each storage unit is used to store 68 bits, the bits in each channel data stream are sequentially input into the p delay lines according to their sequence numbers, each delay line inputs 68 bits at a time and outputs 68 bits at a time, and the consecutive p*68 bits in a second data stream include the 68 bits output by each delay line.

[0153] In some possible implementations, p = 2, with each storage unit used to store 68 bits, or p = 4, with each storage unit used to store 34 bits.

[0154] Seventhly, this application provides a data processing method, which includes the following steps. First, n channel data streams are delayed according to p delay lines to obtain n first data streams. Each of the n channel data streams undergoes first forward error correction (FEC) encoding, where p is an integer greater than 1, each delay line has a different number of storage units, the delay line with the fewest storage units has 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit stores U bits, the bits in each channel data stream are sequentially input into the p delay lines according to their sequence numbers, each delay line inputs U bits at a time and outputs U bits at a time, and a consecutive p*U bits in a second data stream includes the U bits output by each delay line, where Q is an integer greater than or equal to 1, and U is an integer greater than or equal to 1. Then, the n first data streams are respectively subjected to second FEC encoding to obtain n second data streams. In the second data stream after the second FEC encoding, the information data of each codeword is p*U bits output by the p delay lines in a single operation.

[0155] In some possible implementations, p*U = 120, 136, or 160.

[0156] Eighthly, this application provides a data processing apparatus, which includes a convolutional interleaver and an encoder. The convolutional interleaver is used to: delay n channel data streams according to p delay lines to obtain n first data streams. Wherein, all n channel data streams undergo first forward error correction (FEC) encoding, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit stores U bits, the bits in each channel data stream are sequentially input into the p delay lines according to their sequence numbers, each delay line inputs U bits at a time and outputs U bits at a time, and a consecutive p*U bits in a second data stream includes the U bits output by each delay line, where Q is an integer greater than or equal to 1, and U is an integer greater than or equal to 1. The encoder is used to: perform second FEC encoding on the n first data streams to obtain n second data streams. In the second data stream after the second FEC encoding, the information data of each codeword is p*U bits output by the p delay lines in a single operation.

[0157] In some possible implementations, p*U = 120, 136, or 160.

[0158] Ninthly, this application provides a data processing method, which includes the following steps. First, each t channel data stream in n channel data streams is grouped and interleaved to obtain s first data streams, resulting in a total of m first data streams. Where n = q * t, m = q * s, n is an integer greater than 1, n is divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. All n channel data streams undergo first FEC encoding. Each a codeword after first FEC encoding is distributed in b channel data streams, a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. Each consecutive a symbols in each channel data stream come from a different codeword, and each consecutive L1 symbols in each channel data stream come from at least a different codeword, L1 = N * a / b, where N represents the length of the codeword. The n-channel data stream comprises a first group of n / 2-channel data streams and a second group of n / 2-channel data streams. Any symbol in the first group of n / 2-channel data streams and any symbol in the second group of n / 2-channel data streams originates from different codewords. In every t-channel data stream, the first group of t / 2-channel data streams originates from the first group of n / 2-channel data streams, and the second group of t / 2-channel data streams originates from the second group of n / 2-channel data streams. Furthermore, m first data streams are convolved and interleaved to obtain m second data streams.

[0159] In some possible implementations, the first group of n / 2 channel data streams in the n channel data streams comes from the same codeword, and the second group of n / 2 channel data streams in the n channel data streams comes from the same codeword.

[0160] In some possible implementations, t = s, where t channel data streams include a first channel data stream and a second channel data stream. The first channel data stream is one of the n / 2 channel data streams in a first group, and the second channel data stream is one of the n / 2 channel data streams in a second group. A series of a consecutive symbols in the first channel data stream and a consecutive symbols in the second channel data stream are consecutive in any one of the s first data streams.

[0161] In some possible implementations, a = 2, b = n / 2.

[0162] In some possible implementations, each consecutive d symbols in each first data stream comes from v different codewords, and each consecutive L2 symbols in each first data stream comes from at least v different codewords, where v is divisible by a, L2 = t / s * L1, and d = v.

[0163] In some possible implementations, v = 2*a.

[0164] In some possible implementations, t = 2, or t = 4, or t = 8.

[0165] In some possible implementations, convolutionally interleaving a first data stream to obtain a second data stream includes: delaying a first data stream according to p delay lines to obtain a second data stream. p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the fewest storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, and each storage unit is used to store d symbols. Symbols in each channel data stream are sequentially input to the p delay lines according to their sequence numbers. Each delay line inputs d symbols at a time and outputs d symbols at a time. The consecutive p*d symbols in a second data stream include the d symbols output by each delay line, and Q is an integer greater than or equal to 1.

[0166] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 memory cells, d(p*Q+1)≥L2, and L2=t / s*L1. Alternatively, the delay line with the smallest sequence number among the p delay lines includes 0 memory cells, d(p*Q-1)≥L2, and L2=t / s*L1.

[0167] In some possible implementations, after convolutionally interleaving m first data streams to obtain m second data streams, the method further includes: performing second FEC encoding on each of the m second data streams to obtain m encoded data streams. The information data of length K symbols in each encoded data stream comes from at most K different codewords, (p-1)*d <K<(p+1)*d。

[0168] Tenthly, this application provides a data processing apparatus, which includes a group interleaver and a convolutional interleaver. The group interleaver is used to: interleave every t channel data streams in n channel data streams to obtain s first data streams, so as to obtain a total of m first data streams. Wherein, n = q*t, m = q*s, n is an integer greater than 1, n is divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. All n channel data streams are encoded by a first FEC, and each a codeword after the first FEC encoding is distributed in b channel data streams, a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. In each channel data stream, every consecutive a symbols come from a different codeword, and in each channel data stream, every consecutive L1 symbols come from at least a different codeword, L1 = N*a / b, where N represents the length of the codeword. The n-channel data stream comprises a first group of n / 2-channel data streams and a second group of n / 2-channel data streams. Any symbol in the first group of n / 2-channel data streams and any symbol in the second group of n / 2-channel data streams originates from different codewords. In every t-channel data stream, the first group of t / 2-channel data streams originates from the first group of n / 2-channel data streams, and the second group of t / 2-channel data streams originates from the second group of n / 2-channel data streams. The convolutional interleaver is used to convolve and interleave the m first data streams to obtain m second data streams.

[0169] In some possible implementations, the first group of n / 2 channel data streams in the n channel data streams comes from the same codeword, and the second group of n / 2 channel data streams in the n channel data streams comes from the same codeword.

[0170] In some possible implementations, t = s, where t channel data streams include a first channel data stream and a second channel data stream. The first channel data stream is one of the n / 2 channel data streams in a first group, and the second channel data stream is one of the n / 2 channel data streams in a second group. A series of a consecutive symbols in the first channel data stream and a consecutive symbols in the second channel data stream are consecutive in any one of the s first data streams.

[0171] In some possible implementations, a = 2, b = n / 2.

[0172] In some possible implementations, each consecutive d symbols in each first data stream comes from v different codewords, and each consecutive L2 symbols in each first data stream comes from at least v different codewords, where v is divisible by a, L2 = t / s * L1, and d = v.

[0173] In some possible implementations, v = 2*a.

[0174] In some possible implementations, t = 2, or t = 4, or t = 8.

[0175] In some possible implementations, the convolutional interleaver is specifically used to: delay a first data stream according to p delay lines to obtain a second data stream. p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the fewest storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, and each storage unit is used to store d symbols. Symbols in each channel data stream are sequentially input to the p delay lines according to their sequence numbers. Each delay line inputs d symbols at a time and outputs d symbols at a time. The p*d consecutive symbols in the second data stream include the d symbols output by each delay line, and Q is an integer greater than or equal to 1.

[0176] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 memory cells, d(p*Q+1)≥L2, and L2=t / s*L1. Alternatively, the delay line with the smallest sequence number among the p delay lines includes 0 memory cells, d(p*Q-1)≥L2, and L2=t / s*L1.

[0177] In some possible implementations, the data processing apparatus further includes, before encoding, performing convolutional interleaving on m first data streams to obtain m second data streams, and then the encoder performing second FEC encoding on each of the m second data streams to obtain m encoded data streams. The information data of length K symbols in each encoded data stream comes from at most K different codewords, (p-1)*d <K<(p+1)*d。

[0178] Eleventhly, this application provides a data processing method, which includes the following steps. First, each t channel data stream in n channel data streams is multiplexed to obtain one multiplexed data stream, resulting in a total of q multiplexed data streams. Where n = q * t, n is an integer greater than 1, divisible by q, q is an integer greater than or equal to 1, and t is an integer greater than or equal to 1. All n channel data streams undergo first FEC encoding. Each a codeword after first FEC encoding is distributed across b channel data streams, a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. In each channel data stream, each consecutive a symbols come from a different codeword, and in each channel data stream, each consecutive L1 symbols come from at least a different codeword, L1 = N * a / b, where N represents the length of the codeword. The n-channel data stream comprises a first group of n / 2 channel data streams and a second group of n / 2 channel data streams. Any symbol in the first group of n / 2 channel data streams and any symbol in the second group of n / 2 channel data streams originates from different codewords. In every t-channel data stream, the first group of t / 2 channel data streams originates from the first group of n / 2 channel data streams, and the second group of t / 2 channel data streams originates from the second group of n / 2 channel data streams. Then, each multiplexed data stream is distributed to obtain s first data streams, resulting in a total of m first data streams. Here, m = q * s, where s is an integer greater than or equal to 1. Furthermore, the m first data streams are convolved and interleaved to obtain m second data streams.

[0179] In a twelfth aspect, this application provides a data processing apparatus, which includes a multiplexing unit, a distribution unit, and a convolutional interleaver. The multiplexing unit is used to multiplex every t channel data streams from n channel data streams to obtain one multiplexed data stream, resulting in a total of q multiplexed data streams. Here, n = q * t, n is an integer greater than 1, divisible by q, q is an integer greater than or equal to 1, and t is an integer greater than or equal to 1. All n channel data streams undergo first FEC encoding. Each a codeword after first FEC encoding is distributed across b channel data streams, a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. Each consecutive a symbols in each channel data stream come from a different codeword, and each consecutive L1 symbols in each channel data stream come from at least a different codeword, L1 = N * a / b, where N represents the length of the codeword. The n-channel data stream comprises a first group of n / 2 channel data streams and a second group of n / 2 channel data streams. Any symbol in the first group of n / 2 channel data streams and any symbol in the second group of n / 2 channel data streams originates from different codewords. In every t-channel data stream, the first group of t / 2 channel data streams originates from the first group of n / 2 channel data streams, and the second group of t / 2 channel data streams originates from the second group of n / 2 channel data streams. The distribution unit is used to distribute each multiplexed data stream to obtain s first data streams, resulting in a total of m first data streams. Here, m = q * s, where s is an integer greater than or equal to 1. The convolutional interleaver is used to perform convolutional interleaving on the m first data streams to obtain m second data streams.

[0180] In a thirteenth aspect, this application provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by hardware, is capable of implementing some or all of the steps of any one of the methods in the first, third, fifth, seventh, ninth, or eleventh aspects described above.

[0181] In this embodiment, all n-channel data streams are codeword streams encoded with external codes. Convolutional interleaving is then performed on each of the n data streams, and the convolutionally interleaved n data streams are multiplexed into m second data streams, which are then encoded with internal codes. By employing the data interleaving and multiplexing processing scheme provided in this application, multiple symbols continuously output from multiple different external codewords in the multiplexed m data streams can be achieved with a shorter latency. This allows the cascaded FEC scheme to reduce data interleaving latency while maintaining good performance. In other words, the combination of convolutional interleaving and data multiplexing in this application results in a lower overall latency for the cascaded FEC scheme, making it more suitable for applications requiring low latency. Attached Figure Description

[0182] Figure 1This is a schematic diagram of a communication system used in an embodiment of this application;

[0183] Figure 2 for Figure 1 A schematic diagram of a data transmission process in the communication system shown.

[0184] Figure 3(a) is a schematic diagram of the first type of data processing of the originating processing module in an embodiment of this application;

[0185] Figure 3(b) is a schematic diagram of the second type of data processing of the originating processing module in an embodiment of this application;

[0186] Figure 3(c) is a schematic diagram of the third data processing method of the originating processing module in the embodiments of this application;

[0187] Figure 3(d) is a schematic diagram of the fourth data processing method of the originating processing module in the embodiments of this application;

[0188] Figure 3(e) is a schematic diagram of channel data alignment processing in an embodiment of this application;

[0189] Figure 3(f) is a schematic diagram of the fifth type of data processing in the originating processing module of this application embodiment;

[0190] Figure 3(g) is a schematic diagram of the sixth type of data processing in the originating processing module of this application embodiment;

[0191] Figure 3(h) is a schematic diagram of the seventh type of data processing in the originating processing module of this application embodiment;

[0192] Figure 3(i) is a schematic diagram of the eighth type of data processing in the originating processing module of this application embodiment;

[0193] Figure 4(a) is a schematic diagram of the first type of data processing for the receiving end processing module in an embodiment of this application;

[0194] Figure 4(b) is a schematic diagram of the second type of data processing for the receiving end processing module in an embodiment of this application;

[0195] Figure 4(c) is a schematic diagram of the third data processing method for the receiving end processing module in an embodiment of this application;

[0196] Figure 5 A schematic diagram of 32 PCS channels using a 1×800G interface for the transmitting device;

[0197] Figure 6 A schematic diagram of 32 PCS channels using 2×400G interfaces for the transmitting device;

[0198] Figure 7 A schematic diagram of 32 PCS channels using 4×200G interfaces for the transmitting device;

[0199] Figure 8 A schematic diagram of 32 FEC channels for a transmitting device using an 8×100G interface;

[0200] Figure 9 Another schematic diagram of 32 FEC channels for the transmitting device using an 8×100G interface;

[0201] Figure 10 A schematic flowchart of a data processing method provided in an embodiment of this application;

[0202] Figure 11 This is a schematic diagram of a structure in this application embodiment that performs convolutional interleaving on n channel data streams respectively;

[0203] Figure 12(a) is a schematic diagram of the first structure of the convolutional interleaver in the embodiments of this application;

[0204] Figure 12(b) is a schematic diagram of the second structure of the convolutional interleaver in an embodiment of this application;

[0205] Figure 13 This is a schematic diagram of a structure for multiplexing n first data streams in an embodiment of this application;

[0206] Figure 14 This is a schematic diagram of the first structure of the multiplexer in the embodiments of this application;

[0207] Figure 15 This is a schematic diagram of a structure for FEC encoding of m second data streams in an embodiment of this application;

[0208] Figure 16(a) is a schematic diagram of the third structure of the convolutional interleaver in the embodiments of this application;

[0209] Figure 16(b) is a schematic diagram of the fourth structure of the convolutional interleaver in the embodiments of this application;

[0210] Figure 17(a) is a schematic diagram of the second structure of the multiplexer in an embodiment of this application;

[0211] Figure 17(b) is a schematic diagram of the third structure of the multiplexer in the embodiments of this application;

[0212] Figure 17(c) is a schematic diagram of the fourth structure of the multiplexer in the embodiments of this application;

[0213] Figure 18(a) is a schematic diagram of the fifth structure of the convolutional interleaver in the embodiments of this application;

[0214] Figure 18(b) is a schematic diagram of the sixth structure of the convolutional interleaver in the embodiments of this application;

[0215] Figure 19(a) is a schematic diagram of the seventh structure of the convolutional interleaver in the embodiments of this application;

[0216] Figure 19(b) is a schematic diagram of the eighth structure of the convolutional interleaver in the embodiments of this application;

[0217] Figure 20 This is a schematic diagram of the ninth structure of the convolutional interleaver in the embodiments of this application;

[0218] Figure 21 This is a schematic diagram of the tenth structure of the convolutional interleaver in the embodiments of this application;

[0219] Figure 22 This is a schematic diagram of the fifth structure of the multiplexer in the embodiments of this application;

[0220] Figure 23 This is a schematic diagram of the eleventh structure of the convolutional interleaver in the embodiments of this application;

[0221] Figure 24 This is a schematic diagram of the sixth structure of the multiplexer in the embodiments of this application;

[0222] Figure 25 This is a schematic diagram of the twelfth structure of the convolutional interleaver in the embodiments of this application;

[0223] Figure 26 This is a schematic diagram of the thirteenth structure of the convolutional interleaver in the embodiments of this application;

[0224] Figure 27(a) is a schematic diagram of the fourteenth structure of the convolutional interleaver in this application embodiment;

[0225] Figure 27(b) is a schematic diagram of the fifteenth structure of the convolutional interleaver in the embodiments of this application;

[0226] Figure 28(a) is a schematic diagram of the sixteenth structure of the convolutional interleaver in the embodiments of this application;

[0227] Figure 28(b) is a schematic diagram of the seventeenth structure of the convolutional interleaver in the embodiments of this application;

[0228] Figure 29(a) is a schematic diagram of the eighteenth structure of the convolutional interleaver in the embodiments of this application;

[0229] Figure 29(b) is a schematic diagram of the nineteenth structure of the convolutional interleaver in the embodiments of this application;

[0230] Figure 30(a) is a schematic diagram of the twentieth structure of the convolutional interleaver in the embodiments of this application;

[0231] Figure 30(b) is a schematic diagram of the twenty-first structure of the convolutional interleaver in this application embodiment;

[0232] Figure 31(a) is a schematic diagram of the twenty-second structure of the convolutional interleaver in the embodiments of this application;

[0233] Figure 31(b) is a schematic diagram of the twenty-third structure of the convolutional interleaver in the embodiments of this application;

[0234] Figure 32(a) is a schematic diagram of a structure for grouping and interleaving n first data streams in an embodiment of this application;

[0235] Figure 32(b) is a schematic diagram of a group interleaving device in an embodiment of this application;

[0236] Figure 33 This is a schematic diagram of the structure of a data processing device in an embodiment of this application;

[0237] Figure 34 A schematic diagram of an interleaving process provided in an embodiment of this application;

[0238] Figure 35 This is a schematic diagram of a structure for grouping and interleaving n first data streams in an embodiment of this application;

[0239] Figure 36 This is a schematic diagram illustrating one implementation of group interleaving in an embodiment of this application;

[0240] Figure 37 A schematic diagram of the data stream format after channel alignment when the client-side interface is 2×400GbE;

[0241] Figure 38 This is a schematic diagram illustrating one implementation method of group interleaving;

[0242] Figure 39 This is a schematic diagram illustrating another implementation method of grouped interleaving;

[0243] Figure 40 This is a schematic diagram illustrating another implementation method of grouped interleaving;

[0244] Figure 41 This is a schematic diagram illustrating another implementation method of grouped interleaving;

[0245] Figure 42 This is another schematic diagram of the interleaving process provided in the embodiments of this application;

[0246] Figure 43 This is a schematic diagram illustrating one implementation of the first grouping interleaving in an embodiment of this application;

[0247] Figure 44(a) is a schematic diagram of one implementation method of second group interleaving in an embodiment of this application;

[0248] Figure 44(b) is a schematic diagram of a specific implementation of the second grouping interleaving in an embodiment of this application;

[0249] Figure 45(a) is a schematic diagram of one implementation method of the first group interleaving;

[0250] Figure 45(b) is a schematic diagram of one implementation of convolutional interleaving;

[0251] Figure 45(c) is a schematic diagram of another implementation of convolutional interleaving;

[0252] Figure 45(d) is a schematic diagram of one implementation method of second group interleaving;

[0253] Figure 46(a) is a schematic diagram of another implementation of convolutional interleaving;

[0254] Figure 46(b) is a schematic diagram of another implementation of convolutional interleaving;

[0255] Figure 46(c) is a schematic diagram of another implementation method of the second group interleaving;

[0256] Figure 47 This is a schematic diagram illustrating another implementation method for the second group interleaving;

[0257] Figure 48 This is a schematic diagram illustrating another implementation method for the second group interleaving;

[0258] Figure 49 This is a schematic diagram illustrating another implementation method for the first group interleaving;

[0259] Figure 50(a) is a schematic diagram of another structure of the data processing device in an embodiment of this application;

[0260] Figure 50(b) is a schematic diagram of another structure of the data processing device in an embodiment of this application;

[0261] Figure 51 Another flowchart illustrating the data processing method provided in this application embodiment;

[0262] Figure 52 This is a schematic diagram of a structure for grouping and interleaving n channel data streams in an embodiment of this application;

[0263] Figure 53 This is a schematic diagram illustrating an application scenario of grouping interleaving in the embodiments of this application;

[0264] Figure 54 These are schematic diagrams illustrating several specific embodiments of grouping and interleaving in this application.

[0265] Figure 55 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0266] Figure 56 These are schematic diagrams illustrating several specific embodiments of grouping and interleaving in this application.

[0267] Figure 57 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0268] Figure 58 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0269] Figure 59 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0270] Figure 60 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0271] Figure 61 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0272] Figure 62 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0273] Figure 63 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0274] Figure 64 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0275] Figure 65 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0276] Figure 66 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0277] Figure 67 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0278] Figure 68 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0279] Figure 69 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0280] Figure 70 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0281] Figure 71 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0282] Figure 72 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0283] Figure 73 This is a schematic diagram of a structure in which m first data streams are convolved and interleaved respectively in an embodiment of this application;

[0284] Figure 74 This is a schematic diagram of one embodiment of the convolutional interleaver in this application.

[0285] Figure 75 This is a schematic diagram of another embodiment of the convolutional interleaver in this application;

[0286] Figure 76 This is a schematic diagram of another embodiment of the convolutional interleaver in this application;

[0287] Figure 77 This is a schematic diagram of another embodiment of the convolutional interleaver in this application;

[0288] Figure 78 This is a schematic diagram of another embodiment of the convolutional interleaver in this application;

[0289] Figure 79 This is a schematic diagram of another embodiment of the convolutional interleaver in this application;

[0290] Figure 80 This is a schematic diagram of another embodiment of the convolutional interleaver in this application;

[0291] Figure 81 This is a schematic diagram of another embodiment of the convolutional interleaver in this application;

[0292] Figure 82 This is a schematic diagram of another embodiment of the convolutional interleaver in this application;

[0293] Figure 83 This is a schematic diagram of another embodiment of the convolutional interleaver in this application;

[0294] Figure 84 This is a schematic diagram illustrating one implementation of internal code encoding in the embodiments of this application;

[0295] Figure 85 This is a schematic diagram of the structure of a data processing device in an embodiment of this application;

[0296] Figure 86 Another flowchart illustrating the data processing method provided in this application embodiment;

[0297] Figure 87This is a schematic diagram of another structure of the data processing device in the embodiments of this application;

[0298] Figure 88 This is a schematic diagram of another structure of the data processing device in the embodiments of this application;

[0299] Figure 89 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0300] Figure 90 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0301] Figure 91 This is a schematic diagram of a grouping interleaving mapping method in an embodiment of this application;

[0302] Figure 92 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0303] Figure 93 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0304] Figure 94 This is a schematic diagram illustrating another mapping method for grouping interleaving in an embodiment of this application;

[0305] Figure 95 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0306] Figure 96 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0307] Figure 97 This is a schematic diagram illustrating another mapping method for grouping interleaving in the embodiments of this application;

[0308] Figure 98 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0309] Figure 99 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application;

[0310] Figure 100 This is a schematic diagram illustrating another mapping method for grouping interleaving in an embodiment of this application;

[0311] Figure 101 This is a schematic diagram illustrating another application scenario of grouping interleaving in the embodiments of this application. Detailed Implementation

[0312] This application provides a data processing method and a data processing apparatus. It can achieve better performance of the cascaded FEC scheme in scenarios with low latency. It should be noted that the terms "first," "second," etc., in this application specification, claims, and accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be interchanged where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0313] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application. Figure 1 As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches or routers. The transmitting device 01 is also called a host chip located at the transmitting end, and the receiving device 05 is also called a host chip located at the receiving end. The channel transmission medium 03 can be optical fiber. The host chip is sometimes also called a host device. The transmitting device 01 and the transmitting processing module 02 can be connected via an attachment unit interface (AUI), and the receiving device 05 and the receiving processing module 04 can be connected via an AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be an 800LR module (an 800LR module, a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission, and the specifics are not limited here.

[0314] Figure 2 for Figure 1 The diagram illustrates a data transmission process in the communication system shown. Figure 2As shown, during the data transmission from transmitting device 01 to receiving device 05, transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to transmitting processing module 02. Transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits this encoded data to channel transmission medium 03. Channel transmission medium 03 transmits the externally and internally encoded data to receiving processing module 04. Receiving processing module 04 performs internal code decoding on the externally and internally encoded data and transmits the internally decoded data to receiving device 05. Receiving device 05 performs external code decoding on the internally decoded data.

[0315] It should be understood that the distinction between "internal" in internal code and "external" in external code is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with external code, the data encoded by the transmitting processing module 02 is called data encoded with internal code, the data decoded by the receiving device 05 is called data decoded with external code, and the data decoded by the receiving processing module 04 is called data decoded with internal code. In one possible implementation, both the internal and external code encoding described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Hamming code for internal code encoding. As another example, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Bose–Chaudhuri–Hocquenghem (BCH) code for internal code encoding.

[0316] It should be noted that the above content is an exemplary description of the application scenarios of the data interleaving method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data interleaving method. As those skilled in the art know, as business needs change, its application scenarios can be adjusted according to application needs, and the embodiments of this application do not list them one by one.

[0317] For the aforementioned transmission scheme employing cascaded FEC, this application designs a data processing scheme incorporating "convolutional interleaving" and "multiplexing" to achieve better overall performance and lower latency for the cascaded FEC scheme. This allows the cascaded FEC transmission scheme to be applied to a wider range of transmission scenarios, particularly those requiring low latency, such as low-latency data center interconnection scenarios. Data processing is implemented through the aforementioned sending-end processing module 02.

[0318] Figure 3(a) is a schematic diagram of the first type of data processing in the transmitting end processing module of this application. As shown in Figure 3(a), after the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes, it can obtain n Physical Coding Sublayer (PCS) or FEC channel data streams after external code encoding. Alignment locking and channel data alignment processing are then performed to obtain n aligned channel data streams. Then, according to the alignment marker, the data of the n channels is reordered so that the data of the n channels can be arranged in a specified order. The n channel data streams after channel reordering are sent to the designed processor, which includes convolutional interleaving and muxing, for data order shuffling processing before being sent to the internal code encoder for internal code encoding. After internal code encoding, the data streams are processed and then sent to the channel transmission medium for transmission. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing, etc. Here, n is a positive integer greater than 1.

[0319] Figure 3(b) is a schematic diagram of the second type of data processing in the originating processing module of this application embodiment. As shown in Figure 3(b), in some practical application scenarios, the n channel data streams obtained after channel data alignment processing already meet the specified order arrangement. At this time, there is no need to perform channel reordering. The aligned n channel data streams are directly sent to the designed processor containing convolutional interleaving and multiplexing for interleaving and shuffling of the data order, and then sent to the internal code encoder for internal code encoding.

[0320] It should be understood that in some possible implementations, unlike the data processing flow described in Figures 3(a) and 3(b) above, the n-channel data streams that have been aligned after channel data alignment can also be multiplexed directly without convolutional interleaving and then sent to the internal code encoder for internal code encoding.

[0321] Figure 3(c) is a schematic diagram of the third type of data processing in the originating processing module of this application embodiment. As shown in Figure 3(c), unlike the data processing flow shown in Figure 3(a) above, the n channel data streams after channel reordering are not convolutionally interleaved, but are directly multiplexed and sent to the internal code encoder for internal code encoding.

[0322] Figure 3(d) is a schematic diagram of the fourth data processing method of the originating processing module in this application embodiment. As shown in Figure 3(d), unlike the data processing flow shown in Figure 3(b) above, the n channel data streams after channel data alignment processing are not convolutionally interleaved, but are directly multiplexed and sent to the internal code encoder for internal code encoding.

[0323] Figure 3(e) is a schematic diagram of channel data alignment processing in an embodiment of this application. It should be understood that the above-mentioned "channel data alignment processing" can be a lane de-skew process defined by existing standards, ensuring that the data of the n output channel data streams are fully aligned. Alternatively, the above-mentioned "channel data alignment processing" can also be simply channel symbol alignment, ensuring that the data on the n output channel data streams are aligned based on foreign code symbols, specifically based on one or more foreign code symbols. Figure 3(e) illustrates the specific operation of the above-mentioned "channel data alignment processing" using two channel data streams as an example, assuming that the foreign code is an RS code and that an RS code symbol is 10 bits long. In Figure 3(e), scenario (a) shows a 75-bit deviation between the two channel data streams, where AM0 and AM1 are the alignment identifiers for channel data stream 0 and channel data stream 1, respectively. Scenario (b) in Figure 3(e) uses a lane de-skew process defined by existing standards, ensuring that the output channel data stream 0 and channel data stream 1 are without deviation. In Figure 3(e), scenario (c) uses alignment based on one RS symbol, aligning one RS symbol of the output channel data stream 0 with one RS symbol of the output channel data stream 1. However, a 70-bit discrepancy still exists between the two channels. In Figure 3(e), scenario (d) uses alignment based on two RS symbols, aligning two RS symbols of the output channel data stream 0 with two RS symbols of the output channel data stream 1. However, a 60-bit discrepancy still exists between the two channels.

[0324] Figure 3(f) is a schematic diagram of the fifth data processing method of the transmitting end processing module in this embodiment. As shown in Figure 3(f), after the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes, it can obtain n Physical Coding Sublayer (PCS) or FEC channel data streams after external code encoding. Alignment locking and channel data alignment are then performed to obtain n aligned channel data streams. Then, according to the alignment marker, the data of the n channels is reordered so that the data of the n channels can be arranged in a specified order. The n channel data streams after channel reordering are sent to a processor designed with convolutional interleaving and block interleaving for interleaving to shuffle the data order before being sent to an internal code encoder for internal code encoding. After internal code encoding, the data streams are processed and then sent to the channel transmission medium for transmission. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing, etc. Here, n is a positive integer greater than 1.

[0325] Figure 3(g) is a schematic diagram of the sixth data processing method of the transmitting end processing module in this embodiment. As shown in Figure 3(g), after the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes, it can obtain n Physical Coding Sublayer (PCS) or FEC channel data streams after external code encoding, collectively referred to as channel data streams. Alignment locking and channel data alignment processing are then performed to obtain n aligned channel data streams. Then, according to the alignment marker, the data of the n channels is reordered so that the data of the n channels can be arranged in a specified order. The n channel data streams after channel reordering are sent to a designed processor containing first packet interleaving, convolutional interleaving, and second packet interleaving for interleaving and scrambling of the data order, and then sent to an internal code encoder for internal code encoding. After internal code encoding, the data streams are processed and sent to the channel transmission medium for transmission. This data processing may include modulation mapping (maPPing), channel interleaving, polarization distribution, or DSP framing, etc. Here, n is a positive integer greater than 1.

[0326] Figure 3(h) is a schematic diagram of the seventh data processing method of the transmitting end processing module in this embodiment. As shown in Figure 3(h), after the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes, it can obtain n Physical Coding Sublayer (PCS) or FEC channel data streams after external code encoding. Alignment locking and channel data alignment are then performed to obtain n aligned channel data streams. Then, according to the alignment marker, the data of the n channels is reordered so that the data of the n channels can be arranged in a specified order. The n channel data streams after channel reordering are sent to a processor designed with block interleaving and convolutional interleaving for interleaving and scrambling of the data order before being sent to an internal code encoder for internal code encoding. After internal code encoding, the data streams are processed and then sent to the channel transmission medium for transmission. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing, etc. Here, n is a positive integer greater than 1.

[0327] Figure 3(i) is a schematic diagram of the eighth data processing method of the transmitting end processing module in this embodiment. As shown in Figure 3(i), after the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from n synchronous client lanes, such as the AUI-n interface, it can obtain n channel data streams after external code encoding. Here, the PMA sublayer only needs to perform clock data recovery (CDR), PAM4 symbol demodulation, and other signal recovery operations on the data from each client lane to obtain one channel data stream. It does not need to perform other complex operations such as AM locking, channel correction, and channel reordering. The n channel data streams are sent to the designed processor containing convolutional interleaving for interleaving and scrambling of the data order, and then sent to the internal code encoder for internal code encoding. After data processing, the internal code encoded data streams are sent to the channel transmission medium for transmission. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing, etc. Here, n is a positive integer greater than 1.

[0328] It should be understood that in some practical applications, RS (Real RS) external code encoding involves interleaving after encoding with two encoders, such as using bidirectional interleaving (2-way interleaving). This ensures that the RS symbols on even-numbered channels are transmitted in the pattern "ABABAB…", while the RS symbols on odd-numbered channels are transmitted in the pattern "BA BA BA…", where A and B are two RS symbols generated by different encoders. For alignment based on two RS symbols, one implementation is to ensure that at any given time, the RS symbols on all even-numbered channels are generated by the same encoder, and the RS symbols on all odd-numbered channels are generated by another identical encoder; another implementation is to ensure that at any given time, the RS symbols on all channels are generated by the same encoder. The specific method is not limited here.

[0329] Figure 4(a) is a schematic diagram of the first type of data processing for the receiving end processing module in this embodiment of the application. As shown in Figure 4(a), the receiving end processing module receives the data stream from the channel transmission medium. When the data stream of the transmitting end processing module has undergone data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing, the receiving end processing module first performs the corresponding inverse data processing before sending it to the internal code decoder for decoding. After internal code decoding, the data stream is sent to the convolutional de-interleaving and de-muxing processor for processing to obtain n channel data streams, which are then sent to the PMA sublayer. The PMA sublayer processes the data stream and sends it to the receiving end device for external code decoding. Here, the convolutional de-interleaving and de-muxing processing in the receiving end processing module are the inverse operations of the convolutional interleaving and multiplexing processing in the transmitting end processing module. Among them, convolutional de-interleaving is the inverse operation of convolutional interleaving in the transmitting end processing module, and de-muxing is the inverse operation of multiplexing in the transmitting end processing module. The convolutional interleaving and multiplexing processes in the sender processing module are described in detail below. The convolutional deinterleaving and demultiplexing processes in the receiver processing module are the inverse operations of the convolutional interleaving and multiplexing processes in the sender processing module, as shown in Figures 3(a) and 3(b). This is well known to those skilled in the art, and will not be elaborated further here.

[0330] Figure 4(b) is a schematic diagram of the second type of data processing for the receiving end processing module in this embodiment of the application. As shown in Figure 4(b), the receiving end processing module receives the data stream from the channel transmission medium. When the data stream of the transmitting end processing module has undergone data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing, the receiving end processing module first performs the corresponding inverse data processing before sending it to the internal code decoder for decoding. After internal code decoding, the data stream is sent to the de-interleaving and deconvolution interleaving processor for processing to obtain n channel data streams, which are then sent to the PMA sublayer. The PMA sublayer processes the data stream and sends it to the receiving end device for external code decoding. Here, the de-interleaving and deconvolution interleaving processing in the receiving end processing module is the inverse operation of the block interleaving and convolution interleaving processing in the transmitting end processing module as shown in Figure 3(f). Among them, deconvolution interleaving is the inverse operation of convolution interleaving in the transmitting end processing module, and de-interleaving is the inverse operation of block interleaving in the transmitting end processing module.

[0331] Figure 4(c) is a schematic diagram of the third data processing for the receiving end processing module in this embodiment of the application. As shown in Figure 4(c), the receiving end processing module receives the data stream from the channel transmission medium. When the data stream of the transmitting end processing module has undergone data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing, the receiving end processing module first performs the corresponding inverse data processing before sending it to the internal code decoder for decoding. After internal code decoding, the data stream is sent to deinterleaving the second group interleaving, deconvolution interleaving, and deinterleaving the first group interleaving to obtain n channel data streams, which are then sent to the PMA sublayer. The PMA sublayer processes the data stream and sends it to the receiving end device for external code decoding. Here, the deinterleaving of the first group interleaving, deconvolution interleaving, and deinterleaving of the second group interleaving in the receiving end processing module are the inverse operations of the first group interleaving, convolution interleaving, and second group interleaving in the transmitting end processing module, as shown in Figure 3(g). The first group interleaving, convolution interleaving, and second group interleaving processes in the transmitting end processing module are described in detail below. The deinterleaving of the first group, the deinterleaving of the convolution, and the deinterleaving of the second group in the receiving end processing module are the inverse operations of the first group interleaving, the convolution interleaving, and the second group interleaving in the sending end processing module, respectively. As those skilled in the art will know, they will not be described in detail here.

[0332] The following sections first provide several specific scenarios in which the embodiments of this application can be applied. It should be noted that, for ease of explanation, each specific scenario below is described using "channel data alignment processing" with channel skew correction processing as an example.

[0333] Figure 5 This is a schematic diagram of a data stream using 32 PCS channels with a 1×800G interface at the transmitting device. Figure 5As shown, the transmitting device encodes the single 800GbE service data stream to be transmitted using KP4 RS(544,514) external code to obtain 32 PCS lane data streams. Each PCS lane data stream (0-15) has a 68-symbol interval, totaling 16*68 = 1088 symbols, containing two RS codewords. Adjacent symbols in each PCS lane data stream come from different RS codewords, and two symbols at the same position in two adjacent PCS lane data streams also come from different RS codewords. Similarly, each PCS lane data stream (16-31) has a 68-symbol interval, totaling 16*68 = 1088 symbols, containing two RS codewords. Adjacent symbols in each PCS lane data stream also come from different RS codewords, and two symbols at the same position in two adjacent PCS lane data streams also come from different RS codewords. The 32 PCS channel data streams are processed by the PMA and then sent to the sending processing module through the 800GAUI-8 connection unit interface.

[0334] Based on the data processing diagram of the originating processing module shown in Figure 3(a), the originating processing module uses the known alignment markers of the PCS channels to perform alignment lock on the channel data streams. Here, the known alignment markers for each of the 32 channels are different (see the *Ethernet Technology Consortium 800G Specification*). The originating processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, based on the alignment markers, it performs lane reordering processing on the n=32 channel data, ensuring that the n=32 channel data are arranged in a specified order. One possible order is... Figure 5 The data streams from the same channel are sorted from top to bottom in numbers from 0 to 31.

[0335] Figure 6 This is a schematic diagram of a data stream using 32 PCS channels with 2×400G interfaces at the transmitting device. Figure 6As shown, the transmitting device encodes the two 400GbE service data streams to be transmitted using KP4 RS(544,514) code-beyond-code to obtain two PCS channel data streams with a total of 32 streams, each containing 16 PCS channel data streams. Each data stream in PCS channel data streams 0-15 or 16-31 is spaced 68 symbols apart, totaling 16*68=1088 symbols, which includes two RS codewords. Adjacent symbols in each PCS channel data stream come from different RS codewords, and two symbols at the same position in two adjacent PCS channel data streams come from different RS codewords. After PMA processing, the 32 PCS channel data streams are sent to the transmitting processing module through the connection unit interface 2×400GAUI-4.

[0336] Based on the data processing diagram of the originating processing module shown in Figure 3(a), the originating processing module uses the known alignment markers of PCS channels 0-15 or PCS channels 16-31 to perform alignment lock on the 16 channel data streams. Here, PCS channels 0-15 can be considered as PCS channels 0-15 in channel 0 of the 400G, and PCS channels 16-31 can be considered as PCS channels 0-15 in channel 1 of the 400G. The known alignment markers of the 16 channels in channel 0 of the 400G are the same as those of the 16 channels in channel 1. The originating processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, according to the alignment markers of PCS channels 0-15 or PCS channels 16-31, the data of the 16 channels is reordered so that the data of the 16 channels can be arranged in a specified order. Finally, the data of the 32 channels is arranged in a specified order. One order is with Figure 6 The data streams from the same channel are sorted from top to bottom in numbers from 0 to 31.

[0337] Figure 7 This is a schematic diagram of a data stream using 32 PCS channels with 4×200G interfaces at the transmitting device. Figure 7As shown, the transmitting device encodes the four 200GbE service data streams to be transmitted using KP4 RS(544,514) code-beyond-code encoding to obtain four PCS channel data streams totaling 32, with each channel comprising eight PCS channel data streams. Each data stream in PCS channel data streams 0-7, 8-15, 16-23, or 24-31 is spaced 136 symbols apart, totaling 8 * 136 = 1088 symbols, containing two RS codewords. Adjacent symbols in each PCS channel data stream come from different RS codewords, and two symbols at the same position in two adjacent PCS channel data streams come from different RS codewords. After PMA processing, the 32 PCS channel data streams are sent to the transmitting processing module via the 4×200GAUI-2 connection unit interface.

[0338] Based on the data processing diagram of the originating processing module shown in Figure 3(a), the originating processing module uses the known alignment markers of PCS channels 0-7, 8-15, 16-23, or 24-31 to perform alignment lock on the eight channel data streams. Here, PCS channels 0-7, 8-15, 16-23, or 24-31 can be considered as PCS channels 0-7 in the 0th, 1st, 2nd, or 3rd 200G channels, respectively. The originating processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, based on the alignment markers of PCS channels 0-7, 8-15, 16-23, or 24-31, it performs lane reorder processing on the data of the eight channels, so that the data of the eight channels can be arranged in a specified order. This allows the data from the 32 channels to be arranged in a specified order. One possible order is... Figure 7 The data streams from the same channel are sorted from top to bottom in numbers from 0 to 31.

[0339] Figure 8 This is a schematic diagram of a data stream using 32 FEC channels with an 8×100G interface at the transmitting device. Figure 8As shown, the transmitting device encodes the eight 100GbE service data streams to be transmitted using KP4 RS(544,514) code-beyond-code encoding to obtain eight FEC lane data streams with a total of 32 lanes, each including four FEC lane data streams. When using the "100G RS-FEC-Int" mode with two KP4 RS(544,514) codewords interleaved, each data stream in FEC lane data streams 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 is spaced 272 symbols apart, totaling 4*272=1088 symbols, which contains two RS codewords. In each FEC channel data stream, two adjacent symbols come from different RS codewords, and two symbols at the same position in two adjacent FEC channel data streams come from different RS codewords. After processing by the PMA, the 32 FEC channel data streams are sent to the transmitting end processing module through the connection unit interface 8×100GAUI-1.

[0340] Figure 9 This is another schematic diagram of a 32-channel FEC data stream using an 8×100G interface at the transmitting device. (See diagram below.) Figure 9 As shown, it differs from the above. Figure 8 In this scenario, the transmitting device adopts the "100G RS-FEC" mode. Each data stream in FEC channel data streams 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 is spaced 136 symbols apart, totaling 4 * 136 = 544 symbols, which includes one RS codeword. After processing by the PMA, the 32 FEC channel data streams are sent to the transmitting processing module via the 8×100GAUI-1 connection unit interface.

[0341] Based on the data processing diagram of the sending-end processing module shown in Figure 3(a), the sending-end processing module uses the known alignment markers of FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 to perform alignment lock on the four channel data streams. Here, FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 can be considered as FEC channel 0-3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channels, respectively. The originating processing module then performs lane de-skew on the 32 channel data streams to obtain aligned 32 channel data streams. Next, based on the alignment markers of FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31, it performs lane reordering on the data of four channels, arranging the data in a specified order. Finally, the data of all 32 channels is arranged in a specified order. One possible order is... Figure 8 and Figure 9 The data streams from the same channel are sorted from top to bottom in numbers from 0 to 31.

[0342] Figure 10 This is a schematic flowchart of a data processing method provided in an embodiment of this application.

[0343] 1001. Perform convolution and interleaving on n channel data streams to obtain n first data streams.

[0344] In this embodiment, the channel data stream can be either a PCS channel data stream or an FEC channel data stream; the specific type is not limited here. All n channel data streams are data streams encoded using the first FEC, which is the data stream encoded using the external code described above, where n is an integer greater than 1. For example, the external code encoding can use RS code, and the n data streams after external code encoding can include multiple RS codewords. In practical applications, other encoding methods can also be used for external code encoding. For ease of description, RS codewords will be used uniformly below to represent the codewords generated after external code encoding. It should be understood that each 'a' codeword after external code encoding is distributed across b channel data streams, where a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. In the above... Figures 5-9In the different application scenarios shown, the values ​​of a and b may also be different. Figure 5 Taking the application scenario shown as an example, n=32, a=2, b=16, meaning that every 2 codewords are distributed across 16 data stream channels. Figures 6-9 The values ​​of a and b in other application scenarios can be derived from the attached diagrams, and will not be elaborated here. It should be noted that the foreign code length in this application is counted in units of symbols, where a symbol can include one or more bits. For example, the foreign code uses the KP4 RS(544,514) code, with a code length N = 544 symbols, and one symbol contains 10 bits.

[0345] As an example, when a=1, it means that the codewords encoded with external codes at the transmitting device 01 are not interleaved and are directly distributed in the b-channel data stream. For example... Figure 9 As shown, when a=1, the codewords of N=544 symbols encoded by the external code KP4 at the transmitting device 01 are not interleaved and are directly distributed in the data stream of b=4 channels. Figure 9 The 544 symbols in one dashed frame shown in the diagram come from the same KP4 codeword, and in one channel of data stream within each dashed frame, N / b = 544 / 4 = 136 consecutive symbols come from the same KP4 codeword.

[0346] As another example, when a > 1, it means that the a codewords encoded with external codes at the transmitting device 01 are first interleaved and then distributed in the b channel data streams. For example... Figure 8 As shown, a=2. The two codewords encoded by the external code KP4 at the transmitting device 01, totaling aN=2*544=1088 symbols, are first subjected to two-way symbol interleaving and then distributed in the data stream of b=4 channels. Figure 8 The dashed box shown contains 1088 symbols from a = 2 KP4 codewords. Within each dashed box, in one channel of data stream, 2N / b = 2 * 544 / 4 = 272 consecutive symbols from a = 2 KP4 codewords, with adjacent symbols coming from different KP4 codewords. For example... Figure 5 As shown, a=2. The two codewords encoded by the external code KP4 at the transmitting device 01, totaling aN=2*544=1088 symbols, are first bidirectionally interleaved and then distributed in the data stream of b=16 channels. Figure 5 The dashed box shown contains 1088 symbols from a = 2 KP4 codewords. In each dashed box, in a single channel data stream, there are 2N / b = 2 * 544 / 16 = 68 consecutive symbols from a = 2 KP4 codewords, and adjacent symbols come from different KP4 codewords.

[0347] It should be noted that after convolutional interleaving, each consecutive z symbols in the first data stream come from z different codewords, where z is an integer greater than 1. The specific implementation of convolutional interleaving will be introduced below.

[0348] Figure 11 This is a schematic diagram illustrating a structure in this application where n channel data streams are convolved and interleaved. For example... Figure 11 As shown, n convolutional interleavers can be used to convolve and interleave n channel data streams respectively. After convolution and interleaving, each channel data stream can obtain a first data stream with shuffled data order. It should be noted that in this embodiment, each convolutional interleaver uses a similar method to convolve and interleave the input channel data stream. Specifically, each convolutional interleaver includes p delay lines. Each convolutional interleaver delays the input channel data stream according to the p delay lines to obtain the first data stream. Here, p is an integer greater than 1. The number of storage units included in each delay line is different. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit is used to store d symbols, z = p * d. The symbols in each channel data stream are sequentially input to the p delay lines according to their sequence numbers. Each delay line inputs d symbols at a time and outputs d symbols at a time. The consecutive p * d symbols in the first data stream include the d symbols output by each delay line. Where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, if p delay lines each include 0, Q, 2Q, ..., (p-1)Q storage units, and each storage unit stores d symbols, then the p delay lines correspond to p delay values, which include 0, Q×d, 2Q×d, ..., (p-1)Q×d symbols. It should be noted that in this application, delay values ​​are counted in units of symbols, where a symbol can include one or more bits. The more symbols a delay line includes in its delay values, the longer the delay (also called latency) of that delay line on the data stream. It should be understood that when a delay line does not contain any storage units, the delay of the delay line is 0 symbols, which is called zero-latency pass-through.

[0349] The specific structure of the convolutional interleaver is described below with reference to the accompanying diagram.

[0350] Figure 12(a) is a schematic diagram of the first structure of the convolutional interleaver in this embodiment. As shown in Figure 12(a), the number of storage units in the p delay lines decreases sequentially according to the sequence number of the p delay lines. That is, delay line 0 has (p-1)Q storage units, each delay line decreases by Q storage units sequentially, and delay line p-1 has 0 storage units. Figure 12(b) is a schematic diagram of the second structure of the convolutional interleaver in this embodiment. As shown in Figure 12(b), the number of storage units in the p delay lines increases sequentially according to the sequence number of the p delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units sequentially, and delay line p-1 has (p-1)Q storage units.

[0351] It should be noted that at any given moment, the input and output switches of the convolutional interleaver are located on the same delay line. After the current delay line inputs and outputs d symbols in a single operation, the switch is switched to the next delay line. This ensures that the symbols in each channel's data stream are sequentially input to the p delay lines according to their respective delay line numbers, and that the p*d consecutive symbols in the first data stream include the d symbols output by each delay line. The specific data read / write operations are as follows: d symbols are read from the storage unit closest to the output port of the current delay line. The d symbols stored in each storage unit of the current delay line are transferred to the next storage unit. Then, the d symbols are written to the storage unit closest to the input port of the current delay line. Afterward, the switch is made to the next delay line, and the above operations are repeated, and so on. In one possible implementation, if the convolutional interleaver shown in Figure 12(a) is used, the parameters of the convolutional interleaver should satisfy d(p*Q+1)≥a*N / b, where N is the codeword length, so that p*d consecutive symbols in the first data stream output by the convolutional interleaver come from p*d different foreign codewords, where d≤a. In another possible implementation, if the convolutional interleaver shown in Figure 12(b) is used, the parameters of the convolutional interleaver should satisfy d(p*Q-1)≥a*N / b, where N is the codeword length, so that p*d consecutive symbols in the first data stream output by the convolutional interleaver come from p*d different foreign codewords, where d≤a.

[0352] It should be understood that when the same parameters p, Q, and d are used, the convolutional interleaving process in Figure 12(a) and the convolutional interleaving process in Figure 12(b) are the inverse operations of each other. That is, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 12(a), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 12(b). Similarly, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 12(b), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 12(a).

[0353] It should also be understood that any one of the n convolutional interleavers can adopt one of the structures shown in Figure 12(a) or Figure 12(b). In practical applications, all n convolutional interleavers can adopt the structure shown in Figure 12(a); or, all n convolutional interleavers can adopt the structure shown in Figure 12(b); or, some convolutional interleavers can adopt the structure shown in Figure 12(a), and the remaining convolutional interleavers can adopt the structure shown in Figure 12(b).

[0354] It should be noted that in some specific application scenarios, taking n=32 as an example, the value of p can be 2, 3, 4, 6 or 8, and the value of d can be 1 or 2.

[0355] For ease of explanation, the embodiments involving convolutional interleaving described below are all illustrated using the structure shown in Figure 12(a) with n convolutional interleavers. Of course, it can be easily extended to other structures listed above. The specific implementation methods are known to those skilled in the art and will not be elaborated here.

[0356] In some possible implementations, before convolving and interleaving the n channel data streams to obtain the n first data streams, the n channel data streams can be reordered so that they are arranged in a preset order. Taking 32 data streams as an example, the 32 data streams can be arranged from top to bottom in the order of 0 to 31. Of course, it can be easily extended to other orders. The specific implementation methods are known to those skilled in the art and will not be described in detail here.

[0357] In some possible implementations, before convolving and interleaving the n channel data streams to obtain the n first data streams, channel data alignment processing can be performed on the n channel data streams. This channel data alignment processing can be a lane de-skew process defined by existing standards, ensuring that the data in the output n channel data streams are fully aligned. Alternatively, the above-mentioned "channel data alignment processing" can also be simply channel symbol alignment, ensuring that the data in the output n channel data streams are aligned based on foreign code symbols, specifically based on one foreign code symbol or multiple foreign code symbols. For a detailed description of the channel data alignment processing, please refer to the relevant description in Figure 3(e) above, which will not be repeated here.

[0358] 1002. Multiplex every K first data streams from n first data streams to obtain 1 second data stream, so as to obtain a total of m second data streams.

[0359] Figure 13 This is a schematic diagram illustrating a structure for multiplexing n first data streams in an embodiment of this application. For example... Figure 13As shown, multiplexing can be performed using m multiplexers. Specifically, every K first data streams from the n first data streams are input to one multiplexer, and this multiplexer outputs one second data stream. The m multiplexers will output a total of m second data streams, where m = n / K, and k is an integer greater than 1. For ease of description, this embodiment uses the example of an integer n being divisible by K. It should be noted that the n first data streams include G subsets of first data streams, where G is an integer greater than 1, and the symbols in different subsets of first data streams come from different codewords. In one possible implementation, if K ≤ G, one first data stream is selected from each of the K subsets of first data streams, that is, the K first data streams input to a multiplexer come from the K subsets of first data streams respectively. In another possible implementation, if K > G, then K / G first data streams are selected from each subset of first data streams, that is, the K first data streams input to a multiplexer include K / G first data streams from each subset of first data streams. For example, if n = 32, G = 2, K = 4, and m = 8, since K > G, two first data streams need to be taken from each of the two first data stream subsets to obtain four first data streams for the input multiplexer. As another example, if n = 32, G = 4, K = 2, and m = 8, since K < G, two first data stream subsets need to be randomly selected from the four first data stream subsets, and one first data stream needs to be taken from each of these two subsets to obtain two first data streams for the input multiplexer.

[0360] It should be noted that in some specific application scenarios, taking n=32 as an example, the value of K can be 2, 4 or 8.

[0361] It should be understood that the above-mentioned first data stream subset is a concept introduced for ease of description. In practical applications, the n first data streams are a whole and there is no division. Each first data stream subset can be regarded as one or more data streams among the n first data streams.

[0362] It should be noted that since each consecutive z symbols in the first data stream participating in multiplexing come from z different codewords, each consecutive y symbols in the second data stream after multiplexing come from y different codewords, where y > z. In one possible implementation, if K ≤ G, then y = K * z. In another possible implementation, if K > G, then y = G * z.

[0363] The following section describes the specific implementation of multiplexing. For ease of description, the K first data streams input to the multiplexer will be referred to as multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, ..., and multiplexed input data stream K-1.

[0364] Figure 14This is a schematic diagram of the first structure of the multiplexer in an embodiment of this application. For example... Figure 14 As shown, Let Δ represent the multiplexing of Δ consecutive symbols in the input data stream j, which come from Δ different foreign codewords, where 0≤j≤K-1. If K≤G, Δ is a divisor of z; if K>G, Δ=z. This represents Δ·W consecutive RS symbols in the multiplexed input data stream j. It should be noted that the second data stream output by the multiplexer comprises multiple subsets of second data stream symbols, each subset containing K groups of symbols, and each group containing Δ symbols. Furthermore, adjacent groups of symbols within each second data stream subset originate from different subsets of the first data stream. Specifically, the j-th group of symbols in the second data stream subset originates from the j-th multiplexed input data stream among the K multiplexed input data streams, where 0 ≤ j ≤ K-1. It is important to note that if K > G, then two adjacent multiplexed input data streams among the K multiplexed input data streams originate from different subsets of the first data stream. Furthermore, it is important to note that if K > G, each of the G consecutive multiplexed input data streams originates from a different subset of the first data stream.

[0365] It should be noted that since adjacent groups of symbols in each subset of the second data stream come from different subsets of the first data stream, consecutive y symbols in the multiplexed second data stream come from different y codewords, where y > z (y = K*z or y = G*z). It should be understood that obtaining the result of consecutive y symbols from different y codewords in the output data stream solely through convolutional interleaving requires significant latency. In this scheme, however, comparable performance is achieved by reducing the time occupied by convolutional interleaving while combining multiplexing. Furthermore, the time occupied by multiplexing is relatively short, and combining convolutional interleaving and multiplexing allows for comparable performance with even shorter latency.

[0366] It should be understood that the above-mentioned second data stream symbol subset is a concept introduced for ease of description. In practical applications, the symbols in the second data stream are a whole and there is no division. Each second data stream symbol subset can be regarded as multiple symbols in the second data stream.

[0367] by Figure 14 For example, Let it be the 0th subset of the second data stream symbols. Let be denoted as the first subset of symbols of the second data stream, ..., Let this be denoted as the Wth subset of second data stream symbols. Taking the 0th subset of second data stream symbols as an example... This represents the Δth symbol in group 0. This represents the Δ symbols in the first group, ..., This represents the Δth symbol in the (K-1)th group. It can be seen that... from multiplexed input data stream 0, from multiplexed input data stream 1, ..., from multiplexed input data stream K-1. It should be understood that, assuming Δ=z, z consecutive symbols in come from z different codewords, z consecutive symbols in come from z different codewords, ... . If it is required that after multiplexing, y consecutive symbols in the second data stream come from y different codewords, where y>z, then and shall come from different first data stream subsets, that is, multiplexed input data stream 0 and multiplexed input data stream 1 come from different first data stream subsets. Similarly, and shall come from different first data stream subsets, that is, multiplexed input data stream 1 and multiplexed input data stream 2 come from different first data stream subsets, and so on. In this way, after multiplexing, every 2*z consecutive symbols in the second data stream come from 2*z different outer code codewords. It should be noted that if K>G, every G consecutive multiplexed input data streams come from different first data stream subsets, specifically, multiplexed input data stream 0 to multiplexed input data stream G-1 come from different first data stream subsets, multiplexed input data stream G and multiplexed input data stream 2*G-1 come from different first data stream subsets, and so on. In this way, every G*z consecutive symbols in the multiplexed second data come from G*z different outer code codewords.

[0368] That is to say, through the above method, the multiplexer outputs the data of K input data streams to a second data stream in a polling manner with Δ symbols as a unit, that is, sequentially outputs Δ symbols from each of multiplexed input data stream 0 to multiplexed input data stream K-1 to generate the second data stream, and the corresponding data sequence of the second data stream is When K≤G, the K first data streams selected from the first data stream subsets can correspond to multiplexed input data stream 0 to multiplexed input data stream K-1 of the multiplexer in any order, and Δ is a divisor of z, any K*z consecutive symbols in the second data stream after multiplexing output come from different outer code codewords. When K>G, the K first data streams selected from the first data stream subsets need to correspond to multiplexed input data stream 0 to multiplexed input data stream K-1 of the multiplexer according to a certain rule. The specific rule is that every G consecutive multiplexed input data streams of the multiplexer come from different first data stream subsets. A specific manner is that multiplexed input data stream i*G to multiplexed input data stream i*G+G-1 respectively come from first data stream subset 0 to first data stream subset G-1, where 0≤i<K / G. This enables every G*z consecutive symbols in the second data stream output by the multiplexer to come from different outer code codewords.

[0369] 1003. Perform second FEC encoding on each of the m second data streams to obtain the encoded data stream.

[0370] Figure 15 This is a schematic diagram illustrating a structure for FEC encoding of m second data streams in an embodiment of this application. For example... Figure 15 As shown, the m second data streams are each subjected to second FEC encoding, i.e., the internal code encoding mentioned above. The information bit length of the internal code encoding is less than or equal to y RS symbols. After internal code encoding, the data streams are processed and sent to the channel transmission medium for transmission. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing, etc. For example, the internal code encoded data streams can be interleaved before transmission to improve the system's ability to withstand burst errors.

[0371] In this embodiment, all n-channel data streams are codeword streams encoded with external codes. Convolutional interleaving is then performed on each of the n data streams, and the convolutionally interleaved n data streams are multiplexed into m second data streams, which are then encoded with internal codes. By employing the data interleaving and multiplexing processing scheme provided in this application, multiple symbols continuously output from multiple different external codewords in the multiplexed m data streams can be achieved with a shorter latency. This allows the cascaded FEC scheme to reduce data interleaving latency while maintaining good performance. In other words, the combination of convolutional interleaving and data multiplexing in this application results in a lower overall latency for the cascaded FEC scheme, making it more suitable for applications requiring low latency.

[0372] The above will be explained below with reference to some specific embodiments. Figure 10 The process of the described data processing method will be further described.

[0373] Example 1: Applied to a 1×800G interface scenario, the internal code encoding information bit length is 120 bits, using 2:1, 4:1, 8:1 multiplexers, and channel correction processing is adopted.

[0374] Based on the data processing diagram of the originating processing module shown in Figure 3(a), the originating processing module uses the known alignment markers of the PCS channels to perform alignment lock on the channel data streams. Here, the known alignment markers for each of the 32 channels are different (see the *Ethernet Technology Consortium 800G Specification*). The originating processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 fully aligned channel data streams. Then, based on the alignment markers, it performs lane reordering processing on the n=32 channel data, ensuring that the n=32 channel data are arranged in a specified order. One possible order is... Figure 5 The data streams from the same channel are sorted from top to bottom in numbers from 0 to 31.

[0375] The n=32 channel data streams, after channel reordering, are fed into the designed convolutional interleaving and multiplexing processor for processing including convolutional interleaving and multiplexing, and then sent to the internal code encoder for internal code encoding. The internally encoded data streams undergo further data processing before being transmitted through the channel transmission medium. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing, etc.

[0376] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleavers 0, convolutional interleavers 1, convolutional interleavers 2, ..., convolutional interleavers 31 use the same interleaving structure.

[0377] Figure 16(a) is a schematic diagram of the third structure of the convolutional interleaver in this application embodiment. As shown in Figure 16(a), it includes p = 3 delay lines. These p = 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is used to store d = 2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, i.e., no delay.

[0378] As shown in Figure 16(a), C r (.) represents an RS symbol in the data stream r (0 ≤ r ≤ n-1) of this channel. For example, C r (6t), C r(6t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream r, and C r (6t-12Q), C r (6t-12Q+1) represents the two RS symbols output from delay line 0; C r (6t+2), C r (6t+3) represents the next two RS symbols input to delay line 1 in the channel data stream, and C r (6t-6Q+2), C r (6t-6Q+3) represents the two RS symbols output from delay line 1; C r (6t+4), C r (6t+5) represents the next two RS symbols input to delay line 2 in the channel data stream, and C r (6t+4), C r (6t+5) represents the two RS symbols output from delay line 2; C r (6t+6), C r (6t+7) represents the two RS symbols subsequently input to delay line 0 in the channel data stream, and C r (6t-12Q+6), C r (6t-12Q+7) represents the two RS symbols output from delay line 0, and so on. Combined with... Figure 5 It can be seen that when 6Q+2≥68, i.e., Q≥11, the C of the convolutional interleaving output... r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), C r (6t+5) A total of 6 RS symbols come from 6 different RS codewords.

[0379] Figure 16(b) is a schematic diagram of the fourth structure of the convolutional interleaver in an embodiment of this application. As shown in Figure 16(b), in one possible implementation, Q = 11 is selected, and the specific structure of the convolutional interleaver is shown in Figure 16(b). Its corresponding interleaving delay is approximately 22 * ​​2 * 3 / 2 = 66 RS symbols. Using the convolutional interleaver shown in Figure 16(b), 32 PCS channel data streams are convolutionally interleaved to obtain 32 first data streams. (Reference) Figure 5As shown in the PCS channel data stream, it is easy to understand that any RS symbol in the first data stream 0-15 comes from a different RS codeword than any RS symbol in the first data stream 16-31. Therefore, the 32 first data streams contain G = 2 subsets of the first data stream, with first data streams 0-15 being subset 0 and first data streams 16-31 being subset 1. Referring to Figure 16(a), it is easy to understand that the 6 output symbols C of any data stream r_0 in subset 0 of the first data stream... r_0 (6t-12Q), C r_0 (6t-12Q+1), C r_0 (6t-6Q+2), C r_0 (6t-6Q+3), C r_0 (6t+4), C r_0 (6t+5) and the 6 output symbols C of any data stream r_1 in the first data stream subset 1. r_1 (6t-12Q), C r_1 (6t-12Q+1), C r_1 (6t-6Q+2), C r_1 (6t-6Q+3), C r_1 (6t+4), C r_1 (6t+5), a total of 12 RS symbols come from 12 different RS codewords.

[0380] This embodiment adopts Figure 13 One possible implementation of the multiplexing process shown is G=2, K=2, m=16, which generates 16 second data streams, which contain 16 2:1 multiplexing processing modules, and randomly select one first data stream from each of the first data stream subset 0 and the first data stream subset 1 as the input of the 2:1 multiplexer.

[0381] Figure 17(a) is a schematic diagram of the second structure of the multiplexer in an embodiment of this application. As shown in Figure 17(a), the two input data streams of the 2:1 multiplexer i (0≤i≤15) are the first data stream i and the first data stream i+16, respectively. The 2:1 multiplexer represents Δ = 6 consecutive RS symbols in its multiplexed input data stream j, derived from 6 different external RS codewords. The 2:1 multiplexer outputs data from the two input data streams in a polling manner, in units of 6 RS symbols, to the output data stream; that is, the output data order is... It should be noted that since K=G=2, Δ=1,2,3 can also make 12 consecutive RS symbols in the multiplexer output data stream come from 12 different RS codewords.

[0382] This embodiment adopts Figure 13Another possible implementation of the multiplexing process shown is G=2, K=4, m=8, which generates 8 second data streams, containing 8 4:1 multiplexers. Two first data streams are randomly selected from each of the first data stream subset 0 and the first data stream subset 1 as inputs to the 4:1 multiplexers.

[0383] Figure 17(b) is a schematic diagram of the third structure of the multiplexer in this embodiment. As shown in Figure 17(b), the multiplexed input data streams 0, 1, 2, and 3 of the 4:1 multiplexer i (0≤i≤7) correspond to the first data stream i, first data stream i+16, first data stream i+8, and first data stream i+24, respectively. That is, any two consecutive multiplexed input data streams of the multiplexer come from different subsets of the first data stream. This represents Δ = 6 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 3) of the 4:1 multiplexer, which come from 6 different external RS codewords. The 4:1 multiplexer outputs data from the 4 input data streams in a polling manner, in units of 6 RS symbols, to the output data stream, i.e., the output data order is... The output data stream contains 12 consecutive RS symbols derived from 12 different RS codewords.

[0384] This embodiment adopts Figure 13 Another possible implementation of the multiplexing process shown is G=2, K=8, m=4, which generates four second data streams, each containing four 8:1 multiplexers. Four first data streams are randomly selected from each of the first data stream subsets 0 and 1 as inputs to the 8:1 multiplexers.

[0385] Figure 17(c) is a schematic diagram of the fourth structure of the multiplexer in this application embodiment. As shown in Figure 17(c), the multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0≤i≤3) correspond to the first data stream i, the first data stream i+16, the first data stream i+8, the first data stream i+24, the first data stream i+4, the first data stream i+20, the first data stream i+12, and the first data stream i+28, respectively. That is, any two consecutive multiplexed input data streams of the multiplexer come from different subsets of the first data stream. It should be noted that the multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0≤i≤3) can also correspond to the first data stream i, the first data stream i+16, the first data stream i+4, the first data stream i+20, the first data stream i+8, the first data stream i+24, the first data stream i+12, and the first data stream i+28, respectively. That is, any two consecutive multiplexed input data streams of the multiplexer come from different subsets of the first data stream. In the picture This represents Δ = 6 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 7) of the 8:1 multiplexer, which come from 6 different external RS codewords. The 8:1 multiplexer outputs data from the 8 input data streams in a polling manner, in units of 6 RS symbols, to the output data stream, i.e., the output data order is... The output data stream contains 12 consecutive RS symbols derived from 12 different RS codewords.

[0386] The aforementioned 16, 8, or 4 second data streams are each encoded using internal codes, with each internal code having a bit length of 120 bits. Specifically, the internal code encoder adds redundancy to 12 consecutive RS symbols (totaling 120 bits) in each second data stream to obtain an internal codeword data stream. In one possible implementation, Hamming(128, 120) is used for internal code encoding, adding 8 bits of redundancy to 12 consecutive RS symbols (totaling 120 bits) in each second data stream to obtain a 128-bit codeword. In another possible implementation, BCH(136, 120) is used for internal code encoding, adding 16 bits of redundancy to 12 consecutive RS symbols (totaling 120 bits) in each second data stream to obtain a 136-bit codeword.

[0387] After being encoded using internal codes, the data stream undergoes data processing before being transmitted through the channel transmission medium. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing. For example, interleaving the internally encoded data stream can improve the system's resilience to burst errors.

[0388] Using the data interleaving coding scheme of this embodiment 1, the KP4 RS(544,514)+Hamming(128,120) concatenated code under AWGN achieves a post-correction bit error rate (BER) of 1E-15, with a pre-correction BER of approximately 4.5E-3, which approximates the optimal performance of the concatenated FEC scheme.

[0389] Example 2: Applied to a 1×800G interface scenario, the internal code encoding information bit length is 120 bits, using 2:1, 4:1, 8:1 multiplexers, and channel symbol alignment.

[0390] The main difference between Example 2 and Example 1 is that Example 2 is based on the alignment of two RS symbols to obtain an aligned 32-channel data stream.

[0391] Specifically, based on the data processing diagram of the originating processing module shown in Figure 3(a), the originating processing module uses the known alignment marker of the PCS channel to perform alignment lock on the channel data stream. The originating processing module then aligns the 32 channel data streams using two RS symbols to obtain 32 aligned channel data streams. Then, according to the alignment marker, the data of the 32 channels is reordered so that the data of the 32 channels can be arranged in a specified order. One arrangement order is the same as in Figure 3(a), where the channel data streams are sorted from top to bottom from 0 to 31. Another arrangement order is such that the first 16 channel data streams in the 32 channels output by "channel reordering" contain PCS channel data streams 0-15, and the last 16 channels contain PCS channel data streams 16-31. It should be understood that the specific order of the first 16 channel data streams and the last 16 channel data streams are not limited in this case. In other words, channel data stream i in Figure 3(a) does not necessarily correspond to PCS channel data stream i.

[0392] The 32 channel data streams, after channel reordering, are fed into a processor incorporating convolutional interleaving and multiplexing for interleaving and scrambling. After this process, the data is then fed into an internal code encoder for encoding. The encoded data streams undergo further processing before being transmitted through the channel transmission medium. It should be understood that the convolutional interleaving and multiplexing, as well as the internal code encoding scheme used in this embodiment, are all based on the scheme in Embodiment 1.

[0393] The data interleaving coding scheme of Embodiment 2, with its KP4 RS(544,514)+Hamming(128,120) concatenated code under AWGN, achieves a post-correction bit error rate (BER) of 1E-15, corresponding to a pre-correction BER of approximately 4.5E-3. This performance is comparable to the scheme of Embodiment 1, and it also exhibits lower overall latency. However, compared to the scheme of Embodiment 1, the scheme of Embodiment 2 is less effective against burst system errors. This scheme is suitable for scenarios requiring even lower latency.

[0394] Example 3: Applied to a 1×800G interface scenario, the internal code encoding information bit length is 160 bits, using 2:1, 4:1, 8:1 multiplexers, and channel correction processing is adopted.

[0395] Based on Example 1, this example considers an internal code with a code length of 160 bits and adopts a newly designed convolutional interleaver accordingly.

[0396] In this embodiment, the convolutional interleaving process is as follows: Figure 11The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleavers 0, convolutional interleavers 1, convolutional interleavers 2, ..., convolutional interleavers 31 use the same interleaving structure.

[0397] Figure 18(a) is a schematic diagram of the fifth structure of the convolutional interleaver in this application embodiment. As shown in Figure 18(a), it includes p = 4 delay lines. These 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, with each storage unit used to store d = 2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

[0398] As shown in Figure 18(a), C r (.) represents an RS symbol in the data stream r (0 ≤ r ≤ n-1) of this channel. For example, C r (8t), C r (8t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream r, and C r (8t-24Q), C r (8t-24Q+1) represents the two RS symbols output from delay line 0; C r (8t+2), C r (8t+3) represents the next two RS symbols input to delay line 1 in the channel data stream, and C r (8t-16Q+2), C r (8t-16Q+3) represents the two RS symbols output from delay line 1; C r (8t+4), C r (8t+5) represents the next two RS symbols input to delay line 2 in the channel data stream, and C r (8t-8Q+4), C r (8t-8Q+5) represents the two RS symbols output from delay line 2; C r (8t+6), C r (8t+7) represents the two RS symbols subsequently input to delay line 3 in the channel data stream, and C r (8t+6), C r (8t+7) represents the two RS symbols output from delay line 3, and so on. Combined with... Figure 5 It can be seen that when 8Q+2≥68, i.e., Q≥9, the C of the convolutional interleaving output... r (8t-24Q), C r (8t-24Q+1), C r(8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+

[0399] 4), C r (8t-8Q+5), C r (8t+6), C r (8t+7), a total of 8 RS symbols come from 8 different RS codewords.

[0400] Figure 18(b) is a schematic diagram of the sixth structure of the convolutional interleaver in this application embodiment. As shown in Figure 18(b), in one possible implementation, Q=9 is selected, and the specific structure of the convolutional interleaver is shown in Figure 18(b). Its corresponding interleaving delay is approximately 27*2*4 / 2=108 RS symbols. Using the convolutional interleaver shown in Figure 18(b), 32 PCS channel data streams are convolutionally interleaved to obtain 32 first data streams. (Reference) Figure 5 As shown in the PCS channel data stream, it is easy to understand that any RS symbol in the first data stream 0-15 comes from a different RS codeword than any RS symbol in the first data stream 16-31. Therefore, the 32 first data streams contain G = 2 subsets of the first data stream, with first data streams 0-15 being subset 0 and first data streams 16-31 being subset 1. Referring to Figure 18(a), it is easy to understand that the 8 output symbols C of any data stream r_0 in subset 0 of the first data stream... r_0 (8t-24Q), C r_0 (8t-24Q+1), C r_0 (8t-16Q+2), C r_0 (8t-16Q+3), C r_0 (8t-8Q+4), C r_0 (8t-8Q+5), C r_0 (8t+6), C r_0 (8t+7), and the 8 output symbols C of any data stream r_1 in the first data stream subset 1. r_1 (8t-24Q), C r_1 (8t-24Q+1), C r_1 (8t-16Q+2), C r_1 (8t-16Q+3), C r1 (8t-8Q+4), C r_1 (8t-8Q+5), C r_1 (8t+6), C r_1 (8t+7), a total of 16 RS symbols from 16 different RS codewords.

[0401] This embodiment adopts Figure 13One possible implementation of the multiplexing process shown is G=2, K=2, m=16, generating 16 second data streams. This process includes 16 2:1 multiplexing modules, each arbitrarily selecting one first data stream from subset 0 and subset 1 as input to the 2:1 multiplexer. A specific implementation of the corresponding 2:1 multiplexer is shown in Figure 17(a), where the two input data streams of the 2:1 multiplexer i (0≤i≤15) are the first data stream i and the first data stream i+16, respectively. (Figure...) This represents Δ = 8 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 1) of the 2:1 multiplexer, which come from 8 different external RS codewords. The 2:1 multiplexer outputs data from the two input data streams to the output data stream in a polling manner, in units of 8 RS symbols, i.e., the output data order is... The 16 consecutive RS symbols in the output data stream come from 16 different RS codewords. It should be noted that K = G = 2, Δ = 1, 2, 4 can also make the 16 consecutive RS symbols in the multiplexer output data stream come from 16 different RS codewords.

[0402] This embodiment adopts Figure 13 Another possible implementation of the multiplexing process shown is G=2, K=4, m=8, generating 8 second data streams, which contain 8 4:1 multiplexers. Two first data streams are randomly selected from each of the first data stream subsets 0 and 1 as inputs to the 4:1 multiplexers. A specific implementation of the corresponding 4:1 multiplexer is shown in 17(b). The multiplexed input data streams 0, 1, 2, and 3 of the 4:1 multiplexer i (0≤i≤7) correspond to the first data streams i, i+16, i+8, and i+24, respectively. That is, any two consecutive multiplexed input data streams of the multiplexer come from different subsets of the first data symbols. (See figure...) This represents Δ = 8 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 3) of the 4:1 multiplexer, which come from 8 different external RS codewords. The 4:1 multiplexer outputs data from the 4 input data streams in a polling manner, in units of 8 RS symbols, to the output data stream, i.e., the output data order is... The output data stream contains 16 consecutive RS symbols derived from 16 different RS codewords.

[0403] This embodiment adopts Figure 13Another possible implementation of the multiplexing process shown is G=2, K=8, m=4, producing 4 second data streams, which contain 4 8:1 multiplexers. Four first data streams are randomly selected from each of the first data stream subsets 0 and 1 as inputs to the 8:1 multiplexers. A specific implementation of the corresponding 8:1 multiplexer is shown in Figure 17(c). The multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0≤i≤3) correspond to first data stream i, first data stream i+16, first data stream i+4, first data stream i+20, first data stream i+8, first data stream i+24, first data stream i+12, and first data stream i+28, respectively. (Figure...) This represents Δ = 8 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 7) of the 8:1 multiplexer, which come from 8 different external RS codewords. The 8:1 multiplexer outputs data from the 8 input data streams in a polling manner, in units of 8 RS symbols, to the output data stream, i.e., the output data order is... The output data stream contains 16 consecutive RS symbols derived from 16 different RS codewords.

[0404] The aforementioned 16, 8, or 4 second data streams are each encoded using internal code, with the internal code information bit length being 160 bits. Specifically, the internal code encoder adds redundancy to each of the 16 consecutive RS symbols (totaling 160 bits) in the second data stream to obtain an internal codeword data stream. In one possible implementation, Hamming(170, 160) is used for internal code encoding, adding 10 bits of redundancy to each of the 16 consecutive RS symbols (totaling 160 bits) in each second data stream to obtain a 170-bit codeword. In another possible implementation, BCH(176, 160) is used for internal code encoding, adding 16 bits of redundancy to each of the 16 consecutive RS symbols (totaling 160 bits) in each second data stream to obtain a 176-bit codeword. After internal code encoding, the data stream is processed and then transmitted through the channel transmission medium.

[0405] Using the data interleaving coding scheme of this embodiment, when the inner code is Hamming(170,160), the pre-correction BER corresponding to the KP4RS(544,514)+Hamming(170,160) concatenated code under AWGN is approximately 4.3E-3 in order to achieve a post-correction bit error rate (BER) of 1E-15, which is close to the optimal performance of this concatenated FEC scheme. When the inner code is BCH(176,160), the pre-correction BER corresponding to the KP4 RS(544,514)+BCH(176,160) concatenated code under AWGN is approximately 8.3E-3 in order to achieve a post-correction bit error rate (BER) of 1E-15, which is close to the optimal performance of this concatenated FEC scheme.

[0406] Example 4: Applied to a 1×800G interface scenario, the internal code encoding information bit length is 160 bits, using 2:1, 4:1, 8:1 multiplexers, and channel symbol alignment.

[0407] The main difference between Example 4 and Example 3 is that Example 4 is based on the alignment of 2 RS symbols to obtain an aligned 32-channel data stream.

[0408] Specifically, based on the data processing diagram of the originating processing module shown in Figure 3(a), the originating processing module uses the known alignment marker of the PCS channel to perform alignment lock on the channel data stream. The originating processing module then aligns the 32 channel data streams using two RS symbols to obtain 32 aligned channel data streams. Then, according to the alignment marker, the data of the 32 channels is reordered so that the data of the 32 channels can be arranged in a specified order. One arrangement order is the same as in Figure 3(a), where the channel data streams are sorted from top to bottom from 0 to 31. Another arrangement order is such that the first 16 channel data streams in the 32 channels output by "channel reordering" contain PCS channel data streams 0-15, and the last 16 channels contain PCS channel data streams 16-31. It should be understood that the specific order of the first 16 channel data streams and the last 16 channel data streams are not limited in this case. That is, channel data stream i in Figure 3(a) does not necessarily correspond to PCS channel data stream i.

[0409] The 32 channel data streams, after channel reordering, are fed into a processor incorporating convolutional interleaving and multiplexing for interleaving and scrambling. After this process, the data is fed into an internal code encoder for encoding. The encoded data streams are then processed and transmitted through the channel transmission medium. It should be understood that the convolutional interleaving and multiplexing, as well as the internal code encoding scheme used in this embodiment, are all based on the scheme in Embodiment 3.

[0410] The data interleaving coding scheme of Embodiment 4 uses a KP4 RS(544,514)+Hamming(160,120) concatenated code. Under AWGN, to achieve a post-correction bit error rate (BER) of 1E-15, the pre-correction BER is approximately 4.5E-3, which is comparable in performance to the scheme of Embodiment 3, and has a lower overall latency. However, compared with the scheme of Embodiment 3, the scheme of Embodiment 4 is less effective against burst errors in the system. This scheme is suitable for some scenarios requiring lower latency.

[0411] Using the data interleaving coding scheme of Embodiment 4, when the inner code uses Hamming(170,160), its KP4RS(544,514)+Hamming(170,160) concatenated code under AWGN achieves a post-correction bit error rate (BER) of 1E-15 with a pre-correction BER of approximately 4.3E-3, approaching the optimal performance of this concatenated FEC scheme. When the inner code uses BCH(176,160), its KP4 RS(544,514)+BCH(176,160) concatenated code under AWGN achieves a post-correction BER of 1E-15 with a pre-correction BER of approximately 8.3E-3, approaching the optimal performance of this concatenated FEC scheme. It should be understood that, using the same inner code scheme as Embodiment 3, the performance of the scheme in Embodiment 4 is the same as that in Embodiment 3, but it is less effective against sudden system errors. This scheme is suitable for scenarios requiring lower latency.

[0412] Example 5: Applied to a 2×400G interface scenario, the internal code encoding information bit length is 120 or 160 bits, using 2:1, 4:1, or 8:1 multiplexers, and channel correction processing is adopted.

[0413] Unlike embodiments 1-4, this embodiment considers the client-side interface to be 2×400G with each channel at 100Gb / s. For interface details, please refer to "IEEE Std 802.3ckTM / D3.0".

[0414] Specifically, based on the data processing diagram of the originating processing module shown in Figure 3(a), the originating processing module uses the known alignment markers of PCS channels 0-15 or PCS channels 16-31 to perform alignment lock on the 16 channel data streams. The originating processing module then performs lane de-skew on the 32 channel data streams to obtain 32 aligned channel data streams. Then, according to the alignment markers of PCS channels 0-15 or PCS channels 16-31, it performs lane reordering on the data of the 16 channels, so that the data of the 16 channels can be arranged in a specified order. Finally, the data of the 32 channels is arranged in a specified order. One possible order is... Figure 6 The data streams from the same channel are sorted from top to bottom in numbers from 0 to 31.

[0415] The 32 channel data streams, after channel reordering, are fed into a processor that incorporates convolutional interleaving and multiplexing for interleaving and shuffling. The data is then fed into an internal code encoder for encoding. After internal code encoding and further processing, the data streams are transmitted through the channel transmission medium.

[0416] In one possible implementation, when the processor used in this embodiment 5 includes convolutional interleaving and multiplexing, and the internal code encoding is the same as the scheme in embodiment 1, the performance and latency of the cascaded FEC scheme are the same as those in embodiment 1.

[0417] In another possible implementation, when the processor used in this embodiment 5 includes convolutional interleaving and multiplexing, and the internal code encoding is the same as the scheme in embodiment 3, the performance and latency of the cascaded FEC scheme are the same as those in embodiment 3.

[0418] Example 6: Applied to a 2×400G interface scenario, the internal code encoding information bit length is 120 or 160 bits, using 2:1, 4:1, or 8:1 multiplexers, channel symbol alignment is used, and channel reordering is not performed.

[0419] Based on the scheme in Example 5, Example 6 presents a lower latency implementation scheme.

[0420] Specifically, based on the data processing diagram of the sending-end processing module shown in Figure 3(b), the sending-end processing module uses the known alignment markers of PCS channels 0-15 or PCS channels 16-31 to perform alignment lock on the 16 channel data streams. The sending-end processing module then aligns the 32 channel data streams using two RS symbols, resulting in 32 aligned channel data streams. These 32 aligned channel data streams are then directly fed into a processor designed with convolutional interleaving and multiplexing capabilities for interleaving and shuffling of the data order before being fed into an internal code encoder for internal code encoding. After internal code encoding, the data streams undergo further data processing and are then transmitted through the channel transmission medium.

[0421] In one possible implementation, when the processor used in this embodiment 6 includes convolutional interleaving and multiplexing, and the internal code encoding is the same as the scheme in embodiment 2, the performance and latency of the cascaded FEC scheme are the same as those in embodiment 2.

[0422] In another possible implementation, when the processor used in this embodiment 6 includes convolutional interleaving and multiplexing, and the internal code encoding is the same as the scheme in embodiment 4, the performance and latency of the cascaded FEC scheme are the same as those in embodiment 4.

[0423] Example 7: Applied to a 4×200G interface scenario, the internal code encoding information bit length is 120 or 160 bits, using a 4:1 or 8:1 multiplexer, and channel correction processing is adopted.

[0424] This embodiment considers the client-side interface as 4×200G with 100Gb / s per channel. For interface details, please refer to "IEEEStd802.3ckTM / D3.0".

[0425] Based on the data processing diagram of the originating processing module shown in Figure 3(a), the originating processing module uses the known alignment markers of PCS channels 0-7, 8-15, 16-23, or 24-31 to perform alignment lock on the eight channel data streams. Here, PCS channels 0-7, 8-15, 16-23, or 24-31 can be considered as PCS channels 0-7 in the 0th, 1st, 2nd, or 3rd 200G channels, respectively. The originating processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, based on the alignment markers of PCS channels 0-7, 8-15, 16-23, or 24-31, it performs lane reordering processing on the eight channels, so that the data of the eight channels can be arranged in a specified order. This allows the data from the 32 channels to be arranged in a specified order. One possible order is... Figure 7 The data streams from the same channel are sorted from top to bottom in numbers from 0 to 31.

[0426] The 32 channel data streams, after channel reordering, are fed into a processor that incorporates convolutional interleaving and multiplexing for interleaving and shuffling. The data is then fed into an internal code encoder for encoding. After internal code encoding and further processing, the data streams are transmitted through the channel transmission medium.

[0427] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleavers 0, convolutional interleavers 1, convolutional interleavers 2, ..., convolutional interleavers 31 use the same interleaving structure.

[0428] Figure 19(a) is a schematic diagram of the seventh structure of the convolutional interleaver in this application embodiment. As shown in Figure 19(a), it includes p = 2 delay lines. These two delay lines include Q storage units and 0 storage units respectively, and each storage unit is used to store d = 2 symbols. That is, the delay value of delay line 0 is 2Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

[0429] As shown in Figure 19(a), C r(·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (4t), C r (4t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream, and C r (4t-4Q), C r (4t-4Q+1) represents the two RS symbols output from delay line 0; C r (4t+2), C r (4t+3) represents the next two RS symbols input to delay line 1 in the channel data stream, and C r (4t+2), C r (4t+3) represents the two RS symbols output from delay line 1; C r (4t+4), C r (4t+5) represents the next two RS symbols input to delay line 0 in the channel data stream, and C r (4t-4Q+4), C r (4t-4Q+5) represents the two RS symbols output from delay line 0, and so on. Combined with... Figure 7 It can be seen that when 4Q+2≥136, i.e., Q≥34, the four consecutive RS symbols output by the convolutional interleaving are C r (4t-4Q), C r (4t-4Q+1), C r (4t+2), C r (4t+3) comes from 4 different RS codewords.

[0430] Figure 19(b) is a schematic diagram of the eighth structure of the convolutional interleaver in an embodiment of this application. As shown in Figure 19(b), in one possible implementation, Q = 34 is selected, and the specific structure of the convolutional interleaver is shown in Figure 19(b). Its corresponding interleaving delay is approximately 34 * 2 * 2 / 2 = 68 RS symbols. Using the convolutional interleaver shown in Figure 19(b), 32 PCS channel data streams are convolutionally interleaved to obtain 32 first data streams. (Reference) Figure 7 As shown in the PCS channel data streams, it is easy to understand that any RS symbol in the first data stream 0-7, any RS symbol in the first data stream 8-15, any RS symbol in the first data stream 16-23, and any RS symbol in the first data stream 24-31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 4 subsets of the first data streams: first data streams 0-7 are subset 0, first data streams 8-15 are subset 1, first data streams 16-23 are subset 2, and first data streams 24-31 are subset 3.

[0431] This embodiment uses, as follows: Figure 13 One possible implementation of the multiplexing process is G=4, K=4, m=8, which contains eight 4:1 multiplexers. Each multiplexer multiplexes four first data streams to obtain one second data stream, generating a total of eight second data streams. One first data stream is randomly selected from each of the first data stream subsets 0, 1, 2, and 3 as the input to the 4:1 multiplexer.

[0432] A specific implementation of the corresponding 4:1 multiplexer is shown in Figure 17(b). The multiplexed input data streams 0, 1, 2, and 3 of the 4:1 multiplexer i (0≤i≤7) correspond to the first data stream i, first data stream i+16, first data stream i+8, and first data stream i+24, respectively. It should be noted that the multiplexed input data streams 0, 1, 2, and 3 of the 4:1 multiplexer i (0≤i≤7) can also correspond to the first data stream i, first data stream i+8, first data stream i+16, and first data stream i+24, respectively. In this embodiment, as shown in Figure 17(b)... This represents Δ = 4 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 3) of the 4:1 multiplexer, which come from 4 different external RS codewords. The 4:1 multiplexer outputs data from the 4 input data streams to the output data stream in a polling manner, in units of 4 RS symbols, i.e., the output data is sequential. The output data stream contains 16 consecutive RS symbols from 16 different RS codewords. It should be noted that since K = G = 4, taking one first data stream from each of the first data stream subsets 0 to 3 can correspond to the multiplexed input data streams 0 to 3 of the 4:1 multiplexer i (0 ≤ i ≤ 7) in any order; Δ = 1, 2 can still ensure that the second data stream contains 16 consecutive RS symbols from 16 different RS codewords.

[0433] This embodiment uses, as follows: Figure 13 Another possible implementation of the multiplexing process is G=4, K=8, m=4, which contains four 8:1 multiplexers. Each multiplexer multiplexes eight first data streams to obtain one second data stream, generating a total of four second data streams. Two first data streams are randomly selected from each of the first data stream subsets 0, 1, 2, and 3 as inputs to the 8:1 multiplexer.

[0434] One specific implementation of the corresponding 8:1 multiplexer is shown in Figure 17(c). The multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0≤i≤3) correspond to the first data stream i, the first data stream i+16, the first data stream i+8, the first data stream i+24, the first data stream i+4, the first data stream i+20, the first data stream i+12, and the first data stream i+28, respectively. This ensures that any consecutive Q = 4 multiplexed input data streams of the multiplexer come from different subsets of the first data stream. It should be noted that the multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0≤i≤3) can also correspond to the first data stream i, the first data stream i+8, the first data stream i+16, the first data stream i+24, the first data stream i+4, the first data stream i+12, the first data stream i+20, and the first data stream i+28, respectively. (Figure...) This represents Δ = 4 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 7) of the 8:1 multiplexer, which come from 4 different external RS codewords. The 8:1 multiplexer outputs data from the 8 input data streams in a polling manner, in units of 4 RS symbols, to the output data stream, i.e., the output data order is... The output data stream contains 16 consecutive RS symbols derived from 16 different RS codewords.

[0435] The aforementioned 8 or 4 second data streams are respectively encoded using internal codes. The internal code encoding scheme can adopt the encoding scheme given in Example 1 to obtain performance comparable to that of Example 1; or it can adopt the encoding scheme given in Example 3 to obtain performance comparable to that of Example 3, which will not be elaborated here.

[0436] Example 8: Applied to a 4×200G interface scenario, the internal code encoding information bit length is 120 bits, a 2:1 multiplexer is used, and channel correction processing is employed.

[0437] Based on Example 7, this example considers using a 2:1 multiplexer and correspondingly adopts a newly designed convolutional interleaver.

[0438] Specifically, based on the data processing diagram of the originating processing module shown in Figure 3(a), the originating processing module uses the known alignment markers of PCS channels 0-7, 8-15, 16-23, or 24-31 to perform alignment lock on the eight channel data streams. Here, PCS channels 0-7, 8-15, 16-23, or 24-31 can be considered as PCS channels 0-7 in the 0th, 1st, 2nd, or 3rd 200G channels, respectively. The originating processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, based on the alignment markers of PCS channels 0-7, 8-15, 16-23, or 24-31, it performs lane reordering processing on the eight channel data streams so that the data of the eight channels can be arranged in a specified order. This allows the data from the 32 channels to be arranged in a specified order. One possible order is... Figure 7 The data streams from the same channel are sorted from top to bottom in numbers from 0 to 31.

[0439] The 32 channel data streams, after channel reordering, are fed into a processor that incorporates convolutional interleaving and multiplexing for interleaving and shuffling. The data is then fed into an internal code encoder for encoding. After internal code encoding and further processing, the data streams are transmitted through the channel transmission medium.

[0440] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleavers 0, 1, 2, ..., 31 use the same interleaving structure. Figure 16(a) shows a convolutional interleaver structure containing p=3 delay lines. These three delay lines include 2Q, Q, and 0 storage units, respectively, with each storage unit storing d=2 symbols. That is, delay line 0 has a delay of 4Q symbols, delay line 1 has a delay of 2Q symbols, and delay line 2 has a delay of 0 symbols (no delay).

[0441] As shown in Figure 16(a), C r (·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (6t), C r (6t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream, and C r (6t-12Q), Cr (6t-12Q+1) represents the two RS symbols output from delay line 0; C r (6t+2), C r (6t+3) represents the next two RS symbols input to delay line 1 in the channel data stream, and C r (6t-6Q+2), C r (6t-6Q+3) represents the two RS symbols output from delay line 1; C r (6t+4), C r (6t+5) represents the next two RS symbols input to delay line 2 in the channel data stream, and C r (6t+4), C r (6t+5) represents the two RS symbols output from delay line 2; C r (6t+6), C r (6t+7) represents the two RS symbols subsequently input to delay line 0 in the channel data stream, and C r (6t-12Q+6), C r (6t-12Q+7) represents the two RS symbols output from delay line 0, and so on. Combined with... Figure 7 It can be seen that when 6Q+2≥136, i.e., Q≥23, the C of the convolutional interleaving output... r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), C r (6t+5) A total of 6 RS symbols come from 6 different RS codewords.

[0442] Figure 20 This is a schematic diagram of the ninth structure of the convolutional interleaver in the embodiments of this application. For example... Figure 20 As shown, in one possible implementation, Q=23 is selected, and the specific structure of the convolutional interleaver is as follows: Figure 20 As shown. Its corresponding interleaving delay is approximately 46 * 2 * 3 / 2 = 138 RS symbols. Using... Figure 20 The convolutional interleaver shown performs convolutional interleaving on the 32 PCS channel data streams to obtain 32 first data streams. (Reference) Figure 7As can be easily understood from the PCS channel data stream shown, any RS symbol in the first data streams 0-7, any RS symbol in the first data streams 8-15, any RS symbol in the first data streams 16-23, and any RS symbol in the first data streams 24-31 all come from different RS codewords. Therefore, the 32 first data streams comprise G=4 first data stream subsets, where the first data streams 0-7 are the first data stream subset 0, the first data streams 8-15 are the first data stream subset 1, the first data streams 16-23 are the first data stream subset 2, and the first data streams 24-31 are the first data stream subset 3.

[0443] This embodiment adopts as Figure 13 a possible implementation of the multiplexing processing shown is G=4, K=2, m=16, which comprises sixteen 2:1 multiplexers, each multiplexer multiplexes two first data streams to obtain one second data stream, and a total of sixteen second data streams are generated. One first data stream is arbitrarily taken from any two of the first data stream subset 0, the first data stream subset 1, the first data stream subset 2 and the first data stream subset 3 respectively as the input of the 2:1 multiplexer. A specific implementation of the corresponding 2:1 multiplexer is shown in Figure 17(a), where the multiplexing input data stream 0 and input data stream 1 of the 2:1 multiplexer i (0≤i≤15) correspond to the first data stream i and the first data stream i+16 respectively. In the figure represents six consecutive RS symbols with Δ=6 in the multiplexing input data stream j (0≤j≤1) of the 2:1 multiplexer, which come from six different outer code RS codewords. The 2:1 multiplexer outputs the data in the two input data streams to the output data stream in a polling manner with six RS symbols as a unit, that is, the output data sequence is twelve consecutive RS symbols in the output data stream come from twelve different RS codes. It should be noted that since K<G, Δ=1, 2, 3 can still enable twelve consecutive RS symbols in the second data stream to come from twelve different RS codes.

[0444] The foregoing sixteen second data streams are respectively subjected to inner code encoding, and the inner code encoding scheme thereof may adopt the encoding scheme given in Embodiment 1, so as to obtain performance equivalent to that of Embodiment 1, which will not be repeated herein.

[0445] Embodiment 9: In a scenario applied to a 4×200G interface, the length of the inner code encoding information bit is 160 bits, a 2:1 multiplexer is adopted, and channel deviation correction processing is performed.

[0446] Based on Embodiment 8, this embodiment considers an inner code with a code length of 160 bits, and correspondingly adopts a newly designed convolutional interleaver.

[0447] Specifically, this embodiment uses the convolutional interleaver structure shown in Figure 18(a), which includes p = 4 delay lines. These 4 delay lines respectively include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, with each storage unit used to store d = 2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

[0448] As shown in Figure 18(a), C r (·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (8t), C r (8t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream, and C r (8t-24Q), C r (8t-24Q+1) represents the two RS symbols output from delay line 0; C r (8t+2), C r (8t+3) represents the next two RS symbols input to delay line 1 in the channel data stream, and C r (8t-16Q+2), C r (8t-16Q+3) represents the two RS symbols output from delay line 1; C r (8t+4), C r (8t+5) represents the next two RS symbols input to delay line 2 in the channel data stream, and C r (8t-8Q+4), C r (8t-8Q+5) represents the two RS symbols output from delay line 2; C r (8t+6), C r (8t+7) represents the two RS symbols subsequently input to delay line 3 in the channel data stream, and C r (8t+6), C r (8t+7) represents the two RS symbols output from delay line 3, C r (8t+8), C r (8t+9) represents the two RS symbols subsequently input to delay line 0 in the channel data stream, and C r (8t-24Q+8), C r (8t-24Q+9) represents the two RS symbols output from delay line 0, and so on. Combined with... Figure 7 It can be seen that when 8Q+2≥136, i.e., Q≥17, the C of the convolutional interleaving output... r (8t-24Q), C r (8t-24Q+1), Cr (8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), C r (8t+7) A total of 8 RS symbols come from 8 different RS codewords.

[0449] Figure 21 This is a schematic diagram of the tenth structure of the convolutional interleaver in the embodiments of this application. For example... Figure 21 As shown, in one possible implementation, Q=17 is selected, and the specific structure of the convolutional interleaver is as follows: Figure 21 As shown, the corresponding interleaving delay is approximately 51*2*4 / 2 = 204 RS symbols.

[0450] Adopting such Figure 21 The convolutional interleaver shown performs convolutional interleaving on the 32 PCS channel data streams to obtain 32 first data streams. (Reference) Figure 7 As shown in the PCS channel data streams, it is easy to understand that any RS symbol in the first data stream 0-7, any RS symbol in the first data stream 8-15, any RS symbol in the first data stream 16-23, and any RS symbol in the first data stream 24-31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 4 subsets of the first data streams: first data streams 0-7 are subset 0, first data streams 8-15 are subset 1, first data streams 16-23 are subset 2, and first data streams 24-31 are subset 3.

[0451] This embodiment uses, as follows: Figure 13 One possible implementation of the multiplexing process is G=4, K=2, m=16, which contains 16 2:1 multiplexers. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. One first data stream is randomly selected from any two subsets of the first data streams (0, 1, 2, and 3) as the input to the 2:1 multiplexer. A specific implementation of the corresponding 2:1 multiplexer is shown in Figure 17(a). The multiplexed input data streams 0 and 1 of the 2:1 multiplexer i (0≤i≤15) correspond to the first data stream i and first data stream i+16, respectively. (Figure...) representing consecutive Δ=8 RS symbols in the multiplexed input data stream j (0≤j≤1) of the 2:1 multiplexer, which come from 8 different outer code RS codewords. The 2:1 multiplexer outputs the data in the two input data streams to the output data stream in a polling manner with 8 RS symbols as a unit, that is, the output data order is 16 consecutive RS symbols in the output data stream come from 16 different RS codewords. It should be noted that since K<G, when Δ=1, 2 or 4, 16 consecutive RS symbols in the second data stream can still come from 16 different RS codewords.

[0452] The 16 second data streams mentioned above are respectively subjected to inner code encoding, and the inner code encoding scheme can adopt the encoding scheme given in Example 3, obtaining performance equivalent to that of Example 3, which will not be repeated herein.

[0453] Example 10: Applied to the scenario of a 4×200G interface, the length of the inner code encoding information bit is 160 bits, and channel symbol alignment is adopted.

[0454] Based on any one of Examples 7 to 9, this example provides an implementation solution with lower latency.

[0455] Based on the schematic diagram of data processing of the transmitting-end processing module shown in Figure 3(d), the transmitting-end processing module performs identification lock on 8-channel data streams by using the known Alignment markers of PCS channels 0-7, PCS channels 8-15, PCS channels 16-23 or PCS channels 24-31. Here, PCS channels 0-7, PCS channels 8-15, PCS channels 16-23 or PCS channels 24-31 can be respectively regarded as PCS channels 0-7 in the 0th, 1st, 2nd or 3rd 200G channel. Then the transmitting-end processing module performs alignment based on 2 RS symbols for 32 channel data streams to obtain 32 aligned channel data streams. Then the 32 aligned channel data streams are directly sent to the designed processor including multiplexing for processing, and then sent to the inner code encoder for inner code encoding. The inner-code-encoded data stream is processed and then sent to a channel transmission medium for transmission.

[0456] In a possible implementation manner, when both the multiplexing processing and the inner code encoding scheme of this example adopt the scheme of Example 7, the performance of the concatenated code under AWGN is equivalent to that of the scheme of Example 7, and has lower overall latency. However, compared with the scheme of Example 7, the scheme of this example has poorer resistance to system burst errors. This solution is suitable for some scenarios requiring lower latency.

[0457] In another possible implementation, when both the multiplexing processing and the internal code encoding scheme of this embodiment adopt the scheme of embodiment 8, its concatenated code performs comparably to the scheme of embodiment 8 under AWGN, and has a lower overall latency. However, compared with embodiment 8, the scheme of this embodiment is less effective against system burst errors. This scheme is suitable for some scenarios requiring lower latency.

[0458] In another possible implementation, when both the multiplexing processing and the internal code encoding scheme of this embodiment adopt the scheme of Embodiment 9, its concatenated code performs comparably to the scheme of Embodiment 9 under AWGN, and has a lower overall latency. However, compared with Embodiment 9, the scheme of this embodiment is less effective against system burst errors. This scheme is suitable for some scenarios requiring lower latency.

[0459] Example 11: Applied to an 8×100G interface scenario, the internal code encoding information bit length is 120 bits or 160 bits, using an 8:1 multiplexer and channel correction processing.

[0460] This embodiment considers the client-side interface to be 8×100G per channel at 100Gb / s and to be in “100G RS-FEC-Int” mode. For interface details, please refer to “IEEE Std 802.3ckTM / D3.0”.

[0461] Based on the data processing diagram of the sending-end processing module shown in Figure 3(c), the sending-end processing module uses the known alignment markers of FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 to perform alignment lock on the four channel data streams. Here, FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 can be considered as FEC channels 0-3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channels, respectively. The originating processing module then performs lane de-skew on the 32 channel data streams to obtain aligned 32 channel data streams. Next, based on the alignment markers of FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31, it performs lane reordering on the data of four channels, arranging the data in a specified order. Finally, the data of all 32 channels is arranged in a specified order. One possible order is... Figure 11 The channel data streams are sorted from 0 to 31 from top to bottom. The 32 channel data streams after channel reordering are not convolutionally interleaved, but directly multiplexed to obtain a total of 16 second data streams, which are then fed into the internal code encoder for internal code encoding. After internal code encoding, the data streams undergo data processing and are then transmitted through the channel transmission medium.

[0462] refer to Figure 8As shown in the PCS channel data stream, it is not difficult to understand that any RS symbol in channel data streams 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 all come from different RS codewords. Since the channel data streams do not undergo convolutional interleaving, channel data streams 0-31 are equivalent to the first data stream 0-31. Therefore, the 32 first data streams contain G = 8 subsets of first data streams: first data streams 0-3 are subset 0, first data streams 4-7 are subset 1, first data streams 8-11 are subset 2, first data streams 12-15 are subset 3, first data streams 16-19 are subset 4, first data streams 20-23 are subset 5, first data streams 24-27 are subset 6, and first data streams 28-31 are subset 7.

[0463] This embodiment uses, as follows: Figure 13 One possible implementation of the multiplexing process is G=8, K=8, m=4, which multiplexes 32 channel data streams to obtain 4 second data streams. Among them, a certain one from the first data stream subset 0, a certain one from the first data stream subset 1, a certain one from the first data stream subset 2, a certain one from the first data stream subset 3, a certain one from the first data stream subset 4, a certain one from the first data stream subset 5, a certain one from the first data stream subset 6, and a certain one from the first data stream subset 7, a total of 8 channel data streams, serve as the 8 input data streams of the 8:1 multiplexer i (0≤i≤3). One specific implementation is shown in Figure 17(c). Multiplexer i (0≤i≤3) maps the first data streams i, i+16, i+8, i+24, i+4, i+20, i+12, and i+28 to the multiplexed input data streams 0 to 7 of the 8:1 multiplexer, respectively. (Figure...) This represents a consecutive Δ = 2 RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 7) of an 8:1 multiplexer, originating from two different external RS codewords. The 8:1 multiplexer outputs data from the 8 input data streams in a polling manner, in units of 2 RS symbols, to the output data stream; that is, the output data order is... The output data stream contains 16 consecutive RS symbols derived from 16 different RS codewords. It should be noted that since K≤G, Δ=1 can still ensure that the second data stream contains 16 consecutive RS symbols derived from 16 different RS codes.

[0464] Figure 22 This is a schematic diagram of the fifth structure of the multiplexer in the embodiments of this application. For example... Figure 22 As shown, multiplexer i (0≤i≤3) assigns the first data stream i, first data stream i+4, first data stream i+8, first data stream i+12, first data stream i+16, first data stream i+20, first data stream i+24, and first data stream i+28 to the multiplexed input data streams 0 to 7 of the 8:1 multiplexer, respectively. (See figure) This represents a consecutive Δ = 2 RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 7) of an 8:1 multiplexer, originating from two different external RS codewords. The 8:1 multiplexer outputs data from the 8 input data streams in a polling manner, in units of 2 RS symbols, to the output data stream; that is, the output data order is... The output data stream contains 16 consecutive RS symbols derived from 16 different RS codewords. It should be noted that since K≤G, Δ=1 can still ensure that the second data stream contains 16 consecutive RS symbols derived from 16 different RS codes.

[0465] The above four second data streams are respectively encoded with internal codes. The internal code encoding scheme can adopt the encoding scheme given in Example 1 to obtain performance comparable to Example 1; or it can adopt the encoding scheme given in Example 3 to obtain performance comparable to Example 3. It will not be elaborated here.

[0466] Example 12: Applied to an 8×100G interface scenario, the internal code encoding information bit length is 120 bits or 160 bits, a 4:1 multiplexer is used, and channel correction processing is employed.

[0467] Based on the scheme in Example 11, this example provides a second-lowest latency implementation scheme when the multiplexing process uses a 4:1 multiplexer.

[0468] Based on the data processing diagram of the sending-end processing module shown in Figure 3(a), the sending-end processing module uses the known alignment markers of FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 to perform alignment lock on the four channel data streams. Here, FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 can be considered as FEC channels 0-3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channels, respectively. The originating processing module then performs lane de-skew on the 32 channel data streams to obtain aligned 32 channel data streams. Next, based on the alignment markers of FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31, it performs lane reordering on the data of four channels, arranging the data in a specified order. Finally, the data of all 32 channels is arranged in a specified order. One possible order is... Figure 11 The data streams from the same channel are sorted from top to bottom in numbers from 0 to 31.

[0469] The 32 channel data streams, after channel reordering, are fed into a processor that incorporates convolutional interleaving and multiplexing for interleaving and shuffling. The data is then fed into an internal code encoder for encoding. After internal code encoding and further processing, the data streams are transmitted through the channel transmission medium.

[0470] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleavers 0, 1, 2, ..., 31 use the same interleaving structure. Figure 19(a) shows a convolutional interleaver structure containing p=2 delay lines. These two delay lines each include Q and 0 storage units, respectively, with each unit storing d=2 symbols. That is, delay line 0 has a delay of 2Q symbols, and delay line 1 has a delay of 0 symbols, i.e., no delay.

[0471] As shown in Figure 19(a), C r(·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (4t), C r (4t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream, and C r (4t-4Q), C r (4t-4Q+1) represents the two RS symbols output from delay line 0; C r (4t+2), C r (4t+3) represents the next two RS symbols input to delay line 1 in the channel data stream, and C r (4t+2), C r (4t+3) represents the two RS symbols output from delay line 1; C r (4t+4), C r (4t+5) represents the next two RS symbols input to delay line 0 in the channel data stream, and C r (4t-4Q+4), C r (4t-4Q+5) represents the two RS symbols output from delay line 0, and so on. Combined with... Figure 8 It can be seen that when 4Q+2≥272, i.e., Q≥68, the four consecutive RS symbols output by the convolutional interleaving are C r (4t-4Q), C r (4t-4Q+1), C r (4t+2), C r (4t+3) comes from 4 different RS codewords.

[0472] Figure 23 This is a schematic diagram of the eleventh structure of the convolutional interleaver in this application. Figure 23 As shown, in one possible implementation, Q=68 is selected, and the specific structure of the convolutional interleaver is as follows: Figure 23 As shown, the corresponding interleaving delay is approximately 68*2*2 / 2 = 136 RS symbols.

[0473] Adopting such Figure 23 The convolutional interleaver shown performs convolutional interleaving on the 32 PCS channel data streams to obtain 32 first data streams. (Reference) Figure 8As shown in the PCS channel data stream, it is easy to understand that any RS symbol in channel data streams 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 8 subsets of first data streams: first data streams 0-3 are subset 0, first data streams 4-7 are subset 1, first data streams 8-11 are subset 2, first data streams 12-15 are subset 3, first data streams 16-19 are subset 4, first data streams 20-23 are subset 5, first data streams 24-27 are subset 6, and first data streams 28-31 are subset 7.

[0474] This embodiment uses, as follows: Figure 13 One possible implementation of the multiplexing process is G=8, K=4, m=8, which contains eight 4:1 multiplexers. Each multiplexer multiplexes four first data streams to obtain one second data stream, generating a total of eight second data streams. One first data stream is randomly selected from any four subsets of the first data streams (0-7) as the input to the 4:1 multiplexer. A specific implementation is shown in Figure 17(b). The multiplexed input data streams 0 to 3 of the 4:1 multiplexer i (0≤i≤7) correspond to first data stream i, first data stream i+16, first data stream i+8, and first data stream i+24, respectively. (Figure...) The 4:1 multiplexer represents Δ = 4 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 3), which come from 4 different external RS codewords. The 4:1 multiplexer outputs data from the 4 input data streams in a polling manner, in units of 4 RS symbols, to the output data stream; that is, the output data order is... The output data stream contains 16 consecutive RS symbols derived from 16 different RS codewords. It should be noted that since K ≤ G, Δ = 1, 2 still allows the second data stream to contain 16 consecutive RS symbols derived from 16 different RS codes.

[0475] Figure 24 This is a schematic diagram of the sixth structure of the multiplexer in the embodiments of this application. For example... Figure 24 As shown, multiplexer i (0≤i≤3) converts the first data stream i, first data stream i+8, first data stream i+16, and first data stream i+24 into multiplexed input data streams 0 to 3 of the 4:1 multiplexer, respectively. (See figure.) The 4:1 multiplexer represents Δ = 4 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 3), which come from 4 different external RS codewords. The 4:1 multiplexer outputs data from the 4 input data streams in a polling manner, in units of 4 RS symbols, to the output data stream; that is, the output data order is... The output data stream contains 16 consecutive RS symbols derived from 16 different RS codewords. It should be noted that since K ≤ G, Δ = 1, 2 still allows the second data stream to contain 16 consecutive RS symbols derived from 16 different RS codes.

[0476] The above eight second data streams are respectively encoded with internal codes. The internal code encoding scheme can adopt the encoding scheme given in Example 1 to obtain performance comparable to Example 1; or it can adopt the encoding scheme given in Example 3 to obtain performance comparable to Example 3. This will not be elaborated here.

[0477] Example 13: Applied to an 8×100G interface scenario, the internal code encoding information bit length is 120 bits, a 2:1 multiplexer is used, and channel correction processing is employed.

[0478] Based on Example 12, this example considers using a 2:1 multiplexer for multiplexing processing and an internal code with an information length of 120 bits, and correspondingly adopts a newly designed convolutional interleaver and multiplexing processing.

[0479] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleavers 0, 1, 2, ..., 31 use the same interleaving structure. Figure 16(a) shows a convolutional interleaver structure containing p=3 delay lines. These three delay lines include 2Q, Q, and 0 storage units respectively, with each storage unit storing d=2 symbols. That is, delay line 0 has a delay of 4Q symbols, delay line 1 has a delay of 2Q symbols, and delay line 2 has a delay of 0 symbols (no delay).

[0480] As shown in Figure 16(a), C r (·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (6t), C r (6t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream, and C r (6t-12Q), C r (6t-12Q+1) represents the two RS symbols output from delay line 0; C r (6t+2), Cr (6t+3) represents the next two RS symbols input to delay line 1 in the channel data stream, and C r (6t-6Q+2), C r (6t-6Q+3) represents the two RS symbols output from delay line 1; C r (6t+4), C r (6t+5) represents the next two RS symbols input to delay line 2 in the channel data stream, and C r (6t+4), C r (6t+5) represents the two RS symbols output from delay line 2; C r (6t+6), C r (6t+7) represents the two RS symbols subsequently input to delay line 0 in the channel data stream, and C r (6t-12Q+6), C r (6t-12Q+7) represents the two RS symbols output from delay line 0, and so on. Combined with... Figure 8 It can be seen that when 6Q+2≥272, i.e., Q≥45, the C of the convolutional interleaving output... r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), C r (6t+5) A total of 6 RS symbols come from 6 different RS codewords.

[0481] Figure 25 This is a schematic diagram of the twelfth structure of the convolutional interleaver in the embodiments of this application. For example... Figure 25 As shown, in one possible implementation, Q=45 is selected, and the specific structure of the convolutional interleaver is as follows. Figure 25 As shown, the corresponding interleaving delay is approximately 90*2*3 / 2 = 270 RS symbols.

[0482] Adopting such Figure 25 The convolutional interleaver shown performs convolutional interleaving on the 32 PCS channel data streams to obtain 32 first data streams. (Reference) Figure 8As shown in the PCS channel data stream, it is not difficult to understand that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 8 subsets of first data streams: first data streams 0-3 are subset 0, first data streams 4-7 are subset 1, first data streams 8-11 are subset 2, first data streams 12-15 are subset 3, first data streams 16-19 are subset 4, first data streams 20-23 are subset 5, first data streams 24-27 are subset 6, and first data streams 28-31 are subset 7.

[0483] This embodiment uses, as follows: Figure 13 One possible implementation of the multiplexing process is G=8, K=2, m=16, which includes 16 2:1 multiplexers. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. One first data stream is randomly selected from any two subsets of the first data streams 0-7 as the input to the 2:1 multiplexer. A specific implementation of the 2:1 multiplexer is shown in Figure 17(a). The multiplexed input data stream 0 and multiplexed input data stream 1 of the 2:1 multiplexer i (0≤i≤15) correspond to first data stream i and first data stream i+16, respectively. (Figure...) This represents Δ = 6 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 1) of the 2:1 multiplexer, which come from 6 different external RS codewords. The 2:1 multiplexer outputs data from the two input data streams to the output data stream in a polling manner, in units of 6 RS symbols, i.e., the output data order is as follows: The output data stream contains 12 consecutive RS symbols derived from 12 different RS codewords. It should be noted that since K≤G, Δ=1,2,3 can still result in 12 consecutive RS symbols derived from 12 different RS codes in the second data stream.

[0484] The encoding scheme for the 16 second data streams output by the above multiplexing process can all adopt the scheme in Example 1, and the performance is comparable to that of Example 1, which will not be repeated here.

[0485] Example 14: Applied to an 8×100G interface scenario, the internal code encoding information bit length is 160 bits, a 2:1 multiplexer is used, and channel correction processing is employed.

[0486] Based on Example 12, this example considers using a 2:1 multiplexer for multiplexing processing and an internal code with an information length of 160 bits, and correspondingly adopts a newly designed convolutional interleaver and multiplexing processing.

[0487] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleaving 0, convolutional interleaving 1, convolutional interleaving 2, ..., convolutional interleaving 31 use the same interleaving structure. Figure 18(a) shows a convolutional interleaver structure containing p=4 delay lines. These four delay lines include 3Q, 2Q, Q, and 0 storage units respectively, with each storage unit storing d=2 symbols. That is, delay line 0 has a delay of 6Q symbols, delay line 1 has a delay of 4Q symbols, delay line 2 has a delay of 2Q symbols, and delay line 3 has a delay of 0 symbols (no delay).

[0488] As shown in Figure 18(a), C r (·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (8t), C r (8t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream, and C r (8t-24Q), C r (8t-24Q+1) represents the two RS symbols output from delay line 0; C r (8t+2), C r (8t+3) represents the next two RS symbols input to delay line 1 in the channel data stream, and C r (8t-16Q+2), C r (8t-16Q+3) represents the two RS symbols output from delay line 1; C r (8t+4), C r (8t+5) represents the next two RS symbols input to delay line 2 in the channel data stream, and C r (8t-8Q+4), C r (8t-8Q+5) represents the two RS symbols output from delay line 2; C r (8t+6), C r (8t+7) represents the two RS symbols subsequently input to delay line 3 in the channel data stream, and C r(8t+6), C r (8t+7) represents the two RS symbols output from delay line 3, C r (8t+8), C r (8t+9) represents the two RS symbols subsequently input to delay line 0 in the channel data stream, and C r (8t-24Q+8), C r (8t-24Q+9) represents the two RS symbols output from delay line 0, and so on. Combined with... Figure 8 It can be seen that when 8Q+2≥272, i.e., Q≥34, the C of the convolutional interleaving output... r (8t-24Q), C r (8t-24Q+1), C r (8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), C r (8t+7) A total of 8 RS symbols come from 8 different RS codewords.

[0489] Figure 26 This is a schematic diagram of the thirteenth structure of the convolutional interleaver in this application. Figure 26 As shown, in one possible implementation, Q=34 is selected, and the specific structure of the convolutional interleaver is as follows. Figure 26 As shown, its corresponding interleaving delay is approximately 102*2*4 / 2 = 408 RS symbols.

[0490] Adopting such Figure 26 The convolutional interleaver shown performs convolutional interleaving on the 32 PCS channel data streams to obtain 32 first data streams. (Reference) Figure 8As shown in the PCS channel data stream, it is not difficult to understand that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 8 subsets of first data streams: first data streams 0-3 are subset 0, first data streams 4-7 are subset 1, first data streams 8-11 are subset 2, first data streams 12-15 are subset 3, first data streams 16-19 are subset 4, first data streams 20-23 are subset 5, first data streams 24-27 are subset 6, and first data streams 28-31 are subset 7.

[0491] This embodiment uses, as follows: Figure 13 One possible implementation of the multiplexing process is G=8, K=2, m=16, which includes 16 2:1 multiplexers. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. One first data stream is randomly selected from any two subsets of the first data streams 0-7 as the input to the 2:1 multiplexer. A specific implementation of the 2:1 multiplexer is shown in Figure 17(a). The multiplexed input data stream 0 and multiplexed input data stream 1 of the 2:1 multiplexer i (0≤i≤15) correspond to first data stream i and first data stream i+16, respectively. (Figure...) This represents Δ = 8 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 1) of the 2:1 multiplexer, which come from 8 different external RS codewords. The 2:1 multiplexer outputs data from the two input data streams to the output data stream in a polling manner, in units of 8 RS symbols, i.e., the output data order is... The output data stream contains 16 consecutive RS symbols derived from 16 different RS codewords. It should be noted that since K≤G, Δ=1,2,4 can still result in 16 consecutive RS symbols derived from 16 different RS codes in the second data stream.

[0492] The internal code encoding scheme for the 16 second data streams output by the above multiplexing process can be the internal code encoding scheme in Example 3, which achieves performance comparable to Example 3, and will not be repeated here.

[0493] Example 15: Applied to the scenario of 8×100G interface, using channel symbol alignment.

[0494] Based on any of the embodiments in Examples 11-14, this embodiment provides a lower latency implementation scheme.

[0495] Based on the data processing diagram of the transmitting end processing module shown in Figure 3(b), the transmitting end processing module uses known alignment markers from FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 to perform alignment lock on the four channel data streams. The transmitting end processing module then aligns the 32 channel data streams using two RS symbols to obtain 32 aligned channel data streams. These 32 channel data streams are convolved and interleaved to obtain 32 first data streams. The first data streams are then multiplexed to obtain 4, 8, or 16 second data streams, which are then fed into an internal code encoder for internal code encoding. After internal code encoding, the data streams are processed and then transmitted through the channel transmission medium.

[0496] In this embodiment, when the processor employing convolutional interleaving and multiplexing, and the internal code encoding, are the same as in Embodiment 11, the performance of its concatenated code under AWGN is comparable, but slightly worse in resisting system burst errors. This scheme is suitable for some scenarios requiring lower latency.

[0497] In this embodiment, when the processor employing convolutional interleaving and multiplexing, and the internal code encoding are the same as in Embodiment 12, the performance of its concatenated code under AWGN is comparable, but slightly worse in resisting system burst errors. This scheme is suitable for some scenarios requiring lower latency.

[0498] In this embodiment, when the processor employing convolutional interleaving and multiplexing, and the internal code encoding, are the same as those in Embodiment 13, the performance of its concatenated code under AWGN is comparable, but slightly worse in resisting system burst errors. This scheme is suitable for some scenarios requiring lower latency.

[0499] In this embodiment, when the processor employing convolutional interleaving and multiplexing, and the internal code encoding are the same as in Embodiment 14, the performance of its concatenated code under AWGN is comparable, but slightly worse in resisting system burst errors. This scheme is suitable for some scenarios requiring lower latency.

[0500] Example 16: Applied to an 8×100G interface scenario, the internal code encoding information bit length is 120 bits or 160 bits, using an 8:1 multiplexer and channel correction processing.

[0501] This embodiment considers the client-side interface to be 8×100G per channel at 100Gb / s and to be in “100G RS-FEC” mode. For interface details, please refer to “IEEE Std 802.3ckTM / D3.0”.

[0502] Based on the data processing diagram of the sending-end processing module shown in Figure 3(a), the sending-end processing module uses the known alignment markers of FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 to perform alignment lock on the four channel data streams. Here, FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 can be considered as FEC channels 0-3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channels, respectively. The originating processing module then performs lane de-skew on the 32 channel data streams to obtain aligned 32 channel data streams. Next, based on the alignment markers of FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31, it performs lane reordering on the data of four channels, arranging the data in a specified order. Finally, the data of all 32 channels is arranged in a specified order. One possible order is... Figure 9 The data streams from the same channel are sorted from top to bottom in numbers from 0 to 31.

[0503] The 32 channel data streams, after channel reordering, are fed into a processor that incorporates convolutional interleaving and multiplexing for interleaving and shuffling. The data is then fed into an internal code encoder for encoding. After internal code encoding and further processing, the data streams are transmitted through the channel transmission medium.

[0504] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 FEC channel data streams to obtain n=32 first data streams. Among them, convolutional interleavers 0, convolutional interleavers 1, convolutional interleavers 2, ..., convolutional interleavers 31 use the same interleaving structure.

[0505] Figure 27(a) is a schematic diagram of the fourteenth structure of the convolutional interleaver in this application embodiment. As shown in Figure 27(a), it includes p = 2 delay lines. These two delay lines include Q storage units and 0 storage units respectively, and each storage unit is used to store d = 1 symbol. That is, the delay value of delay line 0 is Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

[0506] As shown in Figure 27(a), C r (·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (2t) represents one RS symbol currently input to delay line 0 in the channel data stream, and C r (2t-2Q) represents one RS symbol output from delay line 0; C r (2t+1) represents the next RS symbol input to delay line 1 in the channel data stream, and C r (2t+1) represents one RS symbol output from delay line 1; C r (2t+2) represents the next RS symbol input to delay line 0 in the channel data stream, and C r (2t-2Q+2) represents one RS symbol output from delay line 0, and so on. Combined with... Figure 9 It can be seen that when 2Q+1≥136, i.e., Q≥68, the two consecutive RS symbols C output by the convolutional interleaving are... r (2t-2Q), C r (2t+1) comes from two different RS codewords.

[0507] Figure 27(b) is a schematic diagram of the fifteenth structure of the convolutional interleaver in this application embodiment. As shown in Figure 27(b), in one possible implementation, Q = 68 is selected, and the specific structure of the convolutional interleaver is shown in Figure 27(b). The corresponding interleaving delay is approximately 68 * 2 / 2 = 68 RS symbols.

[0508] The convolutional interleaver shown in Figure 27(b) is used to perform convolutional interleaving on the 32 FEC channel data streams to obtain 32 first data streams. (Reference) Figure 9As shown in the FEC channel data stream, it is not difficult to understand that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 8 subsets of first data streams: first data streams 0-3 are subset 0, first data streams 4-7 are subset 1, first data streams 8-11 are subset 2, first data streams 12-15 are subset 3, first data streams 16-19 are subset 4, first data streams 20-23 are subset 5, first data streams 24-27 are subset 6, and first data streams 28-31 are subset 7.

[0509] This embodiment uses the 8:1 multiplexing processing structure in Embodiment 11 to obtain 4 second data streams, and the 16 consecutive RS symbols in each second data stream come from 16 different RS codewords.

[0510] The above four second data streams are encoded using internal codes. The encoding scheme can be the one given in Example 1, which yields performance comparable to that of Example 1; or the encoding scheme given in Example 3, which yields performance comparable to that of Example 3. This will not be elaborated further here.

[0511] Example 17: Applied to an 8×100G interface scenario, the internal code encoding information bit length is 120 bits, a 4:1 multiplexer is used, and channel correction processing is employed.

[0512] Based on the scheme of Example 16, this example provides a newly designed convolutional interleaver and multiplexing process when the internal code information length is 120 bits and a 4:1 multiplexer is used for multiplexing.

[0513] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleavers 0, convolutional interleavers 1, convolutional interleavers 2, ..., convolutional interleavers 31 use the same interleaving structure.

[0514] Figure 28(a) is a schematic diagram of the sixteenth structure of the convolutional interleaver in this application embodiment. As shown in Figure 28(a), it includes p = 3 delay lines. These p = 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, with each storage unit used to store d = 1 symbol. That is, the delay value of delay line 0 is 2Q symbols, the delay value of delay line 1 is Q symbols, and the delay value of delay line 2 is 0 symbols, i.e., no delay.

[0515] As shown in Figure 28(a), C r (·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (3t) represents one RS symbol currently input to delay line 0 in the channel data stream, and C r (3t-6Q) represents one RS symbol output from delay line 0; C r (3t+1) represents the next RS symbol input to delay line 1 in the channel data stream, and C r (3t-3Q+1) represents one RS symbol output from delay line 1; C r (3t+2) represents the next RS symbol input to delay line 2 in the channel data stream, and C r (3t+2) represents one RS symbol output from delay line 2; C r (3t+3) represents one RS symbol subsequently input to delay line 0 in the channel data stream, and C r (3t-6Q+3) represents one RS symbol output from delay line 0, and so on. Combined with... Figure 9 It can be seen that when 3Q+1≥136, i.e., Q≥45, the C of the convolutional interleaving output... r (3t-6Q), C r (3t-3Q+2), C r (3t+2) A total of 3 RS symbols come from 3 different RS codewords.

[0516] Figure 28(b) is a schematic diagram of the seventeenth structure of the convolutional interleaver in this application. As shown in Figure 28(b), in one possible implementation, Q = 45 is selected, and the specific structure of the convolutional interleaver is shown in Figure 28(b). The corresponding interleaving delay is approximately 90 * 3 / 2 = 135 RS symbols.

[0517] The convolutional interleaver shown in Figure 28(b) is used to perform convolutional interleaving on the 32 FEC channel data streams to obtain 32 first data streams. (Reference) Figure 9As shown in the FEC channel data stream, it is not difficult to understand that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 8 subsets of first data streams: first data streams 0-3 are subset 0, first data streams 4-7 are subset 1, first data streams 8-11 are subset 2, first data streams 12-15 are subset 3, first data streams 16-19 are subset 4, first data streams 20-23 are subset 5, first data streams 24-27 are subset 6, and first data streams 28-31 are subset 7.

[0518] This embodiment adopts the multiplexing processing structure in embodiment 12, and Δ = 1, 3 can obtain 8 second data streams, and the 12 consecutive RS symbols in each second data stream come from 12 different RS codewords.

[0519] The encoding scheme for the eight second data streams output by the above multiplexing process can all adopt the scheme in Example 1, and the performance is comparable to that of Example 1. This will not be repeated here.

[0520] Example 18: Applied to an 8×100G interface scenario, the internal code encoding information bit length is 160 bits, a 4:1 multiplexer is used, and channel correction processing is employed.

[0521] Based on the scheme in Example 16, this example provides a second-lowest latency implementation scheme with an internal code information length of 160 bits and a 4:1 multiplexer for multiplexing processing, and correspondingly adopts a newly designed interleaver and multiplexing processing.

[0522] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleavers 0, convolutional interleavers 1, convolutional interleavers 2, ..., convolutional interleavers 31 use the same interleaving structure.

[0523] Figure 29(a) is a schematic diagram of the eighteenth structure of the convolutional interleaver in this application embodiment. As shown in Figure 29(a), it includes p = 4 delay lines. These p = 4 delay lines respectively include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, with each storage unit used to store d = 1 symbol. That is, the delay value of delay line 0 is 3Q symbols, the delay value of delay line 1 is 2Q symbols, the delay value of delay line 2 is Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

[0524] As shown in Figure 29(a), C r (·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (4t) represents one RS symbol currently input to delay line 0 in the channel data stream, and C r (4t-12Q) represents one RS symbol output from delay line 0; C r (4t+1) represents the next RS symbol input to delay line 1 in the channel data stream, and C r (4t-8Q+1) represents one RS symbol output from delay line 1; C r (4t+2) represents the next RS symbol input to delay line 2 in the channel data stream, and C r (4t-4Q+2) represents one RS symbol output from delay line 2; C r (4t+3) represents the next RS symbol input to delay line 3 in the channel data stream, and C r (4t+3) represents one RS symbol output from delay line 3; C r (4t+4) represents one RS symbol subsequently input to delay line 0 in the channel data stream, and C r (4t-12Q+4) represents one RS symbol output from delay line 0, and so on. Combined with... Figure 9 It can be seen that when 4Q+1≥136, i.e., Q≥34, the C of the convolutional interleaving continuous output is... r (4t-12Q), C r (4t-8Q+1),C r (4t-4Q+2), C r (4t+3) A total of 4 RS symbols come from 4 different RS codewords.

[0525] Figure 29(b) is a schematic diagram of the nineteenth structure of the convolutional interleaver in this application embodiment. As shown in Figure 29(b), in one possible implementation, Q = 34 is selected, and the specific structure of the convolutional interleaver is shown in Figure 29(b). Its corresponding interleaving delay is approximately 102*4 / 2 = 204 RS symbols.

[0526] The convolutional interleaver shown in Figure 29(b) is used to perform convolutional interleaving on the 32 FEC channel data streams to obtain 32 first data streams. (Reference) Figure 9 As shown in the FEC channel data stream, it is not difficult to understand that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 8 subsets of first data streams: first data streams 0-3 are subset 0, first data streams 4-7 are subset 1, first data streams 8-11 are subset 2, first data streams 12-15 are subset 3, first data streams 16-19 are subset 4, first data streams 20-23 are subset 5, first data streams 24-27 are subset 6, and first data streams 28-31 are subset 7.

[0527] This embodiment adopts the multiplexing processing structure in embodiment 13, and when Δ = 1, 2, 4, 8 second data streams can be obtained, and the 16 consecutive RS symbols in each second data stream come from 16 different RS codewords.

[0528] The above eight second data streams are respectively encoded with internal codes. The internal code encoding scheme can adopt the internal code encoding scheme of Example 3, which can achieve performance comparable to Example 3. It will not be described again here.

[0529] Example 19: Applied to an 8×100G interface scenario, the internal code encoding information bit length is 120 bits, a 2:1 multiplexer is used, and channel correction processing is employed.

[0530] Based on the scheme of Example 16, this example provides a newly designed convolutional interleaver and multiplexing process when the internal code information length is 120 bits and a 4:1 multiplexer is used for multiplexing.

[0531] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleavers 0, convolutional interleavers 1, convolutional interleavers 2, ..., convolutional interleavers 31 use the same interleaving structure.

[0532] Figure 30(a) is a schematic diagram of the twentieth structure of the convolutional interleaver in this application embodiment. As shown in Figure 30(a), it includes p = 6 delay lines. These p = 6 delay lines include 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store d = 1 symbol. That is, the delay value of delay line 0 is 5Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 3Q symbols, the delay value of delay line 3 is 2Q symbols, the delay value of delay line 4 is Q symbols, and the delay value of delay line 5 is 0 symbols, i.e., no delay.

[0533] As shown in Figure 30(a), C r (·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (6t) represents one RS symbol currently input to delay line 0 in the channel data stream, and C r (6t-30Q) represents one RS symbol output from delay line 0; C r (6t+1) represents the next RS symbol input to delay line 1 in the channel data stream, and C r (6t-24Q+1) represents one RS symbol output from delay line 1; C r (6t+2) represents the next RS symbol input to delay line 2 in the channel data stream, and C r (6t-18Q+2) represents one RS symbol output from delay line 2; C r (6t+3) represents the next RS symbol input to delay line 3 in the channel data stream, and C r (6t-12Q+3) represents one RS symbol output from delay line 3; C r (6t+4) represents the next RS symbol input to delay line 4 in the channel data stream, and C r (6t-6Q+4) represents one RS symbol output from delay line 4; C r (6t+5) represents the next RS symbol input to delay line 5 in the channel data stream, and C r (6t+5) represents one RS symbol output from delay line 5; C r (6t+6) represents one RS symbol subsequently input to delay line 0 in the channel data stream, and C r (6t-30Q+6) represents one RS symbol output from delay line 0, and so on. Combined with... Figure 9 It can be seen that when 6Q+1≥136, i.e., Q≥23, the C of the convolutional interleaving continuous output is... r (6t-30Q), C r(6t-24Q+1), C r (6t-18Q+2), C r (6t-12Q+3), C r (6t-6Q+4), C r (6t+5) A total of 6 RS symbols come from 6 different RS codewords.

[0534] Figure 30(b) is a schematic diagram of the twenty-first structure of the convolutional interleaver in this application. As shown in Figure 30(b), in one possible implementation, Q = 23 is selected, and the specific structure of the convolutional interleaver is shown in Figure 30(b). The corresponding interleaving delay is approximately 23 * 5 * 6 / 2 = 345 RS symbols.

[0535] The convolutional interleaver shown in Figure 30(b) is used to perform convolutional interleaving on the 32 FEC channel data streams to obtain 32 first data streams. (Reference) Figure 9 As shown in the FEC channel data stream, it is not difficult to understand that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 8 subsets of first data streams: first data streams 0-3 are subset 0, first data streams 4-7 are subset 1, first data streams 8-11 are subset 2, first data streams 12-15 are subset 3, first data streams 16-19 are subset 4, first data streams 20-23 are subset 5, first data streams 24-27 are subset 6, and first data streams 28-31 are subset 7.

[0536] This embodiment adopts the multiplexing processing structure in embodiment 13, and when Δ = 1, 2, 3, 6, 16 second data streams can be obtained, and the 12 consecutive RS symbols in each second data stream come from 12 different RS codewords.

[0537] The aforementioned 16 second data streams are respectively encoded using internal codes. The encoding scheme can adopt the internal code encoding scheme in Example 1 and can achieve performance comparable to Example 1, which will not be elaborated here.

[0538] Example 20: Applied to an 8×100G interface scenario, the internal code encoding information bit length is 160 bits, a 2:1 multiplexer is used, and channel correction processing is employed.

[0539] Based on the scheme of Example 16, this example provides a newly designed convolutional interleaver and multiplexing process when the internal code information length is 160 bits and a 2:1 multiplexer is used for multiplexing.

[0540] In this embodiment, the convolutional interleaving process is as follows: Figure 11 The structure shown performs convolutional interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolutional interleavers 0, convolutional interleavers 1, convolutional interleavers 2, ..., convolutional interleavers 31 use the same interleaving structure.

[0541] Figure 31(a) is a schematic diagram of the twenty-second structure of the convolutional interleaver in this application embodiment. As shown in Figure 31(a), it includes p = 8 delay lines. These p = 8 delay lines respectively include 7Q storage units, 6Q storage units, 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, with each storage unit used to store d = 1 symbol. That is, the delay value of delay line 0 is 7Q symbols, the delay value of delay line 1 is 6Q symbols, the delay value of delay line 2 is 5Q symbols, the delay value of delay line 3 is 4Q symbols, the delay value of delay line 4 is 3Q symbols, the delay value of delay line 5 is 2Q symbols, the delay value of delay line 6 is Q symbols, and the delay value of delay line 7 is 0 symbols, i.e., no delay.

[0542] As shown in Figure 31(a), C r (·) represents an RS symbol in the data stream r (0≤r≤n-1) of this channel. For example, C r (8t) represents one RS symbol currently input to delay line 0 in the channel data stream, and C r (8t-56Q) represents one RS symbol output from delay line 0; C r (8t+1) represents the next RS symbol input to delay line 1 in the channel data stream, and C r (8t-48Q+1) represents one RS symbol output from delay line 1; C r (8t+2) represents the next RS symbol input to delay line 2 in the channel data stream, and C r (8t-40Q+2) represents one RS symbol output from delay line 2; C r (8t+3) represents the next RS symbol input to delay line 3 in the channel data stream, and C r (8t-32Q+3) represents one RS symbol output from delay line 3; C r (8t+4) represents the next RS symbol input to delay line 4 in the channel data stream, and Cr (8t-24Q+4) represents one RS symbol output from delay line 4; C r (8t+5) represents the next RS symbol input to delay line 5 in the channel data stream, and C r (8t-16Q+5) represents one RS symbol output from delay line 5; C r (8t+6) represents the next RS symbol input to delay line 6 in the channel data stream, and C r (8t-8Q+6) represents one RS symbol output from delay line 6; C r (8t+7) represents the next RS symbol input to delay line 7 in the channel data stream, and C r (8t+7) represents one RS symbol output from delay line 7; C r (8t+8) represents one RS symbol subsequently input to delay line 0 in the channel data stream, and C r (8t-56Q+8) represents one RS symbol output from delay line 0, and so on. Combined with... Figure 9 It can be seen that when 8Q+1≥136, i.e., Q≥17, the C of the convolutional interleaving continuous output is... r (8t-56Q), C r (8t-48Q+1),C r (8t-40Q+2), C r (8t-32Q+3),C r (8t-24Q+4), C r (8t-16Q+5),C r (8t-8Q+6),C r (8t+7) A total of 8 RS symbols come from 8 different RS codewords.

[0543] Figure 31(b) is a schematic diagram of the twenty-third structure of the convolutional interleaver in this application embodiment. As shown in Figure 31(b), in one possible implementation, Q = 17 is selected, and the specific structure of the convolutional interleaver is shown in Figure 31(b). Its corresponding interleaving delay is approximately 17 * 7 * 8 / 2 = 476 RS symbols.

[0544] The convolutional interleaver shown in Figure 31(b) is used to perform convolutional interleaving on the 32 FEC channel data streams to obtain 32 first data streams. (Reference) Figure 9As shown in the FEC channel data stream, it is not difficult to understand that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 8 subsets of first data streams: first data streams 0-3 are subset 0, first data streams 4-7 are subset 1, first data streams 8-11 are subset 2, first data streams 12-15 are subset 3, first data streams 16-19 are subset 4, first data streams 20-23 are subset 5, first data streams 24-27 are subset 6, and first data streams 28-31 are subset 7.

[0545] This embodiment adopts the multiplexing processing structure in embodiment 13, and when Δ = 1, 2, 4, 8, 16 second data streams can be obtained, and the 16 consecutive RS symbols in each second data stream come from 16 different RS codewords.

[0546] The aforementioned 16 second data streams are each encoded using internal codes. The internal code encoding scheme can adopt the internal code encoding scheme of Embodiment 3, which can achieve performance comparable to Embodiment 3. This will not be elaborated further here.

[0547] Example 21: Applied to an 8×100G interface scenario, the internal code encoding information bit length is 120 bits or 160 bits, and channel symbol alignment is used.

[0548] Based on any of the embodiments in Examples 16-20, this embodiment provides a lower latency implementation scheme.

[0549] Based on the data processing diagram of the transmitting end processing module shown in Figure 3(d), the transmitting end processing module uses known alignment markers from FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 to perform alignment lock on the four channel data streams. The transmitting end processing module then aligns the 32 channel data streams using one RS symbol to obtain 32 aligned channel data streams. These 32 channel data streams are convolved and interleaved to obtain 32 first data streams. The first data streams are then multiplexed to obtain 4, 8, or 16 second data streams, which are then fed into an internal code encoder for internal code encoding. After internal code encoding, the data streams are processed and then transmitted through the channel transmission medium.

[0550] It should be understood that the multiplexing and internal code encoding schemes used in this embodiment are all based on the schemes given in any of the embodiments in Embodiments 16-20.

[0551] When the multiplexed processor and internal code encoding used in this embodiment are the same as those in Embodiment 16, the performance of its concatenated code under AWGN is comparable, but slightly worse in resisting system burst errors. This scheme is suitable for some scenarios requiring lower latency.

[0552] When the multiplexed processor and internal code encoding used in this embodiment are the same as those in Embodiment 17, the performance of its concatenated code under AWGN is comparable, but slightly worse in resisting system burst errors. This scheme is suitable for some scenarios requiring lower latency.

[0553] When the multiplexed processor and internal code encoding used in this embodiment are the same as those in Embodiment 18, the performance of its concatenated code under AWGN is comparable, but slightly worse in resisting system burst errors. This scheme is suitable for some scenarios requiring lower latency.

[0554] When the multiplexed processor and internal code encoding used in this embodiment are the same as those in Embodiment 19, its concatenated code performs comparably under AWGN, but is slightly worse at handling sudden system errors. This scheme is suitable for scenarios requiring lower latency.

[0555] When the multiplexed processor and internal code encoding used in this embodiment are the same as those in Embodiment 20, the performance of its concatenated code under AWGN is comparable, but it is slightly worse at resisting sudden system errors. This scheme is suitable for some scenarios requiring lower latency.

[0556] It should be noted that in some possible implementations, the multiplexing process described in the above embodiments can also be replaced by group interleaving, which will be described below with reference to a specific embodiment.

[0557] Figure 32(a) is a schematic diagram of a structure for grouping and interleaving n first data streams in an embodiment of this application. As shown in Figure 32(a), group interleaving can be performed using m parallel group interleaving modules. Specifically, each group interleaver generates a second data stream from the K input first data streams through group interleaving, resulting in a total of m second data streams. The selection method of the K first data streams input to each group interleaver is the same as the selection method of the K input multiplexed data streams of the input multiplexer in the above embodiments, and will not be repeated here.

[0558] Figure 32(b) is a schematic diagram of a group interleaver in an embodiment of this application. As shown in Figure 32(b), the first data stream i k A set of Δ consecutive RS symbols is a subset of symbols, denoted by S. k (.) represents, where 0 ≤ k ≤ K-1. Therefore, S k (0),S k (1),…,S k (W) represents the first data stream i k The output consists of W consecutive symbol subsets. In the second data stream, Δ consecutive RS symbols constitute a symbol subset, denoted by S(.). From each of the K input data streams, W symbol subsets are obtained to form a K x W first symbol matrix. Each element in the first symbol matrix is ​​a symbol subset. Then S... k (w) corresponds to the element in the k-th row and w-th column of the first symbol matrix, where 0 ≤ k ≤ K-1, 0 ≤ w ≤ W-1. The first symbol matrix, with k rows and W columns, is interleaved to obtain a second symbol matrix with 1 row and C columns, where C = K*W. Each element in the second symbol matrix is ​​also a subset of symbols, denoted by S(c), where 0 ≤ c ≤ C. The interleaved S(c) and S... k The mapping between (w) can be expressed as: c = K*w + k. The second symbol matrix S(0), S(0), ..., S(K*W-1) after group interleaving corresponds to the information bits of Q internal codes. After encoding, Q internal codes are obtained. If the length of the internal code is D symbols, then K*W*Δ = Q*D.

[0559] It should be noted that the above-mentioned symbol subsets are concepts introduced for ease of description. In practical applications, the first data stream and the second data stream are both independent entities and there is no division between them. Each symbol subset can be considered as one or more symbols in the first or second data stream. Furthermore, in practical applications, the first and second symbol matrices mentioned above may not be presented in matrix form. For example, the first symbol matrix may be presented as a first symbol set, which includes K*W symbol subsets, corresponding to K rows and W columns of elements in the first symbol matrix. The second symbol matrix may be presented as a second symbol set, which includes C symbol subsets, corresponding to 1 row and C columns of elements in the second symbol matrix.

[0560] As an example, based on the convolutional interleaver given in Implementation List 1, a specific implementation of group interleaving is G=2, K=2, m=16. The input first data stream i0 and first data stream i1 of the group interleaver i correspond to the first data stream i and the first data stream i+16, respectively. Taking the group interleaver structure shown in Figure 32(b) as an example, the parameters of the group interleaver can be Δ=6, W=1, Q=1; or Δ=3, W=2, Q=1. The second symbol matrix is ​​mapped to information data with an internal code of 120 bits in length, which can be achieved using the internal code encoding scheme in Implementation List 1, achieving comparable performance.

[0561] As another example, based on the convolutional interleaver given in Implementation List 1, another specific implementation of group interleaving is G=2, K=4, m=16. The input first data streams i0 to i3 of the group interleaver i correspond to first data stream i, first data stream i+16, first data stream i+8, and first data stream i+24, respectively. Taking the group interleaver structure shown in Figure 32(b) as an example, the parameters of the group interleaver can be Δ=6, W=1, Q=2. The second symbol matrix is ​​mapped to information data in two 120-bit internal codes, which can be encoded using the internal code encoding scheme in Implementation List 1 to achieve comparable performance.

[0562] As another example, based on the convolutional interleaver given in Implementation List 1, another specific implementation of group interleaving is G=2, K=8, m=16. The input first data streams i0 to i7 of the group interleaver i correspond to first data stream i, first data stream i+16, first data stream i+8, first data stream i+24, first data stream i+4, first data stream i+20, first data stream i+12, and first data stream i+28, respectively. Taking the group interleaver structure shown in Figure 32(b) as an example, the parameters of the group interleaver can be Δ=6, W=1, Q=4. The second symbol matrix is ​​mapped to information data with a length of 4 information bits of 120 bits, which can adopt the internal code encoding scheme in Implementation List 1 to achieve comparable performance.

[0563] It should be understood that the corresponding implementation of block interleaving can also be derived based on other implementation columns of convolutional interleaving and internal code encoding schemes, which will not be listed here.

[0564] The data processing method provided in the embodiments of this application has been described above. The data processing apparatus provided in the embodiments of this application will be described below.

[0565] Figure 33 This is a schematic diagram of a data processing device according to an embodiment of this application. Figure 33 As shown, the data processing apparatus includes a convolutional interleaver 101 and a multiplexer 102. The convolutional interleaver 101 performs the operation described in the above data processing method of convolutionally interleaving n channel data streams to obtain n first data streams. The multiplexer 102 performs the operation described in the above data processing method of multiplexing every K first data streams from the n first data streams to obtain one second data stream, resulting in a total of m second data streams. For details, please refer to the relevant descriptions of the convolutional interleaving and multiplexing operations in the above data processing method; they will not be repeated here.

[0566] It should be understood that the apparatus provided in this application can also be implemented in other ways. For example, the unit division in the above apparatus is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0567] It should be noted that, in addition to the data processing method described in the above embodiments, this application also provides another data processing method, which will be described in detail below.

[0568] In this embodiment, n channel data streams are first interleaved to obtain m target data streams. Then, each of the m target data streams undergoes second FEC encoding to obtain an encoded data stream. The method of performing second FEC encoding on each of the m target data streams is the same as described above. Figure 10 The method described in step 1003 of the illustrated embodiment is similar and will not be repeated here.

[0569] In this embodiment, the channel data stream can be either a PCS channel data stream or an FEC channel data stream; the specific type is not limited here. All n channel data streams are data streams encoded using the first FEC, which is the data stream encoded using the external code described above. Here, n is an integer greater than 1 and a multiple of 4. For example, the external code encoding can use RS code, and the n data streams after external code encoding can include multiple RS codewords. In practical applications, other encoding methods can also be used for external code encoding. For ease of description, RS codewords will be used uniformly below to represent the codewords generated after external code encoding. It should be understood that each 'a' codeword after external code encoding is distributed across b channel data streams, where a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. In the above... Figures 5-9 In the different application scenarios shown, the values ​​of a and b may also be different. Figure 5 Taking the application scenario shown as an example, n=32, a=2, b=16, meaning that every 2 codewords are distributed across 16 data stream channels. Figures 6-9 In other application scenarios, the values ​​of a and b can be derived from the attached diagram, and will not be elaborated here. Therefore, the maximum value of b is 16, and the minimum value is 4. It should be noted that the code length of the foreign code in this application is counted in units of symbols, where a symbol can include one or more bits. For example, the foreign code uses the KP4 RS(544,514) code, with a code length of N = 544 symbols, and one symbol con...

Claims

1. A data processing method, characterized in that, Grouping and interleaving each of the t channel data streams from the n channel data streams yields s first data streams, resulting in a total of m first data streams, where n=q. t, m=q s, where n is an integer greater than 1, n is divisible by q, q is an integer greater than or equal to 1, t=2, or t=4, or t=8, s is an integer greater than or equal to 1, all n channel data streams are encoded using first forward error correction (FEC), each a codeword after the first FEC encoding is distributed in b channel data streams, a≤b≤n, n is divisible by b, a is an integer greater than 1, each consecutive a symbols in each channel data stream comes from a different codeword, and each consecutive L1 symbols in each channel data stream comes from at least a different codeword, L1=N a / b, where N represents the length of the codeword, the n channel data streams include a first group of n / 2 channel data streams and a second group of n / 2 channel data streams, any symbol in the first group of n / 2 channel data streams and any symbol in the second group of n / 2 channel data streams come from different codewords, the first group of t / 2 channel data streams in each t channel data stream comes from the first group of n / 2 channel data streams, and the second group of t / 2 channel data streams in each t channel data stream comes from the second group of n / 2 channel data streams; The m first data streams are convolved and interleaved to obtain m second data streams.

2. The method according to claim 1, characterized in that, In the n-channel data stream, the first group of n / 2 channel data streams comes from the same codeword, and the second group of n / 2 channel data streams also comes from the same codeword.

3. The method according to claim 1 or 2, characterized in that, t=s, the t channel data streams include a first channel data stream and a second channel data stream. The first channel data stream is one of the n / 2 channel data streams in the first group, and the second channel data stream is one of the n / 2 channel data streams in the second group. A consecutive a symbols in the first channel data stream and a consecutive a symbols in the second channel data stream are consecutive in any one of the s first data streams.

4. The method according to claim 1 or 2, characterized in that, a=2, b=n / 2.

5. The method according to claim 1 or 2, characterized in that, In each of the first data streams, every consecutive d symbols come from v different codewords, and in each of the first data streams, every consecutive L2 symbols come from at least v different codewords, where v is divisible by a, and L2 = t / s. L1, d=v.

6. The method according to claim 5, characterized in that, v=2 and.

7. The method according to claim 1 or 2, characterized in that, s=1。 8. The method according to claim 1 or 2, characterized in that, The second data stream is obtained by convolutional interleaving of a first data stream, including: A second data stream is obtained by delaying a first data stream using p delay lines, where p is an integer greater than 1. Each delay line has a different number of storage units, with the delay line having the fewest storage units (0 units). The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d symbols. The symbols in each first data stream are sequentially input into the p delay lines according to their indices. Each delay line inputs and outputs d symbols at a time. A second data stream contains consecutive p... The d symbols include the d symbols output by each delay line, where Q is an integer greater than or equal to 1.

9. The method according to claim 8, characterized in that, The delay line with the largest sequence number among the p delay lines includes 0 memory cells. L2=t / s L1; or, The delay line with the smallest sequence number among the p delay lines includes 0 memory cells. L2=t / s L1.

10. The method according to claim 8, characterized in that, After performing convolutional interleaving on the m first data streams to obtain m second data streams, the method further includes: The m second data streams are each subjected to second FEC encoding to obtain m encoded data streams. In each encoded data stream, information data of length K symbols comes from at most K different codewords.

11. The method according to claim 1 or 2, characterized in that, Where n=32, the first 16 consecutive channel data streams in the n channel data streams come from the same codeword, the last 16 consecutive channel data streams in the n channel data streams come from the same codeword, and the first 16 consecutive channel data streams and the last 16 consecutive channel data streams in the n channel data streams come from different codewords.

12. The method according to claim 11, characterized in that, When t=8 and s=1, the first data streams (s) are obtained by grouping and interleaving each t channel data stream from the n channel data streams, including: For the 4th i-channel data stream, 4th i+1 channel data stream, 4th i+2 channel data stream, the 4th i+3 channel data streams, the 4th i+16 channel data streams, the 4th i+17th channel data stream, the 4th i+18 channel data streams and the 4th The i+19 channel data streams, comprising 8 channel data streams, are grouped and interleaved to obtain a first data stream, where 0 ≤ i ≤ 3. Each of the 8 channel data streams includes 16 consecutive symbols (2 symbols each) that are consecutive in the first data stream obtained by the grouping and interleaving. Each consecutive 16 symbols in the first data stream comes from at least 4 different codewords, and each consecutive 544 symbols also comes from at least 4 different codewords. The 0th, 1st, 2nd, and 3rd symbols of each consecutive 16 symbols in the first data stream obtained by the grouping and interleaving are... The three symbols come from different codewords. In the first data stream obtained by the group interleaving, the fourth, fifth, sixth, and seventh symbols of every 16 consecutive symbols come from different codewords. The eighth, ninth, tenth, and eleventh symbols of every 16 consecutive symbols of the first data stream obtained by the group interleaving come from different codewords. The twelfth, thirteenth, fourteenth, and fifteenth symbols of every 16 consecutive symbols of the first data stream obtained by the group interleaving come from different codewords.

13. The method according to claim 11, characterized in that, When t=8 and s=1, the first data streams (s) are obtained by grouping and interleaving each t channel data stream from the n channel data streams, including: For the 4th i-channel data stream, 4th i+1 channel data stream, 4th i+2 channel data stream, the 4th i+3 channel data streams, the 4th i+16 channel data streams, the 4th i+17th channel data stream, the 4th i+18 channel data streams and the 4th The i+19 channel data streams, comprising 8 channel data streams, are grouped and interleaved to obtain a first data stream, where 0 ≤ i ≤ 3. In the first data stream, the j-th group of 2 consecutive symbols (a total of 16 symbols) from each of the 8 channel data streams are consecutive in the grouped and interleaved group. Also, j ≥ 0. In the first data stream, every 16 consecutive symbols come from at least 4 different codewords, and every 544 consecutive symbols come from at least 4 different codewords. In the first data stream obtained by group interleaving, the 0th, 1st, 2nd, and 3rd symbols of every consecutive 16 symbols come from different codewords. In the first data stream obtained by group interleaving, the 4th, 5th, 6th, and 7th symbols of every consecutive 16 symbols come from different codewords. In the first data stream obtained by group interleaving, the 8th, 9th, 10th, and 11th symbols of every consecutive 16 symbols come from different codewords. In the first data stream obtained by group interleaving, the 12th, 13th, 14th, and 15th symbols of every consecutive 16 symbols come from different codewords.

14. The method according to claim 1 or 2, characterized in that, The second data stream is obtained by convolutional interleaving of a first data stream, including: A second data stream is obtained by delaying a first data stream using p delay lines, where p is an integer greater than 1. Each delay line has a different number of storage units, with the delay line having the fewest storage units (0 units). The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores 4 symbols. The symbols in each first data stream are sequentially input into the p delay lines according to their numbers. Each delay line inputs and outputs 4 symbols at a time. A second data stream contains p consecutive delay lines. The four symbols include the four symbols output from each delay line, wherein Q satisfies 15. The method according to claim 14, characterized in that, After performing convolutional interleaving on the m first data streams to obtain m second data streams, the method further includes: The m second data streams are respectively subjected to second FEC encoding to obtain m encoded data streams. In each encoded data stream, the information data of length K symbols comes from at most K different codewords, where K ≥ p.

4.

16. A data processing apparatus, comprising a group interleaver and a convolutional interleaver, characterized in that, The data processing device is used to perform the method as described in any one of claims 1-15.

17. A chip comprising a group interleaver and a convolutional interleaver, characterized in that, The chip is used to perform the method as described in any one of claims 1-15.

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