Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

This invention relates to a method for fabricating a semiconductor structure and the semiconductor structure itself. The method includes: providing a substrate and forming an epitaxial layer on the substrate; forming an initial dielectric layer having a first interconnect trench extending to the top surface of the epitaxial layer; forming a first interconnect layer and a first isolation trench located within the first interconnect layer, the first interconnect layer covering a portion of the top surface of the initial dielectric layer and filling the first interconnect trench; removing a portion of the initial dielectric layer to form the first dielectric layer, and forming a second dielectric layer and a target contact hole penetrating the first and second dielectric layers, the orthographic projection of the target contact hole located within the first isolation trench, the second dielectric layer also having a second interconnect trench exposing a portion of the top surface of the first interconnect layer; forming a second interconnect layer and a second isolation trench, the second interconnect layer covering a portion of the top surface of the second dielectric layer and filling the second interconnect trench, the second isolation trench being located at least between the first and second interconnect trenches. The above method allows for flexible cell arrangement, improving chip efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In the field of semiconductor manufacturing technology, especially in metal-oxide-semiconductor field-effect transistors (MOSFETs), the chip efficiency of transistors is one of the important parameters.

[0003] For power MOSFET devices, to ensure proper operation, the gate and source terminals of the transistor need to be brought out. Furthermore, to distinguish the signals from these terminals, the metal layer containing the gate needs to be isolated from the metal layer containing the source. However, this arrangement prevents the placement of transistor cells beneath the gate and source metal layers. The area occupied by these cells is the active region of the transistor; the smaller the active region, the lower the chip's efficiency. Summary of the Invention

[0004] Based on this, embodiments of this application provide a method for preparing a semiconductor structure and a semiconductor structure.

[0005] According to some embodiments, this application provides a method for fabricating a semiconductor structure, the method comprising:

[0006] Provide a substrate and form an epitaxial layer on the substrate;

[0007] An initial dielectric layer is formed on the epitaxial layer, and the initial dielectric layer has a first connection groove that extends to the top surface of the epitaxial layer and the first connection groove extends along a first direction.

[0008] A first connecting layer and a first isolation groove located within the first connecting layer are formed. The first connecting layer covers a portion of the top surface of the initial dielectric layer and fills the first connecting groove. The first isolation groove extends along a first direction.

[0009] A portion of the initial dielectric layer is removed to form a first dielectric layer, and a second dielectric layer and a target contact hole penetrating the first dielectric layer and the second dielectric layer are formed. The orthographic projection of the target contact hole is located in the first isolation groove. The second dielectric layer also has a second connection groove that exposes a portion of the top surface of the first connection layer.

[0010] A second connecting layer and a second isolation groove located within the second connecting layer are formed. The second connecting layer covers a portion of the top surface of the second dielectric layer and fills the second connecting groove. The second isolation groove is located at least between the first connecting groove and the second connecting groove.

[0011] In the semiconductor structure fabrication method of the above embodiments, the first interconnect layer and the first isolation trench located within the first interconnect layer are formed separately from the second interconnect layer and the second isolation trench located within the second interconnect layer. The first interconnect layer covers a portion of the top surface of the initial dielectric layer, and the second interconnect layer covers a portion of the top surface of the second dielectric layer. This reduces the area occupied by the first isolation trench, and allows for cell arrangement in the region except below the first isolation trench, including the region below the second isolation layer. This increases the active area, resulting in higher current capability and switching efficiency, and improves the performance of the device chip.

[0012] In some embodiments, before forming an initial dielectric layer on the epitaxial layer, the method further includes:

[0013] A field oxide layer is formed on the epitaxial layer;

[0014] A gate oxide layer is formed on the field oxide layer, and the gate oxide layer covers the surface of the field oxide layer;

[0015] A gate is formed on the epitaxial layer, and the gate covers a portion of the top surface of the gate oxide layer and a portion of the top surface of the epitaxial layer.

[0016] An initial dielectric layer is formed on the epitaxial layer, including:

[0017] An initial material layer is formed, which covers the top surface of the gate, the top surface of the exposed gate oxide layer, and the top surface of the exposed epitaxial layer.

[0018] A portion of the initial material layer is removed to form the first connection groove, and the remaining initial material layer constitutes the initial dielectric layer.

[0019] In some embodiments, the first connection layer includes a first metal layer and a second metal layer; forming the first connection layer and a first isolation trench located within the first connection layer includes:

[0020] A first metal material layer is formed, which covers the top surface of the initial dielectric layer and fills the first connection groove;

[0021] A portion of the first metal material layer is removed to form a first isolation trench. The first isolation trench is located above the field oxide layer. The remaining first metal material layers constitute a first metal layer and a second metal layer, respectively. The first metal layer and the second metal layer are located on both sides of the first isolation trench. The first metal layer is located on the top surface of the initial dielectric layer, and the second metal layer is located at least within the first connecting trench.

[0022] In some embodiments, removing a portion of the initial dielectric layer to form a first dielectric layer, and forming a second dielectric layer and a target contact hole penetrating the first dielectric layer and the second dielectric layer, includes:

[0023] A dielectric material layer is formed, which covers the top surface of the initial dielectric layer, the top surface of the first metal layer, and the top surface of the second metal layer.

[0024] A portion of the dielectric material layer located on the top surface of the first metal layer is removed to form a second connection groove that exposes a portion of the top surface of the first metal layer;

[0025] A portion of the dielectric material layer and the initial dielectric layer are removed to form a target contact hole that exposes the top surface of the gate portion. The remaining initial dielectric layer constitutes the first dielectric layer, and the remaining dielectric material layer constitutes the second dielectric layer.

[0026] In some embodiments, the second connection layer includes a third metal layer and a fourth metal layer, forming the second connection layer and a second isolation trench located within the second connection layer, including:

[0027] A second metal material layer is formed, which covers the top surface of the second dielectric layer and also fills the second connecting groove and the target contact hole.

[0028] A portion of the second metal material layer is removed to form a second isolation groove. The remaining second metal material layers constitute a third metal layer and a fourth metal layer, respectively. The third metal layer and the fourth metal layer are located on both sides of the second isolation groove. The third metal layer is located at least in the second connecting groove, and the fourth metal layer is located at least in the target contact hole.

[0029] In some embodiments, the second isolation groove includes a first branch groove and a second branch groove; the first branch groove extends along a first direction and is located between the first connecting groove and the second connecting groove, and the second branch groove is located on one side of the opposite sidewall of the second connecting groove along a second direction.

[0030] In some embodiments, the gate includes a first gate extending along a first direction and a plurality of second gates extending along a second direction and spaced apart along the first direction, the first direction being perpendicular to the second direction; the target contact hole is located above the first gate, and one end of the second gate near the target contact hole is connected to the first gate; the target contact hole is a strip-shaped contact hole extending along the first direction.

[0031] In some embodiments, the gate includes a plurality of gate layers extending along a second direction and spaced apart along a first direction, the first direction being perpendicular to the second direction; the target contact hole is located above one end of the gate layer near the field oxide layer, and the target contact hole is circular or polygonal.

[0032] In some embodiments, the thickness of the field oxide layer is 1000 Å to 20000 Å.

[0033] In some embodiments, the thickness of the gate is 0.2um-0.5um.

[0034] In some embodiments, the thickness of the first dielectric layer is 0.5µm-1µm.

[0035] According to some embodiments, this application also provides a semiconductor structure, the semiconductor structure including a substrate and an epitaxial layer on the substrate, a first dielectric layer, a first interconnect layer and a first isolation trench located within the first interconnect layer, a second dielectric layer and a target contact hole penetrating the first dielectric layer and the second dielectric layer, a second interconnect layer and a second isolation trench located within the second interconnect layer; the first dielectric layer is located on the epitaxial layer, and the first dielectric layer has a first interconnect trench extending to the top surface of the epitaxial layer, the first interconnect trench extending along a first direction; the first interconnect layer covers a portion of the top surface of the first dielectric layer and fills the first interconnect trench, the first isolation trench extending along the first direction; the orthographic projection of the target contact hole is located within the first isolation trench, the second dielectric layer also has a second interconnect trench exposing a portion of the top surface of the first interconnect layer; the second interconnect layer covers a portion of the top surface of the second dielectric layer and fills the second interconnect trench, the second isolation trench being located at least between the first interconnect trench and the second interconnect trench.

[0036] In the semiconductor structure of the above embodiment, the first interconnect layer covers part of the top surface of the initial dielectric layer, the second interconnect layer covers part of the top surface of the second dielectric layer, and the second isolation trench is located at least between the first interconnect trench and the second interconnect trench. This can reduce the area occupied by the first isolation trench, and the area other than the area below the first isolation trench, including the area below the second isolation layer, can be arranged into cells, which is beneficial to increase the active area, thereby bringing higher current capability and switching efficiency, and improving the performance of the device chip. Attached Figure Description

[0037] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.

[0038] Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to another embodiment of this application;

[0039] Figure 3 This is a top view schematic diagram of the structure obtained in step S31 of a semiconductor structure fabrication method provided in an embodiment of this application;

[0040] Figure 4 for Figure 3 A schematic cross-sectional view of the structure shown at position AA';

[0041] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S50 of a semiconductor structure fabrication method according to an embodiment of this application;

[0042] Figure 6 for Figure 5A schematic cross-sectional view of the structure shown at position AA';

[0043] Figure 7 This is a top view schematic diagram of the structure obtained in step S71 of a semiconductor structure fabrication method provided in an embodiment of this application;

[0044] Figure 8 A top view schematic diagram of the structure obtained in steps S72 and S73 of a semiconductor structure fabrication method provided in an embodiment of this application;

[0045] Figure 9 for Figure 8 A schematic cross-sectional view of the structure shown at position AA';

[0046] Figure 10 A top view schematic diagram of a gate in a method for fabricating a semiconductor structure according to an embodiment of this application;

[0047] Figure 11 A top view schematic diagram of a gate in a method for fabricating a semiconductor structure according to another embodiment of this application;

[0048] Figure 12 This is a schematic cross-sectional view of the structure obtained in step S90 of a semiconductor structure fabrication method according to an embodiment of this application;

[0049] Figure 13 for Figure 12 The diagram shows a cross-sectional view of the structure at position AA'.

[0050] Explanation of reference numerals in the attached figures: 10, substrate; 101, epitaxial layer; 11, field oxide layer; 111, gate oxide layer; 12, gate; 121, first gate; 122, second gate; 123, gate layer; 20, initial dielectric layer; 201, initial material layer; L1, first connection trench; 21, first dielectric layer; 22, second dielectric layer; 221, dielectric material layer; L2, second connection trench; H1, target contact hole; 31, first connection layer; 311, first metal layer; 312, second metal layer; G1, first isolation trench; G11, first branch trench; G22, second branch trench; 32, second connection layer; 321, third metal layer; 322, fourth metal layer; G2, second isolation trench. Detailed Implementation

[0051] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0053] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0054] Furthermore, to clearly illustrate the multiple layers and regions in the accompanying drawings, the thickness of each layer and each region has been enlarged to clearly demonstrate the relative positions of the layers and the distribution of the regions. When a portion of a layer, film, region, plate, etc., is described as being "on one side" of another portion, this description includes not only the case where it is "directly" above the other portion, but also the case where other layers are present in between. Moreover, it is understood that when a portion of a layer, film, region, plate, etc., is described as being "on one side" of another portion, it generally refers to the side directly above the other portion.

[0055] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0056] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0057] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0058] For power MOSFET devices, to ensure proper operation, the gate and source terminals of the transistor need to be brought out. Furthermore, to prevent short circuits or interference between the gate and source signal lines, the signals at these terminals must be separated, and the metal layers containing the gate and source must be isolated. Otherwise, parasitic capacitance will increase, signal interference will occur, or short circuits may occur. However, this arrangement prevents the placement of transistor cells beneath the gate and source metal layers, as this would cause short circuits or performance degradation. The area occupied by the transistor cells is the active region; the smaller the active region, the lower the chip efficiency.

[0059] Based on this, embodiments of this application provide a method for preparing a semiconductor structure and a semiconductor structure.

[0060] Please see Figure 1 This application provides a method for fabricating a semiconductor structure, which includes the following steps.

[0061] Step S10: Provide a substrate and form an epitaxial layer on the substrate;

[0062] Step S30: An initial dielectric layer is formed on the epitaxial layer, and the initial dielectric layer has a first connecting groove extending through to the top surface of the epitaxial layer, and the first connecting groove extends along a first direction;

[0063] Step S50: Form a first connecting layer and a first isolation groove located in the first connecting layer. The first connecting layer covers part of the top surface of the initial dielectric layer and fills the first connecting groove. The first isolation groove extends along a first direction.

[0064] Step S70: Remove part of the initial dielectric layer to form a first dielectric layer, and form a second dielectric layer and a target contact hole penetrating the first dielectric layer and the second dielectric layer. The orthographic projection of the target contact hole is located in the first isolation groove. The second dielectric layer also has a second connection groove that exposes part of the top surface of the first connection layer.

[0065] Step S90: Form a second connecting layer and a second isolation groove located within the second connecting layer. The second connecting layer covers a portion of the top surface of the second dielectric layer and fills the second connecting groove. The second isolation groove is located at least between the first connecting groove and the second connecting groove.

[0066] In the semiconductor structure fabrication method of the above embodiment, the first interconnect layer and the first isolation trench located within the first interconnect layer are formed separately from the second interconnect layer and the second isolation trench located within the second interconnect layer. The first interconnect layer covers a portion of the top surface of the initial dielectric layer, and the second interconnect layer covers a portion of the top surface of the second dielectric layer. This reduces the area occupied by the first isolation trench, and allows for cell arrangement in the region except below the first isolation trench, including the region below the second isolation layer. This increases the active area, resulting in higher current capability and switching efficiency, and improves the performance of the device chip.

[0067] In some embodiments, before forming an initial dielectric layer on the epitaxial layer, the method further includes:

[0068] Step S21: Form a field oxide layer on the epitaxial layer;

[0069] Step S22: A gate oxide layer is formed on the field oxide layer, and the gate oxide layer covers the surface of the field oxide layer;

[0070] Step S23: A gate is formed on the epitaxial layer, and the gate covers part of the top surface of the gate oxide layer and part of the top surface of the epitaxial layer.

[0071] In some embodiments, step S30, forming an initial dielectric layer on the epitaxial layer, includes:

[0072] Step S31: Form an initial material layer, which covers the top surface of the gate, the exposed top surface of the gate oxide layer, and the exposed top surface of the epitaxial layer.

[0073] Step S32: Remove part of the initial material layer to form the first connection groove, and the remaining initial material layer constitutes the initial dielectric layer.

[0074] In some embodiments, the first connection layer includes a first metal layer and a second metal layer; step S50, forming the first connection layer and a first isolation trench located within the first connection layer, includes:

[0075] Step S51: Form a first metal material layer, which covers the top surface of the initial dielectric layer and fills the first connection groove;

[0076] Step S52: Remove part of the first metal material layer to form a first isolation trench. The first isolation trench is located above the field oxide layer. The remaining first metal material layer constitutes a first metal layer and a second metal layer. The first metal layer and the second metal layer are located on both sides of the first isolation trench. The first metal layer is located on the top surface of the initial dielectric layer, and the second metal layer is located at least in the first connecting trench.

[0077] In some embodiments, step S70, removing a portion of the initial dielectric layer to form a first dielectric layer, and forming a second dielectric layer and a target contact hole penetrating the first dielectric layer and the second dielectric layer, includes:

[0078] Step S71: Form a dielectric material layer, which covers the top surface of the initial dielectric layer, the top surface of the first metal layer, and the top surface of the second metal layer;

[0079] Step S72: Remove a portion of the dielectric material layer located on the top surface of the first metal layer to form a second connection groove that exposes a portion of the top surface of the first metal layer;

[0080] Step S73: Remove part of the dielectric material layer and the initial dielectric layer to form a target contact hole that exposes the top surface of the gate portion. The remaining initial dielectric layer constitutes the first dielectric layer, and the remaining dielectric material layer constitutes the second dielectric layer.

[0081] In some embodiments, the second connection layer includes a third metal layer and a fourth metal layer; step S90, forming the second connection layer and a second isolation trench located within the second connection layer, includes:

[0082] Step S91: Form a second metal material layer, which covers the top surface of the second dielectric layer and also fills the second connecting groove and the target contact hole.

[0083] Step S92: Remove part of the second metal material layer to form a second isolation groove. The remaining second metal material layer constitutes a third metal layer and a fourth metal layer, respectively. The third metal layer and the fourth metal layer are located on both sides of the second isolation groove. The third metal layer is located at least in the second connecting groove, and the fourth metal layer is located at least in the target contact hole.

[0084] In the embodiments disclosed above, unless otherwise expressly stated herein, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, but may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0085] To more clearly illustrate the semiconductor structure fabrication method provided in the above embodiments, the following is combined with... Figures 2 to 13 The method is described in detail.

[0086] like Figures 2 to 4 As shown, for example, step S101 may also be included after step S10.

[0087] Step S101: Ion implantation is performed on a portion of the epitaxial layer 101 to form a first well region (not shown), a second well region (not shown), and a doped layer (not shown) within the epitaxial layer 101; and after ion implantation is completed, a step of performing a high-temperature annealing process on the epitaxial layer 101 may be included to activate the doping elements implanted into the epitaxial layer 101 by the ion implantation process.

[0088] like Figure 4 As shown, in step S10, a substrate 10 is provided. As an example, in embodiments of this disclosure, the substrate 10 can be constructed from any combination of semiconductor materials, insulating materials, conductive materials, or similar materials. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon-germanium (SiGe) substrate 10, a silicon-germanium-carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10, or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art can select the type of substrate 10 according to the type of transistors formed on the substrate 10; therefore, the type of substrate 10 should not limit the scope of protection of this disclosure.

[0089] like Figures 2 to 4 As shown, in some embodiments, before forming the initial dielectric layer 20 on the epitaxial layer 101, the method further includes steps S21 to S23.

[0090] In step S21, a field oxide layer 11 is formed on the epitaxial layer 101. The field oxide layer 11 can be formed by a field oxide process, by depositing a field oxide material layer (not shown), and then removing part of the field oxide material layer by a wet etching process.

[0091] For example, the material of the field oxide layer 11 includes silicon oxide.

[0092] In some embodiments, the thickness of the field oxide layer 11 is 1000 Å to 20000 Å. For example, the thickness of the field oxide layer 11 is 1000 Å, 2000 Å, 5000 Å, 10000 Å or 20000 Å, etc.

[0093] In step S22, a gate oxide layer 111 is formed on the field oxide layer 11, and the gate oxide layer 111 covers the surface of the field oxide layer 11. For example, the gate oxide layer 111 can be formed by a thermal oxidation process or a deposition process.

[0094] In some embodiments, the thickness of the gate oxide layer 111 is 300 Å to 700 Å. For example, the thickness of the gate oxide layer 11 is 300 Å, 400 Å, 500 Å, 600 Å, or 700 Å, etc.

[0095] In step S23, a gate 12 is formed on the epitaxial layer 101. The gate 12 covers part of the top surface of the gate oxide layer 111 and part of the top surface of the epitaxial layer 101. The gate 12 can be formed by depositing a gate material layer (not shown) and then removing part of the gate material layer by a patterned etching process.

[0096] For example, the material of gate 12 includes polysilicon.

[0097] In some embodiments, the thickness of the gate 12 is 0.2um-0.5um. For example, the thickness of the gate 12 is 0.2um, 0.3um, 0.4um, or 0.5um, etc.

[0098] like Figures 3 to 6 As shown, in step S30, an initial dielectric layer 20 is formed on the epitaxial layer 101. The initial dielectric layer 20 has a first connecting groove L1 that extends to the top surface of the epitaxial layer 101 and extends along a first direction.

[0099] For example, the initial dielectric layer 20 can be a single-layer structure or a multi-layer stacked structure. In some embodiments, the initial dielectric layer 20 may include a silicon oxide layer, a boro-phospho-silicate glass (BPSG) layer, a silicon nitride layer, or a combination of these layers.

[0100] In some embodiments, step S30, forming an initial dielectric layer 20 on the epitaxial layer 101, includes steps S31 and S32.

[0101] In step S31, as Figure 3 and Figure 4 As shown, an initial material layer 201 is formed, which covers the top surface of the gate 12, the exposed top surface of the gate oxide layer 111, and the exposed top surface of the epitaxial layer 10.

[0102] In step S32, as Figure 5 and Figure 6 As shown, a portion of the initial material layer 201 is removed to form the first connecting groove L1, and the remaining initial material layer 201 constitutes the initial dielectric layer 20.

[0103] like Figure 5 and Figure 6 As shown, in step S50, a first connecting layer 31 and a first isolation groove G1 located in the first connecting layer 31 are formed. The first connecting layer 31 covers part of the top surface of the initial dielectric layer 20 and fills the first connecting groove L1. The first isolation groove G1 extends along the first direction.

[0104] like Figure 6 As shown, in some embodiments, the first bonding layer 31 includes a first metal layer 311 and a second metal layer 312. For example, the first metal layer 311 and the second metal layer 312 are made of the same metal material, and the first metal layer 311 and the second metal layer 312 can be formed simultaneously based on a one-time deposition process.

[0105] In some embodiments, step S50, forming a first connection layer 31 and a first isolation trench G1 located within the first connection layer 31, includes the following steps S51 and S52.

[0106] Step S51: Form a first metal material layer (not shown). The first metal material layer covers the top surface of the initial dielectric layer 20 and fills the first connecting groove L1.

[0107] Step S52: Remove part of the first metal material layer to form a first isolation trench G1. The first isolation trench G1 is located above the field oxide layer 11. The remaining first metal material layers constitute a first metal layer 311 and a second metal layer 312. The first metal layer 311 and the second metal layer 312 are located on both sides of the first isolation trench G1. The first metal layer 311 is located on the top surface of the initial dielectric layer 20, and the second metal layer 312 is located at least in the first connecting trench L1.

[0108] like Figures 7 to 9As shown, in step S70, a portion of the initial dielectric layer 20 is removed to form a first dielectric layer 21, and a second dielectric layer 22 and a target contact hole H1 penetrating the first dielectric layer 21 and the second dielectric layer 22 are formed. The orthographic projection of the target contact hole H1 is located in the first isolation groove G1. The second dielectric layer 22 also has a second connecting groove L2 that exposes a portion of the top surface of the first connecting layer 31.

[0109] In some embodiments, the thickness of the first dielectric layer 21 is 0.5um-1um. For example, the thickness of the first dielectric layer 21 is 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, or 1um, etc.

[0110] For example, the second dielectric layer 22 can be a single-layer structure or a multi-layer stacked structure. In some embodiments, the second dielectric layer 22 may include a silicon oxide layer, a boro-phospho-silicate glass (BPSG) layer, a silicon nitride layer, or a combination of these layers.

[0111] In some embodiments, step S70, removing a portion of the initial dielectric layer 20 to form a first dielectric layer 21, and forming a second dielectric layer 22 and a target contact hole H1 penetrating the first dielectric layer 21 and the second dielectric layer 22, includes the following steps S71 to S73.

[0112] like Figure 7 As shown, in step S71, a dielectric material layer 221 is formed, which covers the top surface of the initial dielectric layer 20, the top surface of the first metal layer 311, and the top surface of the second metal layer 312.

[0113] like Figure 8 and Figure 9 As shown, in step S72, a portion of the dielectric material layer 221 located on the top surface of the first metal layer 311 is removed to form a second connecting groove L2 that exposes a portion of the top surface of the first metal layer 311.

[0114] like Figure 8 and Figure 9 As shown, in step S73, a portion of the dielectric material layer 221 and the initial dielectric layer 20 are removed to form a target contact hole H1 that exposes a portion of the top surface of the gate 12. The remaining initial dielectric layer 20 constitutes the first dielectric layer 21, and the remaining dielectric material layer 221 constitutes the second dielectric layer 22.

[0115] like Figure 10As shown, in some embodiments, the gate 12 includes a first gate 121 extending along a first direction and a plurality of second gates 122 extending along a second direction and spaced apart along the first direction, the first direction being perpendicular to the second direction; the target contact hole H1 is located above the first gate 121, and one end of the second gate 122 near the target contact hole H1 is connected to the first gate 121; the target contact hole H1 is a strip-shaped contact hole extending along the first direction.

[0116] like Figure 11 As shown, in some embodiments, the gate 12 includes a plurality of gate layers 123 extending along a second direction and spaced apart along a first direction, the first direction being perpendicular to the second direction; a target contact hole H1 is located above one end of the gate layer 123 near the field oxide layer 11, and the target contact hole H1 is circular or polygonal. For example, the target contact hole H1 can be square or rectangular, thereby reducing the area of ​​the gate 12.

[0117] like Figure 12 and Figure 13 As shown, in step S90, a second connecting layer 32 and a second isolation groove G2 located within the second connecting layer 32 are formed. The second connecting layer 32 covers part of the top surface of the second dielectric layer 22 and fills the second connecting groove L2. The second isolation groove G2 is located at least between the first connecting groove L1 and the second connecting groove L2.

[0118] In some embodiments, the second interconnect layer 32 includes a third metal layer 321 and a fourth metal layer 322. For example, the third metal layer 321 and the fourth metal layer 322 are made of the same metal material, and the third metal layer 321 and the fourth metal layer 322 can be formed simultaneously based on a one-time deposition process.

[0119] In some embodiments, step S90, forming the second connection layer 32 and the second isolation trench G2 located in the second connection layer 32, includes the following steps S91 and S92.

[0120] Step S91: Form a second metal material layer (not shown). The second metal material layer covers the top surface of the second dielectric layer 22. The second metal material layer also fills the second connecting groove L2 and the target contact hole H1.

[0121] Step S92: Remove part of the second metal material layer to form the second isolation groove G2. The remaining second metal material layer constitutes the third metal layer 321 and the fourth metal layer 322 respectively. The third metal layer 321 and the fourth metal layer 322 are located on both sides of the second isolation groove G2. The third metal layer 321 is located at least in the second connecting groove L2, and the fourth metal layer 322 is located at least in the target contact hole H1.

[0122] like Figure 13As shown, in some embodiments, the second isolation groove G2 includes a first branch groove G11 and a second branch groove G22; the first branch groove G11 extends along a first direction and is located between the first connecting groove L1 and the second connecting groove L2, and the second branch groove G22 is located on one side of the opposite sidewall of the second connecting groove L2 along a second direction.

[0123] In the semiconductor structure fabrication method of the above embodiment, the first interconnect layer 31 and the first isolation trench G1 located within the first interconnect layer 31 are formed separately from the second interconnect layer 32 and the second isolation trench G2 located within the second interconnect layer 32. The first interconnect layer 31 covers a portion of the top surface of the initial dielectric layer 20, and the second interconnect layer 32 covers a portion of the top surface of the second dielectric layer 22. This reduces the area occupied by the first isolation trench G1, and allows for cell arrangement in the area below the first isolation trench G1, including the area below the second isolation layer. This increases the active area, resulting in higher current capability and switching efficiency, and improving the performance of the device chip.

[0124] Please see Figure 12 and Figure 13 According to some embodiments, this application also provides a semiconductor structure, the semiconductor structure including a substrate 10 and an epitaxial layer 101 located on the substrate, a first dielectric layer 21, a first interconnect layer 31 and a first isolation trench G1 located in the first interconnect layer 31, a second dielectric layer 22 and a target contact hole H1 penetrating the first dielectric layer 21 and the second dielectric layer 22, a second interconnect layer 32 and a second isolation trench G2 located in the second interconnect layer 32; the first dielectric layer 21 is located on the epitaxial layer 101, and the first dielectric layer 21 has a first isolation trench G1 penetrating to the top surface of the epitaxial layer 101. A first connecting groove L1 extends along a first direction; a first connecting layer 31 covers a portion of the top surface of the first dielectric layer 21 and fills the first connecting groove L1; a first isolation groove G1 extends along the first direction; the orthographic projection of the target contact hole H1 is located within the first isolation groove G1; the second dielectric layer 22 also has a second connecting groove L2 that exposes a portion of the top surface of the first connecting layer 31; the second connecting layer 32 covers a portion of the top surface of the second dielectric layer 22 and fills the second connecting groove L2; the second isolation groove G2 is located at least between the first connecting groove L1 and the second connecting groove L2.

[0125] In the semiconductor structure of the above embodiment, the first interconnect layer 31 covers part of the top surface of the initial dielectric layer 20, the second interconnect layer 32 covers part of the top surface of the second dielectric layer 22, and the second isolation trench G2 is located at least between the first interconnect trench L1 and the second interconnect trench L2. This can reduce the area occupied by the first isolation trench G1, and the area other than the area below the first isolation trench G1, including the area below the second isolation layer, can be arranged into cells, which is beneficial to increase the active area, thereby bringing higher current capability and switching efficiency, and improving the performance of the device chip.

[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and an epitaxial layer is formed on the substrate; An initial dielectric layer is formed on the epitaxial layer, and the initial dielectric layer has a first connection groove extending to the top surface of the epitaxial layer, the first connection groove extending along a first direction; A first connecting layer and a first isolation groove located within the first connecting layer are formed. The first connecting layer covers a portion of the top surface of the initial dielectric layer and fills the first connecting groove. The first isolation groove extends along the first direction. A portion of the initial dielectric layer is removed to form a first dielectric layer, and a second dielectric layer and a target contact hole penetrating the first dielectric layer and the second dielectric layer are formed. The orthographic projection of the target contact hole is located within the first isolation groove. The second dielectric layer also has a second connection groove that exposes a portion of the top surface of the first connection layer. A second connecting layer and a second isolation groove located within the second connecting layer are formed. The second connecting layer covers a portion of the top surface of the second dielectric layer and fills the second connecting groove. The second isolation groove is located at least between the first connecting groove and the second connecting groove.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming an initial dielectric layer on the epitaxial layer, the method further includes: A field oxide layer is formed on the epitaxial layer; A gate oxide layer is formed on the field oxide layer, the gate oxide layer covering the surface of the field oxide layer; A gate is formed on the epitaxial layer, the gate covering a portion of the top surface of the gate oxide layer and a portion of the top surface of the epitaxial layer; The formation of an initial dielectric layer on the epitaxial layer includes: An initial material layer is formed, which covers the top surface of the gate, the exposed top surface of the gate oxide layer, and the exposed top surface of the epitaxial layer; A portion of the initial material layer is removed to form the first connection groove, and the remaining initial material layer constitutes the initial dielectric layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The first connection layer includes a first metal layer and a second metal layer; The formation of the first connection layer and the first isolation trench located within the first connection layer includes: A first metal material layer is formed, which covers the top surface of the initial dielectric layer and fills the first connection groove. A portion of the first metal material layer is removed to form the first isolation trench, which is located above the field oxide layer. The remaining first metal material layer constitutes the first metal layer and the second metal layer, which are located on both sides of the first isolation trench. The first metal layer is located on the top surface of the initial dielectric layer, and the second metal layer is located at least within the first connecting trench.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The step of removing a portion of the initial dielectric layer to form a first dielectric layer, and forming a second dielectric layer and a target contact hole penetrating the first dielectric layer and the second dielectric layer includes: A dielectric material layer is formed, which covers the top surface of the initial dielectric layer, the top surface of the first metal layer, and the top surface of the second metal layer; Remove a portion of the dielectric material layer located on the top surface of the first metal layer to form a second connection groove that exposes a portion of the top surface of the first metal layer; A portion of the dielectric material layer and the initial dielectric layer are removed to form a target contact hole that exposes the top surface of the gate portion. The remaining initial dielectric layer constitutes the first dielectric layer, and the remaining dielectric material layer constitutes the second dielectric layer.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The second connection layer includes a third metal layer and a fourth metal layer, and the formation of the second connection layer and the second isolation trench located within the second connection layer includes: A second metal material layer is formed, which covers the top surface of the second dielectric layer and also fills the second connecting groove and the target contact hole. A portion of the second metal material layer is removed to form the second isolation groove. The remaining second metal material layer constitutes the third metal layer and the fourth metal layer, respectively. The third metal layer and the fourth metal layer are located on both sides of the second isolation groove. The third metal layer is located at least in the second connecting groove, and the fourth metal layer is located at least in the target contact hole.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The second isolation groove includes a first branch groove and a second branch groove; The first branch groove extends along the first direction and is located between the first connecting groove and the second connecting groove, and the second branch groove is located on one side of the opposite sidewall of the second connecting groove along the second direction.

7. The method for preparing a semiconductor structure according to claim 2, characterized in that, The gate includes a first gate extending along a first direction and a plurality of second gates extending along a second direction and spaced apart along the first direction, wherein the first direction is perpendicular to the second direction; The target contact hole is located above the first gate, and the end of the second gate near the target contact hole is connected to the first gate; The target contact hole is a strip-shaped contact hole extending along the first direction.

8. The method for preparing a semiconductor structure according to claim 2, characterized in that, The gate includes a plurality of gate layers extending along a second direction and spaced apart along a first direction, wherein the first direction is perpendicular to the second direction; The target contact hole is located above one end of the gate layer near the field oxide layer, and the target contact hole is circular or polygonal.

9. The method for preparing a semiconductor structure according to any one of claims 2-8, characterized in that, Includes at least one of the following features: The thickness of the field oxide layer is 1000 Å-20000 Å; The thickness of the gate is 0.2um-0.5um; The thickness of the first dielectric layer is 0.5um-1um.

10. A semiconductor structure, characterized in that, include: Substrate and epitaxial layer located on said substrate; A first dielectric layer is located on the epitaxial layer, and the first dielectric layer has a first connecting groove extending through to the top surface of the epitaxial layer, and the first connecting groove extends along a first direction. A first connecting layer and a first isolation groove located within the first connecting layer, wherein the first connecting layer covers a portion of the top surface of the first dielectric layer and fills the first connecting groove, and the first isolation groove extends along the first direction; The second dielectric layer and the target contact hole penetrating the first dielectric layer and the second dielectric layer, wherein the orthographic projection of the target contact hole is located in the first isolation groove, and the second dielectric layer also has a second connecting groove that exposes a portion of the top surface of the first connecting layer; A second connecting layer and a second isolation groove located within the second connecting layer, the second connecting layer covering a portion of the top surface of the second dielectric layer and filling the second connecting groove, the second isolation groove being located at least between the first connecting groove and the second connecting groove.

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