Back contact solar cell structure and manufacturing process thereof

Abstract

This invention relates to the field of photovoltaic cell technology, specifically disclosing a back-contact solar cell structure and its manufacturing process. It includes a silicon wafer with alternating textured and polished surfaces on its back side. A P-type doped region is formed on the textured surface. A tunneling oxide layer and intrinsic polycrystalline silicon are deposited across the entire surface of the P-type doped region and the polished surface. N-type doped regions are locally or entirely formed on the intrinsic polycrystalline silicon at corresponding positions on the polished surface. A semiconductor layer is formed on the intrinsic polycrystalline silicon and the N-type doped regions, and P-electrodes and N-electrodes are formed on the semiconductor layer. This invention uniquely utilizes back-side deposition of intrinsic polycrystalline silicon for simultaneous passivation of the P-type and N-type regions, offering advantages of a simple and low-cost process.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and specifically discloses a back-contact solar cell structure and its manufacturing process. Background Technology

[0002] Existing back-contact solar cells require two or more photolithography and etching processes to form P-type and N-type silicon, resulting in higher manufacturing costs compared to other technologies such as PERC or TopCon. Furthermore, TopCon and other manufacturing processes face numerous limitations when applied to existing production lines. TBC (TopCon back-contact) structures offer higher efficiency but require photolithography, masking, and etching processes to form N-type and P-type polycrystalline silicon layers and tunneling silicon oxide (SiO2). Additionally, laser processing is needed to control current leakage at the P-type and N-type contact sites.

[0003] In US patent application 2023 / 0307573A1, a tunneling oxide film and N-type polycrystalline silicon are applied to the N-type emitter based on a P-type silicon wafer, while the P-type BSF is formed through a sintering process using aluminum electrodes. This technology is only applicable to P-type silicon wafers, and using Al2O3 presents limitations when passivating the front and back surfaces. Furthermore, the P-electrode uses aluminum while the N-electrode still uses silver, thus presenting a challenge in terms of material cost control.

[0004] In view of the aforementioned shortcomings of existing back-contact solar cells, there is an urgent need to propose a solution for low-cost, high-efficiency back-contact solar cells, aiming to maximize the use of existing TopCon production line equipment and processes, and reduce manufacturing costs. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a back-contact solar cell structure and its manufacturing process.

[0006] On one hand, this invention discloses a back-contact solar cell structure, employing the following technical solution:

[0007] A back-contact solar cell structure and its manufacturing process include: a silicon wafer, the back of which is alternately provided with a textured surface and a polished surface, a P-type doped region is formed on the textured surface, a tunneling oxide layer and intrinsic polycrystalline silicon are deposited on the P-type doped region and the polished surface, an N-type doped region is formed locally or entirely on the intrinsic polycrystalline silicon at a position corresponding to the polished surface, a semiconductor layer is formed on the intrinsic polycrystalline silicon and the N-type doped region, and a P-electrode and an N-electrode are formed on the semiconductor layer.

[0008] Preferably, the N electrode is in direct contact with the semiconductor layer on the N-type doped region, and the P electrode is in contact with the semiconductor layer on the P-type doped region and / or with the P-type doped region.

[0009] Preferably, the N electrode and / or P electrode is formed from aluminum paste, wherein the silicon content in the aluminum paste is 0-20 wt%.

[0010] Preferably, the thickness of the tunneling oxide layer is 1-2 nm, the thickness of the intrinsic polycrystalline silicon is 50-300 nm, and the thickness of the semiconductor layer is 60-100 nm.

[0011] Preferably, the semiconductor layer is made of one or more layers of TiO2, WO3, MoO3, TeO2, NiO or TiN, and the semiconductor layer contains dopants with a dopant content of 0-5 wt%. The dopants include one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N), and oxygen (O).

[0012] Preferably, an Al2O3 layer and an anti-reflective coating are sequentially formed on the front side of the silicon wafer.

[0013] Preferably, the thickness of the Al2O3 layer is 6–10 nm, and the anti-reflective coating is SiN. x or SiN x / SiO x The multilayer film consists of SiN, wherein the thickness of the antireflective coating is SiN. x 15-90nm or SiN x / SiO x 15~60nm / 30~100nm.

[0014] On the other hand, this invention discloses a manufacturing process for a back-contact solar cell structure, employing the following technical solution:

[0015] A manufacturing process for a back-contact solar cell structure includes the following steps:

[0016] S1. Forming a P-type doped region: The back of the silicon wafer is texturized to form a texturized surface, and boron doping diffusion is performed on the texturized surface to form a P-type doped region;

[0017] S2. Localized polishing surface formation: A polishing surface is formed by localized laser and wet etching on the P-type doped region, exposing part of the back side of the silicon wafer;

[0018] S3. Formation of tunneling oxide layer and intrinsic polysilicon: Deposit tunneling oxide layer and intrinsic polysilicon across the entire surface of the P-type doped region and polished surface;

[0019] S4. Forming an N-type doped region: Phosphorus-containing paste is used to print locally or entirely on the polished surface of the intrinsic polysilicon to form an N-type doped region; the printed paste is heat-treated after drying to allow the phosphorus in the paste to diffuse into the intrinsic polysilicon to form phosphorus-doped polysilicon.

[0020] S5. Forming a semiconductor layer: Remove the oxide film and slurry residue from the surface, and then deposit a semiconductor layer locally or over the entire surface on the intrinsic polysilicon and N-type doped region.

[0021] S6. Printing paste and sintering to form electrodes: Printing paste on the semiconductor layer and sintering to form P electrodes and N electrodes, wherein the N electrode is in direct contact with the semiconductor layer on the N-type doped region, and the P electrode is in contact with the semiconductor layer on the P-type doped region or / and with the P-type doped region.

[0022] Preferably, in S1, the boron doping concentration of the P-type doped region is 1E19 / cm3;

[0023] Preferably, in step S2, localized laser lasing is performed on the p-type doped region to remove BSG and boron doping. The laser pulse duration ranges from picoseconds to continuous wave, and the laser energy density is 0.5 J / cm². 2 ~10J / cm 2 Within the range; then wet etching is performed using an alkaline solution at a temperature above 45°C to remove laser loss and boron doping from the laser-treated area; a polished surface is formed by localized laser and wet etching, exposing part of the silicon wafer, and the exposed part has a flat surface morphology.

[0024] Preferably, in step S3, the tunneling oxide layer is formed by LPCVD, wet process or thermal diffusion process, and the intrinsic polycrystalline silicon is formed by LPCVD, APCVD, PVD or PECVD process.

[0025] Preferably, in step S4, the phosphorus content in the phosphate slurry is 1E19 / cm³. 3 ~1E21 / cm 3 After drying, the printing paste is placed in a diffusion furnace for heat treatment. The diffusion temperature is between 840 and 920°C, and nitrogen or oxygen-containing nitrogen is used as the gas.

[0026] Preferably, in step S5, after annealing, the oxide film and slurry residue on the surface are removed by wet etching. Then, Al2O3 and an anti-reflective coating are deposited on the front side of the silicon wafer by ALD process. On the back side, a semiconductor layer is deposited by PVD, PECVD, APCVD, LPCVD or ALD process. During deposition, hydrogen and NH3 are used for hydrogenation treatment.

[0027] Preferably, in step S6, the slurry is an aluminum slurry with a silicon content of 0-20 wt% and a sintering temperature between 860-920°C.

[0028] Preferably, in step S6, a local laser is used to form a contact hole connecting the P-type doped region on the deposited tunneling oxide layer and the intrinsic polysilicon, and then a printing paste is sintered to form a P electrode, wherein the P electrode is in contact with the P-type doped region.

[0029] Compared with the prior art, the present invention has at least the following beneficial effects:

[0030] 1. Simultaneous passivation of polysilicon in P-type and N-type doped regions: This invention uniquely utilizes back-side deposition of intrinsic polysilicon for simultaneous passivation of P-type and N-type regions. The tunneling oxide layer and intrinsic polysilicon form an integral whole in the P-type and N-type doped regions. The intrinsic polysilicon exists on the P-type doped region, while the intrinsic polysilicon in the N-type doped region is selectively doped with phosphorus to form phosphorus-doped polysilicon, thus bypassing the traditional AlO2 passivation method. x The process does not require additional patterning on the P-type area, and passivation can be formed on both P-type and N-type areas, thus offering the advantages of a simple and low-cost process.

[0031] 2. By first forming a P-type doped region on the texturing surface and then forming an N-type doped region on the etched polished surface, and then covering the entire surface with the intrinsic polysilicon through a tunneling oxide layer, the N-type doped region and the P-type doped region have good vertical isolation, resulting in a longer leakage current path. This means that by increasing the length of the leakage current path, the current leakage caused by the contact between the P-type and N-type doped regions can be better eliminated, and the pseudo capacitance fill factor (pFF) can be improved.

[0032] 3. Use low-cost metal electrodes: Based on the traditional electrode sintering process, a semiconductor layer is formed on polycrystalline silicon. Since the semiconductor layer can prevent Al from diffusing into the polycrystalline silicon and has good contact resistance with Al, low-cost aluminum electrodes can be used to replace traditional silver electrodes, and both P-type and N-type electrodes can be replaced with aluminum.

[0033] 4. Reduce the thickness of polysilicon: By depositing a semiconductor layer on polysilicon, the N electrode contacts the semiconductor layer instead of the polysilicon layer. Compared with the traditional metal electrode directly contacting the polysilicon, this invention can reduce the thickness of polysilicon while ensuring that metal diffusion is avoided.

[0034] 5. Simplified manufacturing process: Simplify the complex manufacturing process of traditional TBC structure back contact solar cells, reduce manufacturing costs, and maximize the use of TopCon production line equipment and process sequence so that existing TopCon production lines can be converted into back contact solar cell production lines in the future. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the overall structure of the back-contact solar cell structure in Example 1;

[0036] Figure 2 This is a schematic diagram of steps S1-S2 of the manufacturing process of the back contact solar cell structure in Example 1;

[0037] Figure 3 This is a schematic diagram of step S3 in the manufacturing process of the back contact solar cell structure of Example 1;

[0038] Figure 4 This is a schematic diagram of step S4 in the manufacturing process of the back contact solar cell structure of Example 1;

[0039] Figure 5 This is a schematic diagram of step S5 in the manufacturing process of the back contact solar cell structure of Example 1;

[0040] Figure 6 This is a schematic diagram of step S6 in the manufacturing process of the back contact solar cell structure of Example 1;

[0041] Figure 7 The following is a flowchart of the manufacturing process steps of the back contact solar cell structure in Example 1: (a) is the process flow diagram of the present invention, and (b) is the existing TopCon process flow.

[0042] Figure 8 This is a comparison chart of the open-circuit voltages of different materials in the back-contact solar cell structure of Example 1;

[0043] Figure 9 This is a schematic diagram of step S6 in the manufacturing process of the back contact solar cell structure of Example 4;

[0044] Figure 10 The chart shows a performance comparison between Example 1 and Example 4.

[0045] Explanation of icon numbers:

[0046] 1. Anti-reflective coating; 2. Al2O3; 3. P-type boron-doped region; 4. Tunneling oxide layer; 5. N-type doped region; 6. Intrinsic polysilicon; 7. Semiconductor layer; 8. Metal electrode; 9. Phosphate paste. Detailed Implementation

[0047] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] Example 1

[0049] In this embodiment, refer to Figure 1 The back-contact solar cell structure includes: a silicon wafer, on the back of which are alternately textured and polished surfaces. A P-type doped region 3 is formed on the textured surface. A tunneling oxide layer 4 and intrinsic polycrystalline silicon 6 are deposited on the entire surface of the P-type doped region 3 and the polished surface. An N-type doped region 5 is locally formed on the intrinsic polycrystalline silicon 6 at the corresponding position on the polished surface. A semiconductor layer 7 is formed on the intrinsic polycrystalline silicon 6 and the N-type doped region 5. Metal electrodes 8, namely P-electrodes and N-electrodes, are formed on the semiconductor layer.

[0050] In this embodiment, refer to Figure 2-6 The manufacturing process of the back-contact solar cell structure includes the following steps:

[0051] S1. Formation of P-type doped region: The back of the silicon wafer is texturized, and then boron doping diffusion is performed on the texturized silicon wafer using a conventional diffusion furnace, with a boron doping concentration of 1E19 / cm³. 3 This forms a P-type doped region, and the surface morphology of the P-type doped region is textured.

[0052] S2. Localized Polishing Surface Formation: Localized BSG and boron doping on the back of the silicon wafer are removed using a green laser (wavelength 532nm), with a pulse duration of 10nsec and a laser energy density of 1.5J / cm². 2 Next, wet etching is performed using an alkaline solution at temperatures above 45°C to remove laser loss from the laser-treated areas and boron doping on the front side. Localized laser and wet etching create a polished surface, exposing the back side of the silicon wafer. The exposed surface is flat, unlike the textured surface of the P-type doped region. (See...) Figure 2 ;

[0053] S3. Formation of Tunneling Oxide and Intrinsic Polysilicon: A tunneling oxide layer and intrinsic polysilicon are simultaneously formed using LPCVD, covering both the textured and planar regions. The tunneling oxide layer is approximately 1.2 nm thick, and the intrinsic polysilicon is approximately 50 nm thick. Besides LPCVD, other deposition processes such as APCVD, PVD, and PECVD can also be used to form intrinsic polysilicon. The tunneling oxide layer can also be formed using wet methods or other thermal diffusion processes. See [link to relevant documentation]. Figure 3 ;

[0054] S4. Formation of N-type doped regions: An N-type doped region is formed by printing a phosphorus-containing paste onto intrinsic polycrystalline silicon. The phosphorus content in the phosphorus paste is approximately 1E20 / cm³. 3The width of the printed area is smaller than the width of the laser-etched area (i.e., the width of the polished surface), leaving intrinsic polysilicon as a barrier between the N-type doped region and the P-type doped region to prevent contact with the P-type doped region. After drying, the printing paste is placed in a diffusion furnace for heat treatment at a diffusion temperature of 920°C. Nitrogen or oxygen-containing nitrogen gas is used to diffuse phosphorus in the paste into the intrinsic polysilicon, forming phosphorus-doped polysilicon. See [link to relevant documentation]. Figure 4 ;

[0055] S5. Forming the semiconductor layer: After annealing, the surface oxide film and slurry residue are removed by wet etching. Subsequently, Al2O3 and an anti-reflective coating are deposited on the front side of the silicon wafer using the ALD process. The Al2O3 layer has a deposition thickness of 8 nm, and the anti-reflective coating is SiN. x The anti-reflective coating is 90 nm thick; a semiconductor layer is deposited on the back side, the semiconductor layer material is TiO2, the semiconductor layer thickness is 60 nm, and the deposition process is LPCVD, but PVD, PECVD, APCVD, or ALD can also be used. During deposition, hydrogen and NH3 are used for hydrogenation treatment, see [link to details]. Figure 5 ;

[0056] S6. Electrode Formation by Printing and Sintering the Printed Paste: P-electrodes and N-electrodes are formed by printing and sintering the printed paste on the semiconductor layer. The N-electrode is in direct contact with the semiconductor layer on the N-type doped region, and the P-electrode is in contact with the semiconductor layer on the P-type doped region. The paste is aluminum paste with a silicon content of 0 wt%, and the sintering temperature is 920℃. See [link / details]. Figure 6 .

[0057] This invention forms a P-type doped region on a textured surface, which effectively reduces reflectivity under light irradiation and improves its duplexity. Furthermore, due to its larger surface area, the textured surface more easily establishes a larger contact area with the electrode. This differs from existing methods that directly passivate P-type polycrystalline silicon (approximately 1E20 / cm²) on polycrystalline silicon. 3 The boron doping concentration in the P-type doped region of this invention is even lower (approximately 1E19 / cm). 3 This helps reduce leakage current.

[0058] On the textured side, a recessed flat surface is formed by laser wet etching, and then a tunneling oxide layer and intrinsic polysilicon are deposited to form a local N-type doped region. This special structure enables better vertical isolation between the P-type doped region and the N-type doped region. The tunneling oxide layer and intrinsic polysilicon improve the leakage current path between the P-type doped region and the N-type doped region, thereby better controlling the leakage circuit.

[0059] Figure 7The process flow of the technology proposed in this invention is shown. The advantage of this invention is that it is similar to the process equipment and flow of existing TopCon production lines, making future upgrades to back-contact solar cell production lines very easy and requiring no additional processes. Furthermore, because existing production lines can be directly utilized, there is no need to expand the equipment area of ​​the production line. In addition, since aluminum can be used as the electrode material for both P-type and N-type doped regions, the cost reduction of electrode materials is very significant compared to PERC (using aluminum only on the back) or TopCon (using silver on both the front and back).

[0060] Figure 8 The present invention demonstrates the passivation characteristics of intrinsic polycrystalline silicon on a silicon wafer. The P-type region is formed using existing processes via boron diffusion within the silicon wafer, while the N-type region utilizes a tunneling oxide layer and intrinsic polycrystalline silicon passivation contacts. In particular, the passivation of the P-type region can bypass AlO₂ by using intrinsic polycrystalline silicon. x As shown in the figure, intrinsic polycrystalline silicon exhibits excellent passivation properties similar to Al2O3, and even better than SiN. x The passivation quality is inherently higher. This indicates that grain boundaries present in polycrystalline silicon can easily contain a large amount of hydrogen to effectively passivate defects at the interface between intrinsic polycrystalline silicon and the wafer.

[0061] Example 2

[0062] The difference from Example 1 is that in S5, a semiconductor layer 7 is formed on the back side by deposition, and the material of the semiconductor layer 7 is WO3.

[0063] Example 3

[0064] The difference from Example 1 is that in S5, a semiconductor layer 7 is formed on the back side by deposition. The semiconductor layer 7 is a double layer, consisting of a first semiconductor layer and a second semiconductor layer sequentially from the silicon wafer outwards. In S5, the first semiconductor layer is first deposited on the back side. The material of the first semiconductor layer is TiO2, and the deposition thickness of the first semiconductor layer is 50 nm. Then, the second semiconductor layer is deposited on the first semiconductor layer. The material of the second semiconductor layer is WO3, and the deposition thickness of the second semiconductor layer is 40 nm.

[0065] Example 4

[0066] The difference from Example 1 is that, see Figure 9 In step S6, prior to the metallization process, localized laser processing is used to form contact holes connecting the P-type doped regions on the deposited tunneling oxide layer and the intrinsic polysilicon. The laser wavelength is 355 nm, the pulse duration is 10 psec, and the energy density ranges from 0.3 to 1.0 J / cm². 2The energy density can be adjusted according to the surface structure and its reflectivity. In other embodiments, it can also be formed by other lasers, such as green lasers with nanosecond pulse durations. After forming contact holes by localized laser, aluminum paste is printed and sintered to form a P-electrode, which contacts the P-type doped region 3.

[0067] Unlike Example 1, where the metal electrode 8 is in contact with the semiconductor layer 7, in Example 4, the metal electrode 8 is in direct contact with the P-type doped region 3. During sintering, the aluminum metal electrode reacts with silicon, forming aluminum-doped silicon (P-type doping) in the contact area. Figure 10 This improves contact characteristics and reduces contact resistance while ensuring that the control line resistance is not too high.

[0068] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A back-contact solar cell structure, characterized in that, include: A silicon wafer, wherein a textured surface and a polished surface are alternately provided on the back side of the silicon wafer, a P-type doped region is formed on the textured surface, a tunneling oxide layer and intrinsic polysilicon are deposited on the entire surface of the P-type doped region and the polished surface, an N-type doped region is formed locally or entirely on the intrinsic polysilicon at the position corresponding to the polished surface, a semiconductor layer is formed on the intrinsic polysilicon and the N-type doped region, and a P electrode and an N electrode are formed on the semiconductor layer; The semiconductor layer is made of one or more layers of TiO2, WO3, MoO3, TeO2, NiO or TiN. The semiconductor layer contains dopants with a dopant content of 0-5 wt%. The dopants include one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N) and oxygen (O).

2. The back-contact solar cell structure according to claim 1, characterized in that, The N electrode is in direct contact with the semiconductor layer on the N-type doped region, and the P electrode is in contact with the semiconductor layer on the P-type doped region and / or with the P-type doped region.

3. The back-contact solar cell structure according to claim 1, characterized in that, The N electrode and / or P electrode are formed from aluminum paste, and the silicon content in the aluminum paste is 0~20wt%.

4. The back-contact solar cell structure according to claim 1, characterized in that, The thickness of the tunneling oxide layer is 1~2nm, the thickness of the intrinsic polycrystalline silicon is 50~300nm, and the thickness of the semiconductor layer is 60~100nm.

5. The back-contact solar cell structure according to claim 1, characterized in that, An Al2O3 layer and an anti-reflective coating are sequentially formed on the front side of the silicon wafer.

6. The back-contact solar cell structure according to claim 5, characterized in that, The thickness of the Al203 layer is 6-10 nm, and the anti-reflection coating is SiN x or SiN x / SiO x multilayer film composed of SiN x of 15-90 nm or SiN x / SiO x of 15-60 nm / 30-100 nm.

7. A manufacturing process for a back-contact solar cell structure according to any one of claims 1-6, characterized in that, Includes the following steps: S1. Forming a P-type doped region: The back of the silicon wafer is texturized to form a texturized surface, and boron doping diffusion is performed on the texturized surface to form a P-type doped region; S2. Localized polishing surface formation: A polishing surface is formed by localized laser and wet etching on the P-type doped region, exposing part of the back side of the silicon wafer; S3. Formation of tunneling oxide layer and intrinsic polysilicon: Deposit tunneling oxide layer and intrinsic polysilicon across the entire surface of the P-type doped region and polished surface; S4. Forming an N-type doped region: Phosphorus-containing paste is used to print locally or entirely on the polished surface of the intrinsic polysilicon to form an N-type doped region. After drying, the printing paste undergoes heat treatment, causing the phosphorus in the paste to diffuse into the intrinsic polycrystalline silicon to form phosphorus-doped polycrystalline silicon. S5. Forming a semiconductor layer: Remove the oxide film and slurry residue from the surface, and then deposit a semiconductor layer locally or over the entire surface on the intrinsic polysilicon and N-type doped region. S6. Printing paste and sintering to form electrodes: Printing paste on the semiconductor layer and sintering to form P electrodes and N electrodes, wherein the N electrode is in direct contact with the semiconductor layer on the N-type doped region, and the P electrode is in contact with the semiconductor layer on the P-type doped region or / and with the P-type doped region.

8. The manufacturing process of a back-contact solar cell structure according to claim 7, characterized in that, In S1, the boron doping concentration of the P-type doped region is 1E19 / cm³. 3 ; In step S2, localized laser lithography is performed on the P-type doped region to remove BSG and boron doping. The laser pulse duration ranges from picoseconds to continuous waves, and the laser energy density is 0.5 J / cm². 2 ~10J / cm 2 Within the range; then wet etching is performed using an alkaline solution at a temperature above 45°C to remove laser loss and boron doping from the laser-treated area; a polished surface is formed by localized laser and wet etching, exposing part of the silicon wafer, and the exposed part has a flat surface morphology. In S3, the tunneling oxide layer is formed by LPCVD, wet process or thermal diffusion process, and the intrinsic polycrystalline silicon is formed by LPCVD, APCVD, PVD or PECVD process. In step S4, the phosphorus content in the phosphate slurry is 1E19 / cm³. 3 ~1E21 / cm 3 After drying, the printing paste is placed in a diffusion furnace for heat treatment. The diffusion temperature is between 840 and 920°C, and nitrogen or oxygen-containing nitrogen is used as the gas. In S5, after annealing, the oxide film and slurry residue on the surface are removed by wet etching, and then Al2O3 and an anti-reflection coating are deposited on the front side of the silicon wafer by ALD process. A semiconductor layer is deposited on the back side using PVD, PECVD, APCVD, LPCVD or ALD processes. During deposition, hydrogen and NH3 are used for hydrogenation treatment. In step S6, the slurry is an aluminum slurry with a silicon content of 0-20 wt% and a sintering temperature between 860-920°C.

9. The manufacturing process of a back-contact solar cell structure according to claim 8, characterized in that, In step S6, a local laser is used to form a contact hole connecting the P-type doped region on the deposited tunneling oxide layer and the intrinsic polysilicon, and then a printing paste is sintered to form a P electrode, which is in contact with the P-type doped region.

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