Flip chip silver mirror light emitting diode chip and method of manufacturing the same

Abstract

The application discloses a flip silver mirror light emitting diode chip and a preparation method thereof, and relates to the technical field of semiconductors. The flip silver mirror light emitting diode chip comprises a substrate, an epitaxial layer, a current expansion layer, a Bragg reflection layer, a metal reflection layer, a first insulating layer, a P-type metal conductive layer and an N-type metal conductive layer. The epitaxial layer comprises an N-type semiconductor layer, an active light emitting layer and a P-type semiconductor layer. The Bragg reflection layer is provided with a Bragg reflection layer P-type through hole, and the first insulating layer is provided with a first insulating layer P-type through hole. The included angle beta between the hole wall of the first insulating layer P-type through hole and the horizontal plane is smaller than the included angle alpha between the hole wall of the Bragg reflection layer P-type through hole and the horizontal plane. The distance L between the projection edge of the first insulating layer P-type through hole and the projection edge of the Bragg reflection layer P-type through hole is 5-12 mu m. The flip silver mirror light emitting diode chip is improved in structure, and the ability of the flip silver mirror light emitting diode chip to resist large current is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a flip-chip silver mirror light-emitting diode chip and its fabrication method. Background Technology

[0002] In the field of semiconductor lighting technology, flip-chip light-emitting diodes (LEDs) have attracted much attention due to their unique structural design and performance advantages. Their back-emitting light characteristic optimizes the light output path and improves light extraction efficiency; excellent heat dissipation effectively reduces the chip's operating temperature, ensuring stable device operation; good solderability, high thrust, and high reliability enable them to exhibit outstanding adaptability and stability in the assembly and long-term use of various electronic devices, thus leading to their widespread application in numerous fields.

[0003] However, with the continuous development and improvement of LED chip technology, flip-chip LEDs are gradually being applied to scenarios with higher power and current requirements, such as automotive lighting and stage lighting. In high-power, high-current operating environments, the chips face more stringent electrical performance tests. How to effectively improve the ability of flip-chip LEDs to withstand high currents has become a key technical problem that urgently needs to be solved, and it is also the core challenge for further expanding the application of flip-chip LEDs in more demanding scenarios. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a flip-chip silver mirror light-emitting diode chip that can improve the flip-chip silver mirror light-emitting diode chip's ability to withstand high current.

[0005] The technical problem to be solved by the present invention is to provide a method for preparing a flip-chip silver mirror light-emitting diode chip, which is used to prepare the above-mentioned flip-chip silver mirror light-emitting diode chip and improve the flip-chip silver mirror light-emitting diode chip's ability to withstand high current.

[0006] To solve the above-mentioned technical problems, the present invention provides a flip-chip silver mirror light-emitting diode chip, comprising a substrate, an epitaxial layer, a Bragg reflector layer, a metal reflector layer, a first insulating layer, a P-type metal conductive layer and an N-type metal conductive layer;

[0007] The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially stacked on the substrate;

[0008] The Bragg reflector layer is stacked on top of the P-type semiconductor layer, and the Bragg reflector layer has a P-type via; the metal reflector layer covers the surface of the Bragg reflector layer, and the metal reflector layer passes through the P-type via and is electrically connected to the current spreading layer.

[0009] The first insulating layer is stacked on top of the metal reflective layer. The first insulating layer has a first insulating layer P-type through hole, and one end of the first insulating layer P-type through hole extends to the metal reflective layer.

[0010] The P-type metal conductive layer and the N-type metal conductive layer are spatially separated. The P-type metal conductive layer is stacked on top of the first insulating layer and is electrically connected to the metal reflective layer through the P-type via of the first insulating layer. The N-type metal conductive layer is electrically connected to the Nth type semiconductor layer.

[0011] The angle β between the hole wall of the first insulating layer P-type through hole and the horizontal plane is smaller than the angle α between the hole wall of the Bragg reflector layer P-type through hole and the horizontal plane;

[0012] The distance L between the projected edge of the P-type via in the first insulating layer and the projected edge of the P-type via in the Bragg reflector layer is 5 μm to 12 μm.

[0013] As an improvement to the above technical solution, the distance L between the projected edge of the P-type through hole in the first insulating layer and the projected edge of the P-type through hole in the Bragg reflector layer is 5μm to 8μm.

[0014] As an improvement to the above technical solution, the difference between the angle β between the hole wall of the first insulating layer P-type through hole and the horizontal plane and the angle α between the hole wall of the Bragg reflector layer P-type through hole and the horizontal plane is ≤20°.

[0015] As an improvement to the above technical solution, the included angle β between the hole wall of the first insulating layer P-type through hole and the horizontal plane is 15° to 20°.

[0016] As an improvement to the above technical solution, the angle α between the hole wall of the P-type through hole in the Bragg reflector layer and the horizontal plane is 25° to 40°.

[0017] As an improvement to the above technical solution, the flip-chip silver mirror light-emitting diode chip further includes a current spreading layer and a current blocking layer;

[0018] The N-type semiconductor layer is stacked on the surface of the substrate. The N-type semiconductor layer includes a first N-type semiconductor portion and a second N-type semiconductor portion that are interconnected. The P-type semiconductor layer and the active light-emitting layer are stacked on top of the first N-type semiconductor portion in sequence. The current spreading layer covers the surface of the P-type semiconductor layer, so that the current spreading layer and the P-type semiconductor layer are electrically connected.

[0019] The current blocking layer covers the surface of the current spreading layer and the second N-type semiconductor, and the Bragg reflector layer covers the surface of the current blocking layer;

[0020] The current blocking layer is provided with a P-type through hole, one end of which is connected to the P-type through hole of the Bragg reflector layer, and the other end extends to the current spreading layer.

[0021] The metal reflective layer is located above the current spreading layer. The metal reflective layer has a protrusion on the side near the substrate. The protrusion sequentially fills the P-type via of the Bragg reflective layer and the P-type via of the current blocking layer, and the end of the protrusion contacts the current spreading layer, so that the metal reflective layer and the current spreading layer are electrically connected.

[0022] As an improvement to the above technical solution, the Bragg reflector layer includes a first Bragg reflector portion and a second Bragg reflector portion connected to each other. The first Bragg reflector portion and the second Bragg reflector portion respectively cover the surface of the current blocking layer, and the first Bragg reflector portion is located above the P-type semiconductor layer, and the second Bragg reflector portion is located above the second N-type semiconductor layer. The first Bragg reflector portion is provided with a P-type via of the Bragg reflector layer; the second Bragg reflector portion is provided with an N-type via of the Bragg reflector layer, and one end of the N-type via of the Bragg reflector layer extends to the current blocking layer.

[0023] The first insulating layer includes a first insulating layer A portion and a first insulating layer B portion that are connected to each other. The first insulating layer A portion is stacked on top of the metal reflective layer, and the first insulating layer B portion is stacked on top of the second Bragg reflective portion. The first insulating layer P-type through hole is located inside the first insulating layer A portion, and the first insulating layer B portion is provided with a first insulating layer N-type through hole, which is located inside the Bragg reflective layer N-type through hole.

[0024] The current blocking layer is further provided with an N-type through-hole of the current blocking layer, one end of which is connected to the N-type through-hole of the first insulating layer, and the other end extends to the second N-type semiconductor part;

[0025] The P-type metal conductive layer and the N-type metal conductive layer are spatially separated. The P-type metal conductive layer covers the surface of the first insulating layer A portion, and the N-type metal conductive layer covers the surface of the first insulating layer B portion and sequentially fills the first insulating layer N-type via and the current blocking layer N-type via until it contacts the second N-type semiconductor portion.

[0026] As an improvement to the above technical solution, the flip-chip silver mirror light-emitting diode chip further includes a second insulating layer. The second insulating layer covers the surface of the P-type metal conductive layer, the N-type metal conductive layer and the exposed first insulating layer. The second insulating layer is provided with a second insulating layer P-type through hole and a second insulating layer N-type through hole. One end of the second insulating layer P-type through hole extends to the P-type metal conductive layer, and one end of the second insulating layer N-type through hole extends to the N-type metal conductive layer.

[0027] Accordingly, the present invention also provides a method for fabricating a flip-chip silver mirror light-emitting diode chip, which is used to fabricate the above-mentioned flip-chip silver mirror light-emitting diode chip, comprising the following steps:

[0028] (1) Provide a substrate, and deposit an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer sequentially on the substrate to obtain an epitaxial layer;

[0029] (2) Remove the P-type semiconductor layer and the corresponding active light-emitting layer in the specified area to expose part of the N-type semiconductor layer. The exposed N-type semiconductor layer is the second N-type semiconductor part.

[0030] (3) Deposit indium tin oxide on the surface of the P-type semiconductor layer to form a current spreading layer on the surface of the P-type semiconductor layer;

[0031] (4) SiO is deposited on the surface of the P-type semiconductor layer, the current spreading layer and the second N-type semiconductor layer to form a current blocking layer;

[0032] (5) A stack of TiO and SiO layers is sequentially deposited on the surface of the current blocking layer to form a Bragg reflection layer;

[0033] (6) Open P-type through holes and N-type through holes of the Bragg reflector at designated locations in the Bragg reflector;

[0034] (7) Open P-type through holes and N-type through holes of the current blocking layer at the designated positions of the current blocking layer;

[0035] (8) A metal reflective layer is grown above a specified location of the Bragg reflective layer, and the metal reflective layer fills the P-type via of the Bragg reflective layer and the P-type via of the current blocking layer.

[0036] (9) Deposit SiO on the metal reflective layer to form a first insulating layer; open a first insulating layer P-type via and a first insulating layer N-type via at a designated position in the first insulating layer;

[0037] (10) A P-type metal conductive layer and an N-type metal conductive layer are formed at designated locations in the first insulating layer, respectively.

[0038] As an improvement to the above technical solution, in step (6), the method of opening P-type through holes and N-type through holes of the Bragg reflector at designated locations of the Bragg reflector includes the following steps:

[0039] A third photoresist is coated on the surface of the Bragg reflector layer. The third photoresist at a designated location on the Bragg reflector layer is removed, and then the exposed Bragg reflector layer is removed to form P-type vias and N-type vias of the Bragg reflector layer. The current blocking layer below the P-type vias and N-type vias of the Bragg reflector layer is exposed, and then the third photoresist is removed. The thickness of the third photoresist is 1.5 μm to 2 μm.

[0040] In step (9), the method of opening a P-type via and an N-type via of the first insulating layer at a designated location of the first insulating layer includes the following steps: coating a sixth photoresist on the surface of the first insulating layer, removing the sixth photoresist at a designated location to expose part of the first insulating layer, and then using a second BOE etching solution to remove the exposed first insulating layer to form a P-type via and an N-type via of the first insulating layer, and removing the sixth photoresist;

[0041] The second BOE etching solution consists of hydrofluoric acid, ammonium fluoride and water, and the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 15:1 to 20:1.

[0042] Implementing this invention has the following beneficial effects: By controlling the angle β between the hole wall of the first insulating layer P-type through hole and the horizontal plane to be smaller than the angle α between the hole wall of the Bragg reflector P-type through hole and the horizontal plane, and by controlling the distance L between the projected edge of the first insulating layer P-type through hole on the horizontal plane and the projected edge of the Bragg reflector P-type through hole on the horizontal plane to be 5μm to 12μm, this invention can significantly improve the flip-chip silver mirror light-emitting diode chip's ability to withstand high current, thereby effectively extending the service life of the flip-chip silver mirror light-emitting diode chip under high current operating conditions. This allows the chip of this invention to be applied to scenarios with high power and current requirements, such as automotive lights and stage lights. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of the flip-chip silver mirror light-emitting diode chip in Embodiment 1 of the present invention;

[0044] Figure 2 This is a partially enlarged schematic diagram of the flip-chip silver mirror light-emitting diode chip according to Embodiment 1 of the present invention;

[0045] Figure 3 yes Figure 2 A magnified view of a portion of the image;

[0046] The structure includes: substrate 10, epitaxial layer 11, current spreading layer 12, current blocking layer 13, Bragg reflector layer 14, metal reflector layer 15, first insulating layer 16, P-type metal conductive layer 171, N-type metal conductive layer 172, second insulating layer 18, N-type semiconductor layer 111, active light emitting layer 112, P-type semiconductor layer 113, first N-type semiconductor portion 1111, second N-type semiconductor portion 1112, current blocking layer P-type via 131, current blocking layer N-type via 132, protrusion 151, first Bragg reflector portion 141, second Bragg reflector portion 142, Bragg reflector layer P-type via 1411, Bragg reflector layer N-type via 1421, first insulating layer P-type via 1611, first insulating layer N-type via 1621, second insulating layer P-type via 181, and second insulating layer N-type via 182. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the present invention.

[0048] Where specific techniques or conditions are not specified in the embodiments, they shall be performed in accordance with the techniques or conditions described in the literature in this field or in accordance with the product instructions. Raw materials whose manufacturers are not specified are all conventional products that can be obtained commercially.

[0049] like Figure 1 and Figure 2 As shown, this embodiment discloses a flip-chip silver mirror light-emitting diode chip, including a substrate 10, an epitaxial layer 11, a current spreading layer 12, a Bragg reflector layer 14, a metal reflector layer 15, a first insulating layer 16, a P-type metal conductive layer 171, and an N-type metal conductive layer 172; the epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113;

[0050] The N-type semiconductor layer 111 is stacked on the surface of the substrate 10. The N-type semiconductor layer 111 includes a first N-type semiconductor portion 1111 and a second N-type semiconductor portion 1112 that are connected to each other. The P-type semiconductor layer 113 and the active light-emitting layer 112 are stacked on top of the first N-type semiconductor portion 1111 from top to bottom. The current spreading layer 12 covers the surface of the P-type semiconductor layer 113, so that the current spreading layer 12 and the P-type semiconductor layer 113 are electrically connected.

[0051] The Bragg reflector layer 14 is stacked above the P-type semiconductor layer 113 and the second N-type semiconductor portion 1112, and the Bragg reflector layer 14 is provided with a Bragg reflector layer P-type via 1411 that runs from top to bottom through the Bragg reflector layer 14;

[0052] The metal reflective layer 15 covers the surface of the Bragg reflective layer 14 and fills the P-type via 1411 of the Bragg reflective layer, and the metal reflective layer 15 is electrically connected to the current spreading layer 12; by setting the Bragg reflective layer 14 on the surface of the metal reflective layer 14, the luminous efficiency of the chip can be improved through the synergistic effect of optical interference principle and material properties, thereby optimizing the optical performance of the chip.

[0053] The first insulating layer 16 is stacked on top of the metal reflective layer 15 and the second N-type semiconductor portion 1112. The first insulating layer 16 is provided with a first insulating layer P-type via 1611, and one end of the first insulating layer P-type via 1611 extends to the metal reflective layer 15.

[0054] The P-type metal conductive layer 171 and the N-type metal conductive layer 172 are spatially separated. The P-type metal conductive layer 171 is stacked on top of the first insulating layer 16 and fills the P-type through-hole 1611 of the first insulating layer, so that the P-type metal conductive layer 171 and the metal reflective layer 15 are electrically connected. The N-type metal conductive layer 172 is stacked on top of the first insulating layer 16 and is electrically connected to the second N-type semiconductor portion 1112.

[0055] The angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane is smaller than the angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane.

[0056] The distance L between the projected edge of the first insulating layer P-type via 1611 on the horizontal plane and the projected edge of the Bragg reflector P-type via 1411 on the horizontal plane is 5 μm to 12 μm. Specifically, the distance L between the projected edge of the first insulating layer P-type via 1611 on the horizontal plane and the projected edge of the Bragg reflector P-type via 1411 on the horizontal plane is exemplary to be 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 9 μm, 10 μm, 11 μm or 12 μm, but is not limited thereto.

[0057] It is worth noting that by providing a first insulating layer P-type through-hole 1611 in the first insulating layer 16, the P-type metal conductive layer 171 is electrically connected to the metal reflective layer 15 located below the first insulating layer 16. By providing a Bragg reflective layer P-type through-hole 1411 in the Bragg reflective layer 14, the metal reflective layer 15 is electrically connected to the P-type semiconductor layer 113 located below the Bragg reflective layer 14. This invention significantly improves the high-current withstand capability of flip-chip LEDs by controlling the angle β between the wall of the first insulating layer P-type via 1611 and the horizontal plane to be smaller than the angle α between the wall of the Bragg reflector P-type via 1411 and the horizontal plane, and by controlling the distance L between the projected edge of the first insulating layer P-type via 1611 on the plane and the projected edge of the Bragg reflector P-type via 1411 on the horizontal plane to be 5μm to 12μm. This effectively extends the lifespan of the flip-chip LED under high-current conditions, allowing the chip to be applied in applications with high power and current requirements, such as automotive lights and stage lights. If the angle β between the wall of the first insulating layer P-type via 1611 and the horizontal plane is greater than or equal to the angle α between the wall of the Bragg reflector P-type via 1411 and the horizontal plane, the chip's high-current withstand capability will decrease significantly. If the distance L between the projected edge of the first insulating layer P-type via 1611 on the horizontal plane and the projected edge of the Bragg reflector layer P-type via 141 on the horizontal plane is less than 5μm, the chip's ability to withstand high current will be greatly reduced; if L is greater than 12μm, it will have limited effect on improving the chip's ability to withstand high current, and when L is greater than 12μm, the chip's operating voltage will increase significantly.

[0058] More preferably, the distance L between the projected edge of the first insulating layer P-type via 1611 on the horizontal plane and the projected edge of the Bragg reflector layer P-type via 1411 on the horizontal plane is 5μm to 8μm. By further limiting the distance L to 5μm to 8μm, L within this range can effectively improve the flip-chip silver mirror LED chip's ability to withstand high current, and within this range, the larger the distance L, the better the chip's ability to withstand high current. In addition, when L is 5μm to 8μm, the chip's operating voltage is relatively low; when L is greater than 8μm and less than or equal to 12μm, the chip's operating voltage will increase, which may easily affect other chip performance, such as potentially increasing chip power consumption and reducing chip stability.

[0059] In one embodiment, the difference between the angle β between the wall of the first insulating layer P-type via 1611 and the horizontal plane and the angle α between the wall of the Bragg reflector layer P-type via 1411 and the horizontal plane is ≤20°. By limiting the difference between angles β and α to ≤20°, the flip-chip silver mirror LED chip can be ensured to have better high-current resistance. If the difference between angles β and α is greater than 20°, the chip's high-current resistance will decrease significantly.

[0060] Specifically, the difference between the angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane and the angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane is exemplary to be 5°, 8°, 10°, 12°, 15°, 18° or 20°, but is not limited thereto.

[0061] In one embodiment, the angle β between the wall of the first insulating layer P-type via 1611 and the horizontal plane is 15°–20°, and the angle α between the wall of the Bragg reflector layer P-type via 1411 and the horizontal plane is 25°–40°. By further controlling the angle β to 15°–20° and the angle α to 25°–40°, the ability of the flip-chip silver mirror LED chip to withstand high currents can be further improved.

[0062] Specifically, the included angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane is exemplary to be 15°, 16°, 17°, 18°, 19° or 20°, and the included angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane is 25°, 26°, 27°, 28°, 29°, 30°, 31°, 32°, 33°, 34°, 35°, 36°, 37°, 38°, 39° or 40°, but is not limited to these, as long as the included angle α - included angle β ≤ 20°.

[0063] In one embodiment, the flip-chip silver mirror light-emitting diode chip further includes a current blocking layer 13, which covers the surface of the current spreading layer 12 and the second N-type semiconductor portion 1112, and the Bragg reflector layer 14 covers the surface of the current blocking layer 13.

[0064] The current blocking layer 13 is provided with a current blocking layer P-type through hole 131. One end of the current blocking layer P-type through hole 131 is connected to the Bragg reflector layer P-type through hole 1411, and the other end extends to the current spreading layer 12, so that the current spreading layer 12 is partially exposed.

[0065] The metal reflective layer 15 has a protrusion 151 on the side near the substrate 10. The protrusion 151 sequentially fills the P-type via 1411 of the Bragg reflective layer and the P-type via 131 of the current blocking layer, and the end of the protrusion contacts the current spreading layer 12, so that the metal reflective layer 15 and the current spreading layer 12 are electrically connected.

[0066] In one embodiment, the Bragg reflector layer 14 includes a first Bragg reflector portion 141 and a second Bragg reflector portion 142 connected to each other. The first Bragg reflector portion 141 and the second Bragg reflector portion 142 respectively cover the surface of the current blocking layer 13, and the first Bragg reflector portion 141 is located above the P-type semiconductor layer 113, and the second Bragg reflector portion 142 is located above the second N-type semiconductor layer 1112. The first Bragg reflector portion 141 has a P-type via 1411 in the Bragg reflector layer; the second Bragg reflector portion 142 has an N-type via 1421 in the Bragg reflector layer, and one end of the N-type via 1421 extends to the current blocking layer 13.

[0067] The first insulating layer 16 includes a first insulating layer A portion 161 and a first insulating layer B portion 162 connected to each other. The first insulating layer A portion 161 is stacked on top of the metal reflective layer 15, and the first insulating layer B portion 162 is stacked on top of the second Bragg reflective portion 142. The first insulating layer P-type through hole 1611 is located inside the first insulating layer A portion 161, and the first insulating layer B portion 162 is provided with a first insulating layer N-type through hole 1621. The first insulating layer N-type through hole 1621 is located inside the Bragg reflective layer N-type through hole 1421.

[0068] The current blocking layer 13 is also provided with a current blocking layer N-type through hole 132, one end of the current blocking layer N-type through hole 132 is connected to the first insulating layer N-type through hole 1621, and the other end extends to the second N-type semiconductor part 1112;

[0069] The P-type metal conductive layer 171 and the N-type metal conductive layer 172 are spatially separated, so that there is no direct physical contact between them. The P-type metal conductive layer 171 covers the surface of the first insulating layer A part 161 and fills the P-type through hole 1611 of the first insulating layer, so that the P-type metal conductive layer 171 and the metal reflective layer 15 are electrically connected. The N-type metal conductive layer 172 covers the surface of the first insulating layer B part 162 and sequentially fills the N-type through hole 1621 of the first insulating layer and the N-type through hole 132 of the current blocking layer, so that the N-type metal conductive layer 172 and the second N-type semiconductor part 1112 are electrically connected.

[0070] In one embodiment, the flip-chip silver mirror light-emitting diode chip further includes a second insulating layer 18, which covers the surfaces of the P-type metal conductive layer 171, the N-type metal conductive layer 172, and the exposed first insulating layer 16. The second insulating layer 18 is provided with a second insulating layer P-type via 181 and a second insulating layer N-type via 182. One end of the second insulating layer P-type via 181 extends to the P-type metal conductive layer 171, exposing a portion of the P-type metal conductive layer 171. One end of the second insulating layer N-type via 182 extends to the N-type metal conductive layer 172, exposing a portion of the N-type metal conductive layer 172.

[0071] Specifically, the second insulating layer P-type via 181 exposes only a specific area of ​​the P-type conductive metal layer 171, allowing upper metal or conductive structures (such as interconnect wiring and electrodes) to form a dedicated electrical connection with it, avoiding short circuits with the N-type conductive metal layer 172. Similarly, the second insulating layer N-type via 182 exposes only a specific area of ​​the N-type conductive metal layer 172, ensuring that the upper structure is only connected to the N-type conductive metal layer 172. The second insulating layer 18 covers the non-via areas of the P-type conductive metal layer 171 and the N-type conductive metal layer 172, as well as the exposed surface of the first insulating layer 16, forming a sealing barrier to prevent excessive metal from contacting air and moisture, thus avoiding oxidation or corrosion and extending device life.

[0072] Specifically, the cooperation of the second insulating layer 18 and the first insulating layer 16 enables the P-type metal conductive layer 171 and the N-type metal conductive layer 172 to be spatially separated and without direct physical contact, thereby realizing circuit connection within the chip and preventing interlayer short circuits.

[0073] Accordingly, this embodiment also discloses a method for fabricating a flip-chip silver mirror light-emitting diode chip, which is used to fabricate the above-mentioned flip-chip silver mirror light-emitting diode chip, including the following steps:

[0074] (1) A substrate 10 is provided, and an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 are sequentially deposited on the substrate 10 using MOCVD process to obtain an epitaxial layer 11; preferably, the substrate 10 can be a GaN substrate, an Al2O3 substrate or a Si substrate.

[0075] (2) A portion of the P-type semiconductor layer 113 and the corresponding active light-emitting layer 112 are removed to expose a portion of the N-type semiconductor layer 111. The exposed N-type semiconductor layer 111 is the second N-type semiconductor portion 1112. In some embodiments, a first photoresist is coated on the surface of the P-type semiconductor layer 113, and then a portion of the first photoresist on the P-type semiconductor layer 113 is removed by exposure and development processes to expose a portion of the P-type semiconductor layer 113. The exposed P-type semiconductor layer 113 and the corresponding active light-emitting layer 112 are removed by inductively coupled plasma etching processes to expose a portion of the N-type semiconductor layer 111. The exposed N-type semiconductor layer 111 is the second N-type semiconductor portion 1112. Then the first photoresist is removed.

[0076] (3) Deposit indium tin oxide on the surface of the P-type semiconductor layer 113 to form a current spreading layer 12 on the surface of the P-type semiconductor layer 113; In some embodiments, indium tin oxide is deposited on the surface of the P-type semiconductor layer 113 and the second N-type semiconductor portion 1112 using a magnetron sputtering process; then a second photoresist is coated on the surface of the indium tin oxide, and then a portion of the second photoresist is removed by exposure and development to expose a portion of the indium tin oxide; then the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then the second photoresist is removed to form a current spreading layer 12 on the surface of the P-type semiconductor layer 113;

[0077] (4) SiO2 is deposited on the surface of the P-type semiconductor layer 113, the current spreading layer 12 and the second N-type semiconductor part 1112 by PECVD process to form a current blocking layer 13 with a thickness greater than 5000A.

[0078] (5) Using electron beam evaporation, 2 to 10 stacks of TiO2 and SiO2 are sequentially deposited on the surface of the current blocking layer 13 to form a Bragg reflector layer 14.

[0079] (6) A P-type via 1411 and an N-type via 1421 of the Bragg reflector layer are formed at a designated location on the Bragg reflector layer 14. In some embodiments, a third photoresist is coated on the surface of the Bragg reflector layer 14, and a portion of the third photoresist on the Bragg reflector layer 14 is removed by exposure and development. Then, the exposed Bragg reflector layer 14 is removed by inductively coupled plasma etching process to form the P-type via 1411 and the N-type via 1421 of the Bragg reflector layer, exposing the current blocking layer 13 below the P-type via 1411 and the N-type via 1421 of the Bragg reflector layer. Then, the third photoresist is removed.

[0080] (7) A P-type via 131 and an N-type via 132 of the current blocking layer are formed at a designated position in the current blocking layer 13. In some embodiments, a fourth photoresist is coated on the surface of the Bragg reflector layer 14, the P-type via 1411 and the N-type via 1421 of the Bragg reflector layer, and a portion of the fourth photoresist in the P-type via 1411 and the N-type via 1421 of the Bragg reflector layer is removed by exposure and development, exposing the current blocking layer 13 below the P-type via 1411 and the N-type via 1421 of the Bragg reflector layer. The exposed current blocking layer 13 is removed by the first BOE etching solution, and the P-type via 131 and the N-type via 132 of the current blocking layer are formed respectively. Then the fourth photoresist is removed.

[0081] (8) A metal reflective layer 15 is grown above a designated location of the Bragg reflective layer 14, and the metal reflective layer 15 fills the Bragg reflective layer P-type via 1411 and the current blocking layer P-type via 131; in some embodiments, a fifth photoresist is first coated on the Bragg reflective layer 14, the Bragg reflective layer P-type via 1411, the Bragg reflective layer N-type via 1421, the current blocking layer P-type via 131, the current blocking layer N-type via 132 and the exposed areas of the current blocking layer 13; part of the fifth photoresist is removed by exposure and development; then Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metal is sequentially deposited by electron beam evaporation to form the metal reflective layer 15 (i.e., the metal reflective layer 15 is an Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metal stack); then the metal above the fifth photoresist is removed by blue film stripping process and the fifth photoresist is removed;

[0082] (9) SiO2 is deposited on the metal reflective layer 15 using a second PECVD process to form a first insulating layer 16; a first insulating layer P-type via 1161 and a first insulating layer N-type via 1621 are opened at designated positions in the first insulating layer 16; in some embodiments, a sixth photoresist is first coated on the surface of the first insulating layer 16, and a portion of the sixth photoresist is removed by exposure and development to expose a portion of the first insulating layer 16, and then the exposed first insulating layer 16 is removed by a second BOE etching solution to form the first insulating layer P-type via 1161 and the first insulating layer N-type via 1621, and the sixth photoresist is removed;

[0083] (10) A P-type metal conductive layer 171 and an N-type metal conductive layer 172 are formed at designated positions on the first insulating layer 16, respectively. In some embodiments, a seventh photoresist is coated on the surface of the first insulating layer 16, the first insulating layer P-type via 1161 and the first insulating layer N-type via 1621, and then a portion of the seventh photoresist is removed by exposure and development. Al / Ti / Al / Ti / Al / Ti / Ni / Au / Ti metal is deposited sequentially by electron beam evaporation to form a P-type metal conductive layer 171 and an N-type metal conductive layer 172 (i.e., both the P-type metal conductive layer 171 and the N-type metal conductive layer 172 are Al / Ti / Al / Ti / Al / Ti / Ni / Au / Ti metal stacks). Then, the metal on the seventh photoresist is removed by blue film stripping process, and then the seventh photoresist is removed.

[0084] (11) On the surface of the P-type metal conductive layer 171, the N-type metal conductive layer 172 and the surface of the first insulating layer 16 not covered by the P-type metal conductive layer 171 and the N-type metal conductive layer 172, SiO2 is deposited as the second insulating layer 18 using the PECVD process; the eighth photoresist is coated on the surface of the second insulating layer 18, and then part of the eighth photoresist is removed by exposure and development to expose part of the second insulating layer 18. Then the exposed second insulating layer is removed by the third BOE etching solution, and then the eighth photoresist is removed to form the second insulating layer P-type via 181 and the second insulating layer N-type via 182.

[0085] In one embodiment, the method of opening a P-type via 1411 and an N-type via 1421 of the Bragg reflector layer 14 at a designated location in step (6) includes the following steps:

[0086] A third photoresist is coated on the surface of the Bragg reflector layer 14. The third photoresist at a specified position on the Bragg reflector layer 14 is removed by exposure and development. Then, the exposed Bragg reflector layer 14 is removed by inductively coupled plasma etching process to form P-type vias 1411 and N-type vias 1421 of the Bragg reflector layer. The current blocking layer 13 below the P-type vias 1411 and N-type vias 1421 of the Bragg reflector layer is exposed. Then, the third photoresist is removed.

[0087] The thickness of the third photoresist is 1.5μm to 2μm; the angle α between the hole wall of the P-type via 1411 of the Bragg reflection layer and the horizontal plane depends on the thickness of the third photoresist. By controlling the thickness of the third photoresist to be 1.5μm to 2μm, the angle α between the hole wall of the P-type via 1411 of the Bragg reflection layer and the horizontal plane can be controlled to be 25° to 40°.

[0088] In step (9), the method of forming a first insulating layer P-type via 1161 and a first insulating layer N-type via 1621 at a designated position in the first insulating layer 16 includes the following steps: coating a sixth photoresist on the surface of the first insulating layer 16, removing the sixth photoresist at the designated position by exposure and development, exposing part of the first insulating layer 16, and then removing the exposed first insulating layer 16 by a second BOE etching solution to form the first insulating layer P-type via 1161 and the first insulating layer N-type via 1621, and removing the sixth photoresist;

[0089] The second BOE etching solution comprises hydrofluoric acid, ammonium fluoride, and water, with a volume ratio of ammonium fluoride to hydrofluoric acid of 15:1 to 20:1. The angle β between the hole wall of the first insulating layer P-type via 1611 and the horizontal plane depends on the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution. By controlling the volume ratio of ammonium fluoride to hydrofluoric acid to 15:1 to 20:1, the angle β between the hole wall of the first insulating layer P-type via 1611 and the horizontal plane can be controlled to be 15° to 20°, thereby enabling the fabricated flip-chip light-emitting diode chip to possess excellent high-current resistance.

[0090] The technical solution of the present invention will be further described below through embodiments and comparative examples.

[0091] Example 1

[0092] This embodiment discloses a flip-chip silver mirror light-emitting diode chip, including a substrate 10, an epitaxial layer 11, a current spreading layer 12, a current blocking layer 13, a Bragg reflector layer 14, a metal reflector layer 15, a first insulating layer 16, a P-type metal conductive layer 171, an N-type metal conductive layer 172, and a second insulating layer 18; the epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113;

[0093] The current blocking layer 13 is provided with a current blocking layer P-type through hole 131 and a current blocking layer N-type through hole 132, and the Bragg reflector layer 14 is provided with a Bragg reflector P-type through hole 1411 and a Bragg reflector N-type through hole 1421.

[0094] The first insulating layer 16 is provided with a first insulating layer P-type through hole 1611 and a first insulating layer N-type through hole 1621;

[0095] In this embodiment, the included angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane is 15°, and the included angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane is 25°.

[0096] The distance L between the projected edge of the first insulating layer P-type via 1611 on the horizontal plane and the projected edge of the Bragg reflector P-type via 1411 on the horizontal plane is 5 μm.

[0097] The fabrication method of the flip-chip silver mirror light-emitting diode chip in this embodiment includes the following steps:

[0098] (1) Provide a substrate 10, and deposit an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 sequentially on the substrate 10 using MOCVD process to obtain an epitaxial layer 11; the substrate 10 is a GaN substrate;

[0099] (2) A first photoresist is coated on the surface of the P-type semiconductor layer 113, and then a portion of the first photoresist on the P-type semiconductor layer 113 is removed by exposure and development process to expose a portion of the P-type semiconductor layer 113; the exposed P-type semiconductor layer 113 and the corresponding active light-emitting layer 112 are removed by inductively coupled plasma etching process to expose a portion of the N-type semiconductor layer 111. The exposed portion of the N-type semiconductor layer 111 is the second N-type semiconductor part 1112, and then the first photoresist is removed.

[0100] (3) Indium tin oxide is deposited on the surface of the P-type semiconductor layer 113 and the second N-type semiconductor layer 1112 using a magnetron sputtering process; then a second photoresist is coated on the surface of the indium tin oxide, and then a portion of the second photoresist is removed by exposure and development to expose a portion of the indium tin oxide; then the exposed indium tin oxide is removed by an indium tin oxide etchant, and then the second photoresist is removed, so that a current spreading layer 12 is formed on the surface of the P-type semiconductor layer 113;

[0101] (4) SiO2 is deposited on the surface of the P-type semiconductor layer 113, the current spreading layer 12 and the second N-type semiconductor part 1112 by PECVD process to form a current blocking layer 13 with a thickness of 5500A.

[0102] (5) Five stacks of TiO2 and SiO2 are sequentially deposited on the surface of the current blocking layer 13 using electron beam evaporation to form a Bragg reflector layer 14.

[0103] (6) A third photoresist is coated on the surface of the Bragg reflector layer 14. Part of the third photoresist on the Bragg reflector layer 14 is removed by exposure and development. Then, the exposed Bragg reflector layer 14 is removed by inductively coupled plasma etching process to form P-type vias 1411 and N-type vias 1421 of the Bragg reflector layer, exposing the current blocking layer 13 below the P-type vias 1411 and N-type vias 1421 of the Bragg reflector layer. Then, the third photoresist is removed. In this embodiment, the thickness of the third photoresist is 1.5 μm.

[0104] (7) A fourth photoresist is coated on the surface of the Bragg reflector layer 14, the P-type via 1411 of the Bragg reflector layer and the N-type via 1421 of the Bragg reflector layer. Part of the fourth photoresist inside the P-type via 1411 and the N-type via 1421 of the Bragg reflector layer is removed by exposure and development, exposing the current blocking layer 13 below the P-type via 1411 and the N-type via 1421 of the Bragg reflector layer. The exposed current blocking layer 13 is removed by the first BOE etching solution, forming the P-type via 131 and the N-type via 132 of the current blocking layer, respectively. Then the fourth photoresist is removed.

[0105] (8) Apply a fifth photoresist to the Bragg reflector layer 14, the P-type via 1411 of the Bragg reflector layer, the N-type via 1421 of the Bragg reflector layer, the P-type via 131 of the current blocking layer, the N-type via 132 of the current blocking layer, and the exposed areas of the current blocking layer 13; remove part of the fifth photoresist by exposure and development; then deposit Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metal sequentially by electron beam evaporation to form a metal reflector layer 15 (i.e., the metal reflector layer 15 is an Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metal stack); then remove the metal above the fifth photoresist and remove the fifth photoresist by blue film stripping process;

[0106] (9) SiO2 is deposited on the metal reflective layer 15 using a second PECVD process to form a first insulating layer 16; a sixth photoresist is coated on the surface of the first insulating layer 16, and part of the sixth photoresist is removed by exposure and development to expose part of the first insulating layer 16. Then, the exposed first insulating layer 16 is removed by a second BOE etching solution to form a first insulating layer P-type via 1161 and a first insulating layer N-type via 1621, and the sixth photoresist is removed; wherein, the components of the second BOE etching solution include hydrofluoric acid, ammonium fluoride and water. In this embodiment, the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 15:1;

[0107] (10) A seventh photoresist is coated on the surface of the first insulating layer 16, the first insulating layer P-type via 1161 and the first insulating layer N-type via 1621. Then, a portion of the seventh photoresist is removed by exposure and development. Al / Ti / Al / Ti / Al / Ti / Ni / Au / Ti metal is deposited sequentially by electron beam evaporation to form a P-type metal conductive layer 171 and an N-type metal conductive layer 172 (i.e., both the P-type metal conductive layer 171 and the N-type metal conductive layer 172 are Al / Ti / Al / Ti / Al / Ti / Ni / Au / Ti metal stacks). Then, the metal on the seventh photoresist is removed by blue film stripping. Finally, the seventh photoresist is removed.

[0108] (11) On the surface of the P-type metal conductive layer 171, the N-type metal conductive layer 172 and the surface of the first insulating layer 16 not covered by the P-type metal conductive layer 171 and the N-type metal conductive layer 172, SiO2 is deposited as the second insulating layer 18 using the PECVD process; the eighth photoresist is coated on the surface of the second insulating layer 18, and then part of the eighth photoresist is removed by exposure and development to expose part of the second insulating layer 18. Then the exposed second insulating layer is removed by the third BOE etching solution, and then the eighth photoresist is removed to form the second insulating layer P-type via 181 and the second insulating layer N-type via 182.

[0109] Example 2

[0110] This embodiment discloses a flip-chip silver mirror light-emitting diode chip. The structure and preparation method of the flip-chip silver mirror light-emitting diode chip in this embodiment are basically the same as those in Embodiment 1. The difference is that: in the flip-chip silver mirror light-emitting diode chip of Embodiment 2, the included angle β between the hole wall of the first insulating layer P-type via 1611 and the horizontal plane is 20°, and the included angle α between the hole wall of the Bragg reflector P-type via 1411 and the horizontal plane is 40°; in step (6), the thickness of the third photoresist is 2μm; in step (9), the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 20:1.

[0111] Example 3

[0112] This embodiment discloses a flip-chip silver mirror light-emitting diode chip. The structure and preparation method of the flip-chip silver mirror light-emitting diode chip in this embodiment are basically the same as those in Embodiment 1. The difference is that: in the flip-chip silver mirror light-emitting diode chip of Embodiment 3, the included angle β between the hole wall of the first insulating layer P-type via 1611 and the horizontal plane is 20°, and the included angle α between the hole wall of the Bragg reflector P-type via 1411 and the horizontal plane is 40°; in step (6), the thickness of the third photoresist is 2μm; in step (9), the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 20:1; the distance L between the projection edge of the first insulating layer P-type via 1611 on the horizontal plane and the projection edge of the Bragg reflector P-type via 1411 on the horizontal plane is 6.5μm.

[0113] Example 4

[0114] This embodiment discloses a flip-chip silver mirror light-emitting diode chip. The structure and preparation method of the flip-chip silver mirror light-emitting diode chip in this embodiment are basically the same as those in Embodiment 1. The difference is that: in the flip-chip silver mirror light-emitting diode chip of Embodiment 3, the included angle β between the hole wall of the first insulating layer P-type via 1611 and the horizontal plane is 20°, and the included angle α between the hole wall of the Bragg reflector P-type via 1411 and the horizontal plane is 40°; in step (6), the thickness of the third photoresist is 2μm; in step (9), the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 20:1; the distance L between the projection edge of the first insulating layer P-type via 1611 on the horizontal plane and the projection edge of the Bragg reflector P-type via 1411 on the horizontal plane is 8μm.

[0115] Example 5

[0116] This embodiment discloses a flip-chip silver mirror light-emitting diode chip. The structure and preparation method of the flip-chip silver mirror light-emitting diode chip in this embodiment are basically the same as those in Embodiment 1. The difference is that: in the flip-chip silver mirror light-emitting diode chip of Embodiment 3, the included angle β between the hole wall of the first insulating layer P-type via 1611 and the horizontal plane is 20°, and the included angle α between the hole wall of the Bragg reflector layer P-type via 1411 and the horizontal plane is 40°; in step (6), the thickness of the third photoresist is 2μm; in step (9), the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 20:1; the distance L between the projection edge of the first insulating layer P-type via 1611 on the horizontal plane and the projection edge of the Bragg reflector layer P-type via 1411 on the horizontal plane is 12μm.

[0117] Comparative Example 1

[0118] This comparative example discloses a flip-chip silver mirror light-emitting diode chip. The structure and preparation method of the flip-chip silver mirror light-emitting diode chip in this comparative example are basically the same as those in Example 1. The difference is that: in the flip-chip silver mirror light-emitting diode chip of Comparative Example 1, the included angle β between the hole wall of the first insulating layer P-type via and the horizontal plane is 65°, and the included angle α between the hole wall of the Bragg reflector P-type via and the horizontal plane is 20°; in step (6), the thickness of the third photoresist is 4μm; in step (9), the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 13:1; the distance L between the projection edge of the first insulating layer P-type via on the horizontal plane and the projection edge of the Bragg reflector P-type via on the horizontal plane is 0μm.

[0119] Specifically, the flip-chip silver mirror light-emitting diode chips prepared in Examples 1 to 5 and Comparative Example 1 were subjected to long-term high-current aging tests at room temperature (25°C). The high current was three times the operating current. The chip brightness was tested and recorded before aging as the initial brightness. During the aging process, the chip brightness was tested every 72 hours as the real-time brightness. When the ratio of the real-time brightness to the initial brightness was less than 90%, the chip was deemed to have failed, and the time of chip failure was recorded. The chip size used in the test was 1200μm × 1200μm, and the operating current was 700mA, i.e., the aging high current was 2100mA. The test results are shown in Table 1 below:

[0120] Table 1 Performance Test Results

[0121]

[0122] As can be seen from the test results in Table 1, by controlling the distance L between the projected edge of the first insulating layer P-type via 1611 on the horizontal plane and the projected edge of the Bragg reflector P-type via 1411 on the horizontal plane to be 5μm to 12μm, and by controlling the included angle β between the hole wall of the first insulating layer P-type via 1611 and the horizontal plane to be smaller than the included angle α between the hole wall of the Bragg reflector P-type via 1411 and the horizontal plane, the lifespan of the chip under a high current of 2100mA can be significantly extended. Under a high current of 2100mA, the chip can work continuously for more than 1700h. Therefore, it can be seen that the flip-chip silver mirror light-emitting diode chips of Examples 1 to 5 have excellent resistance to high current.

[0123] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-described technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A flip-chip silver mirror light-emitting diode chip, characterized in that, It includes a substrate, an epitaxial layer, a Bragg reflector layer, a metal reflector layer, a first insulating layer, a P-type metal conductive layer, and an N-type metal conductive layer; The epitaxial layer comprises an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially stacked on the substrate. The Bragg reflector layer is stacked on top of the P-type semiconductor layer, and the Bragg reflector layer has a P-type via; the metal reflector layer covers the surface of the Bragg reflector layer, and the metal reflector layer passes through the P-type via and is electrically connected to the P-type semiconductor layer. The first insulating layer is stacked on top of the metal reflective layer. The first insulating layer has a first insulating layer P-type through hole, and one end of the first insulating layer P-type through hole extends to the metal reflective layer. The P-type metal conductive layer is stacked on top of the first insulating layer, and the P-type metal conductive layer passes through the P-type via of the first insulating layer and is electrically connected to the metal reflective layer; the N-type metal conductive layer is electrically connected to the N-type semiconductor layer. The angle β between the hole wall of the first insulating layer P-type through hole and the horizontal plane is smaller than the angle α between the hole wall of the Bragg reflector layer P-type through hole and the horizontal plane; The distance L between the projected edge of the P-type via in the first insulating layer and the projected edge of the P-type via in the Bragg reflector layer is 5μm~12μm.

2. The flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that, The distance L between the projected edge of the P-type via in the first insulating layer and the projected edge of the P-type via in the Bragg reflector layer is 5μm~8μm.

3. The flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that, The difference between the angle β between the hole wall of the first insulating layer P-type through hole and the horizontal plane and the angle α between the hole wall of the Bragg reflector layer P-type through hole and the horizontal plane is ≤20°.

4. The flip-chip silver mirror light-emitting diode chip according to claim 1, 2 or 3, characterized in that, The included angle β between the hole wall of the first insulating layer P-type through hole and the horizontal plane is 15°~20°.

5. The flip-chip silver mirror light-emitting diode chip according to claim 4, characterized in that, The angle α between the hole wall of the P-type through-hole in the Bragg reflector layer and the horizontal plane is 25°~40°.

6. The flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that, The flip-chip silver mirror light-emitting diode chip also includes a current spreading layer and a current blocking layer; The N-type semiconductor layer is stacked on the surface of the substrate. The N-type semiconductor layer includes a first N-type semiconductor portion and a second N-type semiconductor portion that are interconnected. The P-type semiconductor layer and the active light-emitting layer are stacked sequentially on top of the first N-type semiconductor portion. The current spreading layer covers the surface of the P-type semiconductor layer, so that the current spreading layer and the P-type semiconductor layer are electrically connected. The current blocking layer covers the surface of the current spreading layer and the second N-type semiconductor, and the Bragg reflector layer covers the surface of the current blocking layer; The current blocking layer is provided with a P-type through hole, one end of which is connected to the P-type through hole of the Bragg reflector layer, and the other end extends to the current spreading layer. The metal reflective layer is located above the current spreading layer. The metal reflective layer has a protrusion on the side near the substrate. The protrusion sequentially fills the P-type via of the Bragg reflective layer and the P-type via of the current blocking layer. The end of the protrusion is in contact with the current spreading layer, so that the metal reflective layer and the current spreading layer are electrically connected.

7. The flip-chip silver mirror light-emitting diode chip according to claim 6, characterized in that, The Bragg reflector layer includes a first Bragg reflector portion and a second Bragg reflector portion connected to each other. The first Bragg reflector portion and the second Bragg reflector portion respectively cover the surface of the current blocking layer, with the first Bragg reflector portion located above the P-type semiconductor layer and the second Bragg reflector portion located above the second N-type semiconductor layer. The first Bragg reflector portion has a P-type via in the Bragg reflector layer, and the second Bragg reflector portion has an N-type via in the Bragg reflector layer, with one end of the N-type via extending into the current blocking layer. The first insulating layer includes a first insulating layer A portion and a first insulating layer B portion that are connected to each other. The first insulating layer A portion is stacked on top of the metal reflective layer, and the first insulating layer B portion is stacked on top of the second Bragg reflective portion. The first insulating layer P-type through hole is located inside the first insulating layer A portion, and the first insulating layer B portion is provided with a first insulating layer N-type through hole, which is located inside the Bragg reflective layer N-type through hole. The current blocking layer is further provided with an N-type through-hole of the current blocking layer, one end of which is connected to the N-type through-hole of the first insulating layer, and the other end extends to the second N-type semiconductor part; The P-type metal conductive layer and the N-type metal conductive layer are spatially separated. The P-type metal conductive layer covers the surface of the first insulating layer A portion, and the N-type metal conductive layer covers the surface of the first insulating layer B portion and sequentially fills the first insulating layer N-type via and the current blocking layer N-type via until it contacts the second N-type semiconductor portion.

8. The flip-chip silver mirror light-emitting diode chip according to claim 7, characterized in that, The flip-chip silver mirror light-emitting diode chip further includes a second insulating layer, which covers the surface of the P-type metal conductive layer, the N-type metal conductive layer and the exposed first insulating layer. The second insulating layer has a second insulating layer P-type via and a second insulating layer N-type via. One end of the second insulating layer P-type via extends to the P-type metal conductive layer, and one end of the second insulating layer N-type via extends to the N-type metal conductive layer.

9. A method for fabricating a flip-chip silver mirror light-emitting diode, characterized in that, The method for preparing the flip-chip silver mirror light-emitting diode chip according to any one of claims 1-8 comprises the following steps: (1) Provide a substrate, and deposit an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer sequentially on the substrate to obtain an epitaxial layer; (2) Remove the P-type semiconductor layer and the corresponding active light-emitting layer in the specified area to expose part of the N-type semiconductor layer. The exposed N-type semiconductor layer is the second N-type semiconductor part. (3) Deposit indium tin oxide on the surface of the P-type semiconductor layer to form a current spreading layer on the surface of the P-type semiconductor layer; (4) SiO2 is deposited on the surface of the P-type semiconductor layer, the current spreading layer and the second N-type semiconductor layer to form a current blocking layer; (5) Two to ten layers of TiO2 and SiO2 are sequentially deposited on the surface of the current blocking layer to form a Bragg reflector layer; (6) Open P-type through holes and N-type through holes of the Bragg reflector at designated locations in the Bragg reflector; (7) Open P-type through holes and N-type through holes of the current blocking layer at the designated positions of the current blocking layer; (8) A metal reflective layer is grown above the Bragg reflective layer at a specified location, and the metal reflective layer fills the P-type via of the Bragg reflective layer and the P-type via of the current blocking layer. (9) SiO2 is deposited on the metal reflective layer to form a first insulating layer; a P-type via and an N-type via of the first insulating layer are opened at a designated position in the first insulating layer; (10) A P-type metal conductive layer and an N-type metal conductive layer are formed at designated locations in the first insulating layer, respectively.

10. The method for fabricating a flip-chip silver mirror light-emitting diode according to claim 9, characterized in that, In step (6), the method of creating P-type and N-type vias in the Bragg reflector at designated locations includes the following steps: A third photoresist is coated on the surface of the Bragg reflector layer. The third photoresist at a designated location on the Bragg reflector layer is removed, and then the exposed Bragg reflector layer is removed to form P-type vias and N-type vias of the Bragg reflector layer. The current blocking layer below the P-type vias and N-type vias of the Bragg reflector layer is exposed, and then the third photoresist is removed. The thickness of the third photoresist is 1.5 μm to 2 μm. In step (9), the method of opening a P-type via and an N-type via of the first insulating layer at a designated location of the first insulating layer includes the following steps: coating a sixth photoresist on the surface of the first insulating layer, removing the sixth photoresist at a designated location to expose part of the first insulating layer, and then using a second BOE etching solution to remove the exposed first insulating layer to form a P-type via and an N-type via of the first insulating layer, and removing the sixth photoresist; The second BOE etching solution consists of hydrofluoric acid, ammonium fluoride and water, and the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 15:1 to 20:1.

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