Negative temperature current biasing circuit and chip including same

Abstract

The embodiment of the application provides a negative temperature current bias circuit and a chip comprising the same, and relates to the technical field of bias circuit. The circuit comprises: a reference power supply unit, comprising: a negative temperature coefficient voltage generating element, used for generating a voltage with a negative temperature coefficient; a resistor, a first end of the resistor and a low voltage end of the negative temperature coefficient voltage generating element are both connected to a first passage; a voltage output element, used for converting a current of a branch where the resistor is located into a voltage; an operational amplifier unit, used for controlling a current flowing through the resistor according to a voltage difference between a second end of the resistor and a high voltage end of the negative temperature coefficient voltage generating element; a starting unit, used for providing a grounding passage of a power supply end of the operational amplifier unit when starting, and shutting off the grounding passage when there is a bias voltage of the operational amplifier unit; and a bias output unit. The negative temperature current bias circuit in the embodiment of the application has high starting reliability and running stability.

Description

Technical Field

[0001] This application relates to the field of bias circuit technology, and more specifically to a negative temperature current bias circuit and a chip including the negative temperature current bias circuit. Background Technology

[0002] As a circuit capable of providing a stable current source, the accuracy and stability of a negative temperature current bias circuit are crucial for ensuring the high-performance operation of the entire system. Traditional current bias circuits and voltage bias circuits can only provide internal reference current and reference voltage independent of the power supply, avoiding bias fluctuations caused by power supply changes or noise, and can realize the biasing function of the corresponding modules inside the chip. However, with the increasing requirements for system automation, stability, and reliability, it is becoming increasingly important to design a bias circuit with a stable negative temperature coefficient and self-starting function to achieve stable and reliable operation of the chip in the high-temperature range.

[0003] For example, some outdoor workplaces, such as solar power generation and high-frequency, high-power operations, are often in environments with high temperature and high temperature fluctuations. The physical properties of semiconductor materials, such as resistivity and carrier mobility, will change with temperature, which may lead to deviations in circuit performance. Figure 1 A schematic diagram of a conventional bias circuit structure in the prior art is shown as follows: Figure 1 As shown, traditional bias circuits can provide bias voltages or currents independent of the VDD power supply. However, they can only provide reference voltages or currents independent of the power supply, and cannot provide voltage and current values ​​with stable and reliable negative temperature coefficients. In traditional biasing, the gate-source voltages are temperature-dependent and affected by the concentration of thermally activated carriers within the semiconductor material. Furthermore, the effect of temperature on the oxide layer and channel modulation can also cause changes in the gate voltage. These changes may affect the operating state of the metal-oxide-semiconductor field-effect transistor (MOS), leading to unstable behavior in high-temperature environments. For environments with frequent high-temperature operation, it is difficult to meet the stability and reliability requirements. Summary of the Invention

[0004] The purpose of this application is to provide a negative temperature current bias circuit and a chip containing it. This application uses the negative feedback mechanism of an operational amplifier to clamp the branch voltage of the reference power supply module, stabilizing the output current. Furthermore, it employs a dual-junction transistor with its base-collector shorted to achieve a negative temperature coefficient for the reference power supply with good linearity, meaning the current value decreases as the temperature increases. In addition, unlike traditional bias circuits, the startup circuit provides bias to the operational amplifier by setting an independent tail transistor of the differential operational amplifier, and ensures that the startup circuit is shut down after the system circuit is turned on by setting a low-impedance path, thus realizing an operational amplifier-based startup function and at least solving some of the problems in the prior art.

[0005] To achieve the above objectives, this application provides a negative temperature current bias circuit, which includes:

[0006] A reference power supply unit includes: a negative temperature coefficient voltage generating element for generating a voltage with a negative temperature coefficient; a resistor, the first end of which and the low-voltage end of the negative temperature coefficient voltage generating element are both connected to a first path; a voltage output element for converting the current in the branch containing the resistor into a voltage; an operational amplifier unit for controlling the current flowing through the resistor based on the voltage difference between the second end of the resistor and the high-voltage end of the negative temperature coefficient voltage generating element; a startup unit for providing a ground path to the power supply terminal of the operational amplifier unit during startup and shutting off the ground path when a bias voltage exists in the operational amplifier unit; and a bias output unit including a plurality of semiconductor transistors, the control terminals of which are all connected to the output terminals of the voltage output element, the sources of which are all connected to the operating voltage, and the drain of each semiconductor transistor being the bias output terminal.

[0007] Optionally, the negative temperature coefficient voltage generating element is a bipolar transistor with its base and collector shorted together.

[0008] Optionally, the reference power supply unit further includes a first semiconductor transistor, which provides a bias voltage to the negative temperature coefficient voltage generating element based on a fixed voltage at its control electrode.

[0009] Optionally, the operational amplifier unit includes an operational amplifier, the inverting input terminal of which is connected to the second terminal of the resistor, the non-inverting input terminal of which is connected to the high voltage terminal of the negative temperature coefficient voltage generating element, the output terminal of which is connected to the input terminal of the source follower, and the output terminal of the source follower is connected to the second terminal of the resistor.

[0010] Optionally, the voltage output element is a second semiconductor transistor with its gate and drain shorted together, the output terminal of the voltage output element is the gate or drain of the second semiconductor transistor, and the output terminal of the voltage output element is connected to the power supply terminal of the source follower.

[0011] Optionally, the circuit further includes an operational amplifier biasing unit, which includes: a current mirror for providing bias current to the operational amplifier unit; and a third semiconductor transistor for converting the voltage output by the voltage output element into the input current of the current mirror.

[0012] Optionally, the circuit further includes a startup confirmation unit, which includes a fourth semiconductor transistor. The fourth semiconductor transistor is connected in the same way as any semiconductor transistor in the bias output unit. The bias output terminal of the fourth semiconductor transistor is connected to the input terminal of a Schmitt trigger. The output terminal of the Schmitt trigger is used to output a level value, which is used to indicate whether there is a bias current input to its input terminal.

[0013] Optionally, the startup unit includes: a fifth semiconductor transistor, the control electrode of the fifth semiconductor transistor being connected to the control electrode of the first semiconductor transistor; the drain of the fifth semiconductor transistor being used to control the connection and disconnection of the power supply terminal and the ground path of the operational amplifier unit; the drain of the fifth semiconductor transistor being connected to the ground terminal when there is an internal bias voltage in the current mirror of the operational amplifier bias unit.

[0014] Optionally, the first path is an NMOS element with its gate and drain shorted, and the source of the NMOS element is grounded.

[0015] Optionally, the aspect ratio of the NMOS element used to control the connection between the drain of the fifth semiconductor transistor and the ground terminal is greater than that of the NMOS element used to control the connection between the power supply terminal and the ground path of the operational amplifier unit.

[0016] This application also provides a chip that includes the aforementioned negative temperature current bias circuit.

[0017] The above technical solution has the following beneficial effects:

[0018] The main design concept of this application is to change the bias module of the startup system circuit to the operational amplifier module of the startup system circuit, and then start the bias module of the system through the operational amplifier module, thereby improving the defects of the traditional bias circuit, such as the instability of the negative temperature coefficient and the failure of the system caused by the channel modulation effect.

[0019] Other features and advantages of the embodiments of this application will be described in detail in the following detailed description section. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the following detailed description to explain the embodiments of this application, but do not constitute a limitation on the embodiments of this application. In the drawings:

[0021] Figure 1 A schematic diagram of a conventional bias circuit structure in the prior art is shown.

[0022] Figure 2 A schematic diagram of the negative temperature current bias circuit according to an embodiment of this application is shown.

[0023] Figure 3 The illustration shows a timing diagram of the bias signal generation and the acknowledgment signal according to an embodiment of this application. Detailed Implementation

[0024] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the embodiments of this application.

[0025] Figure 2 A schematic diagram of the negative temperature current bias circuit according to an embodiment of this application is shown. Figure 2 As shown, a negative temperature current bias circuit includes:

[0026] The reference power supply unit, i.e., module I100 in the figure, includes: a negative temperature coefficient voltage generating element T1, used to generate a voltage with a negative temperature coefficient; a resistor R, the first end of which and the low voltage end of the negative temperature coefficient voltage generating element T1 are both connected to the first path; a voltage output element MP2, used to convert the current in the branch where the resistor R is located into a voltage; the resistor R is used to generate a voltage drop with a negative temperature coefficient when a current with a negative temperature coefficient flows through it.

[0027] The operational amplifier unit, i.e., module I400 in the diagram, controls the current flowing through resistor R based on the voltage difference between the second terminal of resistor R and the high-voltage terminal of the negative temperature coefficient voltage generating element T1. Since the first terminal of resistor R is connected to the low-voltage terminal of the negative temperature coefficient voltage generating element T1, their potentials are equal. When a voltage difference exists between the second terminal of resistor R and the high-voltage terminal of the negative temperature coefficient voltage generating element T1, the operational amplifier unit generates a control voltage or control current based on this voltage difference, changing the current flowing through resistor R. When the current in resistor R changes, the voltage across resistor R also changes accordingly, thereby clamping the voltage across resistor R through negative feedback.

[0028] The startup unit, namely module I300 in the figure, is used to provide a grounding path for the power supply terminal of the operational amplifier unit during startup, namely the path where MN4 is located; and to turn off the grounding path based on the bias voltage of the operational amplifier unit and the voltage taken from the control terminal of MN3.

[0029] The bias output unit includes several semiconductor transistors, namely MP6 to MPn in the figure. The control terminals of the semiconductor transistors are all connected to the output terminal of the voltage output element MP2, and the sources are all connected to the working voltage VDD. The drain of each semiconductor transistor is the bias output terminal, i.e., the Bias port.

[0030] Through the above implementation methods, the main design concept is changed from the bias module of the startup system to the operational amplifier module of the startup system, and then the bias module of the startup system is started through the operational amplifier module. The reference source MOS transistor in the bias module is replaced with a bijunction transistor, which improves the shortcomings of the traditional bias circuit, such as the channel modulation effect causing system failure and unstable temperature characteristics.

[0031] Figure 2 This application only illustrates the selection and connection methods of semiconductor transistors based on functional implementation. Any corresponding changes to the selection and connection methods made by those skilled in the art to achieve the same function are also within the scope of protection of this application. These changes include, for example, swapping the selections of MP (PMOS) and MN (NMOS) in this application and changing their connection methods.

[0032] In some embodiments of this application, the negative temperature coefficient voltage generating element is a bipolar transistor with its base and collector shorted. Specifically, device T1 uses a base-collector short-circuit configuration to generate a voltage V with a negative temperature coefficient. be Due to the characteristics of the PN junction, the short-circuited BJT is equivalent to a diode characteristic curve, which has better linearity.

[0033] In some embodiments of this application, the reference power supply unit further includes a first semiconductor transistor MP1, which provides a bias voltage to the negative temperature coefficient voltage generating element based on a fixed voltage at its control electrode. The fixed voltage can be VDD / 2. MP1 provides bias for this branch, and the fixed gate voltage of VDD / 2 ensures that MP1 starts up and is in saturation. MP2 is a PMOS device with its gate and drain shorted, acting as a current-to-voltage converter to convert the current generated in this branch into voltage and provide bias to subsequent branches such as MP3 to MPn. MN1 is a source follower, providing a negative feedback path for the operational amplifier and the reference power supply module. Its low output impedance allows the operational amplifier output to be effectively transmitted to the reference module, while its high input impedance prevents the reference module from drawing excessive current from the operational amplifier, thus achieving buffer isolation. MN0 is an NMOS device with its gate and drain shorted; because it inevitably saturates, it raises the bias power supply module by a V. dsat To ensure the MOSFETs in other modules of the system are in saturation, the current mirror at the lower end of the circuit must be increased by at least one V to ensure the differential input transistor is saturated. dsat Thus far, we have formed the system's reference power supply module using MP1, MP2, R, T1, and MN1. This module utilizes the properties of shorting the base and collector of a transistor and the current and voltage conduction of a MOS device to enable the bias unit to provide a negative stable temperature coefficient bias.

[0034] In some embodiments of this application, the operational amplifier unit includes an operational amplifier. The inverting input of the operational amplifier is connected to the second terminal of the resistor R, the non-inverting input is connected to the high-voltage terminal of the negative temperature coefficient voltage generating element T1, and the output is connected to the input of the source follower MN1. The output of the source follower MN1 is connected to the second terminal of the resistor R. The operational amplifier unit implements operational amplifier negative feedback, which provides negative feedback to the reference power supply module I100. The output of the operational amplifier causes the voltage at the source terminal of MN1, i.e., the upper end of the resistor, to follow the output of the operational amplifier through the source follower MN1. At this time, if the voltage at the upper end of T1 rises, the output of the operational amplifier rises, causing the voltage at the upper end of the resistor to rise, which affects the inflow to the inverting input of the operational amplifier, reducing the output of the operational amplifier, thereby forming negative feedback. This negative feedback clamps the voltage at the upper end of T1 and the upper end of the resistor R, forcing the voltages at the two points to be equal, thereby causing the current I flowing through R to... R =V be / R,V be Because it has a negative temperature coefficient voltage, the current generated decreases as the temperature rises and is almost independent of the supply voltage. This embodiment achieves a reference power supply with a stable negative temperature coefficient.

[0035] In some embodiments of this application, the voltage output element MP2 is a second semiconductor transistor with its gate and drain shorted, and the output terminal of the voltage output element is either the gate or the drain of the second semiconductor transistor. The output terminal of the voltage output element is connected to the power supply terminal of the source follower. MP2 is a PMOS device with its gate and drain shorted, and its function is as a current-to-voltage converter, converting the current generated in this branch into voltage and providing bias for subsequent branches MP3 to MPn.

[0036] In some embodiments of this application, the circuit further includes an operational amplifier biasing unit, i.e. Figure 2 The I200 module in the IC includes an operational amplifier bias unit comprising: a current mirror for providing bias current to the operational amplifier; and a third semiconductor transistor for converting the voltage output from the voltage output element into the input current of the current mirror. MP3 has a voltage-to-current conversion function; its gate receives the voltage converted from the negative temperature coefficient current generated by MP2 and converts this voltage into current to power this branch. MN2 and MN3 are a pair of aspect ratio-matched NMOS transistors, forming the current mirror structure. A current mirror is a standard component commonly found in analog integrated circuits; its controlled current is equal to the input reference current, and its characteristic is that the output current is a proportional "copy" of the input current, used to generate bias current and as an active load. This current mirror also serves as the tail transistor of the operational amplifier, providing bias. MP3, MN2, and MN3 constitute the bias circuit of the operational amplifier.

[0037] In some embodiments of this application, the circuit further includes a start confirmation unit, i.e. Figure 2 The I500 module in the I500 module includes a startup confirmation unit comprising a fourth semiconductor transistor MP4. The MP4 is connected in the same way as any of the semiconductor transistors (MP6 to MPn) in the bias output unit. The bias output terminal of the MP4 is connected to the input terminal of a Schmitt trigger S1. The output terminal of the Schmitt trigger S1 outputs a voltage level to indicate whether a bias current is input to its input terminal. This startup confirmation unit implements the startup confirmation function. Its function is to generate a Ready signal after all bias signals are correctly generated, serving as a confirmation function for the next-level module. S1 is a Schmitt trigger, internally formed by cascading multiple inverters to create a delay. Its characteristic is that when generating bias current, it ensures that all bias currents from MP6 to MPn flow out, finally flowing through MP4 into the Schmitt trigger to generate the Ready signal. This branch is connected in parallel at the end of all biases to ensure that the Ready signal is generated only after all bias signals are correctly formed.

[0038] In some embodiments of this application, the startup unit includes: a fifth semiconductor transistor MP5, the control electrode of which is connected to the control electrode of the first semiconductor transistor MP1; the drain of the fifth semiconductor transistor MP5 is used to control the connection and disconnection of the power supply terminal and the ground path of the operational amplifier unit; the drain of the fifth semiconductor transistor is connected to the ground terminal when there is an internal bias voltage in the current mirror of the operational amplifier bias unit. This embodiment illustrates the structure of the startup unit. Since there is a dead point in the operational amplifier unit, MN1, and its bias circuit, a startup unit is added. After the startup unit is powered on, the gate voltage of MP1 is VCC / 2, so the startup of MP1, T1, and MN0 is not a problem. The gate of MN1 may be at a low level, and MN1, the bias circuit, and the operational amplifier are in a cutoff state. Since the gate voltage of MP5 is also a fixed value, preferably VCC / 2, MP5 will start, causing the level at the gate port of MN4 to rise, turning on MN4 and providing a path to ground for the operational amplifier. Because the T1 branch is already open, there is a signal at the input of the operational amplifier, allowing it to operate normally. The level at the gate node of MN1 is pulled high, and MN1 enters the open state, thus starting the entire circuit. MN5 uses a multi-finger structure with a width-to-length ratio greater than MN4, resulting in a greater pull-down capability than MN4. After startup, the gate voltage of MN2 turns on MN5, which in turn pulls down the voltage at the gate node of MN4, turning off MN4. This ensures that the startup unit no longer affects the normal operation of the entire circuit. Therefore, this embodiment, by starting the operational amplifier first, improves upon the shortcomings of traditional circuits, such as the instability of the negative temperature coefficient and the failure caused by channel modulation effects, compared to starting the bias module from the beginning.

[0039] In some embodiments of this application, the first path is an NMOS element MN0 with its gate and drain shorted, and the source of the NMOS element is grounded. Its function is that MN0 is an NMOS device with its gate and drain shorted; because it is bound to saturate, it raises the bias power supply module by a V. dsat This ensures that the MOSFETs of other modules in the system are in saturation and meets the bias requirements of the current mirror at the lower end of the operational amplifier. The current mirror must be increased by at least one V to ensure the differential input transistor is saturated. dsat The design of the first path here avoids dead points in the system circuit.

[0040] In some embodiments of this application, the NMOS element used to control the connection between the drain of the fifth semiconductor transistor and the ground terminal has a width-to-length ratio greater than that of the NMOS element used to control the connection between the power supply terminal and the ground path of the operational amplifier unit. This embodiment aims to ensure that the pull-down capability of MN5 is greater than that of MN4 by making the width-to-length ratio of MN5 greater than that of MN4, thereby enabling the turn-off of MN4 and avoiding any impact on the normal operation of the circuit.

[0041] Figure 3 A timing diagram illustrating the generation of the bias signal and the confirmation signal according to an embodiment of this application is shown. Figure 3 As shown, the negative temperature current bias circuit provided in this application clamps the branch voltage of the reference power supply module through the negative feedback mechanism of the operational amplifier, and has the advantages of stable output current and Ready signal feedback.

[0042] Therefore, the negative temperature current bias circuit provided in this application changes the main design concept from the bias module of the startup system to the operational amplifier module of the startup system, which improves the main shortcomings of the traditional bias circuit, such as the channel modulation effect causing system failure and the instability of the negative temperature coefficient.

[0043] The embodiments of this application also provide a chip including the aforementioned negative temperature current bias circuit. Chips employing the aforementioned negative temperature current bias circuit also possess the advantages of reliable startup and temperature stability, and have broad application prospects.

[0044] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0045] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A negative temperature current bias circuit, characterized in that, The circuit includes: A reference power supply unit includes: a negative temperature coefficient voltage generating element for generating a voltage with a negative temperature coefficient; a resistor, wherein a first end of the resistor and a low-voltage end of the negative temperature coefficient voltage generating element are both connected to a first path; and a voltage output element for converting the current in the branch containing the resistor into a voltage. An operational amplifier unit is used to control the current flowing through the resistor based on the voltage difference between the second terminal of the resistor and the high-voltage terminal of the negative temperature coefficient voltage generating element. A startup unit is configured to provide a grounding path to the power supply terminal of the operational amplifier unit during startup, and to shut off the grounding path when a bias voltage exists in the operational amplifier unit. The bias output unit includes several semiconductor transistors. The control terminals of the semiconductor transistors are all connected to the output terminals of the voltage output element, and the sources of the transistors are all connected to the operating voltage. The drain of each semiconductor transistor is the bias output terminal.

2. The circuit according to claim 1, characterized in that, The negative temperature coefficient voltage generating element is a bipolar transistor with its base and collector shorted together.

3. The circuit according to claim 1, characterized in that, The reference power supply unit also includes a first semiconductor transistor, which provides a bias voltage to the negative temperature coefficient voltage generating element based on a fixed voltage at its control electrode.

4. The circuit according to claim 1, characterized in that, The operational amplifier unit includes an operational amplifier, the inverting input terminal of which is connected to the second terminal of the resistor, the non-inverting input terminal of which is connected to the high voltage terminal of the negative temperature coefficient voltage generating element, the output terminal of which is connected to the input terminal of the source follower, and the output terminal of the source follower is connected to the second terminal of the resistor.

5. The circuit according to claim 4, characterized in that, The voltage output element is a second semiconductor transistor with its gate and drain shorted together. The output terminal of the voltage output element is either the gate or the drain of the second semiconductor transistor. The output terminal of the voltage output element is connected to the power supply terminal of the source follower.

6. The circuit according to claim 1, characterized in that, The circuit further includes an operational amplifier biasing unit, which includes: A current mirror is used to provide bias current to the operational amplifier unit; The third semiconductor transistor is used to convert the voltage output by the voltage output element into the input current of the current mirror.

7. The circuit according to claim 1, characterized in that, The circuit further includes a startup confirmation unit, which includes: The fourth semiconductor transistor is connected in the same way as any of the semiconductor transistors in the bias output unit. The bias output terminal of the fourth semiconductor transistor is connected to the input terminal of a Schmitt trigger. The output terminal of the Schmitt trigger is used to output a level value, which is used to indicate whether there is a bias current input to its input terminal.

8. The circuit according to claim 3, characterized in that, The startup unit includes: A fifth semiconductor transistor, wherein the control electrode of the fifth semiconductor transistor is connected to the control electrode of the first semiconductor transistor; The drain of the fifth semiconductor transistor is used to control the connection and disconnection between the power supply terminal and the ground path of the operational amplifier unit. The drain of the fifth semiconductor transistor is connected to the ground terminal when the current mirror in the operational amplifier bias unit has an internal bias voltage.

9. The circuit according to claim 1, characterized in that, The first path is an NMOS device with its gate and drain shorted, and the source of the NMOS device is grounded.

10. The circuit according to claim 8, characterized in that, The aspect ratio of the NMOS element used to control the connection between the drain of the fifth semiconductor transistor and the ground terminal is greater than that of the NMOS element used to control the connection between the power supply terminal and the ground path of the operational amplifier unit.

11. A chip, characterized in that, The chip includes the negative temperature current bias circuit as described in any one of claims 1 to 10.

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