System on chip, electronic device, power consumption management method and training method

Abstract

The application discloses a system chip, an electronic device, a power consumption management method and a training method, and belongs to the computer field. The system chip provided by the application comprises a plurality of core particles, a core particle level management module, a plurality of local management modules and a plurality of load modules are contained in a first core particle in the plurality of core particles, and the first core particle is any one of the plurality of core particles; the core particle level management module in the first core particle is coupled with the plurality of local management modules, and the core particle level management module is used for distributing target resources to the plurality of local management modules in the first core particle, and the target resources are resources affecting power consumption; the local management module in the first core particle is used for managing the power consumption of at least one load module in the plurality of load modules in the first core particle.

Description

Technical Field

[0001] This application belongs to the field of computer science, specifically relating to a system-on-a-chip, electronic device, power management method, and training method. Background Technology

[0002] In system-on-a-chip (SoC), power management techniques are typically used to allocate power consumption rationally, thereby optimizing energy efficiency and improving user experience while ensuring product reliability.

[0003] The related technology discloses a power management system architecture for a system-on-a-chip, including a local management module and an overall management module. The local management module is responsible for performing dynamic voltage and frequency regulation and configuring the corresponding clock and power supply, while the overall management module is responsible for voltage and frequency regulation decisions.

[0004] However, in scenarios where a large number of chips are packaged within a system-on-a-chip (SoC), local data from multiple chips often needs to be aggregated into the chip containing the overall management module for processing and decision-making. This process involves cross-chip data transfer. Since cross-chip data transfer takes a considerable amount of time, this results in low power management efficiency for the SoC. Summary of the Invention

[0005] This application provides a system-on-a-chip, an electronic device, a power management method, and a training method to solve the problem of low power management efficiency of system-on-a-chip in related technologies.

[0006] In a first aspect, embodiments of this application provide a system-on-a-chip, including: a plurality of chips, wherein a first chip among the plurality of chips includes a chip-level management module, a plurality of local management modules and a plurality of load modules, and the first chip is any one of the plurality of chips; The chip-level management module within the first chip is coupled to the plurality of local management modules, and the chip-level management module is used to allocate target resources to the plurality of local management modules within the first chip, wherein the target resources are resources that affect power consumption; The local management module within the first core is used to manage the power consumption of at least one of the plurality of load modules within the first core.

[0007] Secondly, embodiments of this application provide an electronic device, including a system-on-a-chip as described in the first aspect.

[0008] Thirdly, embodiments of this application provide a power management method applied to a system-on-a-chip as described in the first aspect, comprising: The chip-level management module provides target resources to the chip-level management module on the first chip. The core-level management module on the first core allocates target resources to the plurality of local management modules on the first core. The local management module on the first chip counts the estimated power consumption of at least one load module on the first chip; The local management module on the first core adjusts the operating parameters of the at least one load module based on the power consumption estimate of the at least one load module on the first core and the target resources allocated by the core-level management module.

[0009] Fourthly, embodiments of this application provide a method for training a power consumption evaluation model, applied to a system-on-a-chip as described in the first aspect, comprising: Obtain the sampled data set of the event counter of the at least one load module and the power consumption measurement data set of the at least one load module; Using the sampled data set of the event counters of the at least one load module and the power consumption measurement data set of the at least one load module, the power consumption evaluation model to be trained is iteratively trained to obtain the target power consumption evaluation model. The power consumption evaluation model to be trained includes a first fully connected neural network layer, which contains M multiplication units, and the M multiplication units correspond to M weight coefficients. The target power consumption evaluation model includes a second fully connected neural network layer, which contains N multiplication units, each corresponding to N weight coefficients; the N weight coefficients are used to configure the power consumption evaluation unit. Where M and N are positive integers, and M is greater than N.

[0010] In this embodiment, the system-on-a-chip (SoC) includes multiple chips. A first chip among the multiple chips contains a chip-level management module, multiple local management modules, and multiple load modules. The first chip is any one of the multiple chips. The chip-level management module in the first chip is coupled to the multiple local management modules, and the chip-level management module is used to allocate target resources to the multiple local management modules in the first chip. The target resources are resources that affect power consumption. The local management modules in the first chip are used to manage the power consumption of at least one load module among the multiple load modules in the first chip. In this way, when a system-on-a-chip (SoC) consists of multiple chips, each chip has a chip-level management module. The chip-level management module on the first chip can be used to allocate target resources to multiple local management modules on the first chip. Each local management module on the first chip is used to manage the power consumption of the load modules on the first chip. This enables the chip-level management module inside the first chip to uniformly manage the power consumption of all load modules on the first chip, without having to aggregate all the local data from multiple chips to the chip where the chip-level management module is located for processing. This reduces the time spent on transmitting local data across chips, thereby improving the power management efficiency of the SoC. Attached Figure Description

[0011] Figure 1 A schematic diagram of a system-on-a-chip provided for some embodiments of this application; Figure 2 A schematic diagram of a system-on-a-chip provided for some embodiments of this application; Figure 3-1 A schematic diagram of a system-on-a-chip provided for some embodiments of this application; Figure 3-2 A schematic diagram illustrating power management of a system-on-a-chip provided for some embodiments of this application; Figure 4 A schematic diagram of a system-on-a-chip provided for some embodiments of this application; Figure 5 A schematic diagram of a system-on-a-chip provided for some embodiments of this application; Figure 6-1 A schematic diagram of a system-on-a-chip provided for some embodiments of this application; Figure 6-2 A schematic diagram illustrating power management of a system-on-a-chip provided for some embodiments of this application; Figure 7 A schematic diagram of a system-on-a-chip provided for some embodiments of this application; Figure 8 A schematic diagram of a system-on-a-chip provided for some embodiments of this application; Figure 9 Schematic diagram of an electronic device provided for some embodiments of this application; Figure 10-1 A schematic flowchart illustrating a power management method provided for some embodiments of this application; Figure 10-2 A schematic diagram illustrating a power management method provided for some embodiments of this application; Figure 11 A schematic flowchart illustrating the training method for a power consumption evaluation model provided for some embodiments of this application; Figure 12 A schematic flowchart illustrating the training method for a power consumption evaluation model provided for some embodiments of this application.

[0012] Explanation of reference numerals in the attached figures: 10 - System-on-a-Chip (SoC); 100 - Chip; 110 - First Chip; 120 - Second Chip; 101 - Chip-level Management Module; 102 - Local Management Module; 1021 - Power Domain Management Module; 1022 - Clock Domain Management Module; PM_DEV_0 - Clock Domain Management Module; PM_DEV_1 - Clock Domain Management Module; PM_DEV_2 - Clock Domain Management Module; 10221 - Power Consumption Evaluation Unit; 10222 - Operating Parameter Adjustment Request Generation Unit; 1023 - Hardware protection unit; 103- Load module; 1031- Target event counter; 1032- Sensor; 104- Chip-level management module; 105- Power supply module; 106- Clock module; 200- First private bus; 300- Second private bus; U1- Multiplier; U2- Adder; U3- First comparator; U4- First register; U5- Second comparator; U6- Second register; Vcc1- First voltage terminal; Vcc2- Second voltage terminal; 90- Electronic equipment. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0014] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0015] The system-on-a-chip, electronic device, power management method, and training method provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0016] Figure 1 A schematic diagram of a system-on-a-chip provided for some embodiments of this application.

[0017] like Figure 1 As shown, the system-on-a-chip 10 provided in this application embodiment may include multiple dies 100. The first die 110 among the multiple dies includes a die-level management module 101, multiple local management modules 102 and multiple load modules 103. The first die 110 is any one of the multiple dies 100. The chip-level management module 101 within the first chip 110 is coupled to multiple local management modules 102, and the chip-level management module 101 is used to allocate target resources to the multiple local management modules 102 within the first chip 110. The target resources are resources that affect power consumption. The local management module 102 within the first core 110 is used to manage the power consumption of at least one of the multiple load modules 103 within the first core 110.

[0018] In the embodiments of this application, the number of chips 100 in the system-on-a-chip 10 is not specifically limited, and the first chip 110 can be any one of the multiple chips 100 included in the system-on-a-chip 10.

[0019] For example, taking a system-on-a-chip 10 as having X chips: chip 1, chip 2, chip 3, ..., chip X, chip 1 among the multiple chips in the system-on-a-chip 10 can be regarded as the first chip 110. Thus, chip 1 is provided with a chip-level management module 101, multiple local management modules 102 and multiple load modules 103.

[0020] For example, in the embodiments of this application, each of the multiple chips 100 included in the system-on-a-chip 10 can be regarded as the first chip 110. Thus, any one of the multiple chips 100 is provided with a chip-level management module 101, multiple local management modules 102 and multiple load modules 103.

[0021] In the embodiments of this application, the chip-level management module 101 in the first chip 110 is connected to each of the plurality of local management modules 102, so that the chip-level management module 101 in the first chip 110 can be used to allocate target resources to each local management module 102 in the first chip 110. The target resources are resources that affect power consumption, and the target resources may include the power consumption budget data of the local management module 102.

[0022] In the embodiments of this application, within the first core 110, each local management module 102 is connected to at least one load module, and each local management module 102 within the first core 110 is used to manage the power consumption of at least one load module connected to the local management module 102 within the first core 110 according to the allocated target resources.

[0023] Thus, in the case where the system-on-a-chip 10 provided in this application embodiment includes multiple chips 100, since each of the multiple chips 100 is provided with a chip-level management module 101, the chip-level management module 101 on the first chip 110 can be used to allocate target resources to multiple local management modules 102 on the first chip 110. Each local management module 102 on the first chip 110 is used to manage the power consumption of the load module 103 on the first chip 110. This realizes that the chip-level management module 101 inside the first chip 110 uniformly manages the power consumption of all load modules 103 on the first chip 110, without having to aggregate all the local data of multiple chips to a chip where the chip-level management module is located for processing, reducing the time spent on cross-chip transmission of local data, thereby improving the power consumption management efficiency of the system-on-a-chip.

[0024] Figure 2 A schematic diagram of a system-on-a-chip provided for some embodiments of this application.

[0025] like Figure 2 As shown, in some embodiments of this application, in order to manage the total power consumption of the system-on-a-chip 10, a chip-level management module 104 is provided in the second chip 120 among the plurality of chips 100 in the system-on-a-chip 10 provided in the embodiments of this application. The second chip 120 is any one of the plurality of chips 100. Chip-level management module 104 is coupled to chip-level management module 101 within the first chip 110, and chip-level management module 104 is used to provide target resources to chip-level management module 101 within the first chip 110.

[0026] In the embodiments of this application, the system-on-a-chip 10 may include a chip-level management module 104, which is used to manage the total power consumption of the system-on-a-chip 10. The total power consumption of the system-on-a-chip 10 is the sum of the power consumption of the multiple chips 100.

[0027] In embodiments of this application, the chip-level management module 104 may be located within the second chip 120, which may be any one of the plurality of chips 100. For example, the second chip 120 may be the main chip of the system-on-a-chip 10.

[0028] In embodiments of this application, where the second chip 120 and the first chip 110 indicate the same chip in the system-on-a-chip 10, the chip may include a chip-level management module 104, a chip-level management module 101, multiple local management modules 102, and multiple load modules 103.

[0029] In the embodiments of this application, the chip-level management module 104 is coupled to the chip-level management module 101 within the first chip 110, and the chip-level management module 104 is used to provide target resources to the chip-level management module 101 within the first chip 110.

[0030] Thus, by setting a chip-level management module 104 within the system-on-a-chip 10 provided in this application embodiment, and coupling the chip-level management module 104 with the granular management module 101 within the system-on-a-chip 10, it can be regarded as the overall management module of the system-on-a-chip 10, providing target resources to the granular management module 101 within the first granular chip 110, thereby realizing the management of the total power consumption of the system-on-a-chip 10, for example, realizing the assessment and allocation of the total power consumption of the system-on-a-chip 10.

[0031] Figure 3-1 A schematic diagram of a system-on-a-chip provided for some embodiments of this application.

[0032] like Figure 3-1 As shown, in some embodiments of this application, in order to achieve power consumption management for each chip within the system-on-a-chip 10, the number of chip-level management modules 101 in the system-on-a-chip 10 provided in the embodiments of this application is the same as the number of chips 100; each of the plurality of chips 100 includes one chip-level management module 101. The chip-level management module 104 is coupled to multiple chip-level management modules 101 corresponding to multiple chips 100.

[0033] In the embodiments of this application, each of the plurality of cores 100 can be regarded as the first core 110, and each of the plurality of cores 100 can include a core-level management module 101, a plurality of local management modules 102 and a plurality of load modules 103.

[0034] In the embodiments of this application, a second chip 120 exists among the plurality of chips 100. The second chip 120 may include a chip-level management module 104, a chip-level management module 101, a plurality of local management modules 102, and a plurality of load modules 103.

[0035] In the embodiments of this application, the chip-level management module 104 can be connected to multiple chip-level management modules 101 corresponding to multiple chips 100, so that the chip-level management module 104 is used to allocate target resources to the multiple chip-level management modules 101 corresponding to multiple chips 100.

[0036] In the embodiments of this application, each of the multiple granular management modules 101 can be used to allocate target resources to each local management module 102 within the same granularity.

[0037] In this way, by setting a chip-level management module 104 in the system-on-a-chip 10 provided in this application embodiment, the chip-level management module 104 is connected to multiple chip-level management modules 101 corresponding to multiple chips 100 in the system-on-a-chip 10. The chip-level management module 104 provides target resources to each chip-level management module 101. Then, each chip-level management module 101 allocates target resources to each local management module 102 in its own chip, thereby realizing power consumption management of each chip in the system-on-a-chip 10.

[0038] like Figure 3-1 As shown, in some embodiments of this application, in order to avoid existing bus congestion or hang-up affecting power management services, in the system-on-a-chip 10 provided in some embodiments of this application, the chip-level management module 104 is connected to the chip-level management module 101 in the first chip 110 via the first private bus 200, and the chip-level management module 101 is connected to multiple local management modules 102 via the second private bus 300. Among them, the first private bus 200 and the second private bus 300 are both buses dedicated to power management services.

[0039] In the embodiments of this application, the first private bus 200 and the second private bus 300 can be power management private buses (PMPB). Hereinafter, the power management private bus will be simply referred to as the power management bus. The power management bus can be a low-speed global bus dedicated to power management services, and this bus does not carry other services.

[0040] Thus, in the system-on-a-chip 10 provided in this application embodiment, a private bus dedicated to power management services is used to transmit data between the chip-level management module 104, the chip-level management module 101, and the local management module 102. This can prevent bus congestion or hang-ups from affecting power management services and causing system abnormalities. Furthermore, power management services are not sensitive to latency, and the additional overhead of using a low-speed global bus to the system is relatively small.

[0041] In some embodiments of this application, the management level of the chip-level management module 104 is higher than that of the chip-level management module 101, and the management level of the chip-level management module 101 is higher than that of the local management module 102. It should be noted that higher-level management modules have longer management cycles, while lower-level management modules have shorter management cycles, in order to improve the responsiveness to real-time services and thus improve the energy efficiency of the system-on-a-chip.

[0042] For example, such as Figure 3-2 As shown, taking a system-on-a-chip (SoC) 10 comprising X granules: granule 1, granule 2, granule 3, ..., granule X, and each granule comprising Y local management modules: PM1, PM2, ..., PMY, for a single granule, the sum of the power resources allocated to the Y local management modules 102 within that granule is equal to the power resources allocated to the corresponding granule-level management module 101. For the entire SoC 10, the sum of the power resources allocated to the X granule-level management modules 101 corresponding to the X granules is equal to the total power resources of the SoC 10, where the total power resources can be determined by the TDP (Thermal Design Power) of the SoC 10.

[0043] Wherein, the first cycle T1 is the time period during which the chip-level management module 104 provides target resources to the chip-level management module 101 within the first chip 110, the second cycle T2 is the time period during which the chip-level management module 101 allocates target resources to multiple local management modules 102 within the first chip 110, and the third cycle T3 is the time period during which the local management module 102 manages the power consumption of at least one load module among multiple load modules 103 within the first chip 110. The first cycle T1 is greater than the second cycle T2, and the second cycle T2 is greater than the third cycle T3.

[0044] The power management function is a periodic operation, with the first cycle T1, the second cycle T2, and the third cycle T3 being low-speed loops. For example, the first cycle T1 can be 1500us, the second cycle T2 can be 1000us, and the third cycle T3 can be 500us.

[0045] In this way, since lower-level management modules have shorter management cycles, they can improve their responsiveness to real-time services, thereby improving the energy efficiency of the system-on-a-chip.

[0046] In some embodiments of the system-on-a-chip 10 provided in this application, in order to manage the power consumption of the load module, the local management module 102 provided in some embodiments of this application can manage the power consumption of at least one load module 103 by adjusting at least one of the power supply voltage and clock frequency of at least one load module 103 based on the estimated power consumption value of at least one load module 103 and the target resources allocated by the chip-level management module 101, thereby optimizing energy efficiency while ensuring the stable operation of the load module 103. Examples are given below.

[0047] Figure 4 A schematic diagram of a system-on-a-chip provided for some embodiments of this application.

[0048] like Figure 4 As shown, in some embodiments of this application, taking the adjustment of the power supply voltage of at least one load module 103 by the local management module 102 as an example, in the system-on-a-chip 10 provided in some embodiments of this application, the local management module 102 may include a power domain management module 1021; the power domain management module 1021 is connected to the chip-level management module 101 and at least one load module 103 respectively. The first core 110 also includes a power module 105, which is connected to the power domain management module 1021 and at least one load module 103 respectively. The power domain management module 1021 is used to adjust the voltage output by the power module 105 to the at least one load module 103 based on the power consumption estimate of at least one load module 103 and the target resources allocated by the granular management module 101.

[0049] In the embodiments of this application, the power domain management module 1021 is connected to the power module 105 via a configuration bus, the power module 105 is connected to at least one load module 103 via a power line, and the power domain management module 1021 is connected to the load module 103 via a power management bus.

[0050] In embodiments of this application, the power domain management module 1021 is used to configure the power module 105 according to the power consumption estimate of at least one load module 103 and the target resources allocated by the granular management module 101, thereby adjusting the power supply voltage of the load module 103, or turning the power module 105 on / off.

[0051] Thus, in the system-on-a-chip 10 provided in this application embodiment, since the local management module 102 includes a power domain management module 1021, the power domain management module 1021 adjusts the voltage output by the power module 105 to at least one load module 103 based on the power consumption estimate of at least one load module 103 and the target resources allocated by the chip-level management module 101, thereby managing the power consumption of at least one load module 103 and optimizing energy efficiency while ensuring the stable operation of the load module 103.

[0052] Figure 5 A schematic diagram of a system-on-a-chip provided for some embodiments of this application.

[0053] like Figure 5 As shown, in some embodiments of this application, taking the adjustment of the clock frequency of at least one load module 103 by the local management module 102 as an example, in the system-on-a-chip 10 provided in some embodiments of this application, the local management module 102 includes a clock domain management module 1022; the clock domain management module 1022 is connected to the chip-level management module 101 and the load module 103 respectively. The first chip 110 also includes a clock module 106, which is connected to the clock domain management module 1022 and the load module 103 respectively. The clock domain management module 1022 is used to adjust the clock signal output by the clock module 106 to at least one load module 103 based on the power consumption estimate of at least one load module 103 and the target resources allocated by the granular management module 101.

[0054] In the embodiments of this application, the clock domain management module 1022 is connected to the clock module 106 via a configuration bus, the clock module 106 is connected to at least one load module 103, and the clock domain management module 1022 is connected to the load module 103 via a power management bus.

[0055] In embodiments of this application, the clock domain management module 1022 is used to configure the clock module 106 according to the power consumption estimate of at least one load module 103 and the target resources allocated by the granular management module 101, thereby adjusting the clock frequency of the load module 103, or turning the clock module 106 on / off.

[0056] Thus, in the system-on-a-chip 10 provided in this application embodiment, since the local management module 102 includes a clock domain management module 1022, the clock domain management module 1022 adjusts the clock frequency of the electrical load module 103 according to the power consumption estimate of at least one load module 103 and the target resources allocated by the chip-level management module 101, thereby managing the power consumption of at least one load module 103 and optimizing energy efficiency while ensuring the stable operation of the load module 103.

[0057] Figure 6-1 A schematic diagram of a system-on-a-chip provided for some embodiments of this application.

[0058] like Figure 6-1 As shown, in some embodiments of this application, taking the adjustment of the power supply voltage and clock frequency of at least one load module 103 by the local management module 102 as an example, in the system-on-a-chip 10 provided in some embodiments of this application, the local management module 102 includes a power domain management module 1021 and a clock domain management module 1022, the power domain management module 1021 and the clock domain management module 1022 are connected; the power domain management module 1021 is connected to the chip-level management module 101, and the clock domain management module 1022 is connected to the load module 103; The first core 110 also includes a power module 105 and a clock module 106. The power module 105 is connected to the power domain management module 1021 and the load module 103 respectively, and the clock module 106 is connected to the clock domain management module 1022 and the load module 103 respectively. The power domain management module 1021 is used to adjust the voltage output by the power module 105 to the at least one load module 103 based on the power consumption estimate of at least one load module 103 and the target resources allocated by the granular management module 101. The clock domain management module 1022 is used to adjust the clock signal output by the clock module 106 to at least one load module 103 based on the power consumption estimate of at least one load module 103 and the target resources allocated by the granular management module 101.

[0059] In the embodiments of this application, the power management system architecture of the system-on-a-chip 10 includes four management levels: chip-level management module 104, granular-level management module 101, power domain management module 1021, and clock domain management module 1022. The management level of chip-level management module 104 is higher than that of granular-level management module 101, the management level of granular-level management module 101 is higher than that of power domain management module 1021, and the management level of power domain management module 1021 is higher than that of clock domain management module 1022. The management modules at each level are connected via a power management bus.

[0060] In the embodiments of this application, a clock domain management module 1022 can be connected to a load module 103 for clock management, activity monitoring, low power request, power consumption estimation, and voltage and frequency regulation request of the load module 103.

[0061] The clock management refers to the clock domain management module 1022 configuring the clock module through the configuration bus, modifying the clock frequency of the load module, or enabling / disabling the clock module 106; the configuration bus includes, but is not limited to, the Advanced Peripheral Bus (APB), and the clock module 106 includes, but is not limited to, the Phase Locking Loop (PLL).

[0062] The activity monitoring refers to the clock domain management module 1022 periodically sampling the target event counter results output by the load module 103 according to a preset period, and determining whether the load module 103 is currently in an active state or an idle state based on the difference between two consecutive sampling results of the target event counter; wherein the criteria for determining whether the current load module 103 is in an idle state may include, but are not limited to, the difference between two consecutive sampling results being zero.

[0063] The low-power request refers to the clock domain management module 1022 starting to record the duration of the load module 103's idle state when it determines that the load module 103 is in an idle state. For example, if the duration of the load module 103's idle state exceeds a first threshold, it requests to enter a first low-power state, and this low-power request is sent to the power domain management module 1021 via the power management bus. For example, if the duration of the load module 103's idle state exceeds a second threshold, it requests to enter a second low-power state, the energy-saving effect of which is higher than that of the first low-power state, and this request is sent to the power domain management module 1021 via the power management bus. For another example, if the load module 103 recovers from an idle state to an active state, it requests to enter a normal state, and this request is sent to the power domain management module 1021 via the power management bus. The low-power request includes information about a target state, which includes a normal state, a first low-power state, or a second low-power state.

[0064] The power consumption estimation refers to the clock domain management module 1022 periodically sampling the target event counter results output by the load module according to the third cycle T3, and performing a fully connected neural network calculation based on the difference between the two sampling results of the target event counter to obtain the power consumption estimate of the load module.

[0065] The voltage and frequency adjustment request refers to the clock domain management module 1022 determining whether voltage and frequency adjustment are needed based on multiple power consumption estimates and power consumption budgets of the load module 103 over a past period. For example, the multiple power consumption estimates are weighted and averaged to obtain an average power consumption value; a third threshold and a fourth threshold are determined based on the power consumption budget. For example, when the average power consumption value is higher than the third threshold, a request is made to raise the operating point of the load module 103 by one level, and this request is sent to the power domain management module 1021 via the power management bus; when the average power consumption value is lower than the fourth threshold, the clock frequency is first reduced via the configuration bus, and then a request is made to lower ... reduced via the configuration bus, and then a request is made to lower the operating point of the load module 103 by one level, and when the average power consumption value is lower than the fourth threshold, the clock frequency is reduced via the configuration bus, and then a request is made to lower the operating point of the load module 103 by one level, and so on. When the current control cycle is between the third and fourth threshold values, a request is made to ensure that the operating point of the load module 103 does not change. This request is sent to the power domain management module 1021 via the power management bus. The power budget is determined by the target resources allocated by the granular management module 101 and is updated periodically according to the second cycle T2. The operating point level is divided in 50MHz increments, for example, operating point level 10 is 1000MHz, operating point level 9 is 950MHz, ..., and operating point level 0 is 500MHz. The voltage and frequency regulation request includes: request type (e.g., one of operating point increase request, operating point decrease request, or operating point hold request), number of control cycles (e.g., 0, 1, 2, ..., increasing in increments of 1, and resetting to zero upon overflow and restarting the increment), and power consumption estimate.

[0066] In the embodiments of this application, a power domain management module 1021 may be connected to multiple clock domain management modules 1022 for power management and responding to voltage and frequency regulation requests and low power consumption requests from the clock domain management modules 1022.

[0067] The power management refers to the power domain management module 1021 configuring the power module 105 through the configuration bus, adjusting the power supply voltage of the load module 103, or turning the power module 105 on / off; the configuration bus includes, but is not limited to, the Advanced Peripheral Bus (APB), etc., and the power module 105 includes, but is not limited to, the Integrated Voltage Regulator (IVR), etc.

[0068] The response to the voltage and frequency adjustment request from the clock domain management module 1022 refers to the following: the power domain management module 1021 can first select the corresponding voltage value according to the type of the received request; if it is a request to increase the operating point, it will determine whether the power consumption after the boost will exceed the power budget based on the power consumption estimate of the load module 103; if not, it will complete the power boost through the configuration bus and then return an acceptance response to the clock domain management module 1022 through the power management bus; if yes, it will return a rejection response to the clock domain management module 1022 through the power management bus; if it is a request to decrease the operating point, it will complete the power buck through the configuration bus and then return an acceptance response to the clock domain management module 1022 through the power management bus; if it is a request to save the operating point, it will directly return an acceptance response to the clock domain management module 1022 through the power management bus. The above description pertains to a one-to-one relationship between the clock domain management module 1022 and the power domain management module 1021. If the relationship is many-to-one, the specific process is as follows: Figure 6-2 As shown. In Figure 6-2 In the described scenario, the power domain management module 1021 is responsible for connecting with three clock domain management modules 1022 (e.g., PM_DEV_0, PM_DEV_1, PM_DEV_2), and in the previous control cycle (e.g., time node t0), the operating points WP of PM_DEV_0, PM_DEV_1, and PM_DEV_2 are denoted as n0, n1, and n2, respectively. At time node t1, the power domain management module 1021 receives a voltage and frequency adjustment request from PM_DEV_0. The request type is a working point reduction request, the number of control cycles is n, and the power consumption estimate is p0. The power domain management module 1021 refreshes the recorded working point of PM_DEV_0 to n0-1 and records the power consumption estimate as p0. However, it does not perform power configuration but waits for PM_DEV_1 and PM_DEV_2 to send voltage and frequency adjustment requests with a control cycle of n. At time node t2, the power domain management module 1021 receives a voltage and frequency regulation request from PM_DEV_1. The request type is an operating point hold request, the number of control cycles is n, and the power consumption estimate is p1. The power domain management module 1021 refreshes the recorded operating point of PM_DEV_1 to n1 and records the power consumption estimate as p1, but does not perform power configuration and continues to wait for PM_DEV_2 to send a voltage and frequency regulation request with a control cycle of n. At time node t3, the power domain management module 1021 receives a voltage and frequency adjustment request from PM_DEV_2. The request type is an operating point adjustment request, the number of control cycles is n, and the power consumption estimate is p2. The power domain management module 1021 refreshes the recorded operating point of PM_DEV_2 to n2+1 and records the power consumption estimate as p2. Then, the power domain management module 1021 can make operating point decisions: if the highest operating point of PM_DEV_0, PM_DEV_1, and PM_DEV_2 is in the current control cycle. Not exceeding the highest operating point of the previous control cycle Then the working point is refreshed to the highest working point of the current control cycle. If the highest operating point of PM_DEV_0, PM_DEV_1, and PM_DEV_2 is in the current control cycle... Exceeding the highest operating point of the previous control cycle The sum of the power consumption estimates based on PM_DEV_0, PM_DEV_1, and PM_DEV_2 Make decisions based on power budget (PB), for example, if Then the working point is refreshed to the highest working point of the current control cycle. Otherwise, the operating point remains the highest operating point of the previous control cycle. .

[0069] After determining the operating point, the power domain management module 1021 can perform corresponding voltage configuration actions. If the operating point is increased, the power supply is boosted through the configuration bus; if the operating point is decreased, the power supply is bucked through the configuration bus; if the operating point remains unchanged, no power supply adjustment is required. Finally, a response is returned to the three clock domain management modules 1022 through the power consumption management bus: if the determined operating point is not lower than the operating point requested by the load module, an acceptance response is returned; otherwise, a rejection response is returned.

[0070] The response to the low-power request from the clock domain management module 1022 means that the power domain management module 1021 can take corresponding actions based on the target state contained in the received low-power request. For example, if the target state is a first low-power state, the power supply voltage is reduced to the voltage value corresponding to operating point level 0 via the configuration bus, and then an acceptance response is returned to the clock domain management module 1022 via the power management bus. For example, if the target state is a second low-power state, the power supply is turned off via the configuration bus, and then an acceptance response is returned to the clock domain management module 1022 via the power management bus. For another example, if the target state is a normal state, the power supply is turned on via the configuration bus and the voltage is set to the voltage value corresponding to the current operating point of the load module, and then an acceptance response is returned to the clock domain management module 1022 via the power management bus. If the clock domain management module 1022 and the power domain management module 1021 have a many-to-one relationship, then the power domain management module 1021 must take corresponding actions based on the shallowest target state of the multiple clock domain management modules 1022. In this invention example, the depth of the target state is as follows: the normal state is the shallowest, and the second low-power state is the deepest.

[0071] In summary, the power domain management module 1021 can maintain two tables internally: a target state table for each clock domain management module 1022 and an operating point table for each clock domain management module 1022. The low-power request is processed in real time, meaning that when the power domain management module 1021 receives a low-power request from a clock domain management module 1022, it immediately refreshes the target state table and takes action based on the shallowest state of the current target state table. The voltage and frequency adjustment requests are processed uniformly, meaning that in any control cycle, although the power domain management module 1021 refreshes the operating point table immediately upon receiving a voltage and frequency adjustment request from a clock domain management module 1022, it sets the corresponding voltage value based on the operating point obtained from the decision after receiving voltage and frequency adjustment requests from all clock domain management modules 1022.

[0072] In the embodiments of this application, a chip-level management module 101 can be connected to multiple power domain management modules 1021 on the same chip, for periodically performing chip power consumption estimation and chip power consumption allocation according to a second period T2.

[0073] The chip power consumption estimation refers to the chip-level management module 101 obtaining the total chip power consumption by reading the power consumption estimation values ​​of all clock domain management modules 1022 within the chip and summing them; or by reading the event registers of all load modules 103 within the chip and then calculating the total chip power consumption based on the values ​​of the event registers. This application does not impose specific limitations on this.

[0074] The chip power allocation refers to the chip-level management module 101 allocating the chip power budget PB set by the chip-level management module 104 to all power domain management modules 1021 within the chip and all clock domain management modules 1022 at the next lower level. That is, setting the third threshold value and the fourth threshold value corresponding to all clock domain management modules 1022. The power allocation scheme includes, but is not limited to, equal allocation, linear allocation based on the average power consumption value of the load module over a period of time, etc. This application does not impose specific restrictions on this.

[0075] In the embodiments of this application, a chip-level management module 104 can be connected to multiple chip-level management modules 101 to periodically estimate the total chip power consumption and allocate the total chip power consumption according to a first cycle T1.

[0076] The total power consumption estimation of the chip refers to the total power consumption estimation value of the chip obtained by the chip-level management module 104 by reading the power consumption estimation values ​​of all chip-level management modules 101 and summing them; or by reading the power consumption data of the power module on the circuit board outside the system-on-a-chip 10 and summing them. This application does not impose specific limitations on this.

[0077] The total power consumption allocation of the chip refers to the chip-level management module 104 allocating the TDP to all chip-level management modules 101 according to the product specifications of the system-on-a-chip 10, such as the thermal design power (TDP). The power consumption allocation scheme includes, but is not limited to, equal allocation, linear allocation based on the average power consumption estimate of the chip over a period of time, etc. This application does not impose specific limitations on this.

[0078] Thus, in the system-on-a-chip 10 provided in this application embodiment, since the local management module 102 includes a power domain management module 1021 and a clock domain management module 1022, the clock domain management module 1022 adjusts the clock frequency of the electrical load module 103 according to the power consumption estimate of at least one load module 103 and the target resources allocated by the chip-level management module 101. At the same time, the power domain management module 1021 adjusts the power supply voltage of the electrical load module 103 according to the power consumption estimate of at least one load module 103 and the target resources allocated by the chip-level management module 101, thereby managing the power consumption of at least one load module 103 and optimizing energy efficiency while ensuring the stable operation of the load module 103.

[0079] Figure 7 A schematic diagram of a system-on-a-chip provided for some embodiments of this application.

[0080] ,like Figure 7As shown, in some embodiments of this application, in order to enable power management services to be localized and improve management efficiency, the system-on-a-chip 10 provided in some embodiments of this application includes a clock domain management module 1022, which includes a power consumption evaluation unit 10221 and a working parameter adjustment request generation unit 10222. The power consumption evaluation unit 10221 is connected to the working parameter adjustment request generation unit 10222; the power consumption evaluation unit 10222 is connected to a target event counter 1031 in at least one load module 103.

[0081] In the embodiments of this application, the clock domain management module 1022 includes a power consumption evaluation unit 10221 and a working parameter adjustment request generation unit 10222. The power consumption evaluation unit 10221 performs a high-precision estimation of the power consumption of the load module 103 to obtain the power consumption estimate value of the load module 103. The working parameter adjustment request generation unit 10222 generates a working parameter adjustment request based on the power consumption estimate value of the load module 103 and the target resources allocated by the chip-level management module 101. The working parameter adjustment request includes, but is not limited to, frequency modulation request, voltage regulation request, and frequency and voltage modulation request.

[0082] For example, in some embodiments of the system-on-a-chip 10 provided in this application, the power consumption evaluation unit 10221 is used to perform fully connected neural network calculations on the sampled data from the target event counter 1031 to obtain the power consumption estimate of at least one load module 103. The sampled data includes the difference between two count results obtained from two consecutive counts by the target event counter 1031; In some embodiments of the system-on-a-chip 10 provided in this application, the operating parameter adjustment request generation unit 10222 is used to generate an operating parameter adjustment request based on the power consumption estimate of at least one load module 103 and the target resources allocated by the chip-level management module 101. The operating parameter adjustment request is used to adjust the operating parameters of at least one load module 103. The operating parameters include at least one of the voltage output by the power supply module 105 to at least one load module 103 and the clock signal output by the clock module 106 to at least one load module 103.

[0083] Thus, in the system-on-a-chip 10 provided in this application embodiment, the clock domain management module 1022 in the local management module 102 can estimate the power consumption of the load module 103, and generate a working parameter adjustment request based on the power consumption of the load module 103 and the target resources allocated by the chip-level management module 101. As a result, the local management module 102 can make working parameter adjustment decisions without the chip-level management module 104 having to make working parameter adjustment decisions, so that power consumption management services can be decentralized to the local management module, thereby improving management efficiency.

[0084] In some embodiments of this application, when the local management module 102 includes a power domain management module 1021 and a clock domain management module 1022, the power domain management module 1021 is used to receive a working parameter adjustment request output by the clock domain management module 1022, and adjust the working parameters of at least one load module 103 according to the working parameter adjustment request.

[0085] For example, the power domain management module 1021 adjusts the power supply voltage of at least one load module 103 according to the operating parameter adjustment request. Thus, in the system-on-a-chip 10 provided in this embodiment, the operating parameter adjustment request output by the power domain management module 1021 and the clock domain management module 1022 adjusts the power supply voltage output by the power module 105 to at least one load module 103, thereby managing the power consumption of at least one load module 103 and optimizing energy efficiency while ensuring stable operation of the load module 103.

[0086] In some embodiments of this application, such as Figure 8 As shown, in order to make high-precision estimation of the power consumption of the load module, in the system-on-a-chip 10 provided in some embodiments of this application, the total number of event counters in at least one load module 103 is M, and the target event counter 1031 includes N event counters selected from the M event counters; where M is greater than N, and N is a positive integer greater than 1.

[0087] Thus, in the system-on-a-chip 10 provided in this application embodiment, N event counters selected from M event counters in the load module 103 are used as target event counters 1031. By filtering the number of event counters, a high-precision estimation of the power consumption of the load module 103 can be achieved.

[0088] In some embodiments of this application, such as Figure 8 As shown, in order to perform high-precision estimation of the power consumption of the load module, the power consumption evaluation unit 10221 may include a fully connected neural network layer. The fully connected neural network layer includes N multipliers U1 and one adder U2. All N multipliers U1 are connected to the adder U2, and N target event counters 1031 are connected to the N multipliers U1.

[0089] In the fully connected neural network layer, N multipliers U1 have N weight coefficients, with one weight coefficient corresponding to one multiplier U1; the N weight coefficients are trained based on the sampled data set of M event counters in at least one load module and the power consumption measurement data set of at least one load module.

[0090] In this approach, the bit width of the N weight coefficients corresponding to the N multipliers is kept as small as possible to save hardware resources. For example, the bit width of the weight coefficients can be 8 bits, where the high 4 bits represent the integer part and the low 4 bits represent the fractional part. In this way, hardware resources are saved by using low-bit-width weight coefficients.

[0091] The formula for estimating the power consumption of load module 103 is as follows: ; in, , … These are the N weight coefficients corresponding to the N multipliers; , … These are the differences between two consecutive counts of the first target event counter, the difference between two consecutive counts of the second target event counter, ..., the difference between two consecutive counts of the Nth target event counter, and b is the bias parameter of adder U2.

[0092] The difference between two consecutive counts of the target event counter can reflect the change in the target event counter data.

[0093] The sampled data set of the M event counters in the load module can include sampled data from at least two scenarios, thereby enabling high-precision estimation of the power consumption of the load module 103 through multi-scenario hybrid neural network training.

[0094] Thus, in the system-on-a-chip 10 provided in this application embodiment, a fully connected neural network structure with low bit width weight coefficients is used, and the number of target event counters of the load module 103 is filtered, and multi-scenario hybrid neural network training is performed to achieve high-precision estimation of the power consumption of the load module 103, thereby enabling power management services to be localized and improving management efficiency.

[0095] For example, such as Figure 8 As shown, in some embodiments of the system-on-a-chip 10 provided in this application, the operating parameter adjustment request generation unit 10222 may include a first comparator U3 and a first register U4. The first input terminal of the first comparator U3 is connected to the first voltage terminal Vcc1, the second input terminal of the first comparator U3 is connected to the output terminal of the power consumption evaluation unit 10221, and the output terminal of the first comparator U3 is connected to the first register U4; wherein, the first voltage V of the first voltage terminal Vcc1 is... th1 The target resources are obtained based on the allocation of the core-level management module 101.

[0096] In the embodiments of this application, the first voltage V is determined according to the target resources allocated by the granular management module 101.th1 First voltage V th1 It can be the third threshold value mentioned above. When the power consumption estimate of the load module 103 is higher than the third threshold value, the first data is output and stored in the first register U4. The first data is used to generate an operating point up adjustment request, which is sent to the power domain management module 1021 through the power management bus. When the power consumption estimate of the load module 103 is not higher than the third threshold value, the second data is output and stored in the first register U4. The second data is used to generate an operating point hold request, which is sent to the power domain management module 1021 through the power management bus.

[0097] To further improve the accuracy of working parameter adjustment requests, such as Figure 8 As shown, in some embodiments of the system-on-a-chip 10 provided in this application, the operating parameter adjustment request generation unit 10222 further includes a second comparator U5 and a second register U6; the first input terminal of the second comparator U5 is connected to the output terminal of the power consumption evaluation unit 10221, the second input terminal of the second comparator U5 is connected to the second voltage terminal Vcc2, and the output terminal of the second comparator U5 is connected to the second register U6; wherein, the second voltage V of the second voltage terminal Vcc2 is... th2 Based on the target resources allocated by the core-level management module 101, the first voltage V of the first voltage terminal Vcc1 is obtained. th1 The second voltage V is greater than the second voltage terminal Vcc2. th2 .

[0098] In the embodiments of this application, the second voltage V is determined according to the target resources allocated by the granular management module 101. th2 The second voltage V th2 It can be the fourth threshold value mentioned above. When the power consumption estimate of the load module 103 is lower than the fourth threshold value, the third data is output and stored in the second register U6. The third data is used to generate an operating point downgrade request, which is sent to the power domain management module 1021 through the power management bus. When the power consumption estimate of the load module 103 is not lower than the fourth threshold value, the fourth data is output and stored in the second register U6. The fourth data is used to generate an operating point hold request, which is sent to the power domain management module 1021 through the power management bus.

[0099] In some embodiments of this application, the local management module 102 will implement protective measures for unexpected and urgent abnormal events, such as voltage drops, overheating, and overcurrent. These protective measures may include reducing the clock frequency or shutting down the clock. The protective measures are lifted once the alarm signal is cleared. These actions are non-periodic, and the delay from the occurrence of the event to the implementation of the protective measures is, for example, 10 ns, constituting a high-speed loop. This high-speed loop can improve system energy efficiency while reducing the risk of system failure and damage, thereby enhancing system robustness.

[0100] For example, such as Figure 7 As shown, in order to improve system robustness, in some embodiments of the system-on-a-chip 10 provided in this application, the local management module 102 may further include a hardware protection unit 1023, which is connected to a sensor 1032 in at least one load module 103; the hardware protection unit 1023 is used to generate a protection enable signal based on the alarm signal output by the sensor 1032, and the protection enable signal is used to lower the operating parameters of at least one load module 103.

[0101] In the embodiments of this application, the protection enable signal is specifically used to lower the clock frequency of the load module 103, or turn off the clock module 106, or lower the power supply voltage of the load module 103, or turn off the power module 105.

[0102] Thus, in the system-on-a-chip 10 provided in this application embodiment, the hardware protection unit 1023 included in the local management module 102 provides protection measures, which improves system energy efficiency, reduces the risk of system crashes and damage, and thereby improves system robustness.

[0103] Furthermore, to save power, the clock domain management module may also include an activity detection unit (not shown in the figure). The input of the activity detection unit is connected to an event counter in at least one load module, and the input of the activity detection unit is connected to the power domain management module. The activity detection unit can be used to generate a low-power request based on the change in event counter data. In this way, the clock domain management module is used to request low-power power, and the power domain management module is used to respond to the low-power request, thereby saving power consumption of the load modules.

[0104] The system-on-a-chip 10 provided in this application embodiment manages the power consumption of all load modules 103 within the chip by a chip-level management module 101, without needing to aggregate local data from multiple chips to a single chip where the chip-level management module resides for processing. This reduces the time spent transmitting local data across chips, thereby improving the power management efficiency of the system-on-a-chip. Furthermore, higher-level management modules have longer management cycles, while lower-level management modules have shorter management cycles, improving responsiveness to real-time services and thus enhancing the energy efficiency of the system-on-a-chip. In addition, the local clock domain management module 1022 can make frequency and voltage adjustment decisions without requiring the chip-level management module 104 to do so, allowing power management services to be handled locally, thus improving management efficiency. In terms of cost, the power management system architecture provided in this application includes four management levels: chip-level management module 104, chip-level management module 101, power domain management module 1021 and clock domain management module 1022. It has universality and can be adapted to multi-chip SOC (System on Chip) products with different architectures, thereby reducing design costs.

[0105] Based on a concept similar to the system-on-a-chip provided in the above embodiments, some embodiments of this application also provide an electronic device.

[0106] like Figure 9 As shown, some embodiments of this application provide an electronic device 90 including a system-on-a-chip 10.

[0107] It should be noted that the electronic device 90 includes the system-on-a-chip 10 provided in any of the above embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0108] Based on a concept similar to the system-on-a-chip provided in the above embodiments, this application also provides a power management method.

[0109] like Figure 10-1 As shown, some embodiments of this application provide a power management method applied to the system-on-a-chip provided in the above embodiments of this application. The power management method includes: Step 1010: The chip-level management module provides the target resources to the chip-level management module on the first chip; Step 1020: The core-level management module on the first core allocates target resources to multiple local management modules on the first core; Step 1030: The local management module on the first chip counts the estimated power consumption of at least one load module on the first chip; Step 1040: The local management module on the first chip adjusts the operating parameters of at least one load module based on the power consumption estimate of at least one load module on the first chip and the target resources allocated by the chip-level management module.

[0110] Thus, according to the power management method provided in the embodiments of this application, since each of the multiple chips is provided with a chip-level management module, the chip-level management module on the first chip can be used to allocate target resources to multiple local management modules on the first chip. Each local management module on the first chip is used to manage the power consumption of the load module on the first chip. This realizes that the chip-level management module inside the first chip can uniformly manage the power consumption of all load modules on the first chip, without having to aggregate all the local data of multiple chips to a single chip where the chip-level management module is located for processing. This reduces the time spent on transmitting local data across chips, thereby improving the power management efficiency of the system-on-a-chip.

[0111] In practical applications, such as Figure 10-2 As shown, the power management method provided in this application embodiment may include the following steps: Step 1: The chip-level management module 104 reads chip data from each chip-level management module 101 under its jurisdiction according to the first cycle T1. The chip data includes, but is not limited to, chip power consumption data, chip temperature data, etc. Step 2: After reading the chip data a certain number of times, the chip-level management module 104 reallocates the power consumption budget of each chip and sends the reallocated power consumption budget to each chip-level management module 101; wherein, during system initialization, the power consumption budget of each chip can be initialized and allocated in an average manner. Step 3: The core-level management module 101 reads power domain data from the various power domain management modules 1021 under its jurisdiction according to the second cycle T2. The power domain data includes, but is not limited to, power domain power consumption data, power domain temperature data, etc. Step 4: After reading the power domain data a certain number of times, the chip-level management module 101 reallocates the power consumption budget of each power domain management module 1021 and sends the reallocated power consumption budget to the clock domain management module 1022; wherein, during system initialization, the power consumption budget of each power domain can be initialized and allocated in an average manner. Step 5: The clock domain management module 1022 periodically reads the activity information from the connected load module 103 according to the third cycle T3. The activity information includes, but is not limited to, device activity status indication signals, event counter data, etc. Step 6: Based on the changes in event counter data and the power consumption evaluation unit, the clock domain management module 1022 sends a voltage and frequency adjustment request to the power domain management module 1021. This behavior is a periodic behavior. Step 7: When the load module 103 has been idle for a long time, the clock domain management module 1022 sends a low power request to the power domain management module 1021. This signal is a non-periodic behavior. The determination that the load module 103 is idle is based on the fact that the active state indication signal of the load module 103 is invalid, or the change in the event counter data is zero. Step 8: The power domain management module 1021 immediately processes the received low-power request; the power domain management module 1021 periodically processes the received voltage and frequency adjustment requests and makes a decision to reject or accept; the power domain management module 1021 feeds back the rejection or acceptance decision to the clock domain management module 1022. Step 9: When the power domain management module 1021 sends the received response back to the clock domain management module 1022, the clock domain management module 1022 sends a frequency adjustment request to the clock module 106, that is, sends a new target frequency value; the power domain management module 1021 sends a voltage adjustment request to the power module 105, that is, sends a new target voltage value. Step 10: The clock module 106 and the power module 105 handshake with each other to complete the adjustment of the clock and voltage; the adjustment includes, but is not limited to: simultaneously increasing the voltage and frequency, simultaneously decreasing the voltage and frequency, turning off the clock, turning off the clock and power, turning on the clock and power, etc.

[0112] In this way, the chip-level management module 101 inside the chip can uniformly manage the power consumption of all load modules 103 within the chip, without having to aggregate all the local data of multiple chips into a single chip where the chip-level management module is located for processing. This reduces the time spent transmitting local data across chips, thereby improving the power management efficiency of the system-on-a-chip.

[0113] Furthermore, higher-level management modules have longer management cycles, while lower-level management modules have shorter management cycles, in order to improve the responsiveness to real-time services and thus improve the energy efficiency of the system-on-a-chip.

[0114] In addition, the clock domain management module can make frequency and voltage adjustment decisions without the need for the chip-level management module 104 to make such decisions, thus enabling power management services to be decentralized to the local management module and improving management efficiency.

[0115] Based on a concept similar to the system-on-a-chip provided in the above embodiments, this application also provides a training method for a power consumption evaluation model.

[0116] like Figure 11As shown, embodiments of this application provide a training method for a power consumption evaluation model, applied to the system-on-a-chip provided in the above embodiments of this application. This training method may include: Step 1110: Obtain the sampled data set of the event counter of at least one load module and the power consumption measurement data set of at least one load module; Step 1120: Using the sampled data set of the event counters of at least one load module and the power consumption measurement data set of at least one load module, iteratively train the power consumption evaluation model to be trained to obtain the target power consumption evaluation model; The power consumption evaluation model to be trained includes a first fully connected neural network layer, which contains M multiplication units, and the M multiplication units correspond to M weight coefficients. The target power consumption evaluation model includes a second fully connected neural network layer, which contains N multiplication units, each corresponding to N weight coefficients; the N weight coefficients are used to configure the power consumption evaluation units. Where M and N are positive integers, and M is greater than N.

[0117] Specifically, N multiplication units correspond to N weighting coefficients used to configure the N multipliers of the power consumption evaluation unit, and the N multiplication units can be used to filter out N target event counters connected to the N multipliers from the M event counters of the load module.

[0118] Thus, according to the training method provided in the embodiments of this application, N multiplication units are determined to correspond to N weight coefficients, and the N event counters obtained by screening are used as target event counters 1031. The N weight coefficients are used to configure the power consumption evaluation unit in the clock domain management module 1022 to achieve high-precision estimation of the power consumption of the load module 103.

[0119] In one specific embodiment, step 1110 above, obtaining the sampled data set of the event counter of at least one load module and the power consumption measurement data set of at least one load module, includes: When at least two applications are running on the system-on-a-chip, the counting result of the event counter is sampled multiple times according to a preset period to obtain the sampled data set of the event counter; The power consumption of at least one load module is measured multiple times according to a preset cycle to obtain a power consumption measurement data set of at least one load module. Among them, at least two types of applications include compute-intensive applications and access-intensive applications.

[0120] In this way, by sampling the event counter multiple times according to a preset cycle when at least two applications are running on the system-on-a-chip, the sampled data set of the event counter is obtained, which ensures the universality of the target power consumption assessment model and can accurately estimate the power consumption of the load module in at least two typical scenarios (such as compute-intensive applications and access-intensive applications).

[0121] In another specific embodiment, in step 1120 above, the power consumption evaluation model to be trained is iteratively trained using the sampled data set of the event counters of at least one load module and the power consumption measurement data set of at least one load module to obtain the target power consumption evaluation model, including: A first power consumption evaluation model is iteratively trained using the sampled data set of the event counters of at least one load module and the power consumption measurement data set of at least one load module to obtain a second power consumption evaluation model; wherein, the first power consumption evaluation model is obtained based on the power consumption evaluation model to be trained. If the accuracy of the second power consumption evaluation model is greater than the target threshold, the multiplication unit with the lowest weight coefficient in the fully connected neural network layer of the second power consumption evaluation model is removed to obtain the third power consumption evaluation model. Based on the third power consumption evaluation model, the target power consumption evaluation model is obtained.

[0122] In this way, since the multiplication unit with the lowest weight coefficient is removed in each round of training during iterative training, the number of multiplication units is reduced while ensuring accuracy, thereby reducing the number of target event counters. When estimating the power consumption of the load module in the future, the power consumption of the load module 103 can be estimated with high accuracy while reducing the amount of data computation.

[0123] In practical applications, such as Figure 12 As shown, the training method for the power consumption evaluation model provided in this application embodiment may include the following steps: Step 1210: Initialize the M weight coefficients corresponding to the M multiplication units of the power consumption evaluation model to be trained using random numbers; Step 1220: When running applications in at least two different scenarios, sample the event counter data of the load module and measure the power consumption of the load module according to a preset period. Among them, applications in at least two different scenarios can include, but are not limited to, compute-intensive and access-intensive applications; sampling the event counter data of the load module according to a preset period can obtain and measure the power consumption of the load module; the complete event counter data set (i.e., the sampled data set of the event counters of the load module) is denoted as A, A t The sampled data at time t is represented by P; the complete set of power consumption measurement data is denoted as P, Pt This represents the power consumption measurement data at time t; Step 1230: Iteratively train the power consumption evaluation model to be trained to obtain the second power consumption evaluation model; Among them, A1, ..., A n As the training set, P1, ..., P n As training labels, the power consumption evaluation model to be trained is iteratively trained to obtain the second power consumption evaluation model; Step 1240: Determine whether the accuracy of the trained second power consumption evaluation model is greater than the target threshold; Among them, A n+1 A n+2 ... A m As a validation set, P n+1 P n+2 ... P m As a verification label, the verification result is obtained by comparing the prediction result and the verification label. The verification result includes, but is not limited to, the accuracy or prediction error of the second power consumption evaluation model. If the accuracy of the second power consumption evaluation model is greater than the target threshold and the prediction error is less than the fifth threshold, step 1250 is executed. Step 1250: Remove the multiplication unit with the lowest weight coefficient in the second power consumption evaluation model; In this process, the multiplication unit with the lowest weight coefficient in the second power consumption evaluation model is removed to obtain the third power consumption evaluation model. Then, the third power consumption evaluation model is used as the power consumption evaluation model to be trained, and steps 1220 and 1230 are repeated until the accuracy of the power consumption evaluation model obtained by iterative training is equal to or less than the target threshold. At this time, the prediction error of the trained power consumption evaluation model is greater than or equal to the fifth threshold value. Step 1260: Deploy the final target power consumption evaluation model in the power consumption evaluation unit of the system-on-a-chip; In this embodiment, the N multiplication units in the target power consumption evaluation model correspond to N weight coefficients, the N multipliers in the power consumption evaluation unit correspond to N weight coefficients, and based on the N multiplication units, the N target event counters connected to the N multipliers are selected from the M event counters of the load module.

[0124] After training, taking a target threshold of 95% (corresponding to a fifth threshold of 5%) as an example, the obtained target power consumption assessment model can accurately estimate the power consumption of the load module in at least two typical scenarios, with an error of less than ±5.0%. Therefore, by deploying this target power consumption assessment model in the power consumption assessment unit of the local clock domain management module, the power consumption estimate of the load module can be obtained quickly and in real time. The power consumption estimate can reflect the working condition of the load module, thus accurately guiding the dynamic voltage and frequency regulation of the load module.

[0125] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0126] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0127] This application also provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0128] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0129] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0130] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A system-on-a-chip, characterized in that, The system-on-a-chip includes multiple chips, and the first chip in the multiple chips contains a chip-level management module, multiple local management modules and multiple load modules. The first chip is any one of the multiple chips. The chip-level management module within the first chip is coupled to the plurality of local management modules, and the chip-level management module is used to allocate target resources to the plurality of local management modules within the first chip, wherein the target resources are resources that affect power consumption; The local management module within the first core is used to manage the power consumption of at least one of the plurality of load modules within the first core; Among them, a chip-level management module is provided in the second chip among the plurality of chips, and the second chip is any one of the plurality of chips; The chip-level management module is coupled to the chip-level management module within the first chip, and the chip-level management module is used to provide target resources to the chip-level management module within the first chip; Within the system-on-a-chip, the number of the chip-level management modules is the same as the number of the chips; each of the plurality of chips contains one of the chip-level management modules.

2. The system-on-a-chip according to claim 1, characterized in that, The chip-level management module is coupled to the multiple chip-level management modules corresponding to the multiple chips.

3. The system-on-a-chip according to claim 1, characterized in that, The chip-level management module is connected to the chip-level management module within the first chip via a first private bus, and the chip-level management module is connected to the plurality of local management modules via a second private bus; Both the first private bus and the second private bus are dedicated to power management services.

4. The system-on-a-chip according to claim 1, characterized in that, The first cycle is longer than the second cycle, and the second cycle is longer than the third cycle; Wherein, the first cycle is the time period during which the chip-level management module provides target resources to the chip-level management module within the first chip, the second cycle is the time period during which the chip-level management module allocates target resources to the plurality of local management modules within the first chip, and the third cycle is the time period during which the local management module manages the power consumption of at least one of the plurality of load modules within the first chip.

5. The system-on-a-chip according to claim 1, characterized in that, The local management module includes a power domain management module; the power domain management module is connected to the core-level management module and the at least one load module respectively; The first chip also includes a power module, which is connected to the power domain management module and the at least one load module respectively; The power domain management module is used to adjust the voltage output by the power module to the at least one load module based on the power consumption estimate of the at least one load module and the target resources allocated by the granular management module.

6. The system-on-a-chip according to claim 1, characterized in that, The local management module includes a clock domain management module; the clock domain management module is connected to both the core-level management module and the load module. The first chip also includes a clock module, which is connected to both the clock domain management module and the load module. The clock domain management module is used to adjust the clock signal output by the clock module to the at least one load module based on the power consumption estimate of the at least one load module and the target resources allocated by the chip-level management module.

7. The system-on-a-chip according to claim 1, characterized in that, The local management module includes a power domain management module and a clock domain management module, with the power domain management module connected to the clock domain management module; the power domain management module is connected to the chip-level management module, and the clock domain management module is connected to the load module. The first chip also includes a power module and a clock module. The power module is connected to the power domain management module and the load module, respectively, and the clock module is connected to the clock domain management module and the load module, respectively. The power domain management module is used to adjust the voltage output by the power module to the at least one load module based on the power consumption estimate of the at least one load module and the target resources allocated by the chip-level management module. The clock domain management module is used to adjust the clock signal output by the clock module to the at least one load module based on the power consumption estimate of the at least one load module and the target resources allocated by the granular management module.

8. The system-on-a-chip according to claim 7, characterized in that, The clock domain management module includes a power consumption evaluation unit and a working parameter adjustment request generation unit. The power consumption evaluation unit is connected to the working parameter adjustment request generation unit. The power consumption evaluation unit is also connected to a target event counter in the at least one load module.

9. The system-on-a-chip according to claim 8, characterized in that, The power consumption evaluation unit is used to perform fully connected neural network calculations on the sampled data from the target event counter to obtain the power consumption estimate of the at least one load module; the sampled data includes the difference between two counting results obtained from two consecutive counts by the target event counter; The operating parameter adjustment request generation unit is used to generate an operating parameter adjustment request based on the power consumption estimate of the at least one load module and the target resources allocated by the chip-level management module; the operating parameter adjustment request is used to adjust the operating parameters of the at least one load module, the operating parameters including at least one of the voltage output by the power supply module to the at least one load module and the clock signal output by the clock module to the at least one load module.

10. The system-on-a-chip according to claim 9, characterized in that, When the local management module includes a power domain management module and a clock domain management module, the power domain management module is used to receive the operating parameter adjustment request output by the clock domain management module, and adjust the operating parameters of the at least one load module according to the operating parameter adjustment request.

11. The system-on-a-chip according to claim 8, characterized in that, The total number of event counters in the at least one load module is M, and the target event counter includes N event counters selected from the M event counters; The power consumption evaluation unit includes a fully connected neural network layer, which includes N multipliers and one adder. All N multipliers are connected to the adder, and the N event counters are connected to the N multipliers. M is greater than N, and N is a positive integer greater than 1.

12. The system-on-a-chip according to claim 11, characterized in that, In the fully connected neural network layer, the N multipliers have N weight coefficients, with one weight coefficient corresponding to one multiplier; the N weight coefficients are trained based on the sampled data set of M event counters in the at least one load module and the power consumption measurement data set of the at least one load module.

13. The system-on-a-chip according to claim 8, characterized in that, The working parameter adjustment request generation unit includes a first comparator and a first register. The first input terminal of the first comparator is connected to a first voltage terminal, the second input terminal of the first comparator is connected to the output terminal of the power consumption evaluation unit, and the output terminal of the first comparator is connected to the first register. The first voltage at the first voltage terminal is obtained based on the target resources allocated by the core-level management module.

14. The system-on-a-chip according to claim 13, characterized in that, The working parameter adjustment request generation unit further includes a second comparator and a second register; the first input terminal of the second comparator is connected to the output terminal of the power consumption evaluation unit, the second input terminal of the second comparator is connected to the second voltage terminal, and the output terminal of the second comparator is connected to the second register. The second voltage at the second voltage terminal is obtained based on the target resources allocated by the core-level management module, and the first voltage at the first voltage terminal is greater than the second voltage at the second voltage terminal.

15. The system-on-a-chip according to claim 1, characterized in that, The local management module includes a hardware protection unit, which is connected to a sensor in the at least one load module. The hardware protection unit is used to generate a protection enable signal based on the alarm signal output by the sensor, and the protection enable signal is used to lower the operating parameters of the at least one load module.

16. An electronic device, characterized in that, include: The system-on-a-chip as described in any one of claims 1-15.

17. A power management method, applied to a system-on-a-chip as described in any one of claims 1-15, characterized in that, include: The chip-level management module provides target resources to the chip-level management module on the first chip. The core-level management module on the first core allocates target resources to the plurality of local management modules on the first core. The local management module on the first chip counts the estimated power consumption of at least one load module on the first chip; The local management module on the first core adjusts the operating parameters of the at least one load module based on the power consumption estimate of the at least one load module on the first core and the target resources allocated by the core-level management module.

18. A method for training a power consumption evaluation model, applied to the system-on-a-chip as described in claim 12, characterized in that, include: Obtain the sampled data set of the event counter of the at least one load module and the power consumption measurement data set of the at least one load module; Using the sampled data set of the event counters of the at least one load module and the power consumption measurement data set of the at least one load module, the power consumption evaluation model to be trained is iteratively trained to obtain the target power consumption evaluation model. The power consumption evaluation model to be trained includes a first fully connected neural network layer, which contains M multiplication units, and the M multiplication units correspond to M weight coefficients. The target power consumption evaluation model includes a second fully connected neural network layer, which contains N multiplication units, each corresponding to N weight coefficients; the N weight coefficients are used to configure the power consumption evaluation unit.

19. The method according to claim 18, characterized in that, Using the sampled data set of the event counters of the at least one load module and the power consumption measurement data set of the at least one load module, the power consumption evaluation model to be trained is iteratively trained to obtain the target power consumption evaluation model, including: Using the sampled data set of the event counters of the at least one load module and the power consumption measurement data set of the at least one load module, the first power consumption evaluation model is iteratively trained to obtain the second power consumption evaluation model; wherein, the first power consumption evaluation model is obtained based on the power consumption evaluation model to be trained; If the accuracy of the second power consumption evaluation model is greater than the target threshold, the multiplication unit with the lowest weight coefficient in the fully connected neural network layer of the second power consumption evaluation model is removed to obtain the third power consumption evaluation model. Based on the third power consumption evaluation model, the target power consumption evaluation model is obtained.

20. The method according to claim 18, characterized in that, The step of acquiring the sampled data set of the event counters of the at least one load module and the power consumption measurement data set of the at least one load module includes: When at least two applications are running on the system-on-a-chip, the counting result of the event counter is sampled multiple times according to a preset period to obtain a set of sampled data of the event counter; The power consumption of the at least one load module is measured multiple times according to the preset period to obtain a power consumption measurement data set of the at least one load module; The at least two types of applications include compute-intensive applications and access-intensive applications.

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