High-speed signal acquisition and storage method, system and medium based on heterogeneous computing

Abstract

The application discloses a high-speed signal acquisition and storage method and system based on heterogeneous computing, and a medium, and is applied to a processing device containing an FPGA end and a CPU end. The method comprises the following steps: receiving a front-end high-speed data stream through a high-speed data transmission link, and performing edge detection on the high-speed data stream through an edge detection algorithm to identify an effective data boundary; inserting a fixed identifier into the effective data boundary to form effective data containing the fixed identifier; writing the effective data containing the fixed identifier into a DDR for data caching; monitoring the amount of cached data, and issuing a data reading interruption signal when a preset interruption threshold is met; and the data reading interruption signal is used for enabling the CPU end to extract the effective data and store the effective data into a target storage device. Through frame boundary detection of the fixed identifier and dynamic packet storage, the application reduces the storage amount of invalid data, and realizes efficient storage while guaranteeing real-time performance.

Description

Technical Field

[0001] This invention relates to the field of high-speed signal acquisition and storage technology, and in particular to a high-speed signal acquisition and storage method, system, and medium based on heterogeneous computing. Background Technology

[0002] In recent years, high-speed signal acquisition technology has been widely used in communication systems, radar detection, industrial inspection and other fields, and signal bandwidth has continued to improve. However, traditional data acquisition architectures face multiple challenges: First, single processors such as FPGAs or CPUs are limited by hardware interface bandwidth and storage medium speed, making it difficult to achieve real-time reception and stable storage of high-bandwidth data, which can easily lead to data loss or processing delays. Second, analog-to-digital converter (ADC) sampling data contains a large amount of noise or invalid segments. Directly storing the raw data results in wasted space, and subsequent parsing requires additional redundancy removal, increasing processing complexity. Third, fixed partition storage is difficult to match scenarios with dynamically changing data packet lengths, which can easily lead to storage fragmentation or capacity overflow.

[0003] In high-bandwidth signal acquisition scenarios, storage efficiency is low, resources are wasted, and dynamic adaptability is insufficient. How to achieve efficient storage while ensuring real-time performance through hardware architecture innovation and data processing method optimization has become a critical technical bottleneck that urgently needs to be overcome in this field. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a high-speed signal acquisition and storage method, system, and medium based on heterogeneous computing. By using frame boundary detection with fixed identifiers and dynamic packet storage, the amount of invalid data stored is reduced, achieving efficient storage while ensuring real-time performance.

[0005] To address the aforementioned technical problems, the first aspect of this invention discloses a high-speed signal acquisition and storage method based on heterogeneous computing, applied in a processing device comprising an FPGA and a CPU. The method includes: The system receives high-speed data streams from the front end via a high-speed data transmission link and uses edge detection algorithms to identify valid data boundaries. A fixed identifier is inserted at the boundary of the valid data to form valid data containing the fixed identifier; Write valid data containing a fixed identifier to DDR for data caching; The system monitors the amount of cached data and issues a data read interrupt signal when a preset interrupt threshold is met. The data read interrupt signal is used to enable the CPU to extract the valid data and store it in the target storage device.

[0006] In some implementations, valid data containing a fixed identifier is written to DDR for data caching, including: Valid data containing a fixed identifier is cached in a FIFO. When the amount of data in the FIFO reaches a first preset threshold, it is written to DDR through the AXI bus burst transmission mechanism. When the data in the FIFO falls below the second preset threshold, the state machine will switch to the idle state.

[0007] In some implementations, the edge detection algorithm performs edge detection, including: Energy detection is performed on the high-speed data stream from the front end using a dual sliding window. The effective data edge is determined by comparing the energy value ratio of the two sliding windows with the preset threshold of the edge.

[0008] In some implementations, the QSFP interface of the FPGA end board includes four SerDes differential links divided into two groups, with each data transmission channel corresponding to two SerDes differential links; the maximum sampling rate of each data transmission channel is 20Gbps.

[0009] In some implementations, the CPU extracts the valid data and stores it in the target storage device, including: The CPU starts an interrupt thread, sends a semaphore to the receiving thread, and reads cached data containing identifiers in batches from the storage medium on the FPGA side; the cached data read each time does not exceed a preset read threshold. The CPU identifies valid signal boundaries based on byte matching, and extracts and retains valid data. The extracted valid data is stored in the target storage device.

[0010] In some implementations, the interrupt thread on the CPU side checks the data read interrupt signal sent by the FPGA board in a polling manner. The data read interrupt signal is based on the register count value, and each increment of the register count value indicates that a data read request has been received from the FPGA board.

[0011] In some implementations, the preset interrupt threshold and preset read threshold are 512MB; the fixed identifier is 32 bits.

[0012] In some implementations, the fixed identifier starts at 0x55aa55aa and ends at 0xaa55aa55.

[0013] Secondly, a heterogeneous system based on a CPU and an FPGA is disclosed, comprising a processing device with an FPGA and a CPU, wherein the FPGA includes: QSFP and interface modules are used to receive high-speed data streams output from external sampling modules; The edge detection module identifies valid edges in the input data by employing a sliding window energy ratio determination algorithm. The identifier embedding module is used to insert predefined bit identifiers at the beginning and end of detected valid data segments; The DDR write module stores data with identifiers into the onboard DDR; The interrupt triggering module is used to generate an interrupt signal when the cached data reaches a threshold and issue a data read request, which is used to notify the CPU to read the data.

[0014] CPU-side includes: The interrupt thread is used to poll and detect data read interrupt signals sent by the FPGA. The receiving thread responds to the data read interrupt signal and reads batch data from the FPGA-side DDR via DMA. The data recognition module is used to identify valid data boundaries based on the inserted fixed identifier; The sub-packet storage module is used to dynamically write the identified valid data to the hard disk.

[0015] Thirdly, a computer storage medium is disclosed, on which a computer program is stored, wherein when the computer program is executed by a processor, it implements a high-speed signal acquisition and storage method based on heterogeneous computing as described in any of the above.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides a high-speed signal acquisition and storage method, system, and medium based on heterogeneous computing. By combining frame boundary detection with fixed identifiers and a dynamic packet splitting mechanism, it effectively solves the problems of low storage efficiency, resource waste, and insufficient dynamic adaptability in traditional technologies. Edge detection and fixed identifier embedding can accurately filter out invalid data, avoiding redundant storage. The collaborative work between the FPGA and CPU ensures real-time reception and stable storage of high-bandwidth data, significantly improving storage efficiency and system reliability, and providing an efficient and flexible storage solution for high-bandwidth signal acquisition scenarios. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the high-speed signal acquisition and storage method based on heterogeneous computing provided by the present invention; Figure 2 This is a schematic diagram of the FPGA-side flow of the high-speed signal acquisition and storage method based on heterogeneous computing provided by the present invention. Figure 3 This is a schematic diagram of the CPU side in the high-speed signal acquisition and storage method based on heterogeneous computing provided by the present invention. Detailed Implementation

[0018] To better understand and implement this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0019] The terms “comprising” and “having” and any variations thereof in this invention are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules that are explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to such processes, methods, products or devices.

[0020] An embodiment of the present invention discloses a high-speed signal acquisition and storage method based on heterogeneous computing.

[0021] like Figure 1 As shown, this method is applied to a heterogeneous system containing a CPU and an FPGA. The system includes a CPU host, an FPGA board, and a PCIe bus. The CPU host has a PCIe slot, and the FPGA board is equipped with a PCIe interface, a QSFP (Quad Small Form-factor Pluggable) interface, and onboard DDR. The QSFP interface is responsible for receiving the high-speed data stream acquired by the front-end sampling module, and the data is buffered on the board's DDR. The CPU host and the FPGA board exchange data and commands via the PCIe bus.

[0022] Specifically, such as Figure 2 As shown, the FPGA performs the following steps: Step S201: Receive high-speed data stream from the front end through the high-speed data transmission link, and identify valid data boundaries through edge detection algorithm.

[0023] The QSFP interface on the FPGA board serves as the high-speed data stream access point between the front-end sampling module and the FPGA. This interface uses four independent SerDes (Serializer / Deserializer) differential links as the physical transmission medium. By dividing the four links into two groups, each group contains two SerDes differential links, corresponding to two independent data transmission channels, a dual-channel parallel transmission architecture is formed.

[0024] Each SerDes differential link carries the Aurora64 / 66B high-speed serial communication protocol. This protocol uses a little-endian duplex data format and stream transmission mode, with a 156.25MHz reference clock source for clock synchronization and data alignment. The core of the Aurora64 / 66B protocol lies in its 64 / 66-bit encoding mechanism, which inserts 2 control bits into 64 bits of effective data, sacrificing approximately 3% bandwidth for data transmission reliability and link self-synchronization capability. Under this configuration, calculated from the reference clock frequency of 156.25MHz and the 66-bit encoding period: 156.25MHz × 66bit ≈ 10.3125Gbps, the physical layer transmission rate of a single SerDes differential link is 10.3125Gbps. After 64 / 66B encoding and decoding, the effective data rate of a single link is 10.3125Gbps × 64 / 66 ≈ 10Gbps.

[0025] Since each channel group contains two SerDes differential links, the maximum effective data transmission rate of a single channel can reach 20Gbps. The dual-channel, four-link parallel transmission architecture significantly improves the total bandwidth of the interface through physical layer link aggregation, fully matching the output requirements of the high-bandwidth sampling module at the front end and avoiding data congestion or loss due to insufficient transmission bandwidth. Simultaneously, the Aurora64 / 66B protocol's Stream mode and duplex little-endian format design ensure the continuity and low latency of the data stream, providing stable raw data input for subsequent real-time signal processing such as edge detection and identifier embedding on the FPGA side. From the physical layer to the protocol layer, this ensures the real-time performance and reliability of the high-speed signal acquisition system.

[0026] Using edge detection algorithms to identify valid data boundaries includes: Step S2011: Perform energy detection on the front-end high-speed data stream using a dual sliding window; Step S2012: Determine the effective data edge based on the ratio of the energy values ​​of the two sliding windows.

[0027] The FPGA side uses a dual sliding window energy detection algorithm to accurately identify the effective data boundary.

[0028] Utilizing the abrupt changes in signal energy, effective signals such as radar echoes and communication modulation signals typically have significantly higher energy densities than the noise floor, while invalid data such as background noise and idle period signals have relatively stable and lower energy. When the dual-window energy ratio exceeds a threshold, it indicates a sudden change in the data stream from low-energy noise to high-energy effective signals, and vice versa. At this point, the start and end points of the effective data segments can be precisely marked to perform dynamic feature analysis on the input high-speed data stream.

[0029] Two sliding windows of fixed length are employed: a forward window and a backward window. The forward and backward windows slide point-by-point along the data stream time axis, and the energy value within each window is calculated. The energy value can be the sum of squares of the signal amplitude or the root mean square value. By comparing the energy ratio of the two windows in real time, and combining this with a pre-set edge threshold (e.g., when the ratio of the backward window energy to the forward window energy exceeds 1.5 times), the current position is determined to be the start or end boundary of valid data. The real-time performance and low computational complexity of the dual-sliding-window energy detection allow for efficient implementation in FPGA hardware logic, meeting the real-time processing requirements of 20Gbps high-bandwidth data streams. Step S202: Insert a fixed identifier into the valid data boundary to form valid data containing the fixed identifier; Based on the identification results of the above-mentioned valid data boundaries, predefined fixed identifiers are inserted at the start and end points of the valid data boundaries to form a structured data segment of identifier-valid data-identifier. In this application, a 32-bit fixed sequence is used, for example, a start point of 0x55aa55aa and an end point of 0xaa55aa55. The fixed identifier can be 8 bits, 16 bits, or 64 bits, etc., and the specific identifier can be adapted to the actual application scenario; no limitation is made in this application.

[0030] By marking valid data boundaries with identifiers, a clear parsing basis is provided for subsequent dynamic packet storage on the CPU side. This avoids the fragmentation or overflow problems caused by changes in packet length in traditional fixed-partition storage, significantly improving the utilization of storage resources. As a clear physical layer marker, the fixed identifier can quickly locate the start and end positions of valid data simply through byte-level sequence matching, regardless of the dynamic changes in the length of the valid data segment. This provides a boundary identification basis for subsequent data processing without relying on complex protocol parsing or external synchronization signals, significantly reducing the computational complexity of data parsing. Simultaneously, since only valid data is retained, invalid noise data is filtered out by the edge detection module and no longer participates in the storage process, reducing the storage space occupied by redundant data and improving the utilization efficiency of storage resources.

[0031] Step S203: Write valid data containing a fixed identifier into DDR for data caching, including: Step S2031: Cache the valid data containing the fixed identifier into the FIFO. When the amount of data in the FIFO reaches the first preset threshold, write it into the DDR through the AXI bus burst transmission mechanism. Step S2032: When the data in the FIFO is lower than the second preset threshold, the state machine is switched to the idle state.

[0032] Valid data containing a fixed identifier is temporarily stored in a FIFO (First In First Out) buffer. When the FIFO is nearing full capacity, it is written in batches to the DDR cache via the AXI bus burst transfer mechanism. Because only structural fragments containing valid data are retained, invalid, low-energy, and noisy data are automatically filtered out, reducing the amount of redundant data stored. Valid data with a fixed identifier is cached in the FIFO to balance the difference between the high-speed data stream at the front end and the write rate of the DDR storage medium, avoiding write interruptions or data loss due to data stream bursts or fluctuations.

[0033] When the amount of data in the FIFO grows to a first preset threshold, the burst transmission mechanism of the AXI bus is triggered. AXI (Advanced eXtensible Interface), as an on-chip bus protocol, supports continuous data transmission in its burst mode. Only the first data entry needs to provide the starting address; subsequent data automatically increments the address, significantly reducing bus handshake overhead and address switching latency. Under this mechanism, the structured data temporarily stored in the FIFO is batched, that is, packaged into fixed-length burst transmission packets, and efficiently written to the DDR storage medium via the AXI bus, ensuring continuous, low-latency caching of high-bandwidth data streams.

[0034] The write and read operations of the FIFO are dynamically managed by a state machine within the FPGA. When the amount of data in the FIFO is consumed to a second preset threshold due to burst transmissions, the state machine automatically switches to an idle state, pausing read operations on the FIFO. This dynamic switching mechanism avoids invalid transmission requests from the FIFO when the data volume is insufficient, reducing the idle loss of bus resources. At the same time, threshold control ensures that the FIFO always maintains a certain buffer margin, reserving space for the continuous injection of new data and maintaining the continuity of the data flow.

[0035] Valid data containing fixed identifiers is cached in DDR, enabling subsequent hard disk storage to manage storage space dynamically through packet partitioning. The CPU can allocate storage units in real time based on the identifier's location, eliminating the need for pre-setting fixed partition sizes and thus resolving storage fragmentation or capacity overflow issues caused by variations in packet length in traditional fixed-partition storage. Through FIFO rate matching, efficient AXI burst transmission for writing, and dynamic state machine control, seamless integration between high-bandwidth data streams and DDR storage media is achieved.

[0036] Step S204: Monitor the amount of cached data, and when the preset interrupt threshold is met, issue a data read interrupt signal; the data read interrupt signal is used to enable the CPU to extract the valid data and store it in the target storage device.

[0037] The FPGA side achieves precise triggering of read data interrupts to the CPU by real-time monitoring of DDR memory addresses and dynamic calculation of data volume. The FPGA side tracks the DDR write operation address cycle by cycle. When writing to DDR via the AXI bus burst transfer mechanism, the DDR write pointer is continuously incremented using an address counter. Since there is a linear correspondence between DDR memory addresses and data volume, the total amount of data written to DDR is dynamically calculated based on the accumulated value of the address counter.

[0038] When the accumulated data volume reaches a preset interrupt threshold, a data read interrupt signal is generated within the FPGA and transmitted to the CPU via the PCIe bus. In this application, the preset interrupt threshold is 512MB, which is the critical value for a single DDR write. This avoids excessively frequent interrupts due to a threshold that is too small, reducing interrupt handling overhead on the CPU and improving the data read rate. Simultaneously, it prevents data backlog risks caused by a threshold that is too large, allowing for timely transfer of cached data. This preset interrupt threshold can be adjusted according to the actual application scenario and is not limited in this application.

[0039] After being buffered on the FPGA side, the CPU reads the data stored on the FPGA board. For example... Figure 3 As shown, the CPU performs the following steps: Step S301: The CPU creates a receiving thread, which requests a large contiguous memory space and starts working after receiving a data read interrupt signal.

[0040] During the initialization phase, a dedicated receiving thread is created through the operating system's memory management interface, such as mmap in Linux or VirtualAlloc in Windows. This receiving thread is used for batch reading, allocation, and management of target storage areas for FPGA-side DDR cache data. Unlike conventional dynamic memory allocation, the receiving thread requests large, contiguous blocks of physical memory. In this application, this memory space is no less than the FPGA-side DDR write threshold of 512MB, achieved by bypassing the system's paging mechanism, ensuring that the memory space is fragment-free and contiguously addressable in physical addresses.

[0041] Large blocks of contiguous memory ensure continuous physical addresses, eliminating multiple page table lookups from virtual to physical addresses. Only a single address translation is needed, significantly reducing memory access latency. Contiguous memory also provides an efficient transfer path for the DMA controller: the DMA engine can directly initiate batch data transfers based on contiguous physical addresses without interruption or reconfiguration due to address discontinuity, greatly increasing the effective transfer bandwidth of the DMA.

[0042] After completing memory allocation, the receiving thread enters a semaphore waiting state until it receives a data read interrupt signal from the CPU. This ensures that the receiving thread only starts when the amount of data in the FPGA's DDR cache reaches a preset interrupt threshold, avoiding wasted CPU resources due to thread idleness.

[0043] After receiving a data read interrupt signal from the FPGA, perform the following steps: Step S302: The CPU starts an interrupt thread, sends a semaphore to the receiving thread, and reads cached data containing identifiers in batches from the storage medium on the FPGA side through the high-speed interface; the cached data read each time does not exceed the preset read threshold.

[0044] The CPU-side interrupt thread continuously monitors the status of the interrupt register exposed by the FPGA board via the PCIe bus. This interrupt register is essentially a 32-bit or 64-bit hardware counter, and its count directly reflects the status of the FPGA's DDR cache. Each time the FPGA completes a 512MB data write and triggers a read request, the interrupt register's count increments by 1. The interrupt thread uses a polling method to sample this register frequently. This active polling mechanism has lower latency than interrupt response and is suitable for high-speed signal acquisition scenarios with extremely high real-time requirements, enabling rapid detection of register value changes.

[0045] When the interrupt thread detects that the interrupt register counter has incremented by 1 through polling, it indicates that the FPGA has completed DDR caching of 512MB of data. At this point, the receiving thread needs to be notified to initiate the data reading operation. The interrupt thread sends a trigger signal to the receiving thread using a semaphore synchronization primitive provided by the system. The semaphore serves as a lightweight thread synchronization tool, requiring minimal system overhead to complete the interrupt triggered status transmission, avoiding the additional delays that might be introduced by complex message queues or event notification mechanisms.

[0046] The receiving thread pre-allocates a large contiguous memory space during the initialization phase. This contiguous memory is typically no less than 512MB. Upon receiving a semaphore from the interrupt thread, it immediately initiates DMA (Direct Memory Access) transfer. DMA transfer does not require direct CPU involvement in data movement; instead, the DMA controller directly transfers the 512MB of data from the FPGA board's DDR memory to the receiving thread's pre-allocated memory space via the PCIe bus.

[0047] Since the amount of data transmitted is strictly consistent with the DDR write threshold on the FPGA side, the DMA controller can be configured to a single burst transfer mode, which only needs to be initialized once to complete the transfer of all data, significantly reducing the start / stop overhead of traditional multiple transfers and effectively improving the bandwidth utilization of data transmission.

[0048] Step S303: The CPU identifies valid signal boundaries based on byte matching, and extracts and retains valid data; After data transmission is complete, the receiving thread extracts valid data from the 512MB of data in memory. The receiving thread scans the memory data using a byte-level sequence matching algorithm, comparing each byte with a predefined 32-bit fixed sequence starting from the data's beginning address. It identifies the start identifier (0x55aa55aa) and the end identifier (0xaa55aa55). When the start identifier is detected, the beginning position of the valid data segment is marked; when the end identifier is reached, the end position is marked, thus extracting the continuous data between them as valid data. Specifically, this can be achieved through hardware-accelerated string matching instructions, ensuring fast processing even with a large data volume of 512MB.

[0049] Step S304: Store the extracted valid data to the target storage device.

[0050] The extracted valid data segments are encapsulated into binary files and written to the hard disk storage medium through the operating system's file system interface, completing the conversion from cache to persistent storage. The receiving thread determines whether the 512MB of data has been fully processed by monitoring the DMA controller's transfer status register or directly counting the number of bytes written to the hard disk. If the actual number of bytes transferred matches the preset 512MB threshold, the DMA transfer is terminated and related resources are released; if the number of bytes is insufficient due to transmission errors or data loss, a retransmission mechanism is triggered, and a read data request is resent to the FPGA to ensure data integrity and reliability.

[0051] The CPU achieves end-to-end optimization of high-bandwidth signals from acquisition to storage through low-latency response of polling monitoring, lightweight coordination of semaphore synchronization, efficient data transfer of DMA, and accurate data extraction of identifier scanning. This solves the core problems of low storage efficiency and poor dynamic adaptability in traditional solutions, and provides reliable technical support for high-bandwidth signal processing in fields such as communication systems and radar detection.

[0052] Based on the same inventive concept, this application also provides a heterogeneous system based on a CPU and an FPGA, comprising a processing device with an FPGA and a CPU, wherein the FPGA includes: QSFP and interface modules are used to receive high-speed data streams output from external sampling modules; The edge detection module identifies valid edges in the input data by employing a sliding window energy ratio determination algorithm. The identifier embedding module is used to insert predefined bit identifiers at the beginning and end of detected valid data segments; The DDR write module stores data with identifiers into the onboard DDR; The interrupt triggering module is used to generate an interrupt signal when the cached data reaches a threshold and issue a data read request, which is used to notify the CPU to read the data.

[0053] CPU-side includes: The interrupt thread is used to poll and detect data read interrupt signals sent by the FPGA. The receiving thread responds to the data read interrupt signal and reads batch data from the FPGA-side DDR via DMA. The data recognition module is used to identify valid data boundaries based on the inserted fixed identifier; The sub-packet storage module is used to dynamically write the identified valid data to the hard disk.

[0054] The specific execution on the FPGA and CPU sides can be referred to the description of the above method, and will not be repeated here.

[0055] This invention embeds predefined fixed identifiers into the data stream when processing high-speed data streams on the FPGA side, and writes them synchronously to the DDR cache along with the valid data. By directly marking the physical boundaries of valid data packets with a fixed bit sequence, it eliminates the need for complex protocol parsing processes or external synchronization signals found in traditional solutions, effectively reducing the logical complexity and implementation cost of data boundary identification.

[0056] Meanwhile, a heterogeneous collaborative storage architecture is constructed on the FPGA-CPU side. By constructing the heterogeneous collaborative storage architecture on the FPGA side, the FPGA side acts as the front-end processing unit, undertaking real-time tasks such as high-speed data reception, identifier embedding, and DDR cache writing; the CPU side acts as the back-end storage unit, reading cached data in the FPGA side DDR in batches through the interrupt triggering mechanism, parsing the valid data packet boundaries based on predefined identifiers, retaining only the valid data segments, and dynamically subpackaging and storing them to the hard disk.

[0057] Furthermore, since the start and end of valid data packets are clearly marked by identifiers, the storage system can flexibly adjust the allocation strategy of storage units according to the actual data packet length, avoiding storage fragmentation or capacity overflow problems caused by dynamic changes in data packet length. Experimental data shows that, using the number of valid packets that can be stored in 1MB of storage space as an evaluation metric, the traditional method of directly storing raw sampling data can only store 11,680 packets, while with the present invention, the same storage space can store 15,240 packets, increasing the number of stored packets by about 30%, significantly improving storage efficiency and dynamic adaptability.

[0058] Based on the same inventive concept, the present invention also provides a computer device, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed the steps of the above-described high-speed signal acquisition and storage method based on heterogeneous computing.

[0059] The processing methods for computer devices can be referred to the description of the methods above, and will not be repeated here.

[0060] This application also provides a non-transitory machine-readable storage medium storing an executable program, which, when run by a microprocessor, causes the processor to execute the method provided in the above embodiments.

[0061] This invention discloses a computer-readable storage medium storing a computer program for electronic data interchange, wherein the computer program causes a computer to perform the described methods.

[0062] This invention discloses a computer program product including a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform the described method.

[0063] The embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0064] Through the detailed description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0065] Finally, it should be noted that the embodiments disclosed in this invention are merely preferred embodiments of this invention and are only used to illustrate the technical solutions of this invention, not to limit it. Although this invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this invention.

Claims

1. A high-speed signal acquisition and storage method based on heterogeneous computing, characterized in that, Applied in a processing device comprising an FPGA and a CPU, the FPGA performs the following steps: The system receives high-speed data streams from the front end via a high-speed data transmission link and uses edge detection algorithms to identify valid data boundaries. A fixed identifier is inserted at the boundary of the valid data to form valid data containing the fixed identifier; Write valid data containing a fixed identifier to DDR for data caching; The system monitors the amount of cached data and issues a data read interrupt signal when a preset interrupt threshold is met. The data read interrupt signal is used to enable the CPU to extract the valid data and store it in the target storage device. The step of writing valid data containing a fixed identifier into DDR for data caching includes: caching the valid data containing the fixed identifier into FIFO; writing the data into DDR through an AXI bus burst transmission mechanism when the amount of data in FIFO reaches a first preset threshold; and switching the state machine to an idle state when the amount of data in FIFO is lower than a second preset threshold. The edge detection algorithm performs edge detection, including: Energy detection is performed on the high-speed data stream from the front end using a dual sliding window. The effective data edge is determined by comparing the energy value ratio of the two sliding windows with the preset threshold of the edge.

2. The high-speed signal acquisition and storage method based on heterogeneous computing according to claim 1, characterized in that, The FPGA end board's QSFP interface includes four SerDes differential links divided into two groups, with each data transmission channel corresponding to two SerDes differential links; the maximum sampling rate of each data transmission channel is 20Gbps.

3. The high-speed signal acquisition and storage method based on heterogeneous computing according to claim 1, characterized in that, The CPU extracts the valid data and stores it in the target storage device, including: The CPU starts an interrupt thread, sends a semaphore to the receiving thread, and reads cached data containing identifiers in batches from the storage medium on the FPGA side; the cached data read each time does not exceed a preset read threshold. The CPU identifies valid signal boundaries based on byte matching, and extracts and retains valid data. The extracted valid data is stored in the target storage device.

4. The high-speed signal acquisition and storage method based on heterogeneous computing according to claim 1, characterized in that, The CPU-side interrupt thread checks the data read interrupt signals sent by the FPGA-side board in a polling manner. The data read interrupt signals are based on the register count value. Each increment of the register count value indicates that a data read request has been received from the FPGA-side board.

5. The high-speed signal acquisition and storage method based on heterogeneous computing according to claim 4, characterized in that, The preset interrupt threshold and preset read threshold are 512MB; the fixed identifier is 32 bits.

6. The high-speed signal acquisition and storage method based on heterogeneous computing according to claim 5, characterized in that, The fixed identifier starts at 0x55aa55aa and ends at 0xaa55aa55.

7. A heterogeneous system based on a CPU and an FPGA, characterized in that, In processing devices that include both FPGA and CPU components, the FPGA component includes: QSFP and interface modules are used to receive high-speed data streams output from external sampling modules; The edge detection module identifies valid edges in the input data by employing a sliding window energy ratio determination algorithm. The identifier embedding module is used to insert predefined bit identifiers at the beginning and end of detected valid data segments; The DDR write module stores data with identifiers into the onboard DDR; An interrupt triggering module is used to generate an interrupt signal and issue a data read request when the cached data reaches a threshold. The data read request is used to notify the CPU to read the data. CPU-side includes: The interrupt thread is used to poll and detect data read interrupt signals sent by the FPGA. The receiving thread responds to the data read interrupt signal and reads batch data from the FPGA-side DDR via DMA. The data recognition module is used to identify valid data boundaries based on the inserted fixed identifier; The sub-packet storage module is used to dynamically write the identified valid data to the hard disk.

8. A computer storage medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the steps of a high-speed signal acquisition and storage method based on heterogeneous computing as claimed in any one of claims 1-6.

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