Method for managing memory access operations, system on chip and electronic device

Abstract

At least one embodiment of the present disclosure provides a method, a system on chip and an electronic device for managing access operations to a memory. The method comprises: in a first mode, classifying a plurality of access instructions for the memory into at least a first priority and a second priority; mapping the access instructions with the first priority to a first priority channel in a storage channel corresponding to the memory, and mapping the access instructions with the second priority to a second priority channel in the storage channel corresponding to the memory; and in accordance with a read-write direction of a first target access instruction with the first priority to be transmitted by the first priority channel, selecting a second target access instruction with the second priority to be transmitted by the second priority channel, which is synchronized with the read-write direction of the first target access instruction, to synchronously transmit the first target access instruction and the second target access instruction. The method can reduce access delay to the memory and improve user experience.

Description

Technical Field

[0001] Embodiments of this disclosure relate to methods for managing memory access operations, on-chip systems, and electronic devices. Background Technology

[0002] Memory is a core component in a computer system used to store data and programs. It is typically divided into main memory (such as random access memory (RAM)) and auxiliary memory (such as hard disks or solid-state drives). Main memory is used for temporary data access, while auxiliary memory is used for long-term data storage. A storage channel is a data transfer path connecting the memory and the computer processor (such as the memory controller). It is usually implemented through various buses or interfaces to efficiently transfer data and instructions. The design and bandwidth of the storage channel directly affect system performance, determining the data read / write speed and overall computational efficiency. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a method for managing memory access operations, comprising: in a first mode, classifying a plurality of memory access instructions for the memory into at least a first priority and a second priority; mapping memory access instructions with the first priority to a first priority channel in a memory channel corresponding to the memory, and mapping memory access instructions with the second priority to a second priority channel in a memory channel corresponding to the memory; and selecting a second target memory access instruction that is synchronized with the read / write direction of the first target memory access instruction among the memory access instructions with the first priority to be transmitted in the first priority channel, based on the read / write direction of the first target memory access instruction, so as to synchronously transmit the first target memory access instruction and the second target memory access instruction.

[0004] At least one embodiment of this disclosure provides a system-on-a-chip (SoC) including an on-chip network and a memory controller. The memory controller is used for a memory and includes a memory channel corresponding to the memory and a synchronization arbitration module. The memory channel includes a first priority channel and a second priority channel. The on-chip network is configured to: in a first mode, classify multiple memory access instructions for the memory into at least a first priority and a second priority; map memory access instructions with the first priority to the first priority channel and map memory access instructions with the second priority to the second priority channel; and the synchronization arbitration module is configured to: based on the read / write direction of a first target memory access instruction among the memory access instructions with the first priority to be transmitted in the first priority channel, select a second target memory access instruction that is synchronized with the read / write direction of the first target memory access instruction from the memory access instructions with the second priority to be transmitted in the second priority channel, so as to synchronously transmit the first target memory access instruction and the second target memory access instruction.

[0005] At least one embodiment of this disclosure provides an electronic device, including: at least one processor; and at least one memory storing instructions thereon, wherein the instructions, when executed by the processor, cause the processor to perform the method described above.

[0006] At least one embodiment of this disclosure provides a computer-readable storage medium having computer-readable instructions stored thereon, wherein the computer-readable instructions, when executed by a processor, cause the processor to perform the method described above. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments of this disclosure will be briefly described below. Clearly, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit the scope of this disclosure.

[0008] Figure 1 A schematic diagram illustrating an exemplary memory access operation is shown.

[0009] Figure 2 A schematic diagram of an exemplary multi-core, big.LITTLE architecture is shown.

[0010] Figure 3 A flowchart illustrating a method for managing memory access operations according to at least one embodiment of the present disclosure is shown;

[0011] Figure 4 A schematic diagram of a system-on-a-chip according to at least one embodiment of the present disclosure is shown;

[0012] Figure 5 A schematic diagram of a priority classification module and its interaction with upstream and downstream components according to at least one embodiment of the present disclosure is shown.

[0013] Figure 6 A schematic diagram of a memory channel interleaving allocation scheme according to at least one embodiment of the present disclosure is shown;

[0014] Figure 7 A schematic diagram illustrating the interaction between the synchronous arbitration module and high and low priority channels according to at least one embodiment of the present disclosure is shown.

[0015] Figure 8 A schematic diagram of another system-on-a-chip according to at least one embodiment of the present disclosure is shown;

[0016] Figure 9 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown;

[0017] Figure 10 A schematic diagram of a computer-readable storage medium according to at least one embodiment of the present disclosure is shown;

[0018] Figure 11 A schematic diagram of another electronic device according to at least one embodiment of the present disclosure is shown. Detailed Implementation

[0019] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0020] To enable those skilled in the art to better understand this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of this disclosure to the specific shapes, hardware, connections, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can utilize the concepts of this disclosure to construct further embodiments not mentioned herein by reading this specification.

[0022] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0023] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0024] First, the abbreviations and related terms involved in this application are defined and explained.

[0025] MRDIMM (multi-ranked buffered Dual Inline Memory Module): Multi-ranked buffered dual inline memory module.

[0026] MRCD (Multiplexed Rank Registering Clock Driver): A multi-rank clock buffer driver chip.

[0027] MDB (Multiplexed Rank Data Buffer): A multi-rank data buffer chip.

[0028] NOC (Network on Chip): Network on a chip.

[0029] DF (Data Fabric): Data weaving, a type of general-purpose on-chip network.

[0030] MC (Memory controller): Memory controller.

[0031] MEMCH (Memory controller channel): Memory controller channel.

[0032] QOS (Quality of Service): Priority Service

[0033] PS (pseudo channel): A type of channel in MRDIMM. Two PSs constitute a memory channel in the traditional sense.

[0034] It is understood that the terms defined above are merely exemplary definitions in a specific application scenario to better understand this application, and this disclosure is not limited thereto. For example, the various terms described above for memory can be mapped or extended to other types of memory.

[0035] The memory module can be connected to the corresponding memory control module (e.g., memory controller) through the memory channel, thereby enabling the control module to perform memory access operations (e.g., read operations and / or write operations) on the memory module.

[0036] Figure 1 A schematic diagram of an exemplary memory access operation is shown.

[0037] See Figure 1 The host (e.g., CPU, GPU) can perform read and write operations on the memory module via the memory controller. The memory controller can transmit memory access instructions by coupling with the memory module through the memory channel.

[0038] To improve the bandwidth of memory module access, traditional memory channels can be logically divided into multiple parallel channels. However, dividing traditional memory channels into multiple parallel channels requires memory access instructions to be synchronized, which introduces instruction coordination and corresponding latency.

[0039] For example, MRDIMM is a newly emerging type of memory module that uses MRCD MDB chips to buffer clocks, instructions, and data. It utilizes time-division multiplexing and pseudo-channels to send memory access instructions (e.g., read / write instructions) to multiple memory rank, thereby doubling the read / write bandwidth without requiring DRAM chip bandwidth. However, if doubling the bandwidth is required using MRDIMM, the read / write directions of the two pseudo-channels need to be synchronized. This introduces instruction coordination and corresponding latency.

[0040] The host can initiate memory access commands to operate on the MRDIMM. These commands can be routed via the routing module in the NOC to a cache module (such as a FIFO cache module). The cache module can then transmit the memory access commands to pseudo-channels in the memory controller. The synchronization arbitration module in the memory controller then performs synchronization arbitration on the memory access commands in the corresponding set of pseudo-channels to achieve read / write direction synchronization. For example, the memory controller may include two synchronization arbitration modules, each performing synchronization arbitration on a corresponding set of pseudo-channels. Specifically, each synchronization arbitration module needs to ensure read / write direction synchronization within its corresponding set of pseudo-channels. For instance, when a read-oriented memory access command needs to be transmitted in one pseudo-channel of a set of pseudo-channels, the synchronization arbitration module needs to select another read-oriented memory access command to transmit in another pseudo-channel within the same set of pseudo-channels to the MRDIMM. For example, when a memory access instruction needs to be transmitted in one of the pseudo-channels in a set of pseudo-channels, and that instruction is write-oriented, the synchronous arbitration module needs to select another write-oriented memory access instruction to be transmitted in another pseudo-channel within the same set. In other words, when memory access instructions are transmitted simultaneously or in parallel within a set of pseudo-channels, the memory access instructions in that set of pseudo-channels must be in the same read or write direction.

[0041] However, the inventors of this disclosure realized that in the above example, since the sources of memory access instructions in a set of pseudo-channels are random and their importance cannot be distinguished, and the synchronization arbitration module only performs read-write direction synchronization, there may be more important memory access instructions that may be delayed due to synchronization, which is detrimental to the read-write performance of MRDIMM. For example, this example is not friendly to latency-sensitive scenarios.

[0042] Figure 2 A schematic diagram of an exemplary multi-core, big.LITTLE architecture is shown. This schematic diagram can serve as an example for latency-sensitive scenarios.

[0043] See Figure 2A processor (such as a CPU) can be a multi-core processor using multi-core technology, including big cores and little cores. Big cores (performance cores) have higher frequencies and higher performance, while little cores (energy-efficient cores) have lower frequencies and lower performance. Additionally, big and little cores typically have their own dedicated cache clusters, such as L2 cache and L3 cache.

[0044] Therefore, the inventors of this disclosure realized that there is a need for read / write direction synchronization in memory such as MRDIMM or other types of memory, which introduces latency, and that different cores of the processor have different latency requirements for data retrieval in different working states, thus there is a need for optimization.

[0045] At least one embodiment of the present invention provides a method, system-on-chip, electronic device, and computer-readable storage medium for managing memory access operations. By prioritizing multiple memory access instructions and mapping them to corresponding channels, low-priority memory access instructions can be selected based on the read / write direction of high-priority memory access instructions. This reduces memory access latency and improves user experience when there is a need for read / write direction synchronization in the memory's storage channels.

[0046] Figure 3 A flowchart of a method 300 for managing memory access operations according to at least one embodiment of the present disclosure is shown. Figure 4 A schematic diagram of a system-on-a-chip according to at least one embodiment of the present disclosure is shown. Figure 5 A schematic diagram of a priority classification module and its interaction with upstream and downstream components according to at least one embodiment of the present disclosure is shown. Figure 6 A schematic diagram of a memory channel interleaving allocation scheme according to at least one embodiment of the present disclosure is shown. Figure 7 A schematic diagram illustrating the interaction between a synchronous arbitration module and high / low priority channels according to at least one embodiment of the present disclosure is shown.

[0047] See Figure 3 The method 300 for managing memory access operations, and its additional aspects, described below, can be found in [the following text]. Figure 8 The system-on-a-chip 800, electronic device, hardware architecture, software architecture, or a combination of hardware and software architecture are described.

[0048] See Figure 3 The method 300 for managing memory access operations includes steps S310, S320, and S330. Furthermore, the following is in conjunction with... Figures 4 to 7 This disclosure describes a method 300 for managing memory access operations according to at least one embodiment of the present disclosure, and additional aspects thereof. It will be understood that the following... Figures 4 to 6The various aspects described are merely examples and not limitations, intended to implement the method 300 for managing memory access operations according to at least one embodiment of this disclosure and its additional aspects in specific application scenarios, and are further elaborated below. Figures 4 to 6 The described aspects can be combined with the method 300 for managing memory access operations of at least one embodiment of the present disclosure and its additional aspects.

[0049] For example, see Figure 4 The instruction source (e.g., host 1 to host 6) can perform memory access operations through their respective memory access instructions.

[0050] A memory access instruction can be any instruction and / or associated data that performs a memory access operation. For example, a memory access instruction can include a read instruction and / or a write instruction and / or its associated data.

[0051] Back Figure 3 In step S310, in the first mode, multiple memory access instructions for memory are classified into at least a first priority and a second priority.

[0052] It is understandable that the first and second priorities here can be used to classify memory access instructions based on one or more of the following: urgency, importance, time sensitivity, and resource requirements. Additionally or alternatively, the first and second priorities here can be used to classify memory access instructions based on the performance requirements or performance load of the source of the memory access instruction (hereinafter referred to as the instruction source). For example, if the instruction source includes both large and small cores, the performance requirements of the large cores are higher than those of the small cores; therefore, memory access instructions from the large cores and those from the small cores can be classified as first and second priorities, respectively.

[0053] Due to differences in the urgency, importance, time sensitivity, resource requirements, and / or instruction sources of memory access instructions, multiple memory access instructions can be classified into high-priority and low-priority categories. For example, in cases where the instruction sources include large and small cores, or in other situations, the first priority can be high-priority, and the second priority can be low-priority.

[0054] For example, multiple memory access instructions can be categorized into more than two priorities.

[0055] See Figure 4 Memory access instructions from the host can be transmitted to the priority classification module 402 in the NOC. The priority classification module 402 can classify memory access instructions into first priority (e.g., high priority) and second priority (e.g., low priority).

[0056] In step S320, memory access instructions with a first priority are mapped to the first priority channel in the memory corresponding to the memory channel, and memory access instructions with a second priority are mapped to the second priority channel in the memory corresponding to the memory channel.

[0057] See Figure 4 When interleaving is required and exists, different interleaving modules (high-priority interleaving module 404 and low-priority interleaving module 406) and an optional FIFO can be used to map memory access instructions with first priority to the first priority channel (such as high-priority channels PS0 408 and 412) in the corresponding memory channel, and memory access instructions with second priority to the second priority channel (such as low-priority channels PS0 410 and 414) in the corresponding memory channel. Of course, the embodiments of this disclosure are not limited to this. When interleaving is not required, a routing module or other data transmission module can be used to map memory access instructions with first priority and memory access instructions with second priority to the first and second priority channels in the corresponding memory channel, respectively.

[0058] By mapping memory access instructions with different priorities to different channels, each channel is dedicated to transmitting memory access instructions of different priorities. For example, the first priority channel is used to transmit high-priority memory access instructions, while the second priority channel is used to transmit low-priority memory access instructions. Therefore, the first priority channel can be considered a high-priority channel, and the second priority channel can be considered a low-priority channel.

[0059] In step S330, based on the read / write direction of the first target memory access instruction among the memory access instructions with the first priority to be transmitted through the first priority channel, a second target memory access instruction that is synchronized with the read / write direction of the first target memory access instruction is selected from the memory access instructions with the second priority to be transmitted through the second priority channel, so as to transmit the first target memory access instruction and the second target memory access instruction synchronously.

[0060] See Figure 4Taking high-priority channel PS0 408 and low-priority channel PS1 410 as examples, the synchronization arbitration module 416 can select a second target memory access instruction synchronized with the read / write direction of the first target memory access instruction among the memory access instructions with first priority to be transmitted on the first priority channel (such as high-priority channel PS0 408), and select the second target memory access instruction from the memory access instructions with second priority to be transmitted on the second priority channel (such as low-priority channel PS1 410). This allows for the synchronous transmission of both the first and second target memory access instructions, meaning they are transmitted at roughly the same or similar times. In this way, each time a memory access instruction is transmitted via the first and second priority channels, the read / write direction of a certain instruction on the first priority channel can be used as a reference, and a certain instruction from the second priority channel with the same read / write direction can be piggybacked for transmission. This reduces the transmission waiting time for instructions on the first priority channel.

[0061] There can be one or more memory access instructions with first priority and memory access instructions with second priority. Thus, when transmitting one of the memory access instructions with first priority (such as the first target memory access instruction) through the first priority channel, an instruction with the same read / write direction as the first target memory access instruction (such as the second target memory access instruction) can be selected from the memory access instructions with second priority to achieve synchronous transmission of the read / write directions of the first target memory access instruction and the second target memory access instruction.

[0062] As described above, the method for managing memory access operations according to at least one embodiment of the present disclosure can prioritize multiple memory access instructions and map them to corresponding channels. This allows the selection of low-priority memory access instructions based on the read / write direction of high-priority memory access instructions, thereby reducing memory access latency and improving user experience when there is a need for read / write direction synchronization in the memory's storage channels.

[0063] The following describes some exemplary additional aspects of a method for managing memory access operations according to at least one embodiment of the present disclosure.

[0064] For example, according to at least one embodiment of the present disclosure, the method for managing memory access operations may correspond to a plurality of first priority channels and a plurality of second priority channels, and mapping memory access instructions with first priority to the first priority channels and mapping memory access instructions with second priority to the second priority channels may include: interleaving memory access instructions with first priority to the plurality of first priority channels and interleaving memory access instructions with second priority to the plurality of second priority channels.

[0065] See Figure 4The memory can correspond to multiple first-priority channels (such as high-priority channels PS0408 and 412) and multiple second-priority channels (such as low-priority channels PS0410 and 414). Therefore, a memory channel can include multiple first-priority channels and multiple second-priority channels. When interleaving is required, the high-priority interleaving module 404 can interleave first-priority memory access instructions (such as high-priority memory access instructions) into multiple first-priority channels (such as high-priority channels PS0408 and 412) and interleave second-priority memory access instructions (such as low-priority memory access instructions) into multiple second-priority channels (such as low-priority channels PS0410 and 414).

[0066] Thus, the method for managing memory access operations according to at least one embodiment of the present disclosure can achieve the interleaving of high-priority memory access instructions and low-priority memory access instructions, thereby improving the data transfer efficiency of memory access.

[0067] For example, in the method for managing memory access operations according to at least one embodiment of the present disclosure, the memory may be a multi-row buffered dual in-line memory module, and the first priority channel and the second priority channel may be pseudo channels.

[0068] See Figure 4 The first priority channel (such as high priority channels PS0 408 and 412) and the second priority channel (such as low priority channels PS0 410 and 414) in the memory controller can be connected to a multi-row buffered dual in-line memory module (MRDIMM) to enable memory access operations on the MRDIMM. Additionally, the high priority channels PS0 408 and 412 and the low priority channels PS0 410 and 414 can be pseudo-channels.

[0069] Therefore, the method for managing memory access operations according to at least one embodiment of this disclosure can be applied to application scenarios that perform memory access operations on MRDIMMs. Of course, the embodiments of this disclosure are not limited thereto, and the method for managing memory access operations according to at least one embodiment of this disclosure can be applied to other types of memory.

[0070] For example, according to at least one embodiment of the present disclosure, the method for managing memory access operations may classify multiple memory access instructions into at least a first priority and a second priority, which may include classifying the multiple memory access instructions into at least a first priority and a second priority based on the performance requirements of the respective instruction sources that initiate the multiple memory access instructions.

[0071] For example, the instruction source can be any device that performs memory access operations via memory access instructions. For example, the instruction source can be... Figure 4The host 1 to host 6 are illustrated in the example. Alternatively or additionally, the instruction source may be a device other than the system-on-chip. For example, different hosts may have different performance requirements, such as different power consumption and operating frequencies, and thus different sensitivities to latency.

[0072] Thus, the method for managing memory access operations according to at least one embodiment of the present disclosure can be applied to scenarios with instruction sources that have different performance requirements.

[0073] For example, in a method for managing memory access operations according to at least one embodiment of this disclosure, the instruction source includes a large core and a small core, wherein the performance requirements of the large core are higher than those of the small core, and memory access instructions initiated by the large core are classified as first priority, while memory access instructions initiated by the small core are classified as second priority. For example, the specifications of the large core (e.g., the number of integrated transistors, operating frequency, or instruction throughput, etc.) are greater than those of the small core.

[0074] For example, the instruction source may include Figure 2 and / or Figure 5 The large and small cores in the same processor are shown, for example, if the processor is a multi-core processor or a system-on-a-chip (SoC). Additionally or alternatively, the instruction source may also include other host components, such as a direct memory access (DMA) controller.

[0075] Thus, the method for managing memory access operations according to at least one embodiment of the present disclosure can be applied to application scenarios with big and small cores, improving the efficiency of processor accessing memory.

[0076] For example, in a method for managing memory access operations according to at least one embodiment of the present disclosure, a plurality of memory access instructions each include a flag bit used to indicate the instruction source of the plurality of memory access instructions.

[0077] See Figure 5 Memory access instructions initiated by the naming source can be transmitted to the priority classification module (e.g., Figure 4 The priority classification module 402 in the memory access module can be used to identify the instruction source of a memory access instruction. The memory access instruction may include flag bits and other information. The flag bits can be used to indicate the instruction source of each memory access instruction. For example, the priority classification module can identify that a memory access instruction originating from a large core is based on the flag bits in the memory access instruction initiated by the large core; the priority classification module can identify that a memory access instruction originating from a small core is based on the flag bits in the memory access instruction initiated by another host; and the priority classification module can identify that a memory access instruction originating from another host is based on the flag bits in the memory access instruction initiated by another host.

[0078] Thus, the method for managing memory access operations according to at least one embodiment of the present disclosure can facilitate the identification of the instruction source corresponding to the memory access instruction, thereby promoting the classification of memory access instructions.

[0079] See also Figure 5 After classification, the priority classification module can transmit memory access instructions to the high-priority interleaving module (such as high-priority interleaving module 404 and low-priority interleaving module 406) via the multiplexing module (MUX).

[0080] The inventors of this disclosure recognized that managing memory access operations in a single mode is inefficient due to the diversity of operating conditions. Therefore, it is necessary to provide options for managing memory access operations in different modes to suit different operating conditions. For example, in the presence of multiple first-priority channels (such as high-priority channels PS0 408 and 412) and multiple second-priority channels (such as low-priority channels PS0 410 and 414), there is a need for low power consumption, which can be achieved through the second mode described below. Furthermore, in some operating conditions, such as when latency is not a concern, the priority classification described above is not required, which can be achieved through the third mode described below.

[0081] For example, the method for managing memory access operations according to at least one embodiment of the present disclosure may further include: in a second mode, mapping multiple memory access instructions to multiple first priority channels or multiple second priority channels.

[0082] For example, see Figure 4 In the second mode, multiple memory access instructions can be mapped to multiple first-priority channels (such as high-priority channels PS0 408 and 412) or multiple second-priority channels (such as low-priority channels PS1 410 and 414). That is, it is only necessary to map them to one of the high-priority channels and low-priority channels, without having to map them to both of the high-priority channels and low-priority channels at the same time.

[0083] Thus, the method for managing memory access operations according to at least one embodiment of the present disclosure can reduce the power consumption of channel operation.

[0084] In some embodiments, the selection of low-priority memory access instructions can be based on the read / write direction of high-priority memory access instructions, similar to the first mode. Therefore, in the second mode, multiple memory access instructions can be mapped to multiple first-priority channels, i.e., high-priority channels. This maintains the synchronous arbitration function of the first mode while reducing the configuration and modification of synchronous arbitration.

[0085] For example, the method for managing memory access operations according to at least one embodiment of the present disclosure may further include: in a third mode, randomly mapping multiple memory access instructions for the memory to a first priority channel and a second priority channel; and when a first randomly mapped memory access instruction is transmitted in the first priority channel, selecting a second randomly mapped memory access instruction synchronized with the read / write direction of the first randomly mapped memory access instruction in the second priority channel for transmission in the second priority channel.

[0086] For example, it can be disabled in the third mode. Figure 4 The priority classification module 402 and / or the high priority interleaving module 404 and the low priority interleaving module 406 in the system map memory access instructions to the first priority channel and the second priority channel via, for example, the routing module in the NOC.

[0087] It's understandable that "random" here refers to memory access instructions having no priority. Therefore, memory access instructions within the first and second priority channels essentially have no priority.

[0088] For example, see Figure 6 Memory access instructions 0 to N can be alternately mapped to channels (such as first priority channels and second priority channels) at predetermined addresses or time intervals.

[0089] Thus, the method for managing memory access operations according to at least one embodiment of the present disclosure can be applied to, for example, latency-insensitive operating conditions.

[0090] In some embodiments, since the memory access instructions in the first priority channel and the second priority channel do not actually have different priorities, it is not necessary to configure a synchronization arbitration module to select the low priority memory access instruction based on the read / write direction of the high priority memory access instruction. Instead, it is only necessary to keep the read / write directions of the memory access instructions in the two channels synchronized.

[0091] Additionally, the first, second, and third modes described above can be enabled through configuration. For example, the firmware of the on-chip system can be configured to set registers to the NOC (e.g., Figure 4 The priority classification module 402, high-priority interleaving module 404, low-priority interleaving module 406, etc. in the memory controller and the synchronization arbitration module in the memory controller (e.g., Figure 4 Synchronous arbitration (416 and 418) in the model is used to implement the functions or operations of the corresponding modes. For example, Figure 5 The priority classification module supports three modes: mode 1, mode 2, and mode 3. These modes can be enabled by configuring registers.

[0092] For example, the method for managing memory access operations according to at least one embodiment of the present disclosure may further include: in response to the absence of a second target memory access instruction synchronized with the read / write direction of the first target memory access instruction in the second priority channel, transmitting the first target memory access instruction separately.

[0093] For example, when the first target memory access instruction in a memory access instruction with the first priority is transmitted in the first priority channel (such as the high priority channel), there is no second target memory access instruction in the second priority channel (such as the low priority channel) that is synchronized with the read / write direction of the first target memory access instruction. Instead of waiting for the second target memory access instruction that is synchronized with the read / write direction of the first target memory access instruction, the first target memory access instruction is transmitted directly and separately.

[0094] Thus, the method for managing memory access operations according to at least one embodiment of the present disclosure can avoid delays caused by waiting for a second target memory access instruction that is synchronized with the read / write direction of the first target memory access instruction.

[0095] For example, the method for managing memory access operations according to at least one embodiment of the present disclosure may further include: in response to the existence of a timeout waiting memory access instruction in a second priority channel with a waiting time exceeding a threshold, transmitting the timeout waiting memory access instruction, and selecting a third target memory access instruction from memory access instructions having a first priority that is synchronized with the read / write direction of the timeout waiting memory access instruction for transmission in the first priority channel.

[0096] For example, see Figure 7 It can time the waiting time for memory access instructions in the second priority channel (such as the low priority channel) to be transmitted. When the waiting time for a certain memory access instruction (such as memory access instruction 0) is above the threshold (such as 60 microseconds or other time), the memory access instruction in the first priority channel (such as the high priority channel) can be selected for transmission based on the read / write direction of the memory access instruction.

[0097] See Figure 7 In one example, for instance, memory access instruction 0 in a low-priority channel is read-oriented, and memory access instruction 0 waits for 60 microseconds to be transmitted because a write-oriented memory access instruction was previously executed in a high-priority channel or memory access instruction 0 was not selected and transmitted. If this wait time exceeds the threshold of 60 microseconds, memory access instruction 0 can be transmitted, and a memory access instruction 0' that is also read-oriented in the high-priority channel can be selected for transmission.

[0098] Thus, the method for managing memory access operations according to at least one embodiment of the present disclosure sets up an anti-starvation mechanism for low-priority channels, which avoids the long-term non-transmission of memory access instructions in the priority channel and affects their execution while maintaining the read and write direction of low-priority memory access instructions in accordance with the read and write direction of high-priority memory access instructions.

[0099] See Figure 4 and Figure 5 In the exemplary structure, the first mode may be referred to as performance mode. Performance mode can be applied to, for example, latency-sensitive operating conditions. When performance mode is enabled, default high-priority channels can be allocated to performance cores (big cores) in the NOC's interleaving modules (such as high-priority interleaving module 404 and low-priority interleaving module 406). Interleaving is limited to within high-priority channels and low-priority channels and cannot be interleaved with each other. For example, in performance mode, the NOC (such as DF or other types of NOC) can classify memory access instructions from different cores (or L3 cache information) according to the issued memory access instructions (e.g., by including fields in the memory access instructions given to the NOC to indicate the source of the memory access instruction as information). Memory access instructions belonging to big cores and small cores will be interleaved and placed into different memory channel buffer modules (such as FIFOs) and passed to the memory controller, where big cores correspond to high-priority channel PS0 and small cores correspond to low-priority channel PS1. Additionally, a memory control register can be configured to use a synchronous arbitration module (such as synchronous arbitration modules 416 and 418) for priority channel arbitration. In this case, memory access instructions in the low-priority channel will be matched according to the read / write direction of memory access instructions in the high-priority channel, ensuring that read / write operations in the high-priority channel are not hindered. Furthermore, memory access instructions in the low-priority channel can be equipped with the anti-starvation mechanism described above and corresponding read / write pipeline control. Under critical conditions, the synchronous arbitration module is notified to adjust the arbitration strategy, ensuring that memory access instructions in the low-priority channel can be issued.

[0100] The second mode can be referred to as low-power mode. Low-power mode is suitable for applications with low bandwidth requirements, for example. When low-power mode is enabled, the NOC can allocate all new write commands to, for example, the high-priority channel PS0, while putting the low-priority channel PS1 into self-refresh mode, using only half of the DRAM, thereby reducing power consumption.

[0101] The third mode can be called energy efficiency mode. Energy efficiency mode is suitable for situations where, for example, the workload of large cores is not high. When energy efficiency mode is enabled, regular interleaving modes (such as page interleaving, cache line interleaving, cache flag interleaving, etc.) can be used to properly allocate memory access instructions to various channels.

[0102] Therefore, in Figure 4 and Figure 5 In the exemplary structure, high and low priority control logic is added to the synchronous arbitration module of the memory controller, and high and low channels are allocated in the interleaving module inside the NOC to adapt to the needs of different cores, so as to support the implementation of high and low priority memory channels on, for example, MRDIMM.

[0103] In performance mode, allocating higher-priority channels to larger, more heavily loaded cores reduces memory access latency, minimizes pipeline bubbles, increases instructions per cycle (IPC), and improves CPU efficiency and user experience. Additionally, in energy efficiency mode, normal interleaving (i.e., without using the priority classification module's classification function) maintains the system's bandwidth requirements under balanced core load. Furthermore, in low-power mode (e.g., using only some smaller cores with lower bandwidth requirements), a certain number of memory channels can be disabled, and only high-priority channels are allocated to energy efficiency cores.

[0104] In some embodiments, the method for managing memory access operations according to at least one embodiment of this disclosure can be an improvement on existing on-chip systems used for memory access operations on MRDIMMs. For example, a priority classification module can be added to the DF (Distribution Controller) to allocate priorities based on the source of memory access instructions before sending them to their respective interleaving modules. For example, a priority submodule can be added to the synchronization arbitration module of the MRDIMM memory controller. This priority submodule has priority-related functional support, including automatically matching the read / write direction of memory access instructions in low-priority channels with the read / write method of memory access instructions in high-priority channels, and additionally setting an anti-starvation mechanism for memory access instructions in low-priority channels. For example, the priority classification module can be configured to enter three modes through channel arbitration selection: performance mode, energy efficiency mode, and low-power mode.

[0105] In addition, the method for managing memory access operations according to at least one embodiment of the present disclosure can be applied to various memory modules introduced by MRCD chips and other DRAMs such as LPDDR that introduce clock buffering and time-division multiplexing technologies similar to MRCD MDB.

[0106] In addition, the priority classification module can be set in other locations, such as the memory controller entry point or the interleaving module of the NOC memory network, but the core function is still to classify and specify the priority according to the source of the memory access instruction.

[0107] Corresponding to the method 300 for managing memory access operations according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure also provides a system-on-a-chip.

[0108] Figure 8A schematic diagram of another system-on-a-chip 800 according to at least one embodiment of the present disclosure is shown.

[0109] See Figure 8 The system-on-chip 800 includes an on-chip network 810 and a memory controller 820. The memory controller is used for the memory and includes a memory channel corresponding to the memory and a synchronization arbitration module. The memory channel includes a first priority channel and a second priority channel.

[0110] The on-chip network 810 is configured to: in a first mode, classify multiple memory access instructions for memory into at least a first priority and a second priority; and map memory access instructions with the first priority to a first priority channel and memory access instructions with the second priority to a second priority channel.

[0111] The synchronous arbitration module 826 is configured to: select a second target memory access instruction that is synchronized with the read / write direction of the first target memory access instruction among the memory access instructions with the first priority to be transmitted on the first priority channel, based on the read / write direction of the first target memory access instruction, so as to synchronously transmit the first target memory access instruction and the second target memory access instruction.

[0112] In some embodiments, the on-chip network 810, the first priority channel 822 of the memory controller 820, the second priority channel 824, and the synchronization arbitration module 826 may correspond to the above-mentioned... Figure 4 The NOC, memory controller, high-priority channel PS0, low-priority channel PS1, and synchronous arbitration module are described.

[0113] The additional aspects of the system-on-chip 800 according to at least one embodiment of the present disclosure can correspond to the additional aspects of the method 300 for managing memory access operations according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the method 300 for managing memory access operations according to at least one embodiment of the present disclosure can also be mapped to the additional aspects of the system-on-chip 800 according to at least one embodiment of the present disclosure, which will not be repeated here.

[0114] For example, in a system-on-a-chip according to at least one embodiment of the present disclosure, the memory channel may include a plurality of first priority channels and a plurality of second priority channels, and the on-chip network may further include: a first priority interleaving module configured to: interleave first priority memory access instructions to the plurality of first priority channels; and a second priority interleaving module configured to: interleave second priority memory access instructions to the plurality of second priority channels.

[0115] For example, in a system-on-a-chip according to at least one embodiment of the present disclosure, the on-chip network is further configured to: in a second mode, map multiple memory access instructions to multiple first priority channels or multiple second priority channels.

[0116] For example, in a system-on-chip according to at least one embodiment of the present disclosure, the synchronization arbitration module is further configured to: transmit the timeout waiting memory access instruction in response to the existence of a timeout waiting memory access instruction in the second priority channel with a waiting time exceeding a threshold, and select a third target memory access instruction from the memory access instructions with a first priority that is synchronized with the read / write direction of the timeout waiting memory access instruction for transmission in the first priority channel.

[0117] For example, according to at least one embodiment of the system-on-chip of the present disclosure, the on-chip network is further configured to: in a third mode, randomly map a plurality of memory access instructions for memory to a first priority channel and a second priority channel; and when a first randomly mapped memory access instruction is transmitted in the first priority channel, select a second randomly mapped memory access instruction synchronized with the read / write direction of the first randomly mapped memory access instruction in the second priority channel for transmission in the second priority channel.

[0118] For example, in a system-on-a-chip according to at least one embodiment of the present disclosure, the memory is a multi-row buffered dual in-line memory module, and the first priority channel and the second priority channel are pseudo channels.

[0119] For example, in a system-on-a-chip according to at least one embodiment of the present disclosure, the on-chip network is further configured to classify the multiple memory access instructions into at least a first priority and a second priority based on the performance requirements of the respective instruction sources that initiate the multiple memory access instructions.

[0120] Figure 9 A schematic diagram of an electronic device 900 according to at least one embodiment of the present disclosure is shown.

[0121] like Figure 9 As shown, the electronic device 900 includes at least one processing unit 920 and a memory 910. The memory 910 stores computer-readable instructions and is communicatively connected to the processing unit 920. The processing unit 920 executes the computer-readable instructions stored in the memory 910 to implement a method for managing memory access operations according to at least one embodiment of the present disclosure, and additional aspects thereof.

[0122] For example, the memory 910 and the processing unit 920 can communicate with each other directly or indirectly. For example, in some examples, such as... Figure 9As shown, the electronic device 900 may also include a system bus 930, through which the memory 910 and the processing unit 920 can communicate with each other. For example, the processing unit 920 can access the memory 910 through the system bus 930. For example, in other examples, components such as the memory 910 and the processing unit 920 can communicate through a network on-chip (NOC) connection.

[0123] For example, the processing unit 920 can control other components in the electronic device 900 to perform desired functions. The processing unit 920 can be a device with data processing and / or program execution capabilities, such as a central processing unit (CPU), tensor processor (TPU), network processor (NP), or graphics processor (GPU), or it can be a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0124] For example, memory 910 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0125] For example, one or more computer-readable instructions can be stored on the memory 910, and the processing unit 920 can execute the computer-readable instructions to perform various functions. Various application programs and various data, such as instruction processing code and various data used and / or generated by the application programs, can also be stored in the computer-readable storage medium.

[0126] For example, when some computer instructions stored in memory 910 are executed by processing unit 920, one or more steps of the method for managing memory access operations as described above can be performed.

[0127] For example, such as Figure 9 As shown, the electronic device 900 may further include an input interface 940 that allows external devices to communicate with the electronic device 900. For example, the input interface 940 may be used to receive instructions from external computer devices, users, etc. The electronic device 900 may also include an output interface 950 that enables the electronic device 900 to connect to one or more external devices. For example, the electronic device 900 can communicate via the output interface 950, etc.

[0128] It should be noted that the electronic device 900 according to at least one embodiment of the present disclosure is exemplary and not restrictive. Depending on the actual application needs, the electronic device 900 may also include other conventional components or structures. For example, in order to realize the necessary functions of the electronic device, those skilled in the art can set other conventional components or structures according to the specific application scenario. The embodiments of the present disclosure do not limit this.

[0129] At least one embodiment of this disclosure also provides a computer-readable storage medium. Figure 10 A schematic diagram of a computer-readable storage medium 1000 according to at least one embodiment of the present disclosure is shown.

[0130] For example, such as Figure 10 As shown, the computer-readable storage medium 1000 stores computer-readable instructions 1010, which, when executed by a computer (including a processor), can implement a method for managing memory access operations according to at least one embodiment of the present disclosure, and additional aspects thereof.

[0131] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 1000. Some of the computer-readable instructions stored on the computer-readable storage medium 1000 may be, for example, instructions for implementing one or more steps in the method described above for managing memory access operations.

[0132] For example, a computer-readable storage medium may include the storage component of a tablet computer, a hard disk of a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical disc read-only memory (CD-ROM), flash memory, or any combination of the above computer-readable storage media, or other suitable storage media. For example, computer-readable storage medium 1000 may include the memory 910 in the electronic device 900 described above.

[0133] At least some embodiments of this disclosure also provide an electronic device. Figure 11 A schematic diagram of another electronic device 1100 according to at least one embodiment of the present disclosure is shown.

[0134] The electronic device according to at least one embodiment of the present disclosure can be implemented as, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs, desktop computers, etc.

[0135] Figure 11The electronic device 1100 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0136] For example, such as Figure 11 As shown, in some examples, electronic device 1100 includes processor 1101, which may include the processor of any of the above embodiments (e.g., a single-threaded or multi-threaded processor), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1102 or a program loaded from storage device 1108 into random access memory (RAM) 1103. Various programs and data required for the operation of the computer system are also stored in RAM 1103. Processor 1101, ROM 1102, and RAM 1103 are connected via bus 1104. Input / output (I / O) interface 1105 is also connected to bus 1104.

[0137] For example, the following components can be connected to I / O interface 1105: input devices 1106 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1107 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1108 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1109, such as network interface cards like LAN cards and modems, etc. Communication device 1109 allows electronic device 1100 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1110 is also connected to I / O interface 1105 as needed. Removable media 1111, such as disks, optical discs, magneto-optical discs, semiconductor memories, etc., are installed on drive 1110 as needed so that computer programs read from them can be installed into storage device 1108 as needed. Although Figure 11 An electronic device 1100 including various means is shown; however, it should be understood that implementation or inclusion of all the means shown is not required. More or fewer means may be implemented or included alternatively.

[0138] For example, the electronic device 1100 may further include a peripheral interface (not shown). This peripheral interface can be of various types, such as a USB interface, a Lightning interface, etc. The communication device 1109 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0139] In addition to the exemplary descriptions above, the following points should be noted regarding this disclosure:

[0140] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0141] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0142] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A method for managing memory access operations, comprising: In the first mode, The multiple memory access instructions for the memory are classified into at least a first priority and a second priority. The memory access instruction with the first priority is mapped to the first priority channel in the memory channel corresponding to the memory, and the memory access instruction with the second priority is mapped to the second priority channel in the memory channel corresponding to the memory, wherein the first priority channel and the second priority channel have the requirement of read-write direction synchronization; as well as Based on the read / write direction of the first target memory access instruction among the memory access instructions with the first priority to be transmitted through the first priority channel, a second target memory access instruction that is synchronized with the read / write direction of the first target memory access instruction is selected from the memory access instructions with the second priority to be transmitted through the second priority channel, so as to synchronously transmit the first target memory access instruction and the second target memory access instruction.

2. The method according to claim 1, wherein, The memory corresponds to multiple first-priority channels and multiple second-priority channels, and Mapping memory access instructions with the first priority to the first priority channel, and mapping memory access instructions with the second priority to the second priority channel, includes: The memory access instructions of the first priority are interleaved into the plurality of first priority channels, and the memory access instructions of the second priority are interleaved into the plurality of second priority channels.

3. The method according to claim 2, further comprising: In the second mode, The plurality of memory access instructions are mapped to the plurality of first priority channels or the plurality of second priority channels.

4. The method according to claim 3, wherein, The memory is a multi-row buffered dual in-line memory module, and the first priority channel and the second priority channel are pseudo channels.

5. The method according to any one of claims 1 to 3, wherein, The step of classifying multiple memory access instructions for the memory into at least a first priority and a second priority includes: Based on the performance requirements of the respective instruction sources that initiate the multiple memory access instructions, the multiple memory access instructions are classified into at least a first priority and a second priority.

6. The method according to claim 5, wherein, The instruction source includes large cores and small cores, wherein the performance requirements of the large cores are higher than those of the small cores, and memory access instructions initiated by the large cores are classified as the first priority, while memory access instructions initiated by the small cores are classified as the second priority.

7. The method according to any one of claims 1 to 3, further comprising: In response to the absence of a second target memory access instruction synchronized with the read / write direction of the first target memory access instruction in the second priority channel, the first target memory access instruction is transmitted separately.

8. The method according to any one of claims 1 to 3, further comprising: In response to a timeout memory access instruction in the second priority channel whose waiting time for transmission exceeds a threshold, the timeout memory access instruction is transmitted, and a third target memory access instruction that is synchronized with the read / write direction of the timeout memory access instruction is selected from the memory access instructions with the first priority to be transmitted in the first priority channel.

9. The method according to any one of claims 1 to 3, further comprising: In the third mode, Multiple memory access instructions for the memory are randomly mapped to the first priority channel and the second priority channel; as well as When a first random mapping memory access instruction is transmitted in the first priority channel, a second random mapping memory access instruction that is synchronized with the read / write direction of the first random mapping memory access instruction is selected in the second priority channel for transmission within the second priority channel.

10. The method according to any one of claims 1 to 3, wherein, Each of the plurality of memory access instructions includes a flag bit, which is used to indicate the instruction source of each of the plurality of memory access instructions.

11. A system-on-a-chip, comprising an on-chip network and a memory controller, wherein, The memory controller is used to control the memory and includes a memory channel corresponding to the memory and a synchronization arbitration module. The memory channel includes a first priority channel and a second priority channel. The on-chip network is configured as follows: In the first mode, multiple memory access instructions for the memory are classified into at least a first priority and a second priority. and Memory access instructions with the first priority are mapped to the first priority channel, and memory access instructions with the second priority are mapped to the second priority channel, wherein the first priority channel and the second priority channel have a requirement for read-write direction synchronization; as well as The synchronous arbitration module is configured as follows: Based on the read / write direction of the first target memory access instruction among the memory access instructions with the first priority to be transmitted through the first priority channel, a second target memory access instruction that is synchronized with the read / write direction of the first target memory access instruction is selected from the memory access instructions with the second priority to be transmitted through the second priority channel, so as to synchronously transmit the first target memory access instruction and the second target memory access instruction.

12. The system-on-a-chip according to claim 11, wherein, The storage channel includes multiple first-priority channels and multiple second-priority channels, and the on-chip network further includes: The first priority interleaving module is configured to: interleave memory access instructions of the first priority to the plurality of first priority channels; and The second priority interleaving module is configured to interleave memory access instructions of the second priority to the plurality of second priority channels.

13. The system-on-a-chip according to claim 12, wherein, The on-chip network is also configured to: in a second mode, map the plurality of memory access instructions to the plurality of first priority channels or the plurality of second priority channels.

14. The system-on-a-chip according to claim 11, wherein, The synchronous arbitration module is further configured to: in response to a timeout memory access instruction in the second priority channel whose waiting time for transmission exceeds a threshold, transmit the timeout memory access instruction, and select a third target memory access instruction from the memory access instructions with the first priority that is synchronized with the read / write direction of the timeout memory access instruction for transmission in the first priority channel.

15. The system-on-a-chip according to claim 11, wherein, The on-chip network is also configured to: In the third mode, multiple memory access instructions for the memory are randomly mapped to the first priority channel and the second priority channel; as well as When a first random mapping memory access instruction is transmitted in the first priority channel, a second random mapping memory access instruction that is synchronized with the read / write direction of the first random mapping memory access instruction is selected in the second priority channel for transmission within the second priority channel.

16. The system-on-a-chip according to claim 11, wherein, The memory is a multi-row buffered dual in-line memory module, and the first priority channel and the second priority channel are pseudo channels.

17. The system-on-a-chip according to claim 11, wherein, The on-chip network is also configured to classify the plurality of memory access instructions into at least a first priority and a second priority based on the performance requirements of the respective instruction sources that initiate the plurality of memory access instructions.

18. An electronic device comprising: At least one processor; At least one memory, on which instructions are stored, When the instruction is executed by the processor, it causes the processor to perform the method as described in any one of claims 1 to 10.

19. A computer-readable storage medium having computer-readable instructions stored thereon, in, When executed by a processor, the computer-readable instructions cause the processor to perform the method as described in any one of claims 1 to 10.

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