A layout method based on a venne diagram, an electronic device, and a storage medium

Abstract

The present application relates to chip design technical field, particularly to a kind of based on venne diagram layout method, electronic equipment and storage medium, it is by the non-separable unit group in original netlist as movable node condensation netlist, and set a fixed reference node for each movable node and configure reference line net;By iteration optimization the total bus length of all line nets, and based on the optimization result of total bus length generates venne diagram, and iteration optimization the position of cell vertex and station makes cell swell or shrink, when total bus length converges and cell converges to target area, then iteration ends, realize the purpose of obtaining suitable layout result for division under the condition of meeting specific constraints.In the premise that layout result is used for chip grain division reference, modeling is carried out according to non-separable unit group, significantly reduces the problem scale, accelerates the solution speed, shortens the design cycle.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a layout method based on a Vinyson diagram, an electronic device, and a storage medium. Background Technology

[0002] As chip manufacturing processes approach the physical limits of materials, improving integrated circuit performance by shrinking transistor size faces increasing technological bottlenecks and rising manufacturing costs. Chip-to-chip (CTC) technology, through novel packaging techniques, interconnects and packages chips manufactured using different processes into a single heterogeneous chip, thereby improving yield, reducing costs, increasing design flexibility, and shortening design cycles. Therefore, CTCs and their integrated packaging technologies have become a technological trend for maintaining the industry's continued development.

[0003] Chip development based on chip technology begins with dividing the system-level design into multiple sub-designs as chips, which are then designed and manufactured separately. The logical partitioning and physical layout of these chips are crucial steps affecting the performance of the integrated chip system. Currently, modeling the chip partitioning problem is still in the exploratory stage, and many designs still rely on manual methods, depending on prior knowledge and experience. With technological advancements, the increasing number of chips will lead to an exponential increase in partitioning complexity, even a combinatorial progression. In this case, manual partitioning will struggle to find the optimal solution. Modeling the chip partitioning problem for global optimization typically involves first performing a global layout, and then using the layout result as a reference for chip partitioning, achieving unified optimization of logical and physical partitioning. Considering both the explicitness of the logical design and the physical realizability, chip partitioning should generally satisfy the following constraints: First, chip regions should not overlap; second, standard cells and macrocells (indivisible cell groups) within the same indivisible unit group should be partitioned into the same chip. Unit group rules include, but are not limited to, the number of cells, cell type, logical hierarchy, and other constraints provided by the designer. Layout methods for core partitioning should fully consider the actual needs and constraints of core partitioning, providing feasible reference layouts. Therefore, there is an urgent need for a layout method that provides suitable layout results for partitioning under the aforementioned specific constraints. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution: a layout method based on a Vinio diagram, the method comprising the following steps: S100, the indivisible unit groups in the original netlist are used as movable nodes to shrink the netlist, resulting in a new shrunken netlist.

[0005] S200, set a fixed reference node for each movable node in the new netlist, set a net between the movable node and its reference node, and update the new netlist.

[0006] S300, calculate the gradient of the new netlist with respect to the bus length, and iteratively optimize the position of the movable node.

[0007] S400, using the position of each of the movable nodes as a station, generate a Veno map.

[0008] S500: Obtain the area difference between the target area and the current area of ​​each cell in the Venn diagram, and iteratively optimize the position of the vertices and stations of each cell based on the area difference, so that the area of ​​each cell expands or contracts.

[0009] S600: When the bus length converges and the cell converges to the target area, the iteration ends and the layout result is obtained; otherwise, the position of the reference node is updated to the geometric center of the current cell, the reference mesh weight is increased, and the process returns to execute S300.

[0010] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.

[0011] In addition, the present invention provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0012] The present invention has at least the following beneficial effects: This invention provides a layout method, electronic device, and storage medium based on a Venn diagram. It shrinks the netlist by treating the indivisible unit groups in the original netlist as movable nodes, and sets a fixed reference node and configures a reference net for each movable node. By iteratively optimizing the bus length of all nets, a Venn diagram is generated based on the optimization results. The positions of the vertices and stations of cells are iteratively optimized to cause cell expansion or contraction. The iteration ends when the bus length converges and the cell converges to the target area, achieving the goal of obtaining a layout result suitable for partitioning under specific constraints. Furthermore, the layout result fully considers the core-grain partitioning constraints: there is no overlap between different indivisible unit groups, and the units within a group are not scattered. Through the Venn diagram and cells, the irregular envelope trend formed by all standard units and macrounits within the indivisible unit groups under optimized layout is explored and characterized. Convergence is ensured as the weight of the reference net increases. Under the premise that the layout result is used as a reference for core-grain partitioning, modeling by indivisible unit groups significantly reduces the problem size, accelerates the solution speed, and shortens the design cycle. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart of a layout method based on a Vinio diagram, provided as an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.

[0017] First, it should be noted that the core partitioning based on the layout result requires unified optimization of both logical and physical partitioning. Considering both the clarity of the logical design and the physical realizability, core partitioning should satisfy the following constraints: First, core regions should not overlap. Second, standard cells and macrocells within the same indivisible unit group should be partitioned into the same core. Under the condition of satisfying the core partitioning constraints, this invention provides a layout method based on a Vinograph.

[0018] Please see Figure 1 It illustrates a layout method based on a Vinio diagram, the method comprising the following steps: S100, the indivisible unit groups in the original netlist are used as movable nodes to shrink the netlist, resulting in a new shrunken netlist.

[0019] Among them, the indivisible unit group is the basic unit that moves in the layout and cannot be subdivided into different core particles.

[0020] The indivisible unit group includes standard units, macro units, or both. Indivisible unit groups are aggregated according to user-defined constraints. Standard units are basic logic units in integrated circuits, while macro units are functional modules, such as memory and computing units.

[0021] In one embodiment, the constraint is one or more of the following: unit type, number of units, and logical level. Other types of constraints also fall within the protection scope of this invention.

[0022] When the grouping constraints are element type and element number, as an example, N macroelements are aggregated into a single indivisible element group. Alternatively, N macroelements and standard elements are aggregated into a single indivisible element group.

[0023] As an example, the chip design includes unit A, unit B, and indivisible unit group C. Unit A and unit B are units of the same type. According to the user's preset, unit A and unit B are condensed into indivisible unit group D according to the unit type, and D is connected to C.

[0024] It should be noted that the number of movable nodes in the condensed netlist is significantly reduced compared to the number of elements in the original netlist, which means a significant reduction in the number of nodes that need to be optimized, thus reducing the problem size and improving optimization efficiency.

[0025] S200, set a fixed reference node for each movable node in the new netlist, set a reference net between the movable node and its reference node, and update the new netlist.

[0026] The weight of the wire mesh is used to represent the priority of the wire mesh in the optimization.

[0027] S300, calculate the gradient of the new netlist with respect to the bus length, and iteratively optimize the position of the movable node.

[0028] The bus length is the sum of all nets in the new netlist, which includes nets between movable nodes and reference nets.

[0029] The bus length is obtained once the positions of all movable nodes are determined. Based on the bus length and the position of each node, the gradient direction of each movable node that causes the bus length to decrease is calculated.

[0030] The purpose of iterative optimization is to gradually adjust the position of movable nodes through gradient descent to minimize the bus length.

[0031] Here, the gradient of the bus length represents the direction and rate of change of the bus length. The gradient of the bus length helps determine how movable nodes should adjust their positions to reach the optimal bus length as quickly as possible. For example, moving the movable node in the opposite direction of the gradient usually results in the fastest reduction of the bus length, providing a clear search direction for the optimization algorithm and helping to improve the efficiency of the optimization process.

[0032] In one implementation, the gradient of the bus length is a weighted sum of the gradients of all nets. The weights are used to adjust the priority of different net optimizations, amplifying the gradient components of key nets to have a greater impact on the movement direction of movable nodes.

[0033] In one implementation, the initial weight of the reference net is 0.

[0034] In one implementation, the weights of the nets between the movable nodes are determined based on the number of original nets they contain before shrinking. The weights apply to the entire net.

[0035] In one implementation, each original net has a weight of 1, and the weight of the nets between the movable nodes is equal to the number of original nets shrunk. As an example, when the shrunk unit D shrunk two nets, the net weight of unit D is 2.

[0036] In one implementation, the method for adjusting the weights of the nets between the movable nodes includes: if the current net is a net containing a critical timing path, increasing or decreasing the weight value according to a preset strategy. For example, for critical timing paths, when the path shape of the critical timing path is a straight path or a curved path, the signal transmission delay of the straight path is small, which is beneficial to meeting timing requirements. The winding in the curved path increases the wire length and parasitic resistance, resulting in increased delay. Increasing the weight value can force the placement and routing tool to prioritize straightening the critical path and reduce winding. However, in order to avoid over-optimizing a single critical path and causing other paths to deteriorate, it is necessary to appropriately reduce the weight; for example, if forcibly straightening a path will make other critical paths more complex, its weight needs to be reduced to balance the global placement.

[0037] In one implementation, the gradient algorithm for the line length is an LSE (Log-Sum-Exp) model, a WA (Weighted Average) model, or a numerical difference method. Other algorithms for calculating the line length gradient also fall within the scope of protection of this invention.

[0038] S400, using the position of each of the movable nodes as a station, generate a Veno map.

[0039] The Voronoi Diagram, also known as the Thiessen polygon or Dirichlet diagram, is a continuous polygon composed of a set of perpendicular bisectors of lines connecting two adjacent points.

[0040] In a Venn diagram, a cell is a polygonal region bounded by the perpendicular bisectors of the line segments connecting adjacent stations. These perpendicular bisectors divide the plane into multiple distinct regions, each region being a cell, and each cell uniquely corresponding to a station.

[0041] In one embodiment, the method for generating a Venn diagram is the divide-and-conquer method, the scan-line algorithm, or the Delaunay triangulation algorithm. Other algorithms for generating Venn diagrams also fall within the protection scope of this invention.

[0042] S500: Obtain the area difference between the target area and the current area of ​​each cell in the Venn diagram, and iteratively optimize the position of the vertices and stations of each cell based on the area difference, so that the area of ​​each cell expands or contracts.

[0043] In the Vinno diagram, the area of ​​the cell is known.

[0044] Among them, the target area of ​​a cell is the ideal area of ​​a cell under a specific layout planning or resource allocation scenario. It reflects the share that a cell should occupy in the overall resource allocation, provides a reference standard for cell space planning, and can be used to judge whether the cell resource allocation is reasonable and whether the space utilization is efficient, so as to achieve the optimization of the overall layout.

[0045] In one implementation, the target area satisfies: A target =A unit / D, where A target For the target area of ​​the current cell, A unit The sum of the areas of all units in the current cell's unit group is given by denoted as ...

[0046] In one implementation, D satisfies: D=A 总单元 / A 布局 , where A 总单元 Let A be the total area covered by all cells in the Venn diagram. 布局 This represents the total area used for layout within the entire hardware. A 布局 It is the physical space used to house all the cells.

[0047] In one implementation, D is directly specified by the user.

[0048] It should be noted that other methods for calculating target density also fall within the scope of protection of this invention.

[0049] In a Vinograph, typically three cells share a vertex. However, in certain special cases, multiple adjacent vertices may degenerate into the same point, in which case a vertex may be shared by more than three cells. Additionally, vertices located at the boundaries of a placeable region may be shared by only one or two cells. Let M represent the number of cells sharing the same vertex, where M is greater than or equal to 1. The area differences among the M cells sharing the same vertex may differ, and these differences exert varying pressures on the shared vertex. The pressure on the vertex is balanced by iteratively optimizing the vertex's position to allow the cells to expand or contract.

[0050] In one implementation, S500 further includes iterative optimization of each vertex position of each cell: S510, retrieve the M target cells that share the current vertex.

[0051] S520, obtain the area difference between the target area and the current area of ​​each target cell to obtain the pressure vector of each target cell on the current vertex. In one embodiment, the value of the pressure vector is the area difference.

[0052] S530, add the M pressure vectors of the current vertex to obtain the vertex movement vector of the current vertex, and move the position of the current vertex according to the vertex movement vector.

[0053] It should be noted that the position of each vertex of each cell is optimized through S510-S530 iterations.

[0054] In one implementation, S500 further includes iterative optimization of the site location for each cell: S540: Obtain multiple neighboring cells that share an edge with the current cell.

[0055] S550, obtain the area difference between the target area and the current area of ​​each of the adjacent cells, and obtain the pressure vector of each target cell on the current cell.

[0056] S560, sum all the pressure vectors of the current cell to obtain the station movement vector of the current cell, and move the position of the current cell's station according to the station movement vector.

[0057] It should be noted that iteratively optimizing the positions of vertices and stations through area difference can make resource allocation more even and reasonable, avoiding situations where some cells are too large, resulting in resource waste, while others are too small, leading to resource shortages, thereby improving overall resource utilization. Furthermore, the area difference of cells reflects the gap between wiring resource requirements and current capacity. Iteratively optimizing the positions of vertices and stations through area difference allows cells to expand or contract, reducing the gap between wiring resource requirements and current capacity. This results in more even wiring resources, smoother wiring channels, reduced wiring crossings and overlaps, reduced wiring complexity, reduced signal delay, and improved chip performance.

[0058] S600: When the bus length converges and the cell converges to the target area, the iteration ends and the layout result is obtained; otherwise, the position of the reference node is updated to the geometric center of the current cell, the reference mesh weight is increased, and the process returns to execute S300.

[0059] In each iteration, the weights of the reference mesh are incremented by a preset amount. For the cell, the gradient direction points towards the geometric center of the cell. The larger the weights of the reference mesh, the more sensitive the bus length is to the position of the reference node.

[0060] It's important to note that area is not considered during the iterative optimization of the bus length. The goal of this optimization is to minimize the bus length, thus achieving the shortest possible bus length. Based on this minimum bus length optimization, area is further considered. Through cell-level iterative optimization, the cell area is expanded or contracted, and the reference node generates an outward-spreading "pull" in each iteration of bus length and cell size, ensuring a uniform cell density distribution while optimizing the bus length. Specifically, in the first iteration, the initial weight of the reference mesh is 0, and the inseparable unit groups converge towards the center, shortening the bus length and increasing the density at the center. In the second iteration, the weight of the reference mesh increases, and the inseparable unit groups may again converge towards the center, shortening the bus length and again increasing the density at the center. In the i-th iteration, the movement of the inseparable unit groups towards the center is hindered, and iterative optimization forces them to bypass the center and diffuse towards the cell edges, resulting in a more uniform density. When the bus length converges and the cells converge to the target area, the iterative result is a shorter bus length and a uniform cell density distribution.

[0061] In summary, this invention provides a layout method based on a Veno diagram. It shrinks the netlist by using indivisible unit groups from the original netlist as movable nodes, and sets a fixed reference node and configures a reference net for each movable node. By iteratively optimizing the bus length of all nets and generating a Veno diagram based on the optimization results, the positions of the vertices and stations of cells are iteratively optimized to cause cell expansion or contraction. The iteration ends when the bus length converges and the cell converges to the target area, achieving the goal of obtaining a layout result suitable for partitioning under specific constraints. Furthermore, the layout result fully considers the core-grain partitioning constraints: there is no overlap between different indivisible unit groups and the units within a group are not scattered. Through the Veno diagram and cells, the irregular envelope trend formed by all standard units and macrounits within the indivisible unit group under optimized layout is explored and characterized. As the weight of the reference net increases, convergence is ensured. Under the premise that the layout result is used as a reference for core-grain partitioning, modeling by indivisible unit groups significantly reduces the problem size, accelerates the solution speed, and shortens the design cycle.

[0062] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.

[0063] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0064] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0065] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0066] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A layout method based on a Vinio diagram, characterized in that, The method includes the following steps: S100, the indivisible unit groups in the original netlist are used as movable nodes to shrink the netlist, resulting in a new shrunken netlist. S200, set a fixed reference node for each movable node in the new netlist, set a reference net between the movable node and its reference node, and update the new netlist; S300, calculate the gradient of the new netlist with respect to the bus length, and iteratively optimize the position of the movable node; S400, using the position of each of the movable nodes as a station, generate a Venn diagram; S500, obtain the area difference between the target area and the current area of ​​each cell in the Venn diagram, and iteratively optimize the position of the vertices and stations of each cell based on the area difference, so that the area of ​​each cell expands or contracts. S600: When the bus length converges and the cell converges to the target area, the iteration ends and the layout result is obtained; otherwise, the position of the reference node is updated to the geometric center of the current cell, the reference mesh weight is increased, and the process returns to execute S300.

2. The method according to claim 1, characterized in that, The S500 also includes iterative optimization for each vertex position of each cell: S510, Get M target cells that share the current vertex, where M is greater than or equal to 1; S520, obtain the area difference between the target area and the current area of ​​each target cell, and obtain the pressure vector of each target cell on the current vertex; S530, add the M pressure vectors of the current vertex to obtain the vertex movement vector of the current vertex, and move the position of the current vertex according to the vertex movement vector.

3. The method according to claim 1, characterized in that, The S500 also includes iterative optimization of the site location for each cell: S540: Obtain multiple neighboring cells that share an edge with the current cell; S550, obtain the area difference between the target area and the current area of ​​each of the adjacent cells, and obtain the pressure vector of each target cell on the current cell; S560, sum all the pressure vectors of the current cell to obtain the station movement vector of the current cell, and move the position of the current cell's station according to the station movement vector.

4. The method according to claim 1, characterized in that, The target area satisfies: A target =A unit / D, where A target For the target area of ​​the current cell, A unit The sum of the areas of all units in the current cell's unit group is given by denoted as ...

5. The method according to claim 4, characterized in that, D satisfies: D=A 总单元 / A 布局 , where A 总单元 Let A be the total area covered by all cells in the Venn diagram. 布局 This represents the total area used for layout within the entire hardware.

6. The method according to claim 1, characterized in that, In S300, the gradient of the bus length is the weighted sum of the gradients of all wires.

7. The method according to claim 6, characterized in that, The initial weight of the reference net is 0.

8. The method according to claim 6, characterized in that, The weights of the nets between the movable nodes are determined based on the number of original nets they contain before shrinking.

9. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 9.

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