An efficient deployment method and device for artificial neural networks for neuromorphic chips

Abstract

This invention discloses an efficient deployment method and apparatus for artificial neural networks on neuromorphic chips, including pulsed transmission between layers of the quantized artificial neural network, sparse encoding of the pulses, and compatibility design based on the storage function of the neuromorphic chip. Typically, networks running on neuromorphic chips are spiking neural networks. This method is a novel approach: by pulsed activation values ​​of the quantized artificial neural network, the transformed network can perform high-precision, low-latency inference. This method proposes a neuronal behavior equivalent to quantized inference of artificial neural networks and successfully deploys the network on a neuromorphic chip, combining the discreteness of quantized networks with the event-driven characteristics of neuromorphic chips. Furthermore, limited by the precision of different hardware, this invention proposes a method for scaling intermediate computation results to avoid overflow risks.

Description

Technical Field

[0001] This invention belongs to the field of neuromorphic computing technology, specifically relating to an efficient deployment method and apparatus for artificial neural networks for neuromorphic chips. Background Technology

[0002] Spiking neural networks, as a third-generation neural network, represent one of the directions of artificial intelligence development. They are neural networks composed of spike neurons that transmit information through discrete spikes (composed of 0s and 1s). Furthermore, compared to artificial neural networks that heavily rely on matrix multiplication, spiking neural networks abandon multiplication and use only accumulation operations, thus possessing the potential to achieve ultra-low-power inference.

[0003] The goal of neuromorphic engineering is to build computational hardware that simulates biological signal processing. These hardware architectures utilize asynchronous, event-driven communication between neurons and fine-grained parallelism with local memory, enabling energy-efficient implementation of spiking neural network-based algorithms. With the emergence of new neuromorphic hardware such as TrueNorth, Loihi, and Darwin, spiking neural networks combined with neuromorphic engineering hold promise for overcoming the bottlenecks of von Neumann architectures, enabling brain-like computing with lower power consumption.

[0004] Deploying spiking neural networks (SNNs) on neuromorphic chips, combined with the event-driven nature of these chips, can effectively achieve low-power inference for SNNs. However, current SNN construction algorithms and hardware designs do not coordinate well. Some of the latest SNN construction algorithms (mainly divided into direct training and artificial neural network conversion into SNNs) do not consider the hardware limitations of actual deployment. Therefore, SNNs currently deployed on hardware are only tested on simple tasks. This method aims to quickly deploy pre-trained and quantized artificial neural networks onto neuromorphic chips while maintaining high precision and low latency, and then combine this with the in-memory computing and event-driven computing paradigm of neuromorphic chips to achieve low-power intelligent applications.

[0005] Hardware constraints can hinder inference in quantized artificial neural networks, and there is a risk of overflow when the intermediate results of weight sums are not precise enough. In addition, in quantized artificial neural networks, weights, inputs, outputs, and biases all have corresponding quantization coefficients. In traditional quantized inference, the quantization coefficient of the bias term is determined by the first three, and the quantized bias term needs to occupy more bit width (for example, if the input, output, and weights are all quantized to 8 bits, then the bias term needs to be represented by 32 bits). However, most neuromorphic chips (such as Loihi, TrueNorth, and Darwin) do not support 32-bit precision in order to pursue extremely low power consumption. Therefore, under limited precision (such as 16 bits or 8 bits), the hardware may not be able to represent the distribution range of the bias term. Summary of the Invention

[0006] In view of the above, the purpose of this invention is to provide an efficient deployment method and apparatus for artificial neural networks on neuromorphic chips, which solves the problem of poor performance of spiking neural networks on neuromorphic chips in the prior art.

[0007] To achieve the above-mentioned objectives, the embodiments provide an efficient deployment method for artificial neural networks on neuromorphic chips, comprising the following steps:

[0008] The trained artificial neural network is uniformly quantized, and bias calibration is performed based on the quantization parameters determined according to the bias term range to obtain the quantized network.

[0009] The cumulative-spiking neuron model replaces the weights and the process of calculating the output activation value in the quantization network. In the accumulation stage, the weights and the corresponding multiply-accumulate operations in the quantization network are decomposed into the accumulation of membrane potentials in multiple time steps. In the pulse generation stage, the output activation value is decomposed into the quantization bit range of the activation value output by introducing scaling factors and mapping it to the activation value output through linear transformation. The activation value is sparsely encoded and a pulse sequence is generated.

[0010] A pipeline acceleration mechanism is introduced to enable neurons in different layers to process data in parallel during the replacement process, thereby reducing the average inference time per sample to the number of time steps corresponding to the quantization bit width.

[0011] Based on the two-layer synaptic connection structure obtained by convolution or fully connected in the cumulative-spiking neuron model, each layer of the model corresponds to a group of cores of the neuromorphic chip. The synaptic connections of the cores are configured and the cumulative-spiking neuron model and pipeline acceleration mechanism are written using the instructions of the neuromorphic chip, so as to realize the deployment of artificial neural networks on the neuromorphic chip.

[0012] Preferably, uniform quantization is performed on the trained artificial neural network, including:

[0013] The weights, biases, inputs, and outputs of each layer of the floating-point artificial neural network are linearly transformed to the range of INT type using their respective quantization parameters, and then completely converted to INT type by rounding to achieve uniform quantization.

[0014] Preferably, bias calibration is performed based on quantization parameters determined according to the bias term range, including:

[0015] During uniform quantization, the range of the bias term is recorded. When the quantized bias term can be represented with hardware-acceptable precision, the standard bias term quantization parameters are used. When the precision supported by the hardware cannot represent the range of the quantized bias term in the standard quantization algorithm, the bias term quantization parameters are adjusted, that is, the output quantization parameters are used as the bias term quantization parameters. At this time, the quantized bias term and the quantized output have the same precision, reducing the hardware implementation complexity.

[0016] Preferably, the cumulative-spiking neuron model divides the neuron's working time window into a working time period of cumulative membrane potential of length K, referred to as the accumulation phase, and a working time period of firing pulses, referred to as the pulse generation phase. Each forward propagation of the model consumes 1 time step.

[0017] The accumulation phase decomposes the weights and corresponding multiply-add operations in the quantization network into multi-time-step membrane potential accumulation, including: mapping the multiply-add operations in the artificial neural network to a series of addition operations, that is, taking out the corresponding bit in the pulse sequence of the output of the previous layer at each time step, and if it is 1, accumulating the corresponding synaptic weight to the corresponding neuron. After accumulating the membrane potential through multiple time steps, a weight sum similar to that of an artificial neural network is obtained.

[0018] The output activation value is decomposed into a pulse generation stage by introducing a scaling factor and mapping the activation value range through a linear transformation. The activation value is sparsely encoded and a pulse sequence is generated. This includes: the neuron scales the membrane potential twice based on the scaling factor, performs a linear transformation on the scaled membrane potential to map the range of the membrane potential to the quantization bit range of the activation value output of the artificial neural network, and then sparsely encodes the binary corresponding to the activation value as the output pulse sequence. At each time step, the pulse at the corresponding sequence position is sent to the next layer.

[0019] Preferably, the scaling factor is calculated based on the maximum value of the sum of weights recorded during the network uniform quantization process and the integer precision range supported by the hardware;

[0020] The neuron performs a second scaling of the membrane potential based on a scaling factor, including: first scaling the intermediate quantization result corresponding to the membrane potential during the quantization inference process using the scaling factor, and then scaling the scaled intermediate result a second time using the same scaling factor. This mapping ensures compatibility with the storage and computational precision of the neuromorphic chip.

[0021] Preferably, sparse encoding of the activation values ​​includes:

[0022] For the binary representation of the activation value, rounding the low-order bits reduces the number of pulse transmissions between layers and the number of synaptic operations on the neuromorphic chip. Different numbers of bits are rounded in different layers, and sparsity can be adjusted in combination with the network topology to achieve sparse coding.

[0023] Preferably, the pipeline acceleration mechanism includes:

[0024] Since the membrane potential accumulation and pulse firing processes are separated in the cumulative-spiking neuron model, a certain inference delay is introduced in each layer. For each data point, the pulse reception / firing of each neuron in each layer requires K time steps. Pulse reception and firing are processed in parallel for two sets of data in each layer. While the current layer fires a pulse, the receiving part of the next layer's neuron is responsible for receiving the pulse emitted by the current layer, so that different layers can process data in parallel, reducing the average inference time per sample to K time steps, where K time steps are the time steps corresponding to the quantization bit width.

[0025] To achieve the above-mentioned objectives, embodiments of the present invention also provide an efficient deployment device for artificial neural networks on neuromorphic chips, comprising:

[0026] The quantization module is used to uniformly quantize the trained artificial neural network and perform bias calibration based on the quantization parameters determined according to the bias term range to obtain the quantized network.

[0027] The mapping module is used to replace the weights and calculation of the output activation value in the quantization network with the cumulative-spiking neuron model. In the accumulation stage, the weights and calculation of the corresponding multiply-accumulate operations in the quantization network are decomposed into the accumulation of membrane potentials in multiple time steps. In the pulse generation stage, the output activation value is decomposed into the quantization bit range of the activation value output by introducing scaling factors and mapping it to the activation value output through linear transformation. The activation value is sparsely encoded and a pulse sequence is generated.

[0028] The pipeline control module is used to introduce a pipeline acceleration mechanism, enabling neurons in different layers to process data in parallel during the replacement process, reducing the average inference time per sample to the number of time steps corresponding to the quantization bit width.

[0029] The deployment module is used to obtain a two-layer synaptic connection structure based on the convolution or fully connected layers in the cumulative-spiking neuron model. Each layer of the model corresponds to a group of cores of the neuromorphic chip. The module configures the synaptic connections of the cores and writes the cumulative-spiking neuron model and pipeline acceleration mechanism using the instructions of the neuromorphic chip, thereby enabling the deployment of artificial neural networks on the neuromorphic chip.

[0030] Compared with the prior art, the beneficial effects of the present invention include at least the following:

[0031] This invention combines the discreteness of information after quantization in artificial neural networks with the event-driven nature of neuromorphic chips to achieve ultra-low power intelligent application inference. Specifically, it proposes an accumulative-spiking neuron model, which pulses the activation values ​​of the quantized artificial neural network to enable high-precision, low-latency inference. It also proposes a quadratic scaling method to scale intermediate results to avoid overflow risk; a bias calibration method to calibrate the bias so that the quantized bias term can be represented with the same precision as the output; and a pipeline acceleration mechanism to shorten inference time. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart of an efficient deployment method for artificial neural networks for neuromorphic chips provided in the embodiment;

[0034] Figure 2 This is the construction process of the pulse-driven artificial neural network provided in the embodiment;

[0035] Figure 3 This is a schematic diagram of the cumulative-spiking neuron model provided in the embodiment;

[0036] Figure 4 This is a schematic diagram of pipelined accelerated inference provided in the embodiment;

[0037] Figure 5 This is the intelligent application process based on neuromorphic chips provided in the embodiment;

[0038] Figure 6 This is a schematic diagram of the structure of an efficient deployment device for artificial neural networks for neuromorphic chips provided in the embodiment. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the scope of protection of this invention.

[0040] The inventive concept of this invention is to solve the problem of poor performance of spiking neural networks on neuromorphic chips in the prior art. The embodiments of this invention provide a solution for rapidly deploying artificial neural networks on neuromorphic chips.

[0041] The cumulative-spiking neuron model proposed in this invention divides the neuron's working time window into two working time periods of length K: an accumulation of membrane potential and a firing pulse. Each forward propagation of the model consumes one time step. During the accumulation period, each time step neuron adds the received pulses to the membrane potential. During the firing pulse period, the neuron performs a linear transformation on the membrane potential, mapping the range of the membrane potential to the range of the quantized activation value output of the artificial neural network, and uses the corresponding binary code as the output pulse sequence. Each time step sends a pulse at the corresponding sequence position to the next layer. This neuron model supports fixed-point environments to ensure successful deployment on neuromorphic chips.

[0042] The proposed secondary scaling method includes: during the quantization of the artificial neural network, calculating a scaling factor by statistically analyzing the maximum value of the synaptic current (the neuron's output is passed to the next layer as synaptic current through weighted synapses) and the maximum value of an INT type (e.g., INT16) integer at a certain precision. During subsequent quantization inference in the artificial neural network, each synaptic current calculation is first performed using this scaling factor to ensure that the intermediate result does not exceed the maximum value represented by the hardware precision, thus preventing severe precision loss due to overflow. After calculation, the intermediate result (typically INT16) is scaled a second time to map the result to the range that can be represented by the quantization bits of the activation value.

[0043] The bias calibration method proposed in this invention includes: when it is detected that the precision supported by the hardware cannot represent the range of the bias term in the quantization algorithm in a pure vertex environment, the output quantization parameter is used as the quantization parameter of the bias term, so that the quantized bias term can be represented with the same precision as the output.

[0044] The pipeline acceleration mechanism proposed in this invention includes the following: Since the accumulation and firing processes of the proposed accumulation-spiking neuron model are separated during inference, each layer introduces a certain inference delay. This invention introduces a pipeline acceleration mechanism that allows different layers to process data in parallel, reducing the average inference time per sample to K (quantization bit width) time steps.

[0045] Based on the above, the present invention provides an efficient deployment scheme for artificial neural networks on neuromorphic chips, aiming to achieve efficient deployment of quantized artificial neural networks on neuromorphic chips and adapt to the computational characteristics of different neuromorphic hardware. The overall process includes model quantization, binary pulse coding, neuron behavior modeling, pulse sparsification, and pipeline acceleration, ultimately forming a pulse-driven artificial neural network that can run directly on neuromorphic chips. This scheme is the first to run a large-scale network (containing 5.76 megapixels) on a neuromorphic chip for a complex visual task and achieve similar results to artificial neural networks.

[0046] Figure 1As shown, the efficient deployment method for artificial neural networks for neuromorphic chips provided by this embodiment of the invention includes the following steps:

[0047] S1, uniformly quantize the trained artificial neural network, and simultaneously perform bias calibration based on the quantization parameters determined according to the bias term range to obtain the quantized network.

[0048] For a trained artificial neural network, we first apply a uniform quantization method to quantize its weights and activations, specifically, such as... Figure 2 As shown, the weights, biases, inputs, and outputs of each layer of a floating-point artificial neural network are linearly transformed to the range of INT type using their respective quantization parameters. This is then completely converted to INT type through rounding, achieving uniform quantization and resulting in a quantized neural network, or simply a quantized network. During quantization, the maximum value of the sum of quantized weights and the range of the bias term for each layer are recorded. The maximum value of the sum of quantized weights is used to calculate the scaling factor, and the range of the bias term is used to calculate the quantization parameters used for bias calibration.

[0049] When the quantized bias term can be represented with hardware-acceptable precision, the standard quantization parameters for the bias term are used, specifically calculated based on the quantization parameters of the weights, inputs, and outputs. When the hardware-supported precision cannot represent the range of the bias term quantized by the standard quantization algorithm, the quantization parameters of the bias term are adjusted, using the output quantization parameters as the bias term's quantization parameters. In this case, the quantized bias term and the quantized output have the same precision. This bias calibration adjusts the bias precision to meet hardware requirements, reducing hardware implementation complexity. The quantization process yields an integer-based artificial neural network.

[0050] S2 replaces the weights and the process of calculating the output activation value in the quantization network with a cumulative-spiking neuron model.

[0051] After S1, the binary representation of the activation values ​​is used as a pulse sequence, and then the cumulative-spiking neuron model is used to simulate the quantization inference process of the artificial neural network. For example... Figure 3 As shown, the cumulative-spiking neuron model is mainly divided into a cumulative phase and a spiking phase. These two phases work in coordination through time steps, using spiking sequences to simulate the transmission of quantized activation values.

[0052] During the accumulation phase, neurons receive pulse sequences (phase-encoded) from neurons in the previous layer and gradually accumulate these inputs to the membrane potential. The accumulation phase decomposes the multiply-add operations corresponding to the weights in the quantized network into multi-time-step membrane potential accumulation. Specifically, it maps the multiply-add operations in the artificial neural network to a series of addition operations. At each time step, a corresponding bit is extracted from the pulse sequence of the previous layer's output; if it is 1, the corresponding synaptic weight is added to the corresponding neuron. After accumulating the membrane potential through multiple time steps, a weight sum similar to that in an artificial neural network is obtained.

[0053] After the accumulation phase, the membrane potential value is scaled and its binary code is emitted as a pulse sequence. In the pulse generation phase, the output activation value is decomposed into a value with a scaling factor and mapped to the quantization bit range of the activation value output through a linear transformation. Specifically, each neuron scales the membrane potential a second time based on the scaling factor, then performs a linear transformation on the scaled membrane potential to map its range to the quantization bit range of the artificial neural network's activation value output. The binary code corresponding to the activation value is then sparsely encoded as the output pulse sequence. At each time step, a pulse at the corresponding sequence position is sent to the next layer.

[0054] The scaling factor is calculated based on the maximum value of the weight sum recorded during the network's uniform quantization process and the integer precision range supported by the hardware. A set of scaling factors is calculated based on the maximum value of the weight sum so that the maximum value of the intermediate result can be mapped to a hardware-acceptable precision. The secondary scaling process based on the calculated scaling factors is as follows: the intermediate quantization result corresponding to the membrane potential during the quantization inference process is scaled for the first time using the scaling factor, and the scaled intermediate result is then scaled for the second time using the same scaling factor. This mapping ensures compatibility with the storage and computational precision of the neuromorphic chip.

[0055] For the binary representation of the activation value, rounding the lower bits reduces the number of pulse transmissions between layers and the number of synaptic operations on the neuromorphic chip. Specifically, it reduces the number of 1s in the lower bits of the binary code of the activation value, thereby reducing the number of pulse transmissions between layers and the number of synaptic operations on the neuromorphic chip. Different numbers of bits are rounded in different layers, and sparsity can be adjusted in combination with the network topology to achieve sparse coding. This can reduce the number of synaptic operations between layers, thereby achieving a balance between accuracy and energy consumption, forming a pulse-driven neural network.

[0056] S3 introduces a pipeline acceleration mechanism, enabling neurons in different layers to process data in parallel during the replacement process, reducing the average inference time per sample to the number of time steps corresponding to the quantization bit width.

[0057] Specifically, such as Figure 4As shown, for each data set, the pulse reception / emission of each layer of neurons requires K time steps. Within each layer, pulse reception and emission are processed in parallel for two sets of data. While the current layer is firing a pulse, the receiving part of the next layer's neurons is responsible for receiving the pulse emitted by the current layer. This allows different layers to process data in parallel, reducing the average inference time per sample to K time steps, where K time steps are the time steps corresponding to the quantization bit width. Thus, using the pipeline mechanism proposed in this invention to process multiple data sets, each layer of neurons can process different data sets simultaneously without interference.

[0058] S4 enables the mapping and deployment of the cumulative-spiking neuron model to a neuromorphic chip.

[0059] In this embodiment, after constructing the cumulative-spiking neuron model, a two-layer synaptic connection structure is obtained based on the convolution or fully connected layers in the model. Each layer of the model corresponds to a group of cores on the neuromorphic chip. The synaptic connections of the cores are configured, and the cumulative-spiking neuron model and pipeline acceleration mechanism are written using instructions from the neuromorphic chip, thus enabling the deployment of the artificial neural network on the neuromorphic chip. The subsequent model inference process is as follows: Figure 5 As shown, the data is first processed into pulses and sent to the corresponding nucleus of the neuromorphic chip's input layer for on-chip inference. During inference, each neuron in the core of the neuromorphic chip receives and emits pulses according to the proposed cumulative-spiking neuron model. The pulses are transmitted to the target core neurons through the routing information stored in the axonal and dendritic tables in the nucleus, thus realizing information transmission. Then, the pulses emitted by the corresponding nucleus of the chip's output layer are returned as the result. After decoding, the prediction results for tasks such as classification / regression can be obtained.

[0060] like Figure 6 As shown, the embodiment also provides an efficient deployment device for artificial neural networks for neuromorphic chips, including a quantization module, a mapping module, a pipeline control module, and a deployment module. The quantization module performs uniform quantization on the trained artificial neural network and performs bias calibration based on quantization parameters determined according to the bias term range to obtain a quantized network. The mapping module replaces the weights in the quantized network with a cumulative-spiking neuron model and calculates the output activation value. The pipeline control module introduces a pipeline acceleration mechanism to enable parallel data processing by neurons in different layers during the replacement process, reducing the average inference time per sample to the number of time steps corresponding to the quantization bit width. The deployment module implements the mapping and deployment of the cumulative-spiking neuron model to the neuromorphic chip.

[0061] It should be noted that when the efficient deployment device for artificial neural networks for neuromorphic chips provided in the above embodiments is deployed efficiently, the above functional modules should be used as an example. The above functions can be assigned to different functional modules as needed, that is, the internal structure of the terminal or server can be divided into different functional modules to complete all or part of the functions described above.

[0062] The specific embodiments described above illustrate the technical solution and beneficial effects of the present invention in detail. It should be understood that the above description is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, additions, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for efficiently deploying artificial neural networks for neuromorphic chips, characterized in that, Includes the following steps: The trained artificial neural network is uniformly quantized, and bias calibration is performed based on the quantization parameters determined according to the bias term range to obtain the quantized network. The cumulative-spiking neuron model replaces the weights and the process of calculating the output activation value in the quantization network. In the accumulation stage, the weights and the corresponding multiply-accumulate operations in the quantization network are decomposed into the accumulation of membrane potentials in multiple time steps. In the pulse generation stage, the output activation value is decomposed into the quantization bit range of the activation value output by introducing scaling factors and mapping it to the activation value output through linear transformation. The activation value is sparsely encoded and a pulse sequence is generated. A pipeline acceleration mechanism is introduced to enable neurons in different layers to process data in parallel during the replacement process, thereby reducing the average inference time per sample to the number of time steps corresponding to the quantization bit width. Based on the two-layer synaptic connection structure obtained by convolution or fully connected in the cumulative-spiking neuron model, each layer of the model corresponds to a group of cores of the neuromorphic chip. The synaptic connections of the cores are configured and the cumulative-spiking neuron model and pipeline acceleration mechanism are written using the instructions of the neuromorphic chip, so as to realize the deployment of artificial neural networks on the neuromorphic chip.

2. The efficient deployment method for artificial neural networks for neuromorphic chips according to claim 1, characterized in that, The trained artificial neural network is uniformly quantized, including: The weights, biases, inputs, and outputs of each layer of the floating-point artificial neural network are linearly transformed to the range of INT type using their respective quantization parameters, and then completely converted to INT type by rounding to achieve uniform quantization.

3. The efficient deployment method for artificial neural networks for neuromorphic chips according to claim 1, characterized in that, Bias calibration is performed based on quantization parameters determined according to the bias term range, including: During uniform quantization, the range of the bias term is recorded. When the quantized bias term can be represented with hardware-acceptable precision, the standard bias term quantization parameters are used. When the precision supported by the hardware cannot represent the range of the quantized bias term in the standard quantization algorithm, the bias term quantization parameters are adjusted, that is, the output quantization parameters are used as the bias term quantization parameters. At this time, the quantized bias term and the quantized output have the same precision, reducing the hardware implementation complexity.

4. The efficient deployment method for artificial neural networks for neuromorphic chips according to claim 1, characterized in that, The cumulative-spiking neuron model divides the neuron's working time window into a working time period of cumulative membrane potential of length K, referred to as the accumulation phase, and a working time period of firing pulses, referred to as the pulse generation phase. Each forward propagation of the model consumes 1 time step. The accumulation phase decomposes the weights and corresponding multiply-add operations in the quantization network into multi-time-step membrane potential accumulation, including: mapping the multiply-add operations in the artificial neural network to a series of addition operations, that is, taking out the corresponding bit in the pulse sequence of the output of the previous layer at each time step, and if it is 1, accumulating the corresponding synaptic weight to the corresponding neuron. After accumulating the membrane potential through multiple time steps, a weight sum similar to that of an artificial neural network is obtained. The output activation value is decomposed into a pulse generation stage by introducing a scaling factor and mapping the activation value range through a linear transformation. The activation value is sparsely encoded and a pulse sequence is generated. This includes: the neuron scales the membrane potential twice based on the scaling factor, performs a linear transformation on the scaled membrane potential to map the range of the membrane potential to the quantization bit range of the activation value output of the artificial neural network, and then sparsely encodes the binary corresponding to the activation value as the output pulse sequence. At each time step, the pulse at the corresponding sequence position is sent to the next layer.

5. The efficient deployment method for artificial neural networks for neuromorphic chips according to claim 1 or 4, characterized in that, The scaling factor is calculated based on the maximum value of the sum of weights recorded during the network uniform quantization process and the integer precision range supported by the hardware. The neuron performs a second scaling of the membrane potential based on a scaling factor, including: first scaling the intermediate quantization result corresponding to the membrane potential during the quantization inference process using the scaling factor, and then scaling the scaled intermediate result a second time using the same scaling factor. This mapping ensures compatibility with the storage and computational precision of the neuromorphic chip.

6. The efficient deployment method for artificial neural networks for neuromorphic chips according to claim 1 or 4, characterized in that, Sparse encoding of activation values ​​includes: For the binary representation of the activation value, rounding the low-order bits reduces the number of pulse transmissions between layers and the number of synaptic operations on the neuromorphic chip. Different numbers of bits are rounded in different layers, and sparsity can be adjusted in combination with the network topology to achieve sparse coding.

7. The efficient deployment method for artificial neural networks for neuromorphic chips according to claim 1, characterized in that, The pipeline acceleration mechanism includes: Since the membrane potential accumulation and pulse firing processes are separated in the cumulative-spiking neuron model, a certain inference delay is introduced in each layer. For each data point, the pulse reception / firing of each neuron in each layer requires K time steps. Pulse reception and firing are processed in parallel for two sets of data in each layer. While the current layer fires a pulse, the receiving part of the next layer's neuron is responsible for receiving the pulse emitted by the current layer, so that different layers can process data in parallel, reducing the average inference time per sample to K time steps, where K time steps are the time steps corresponding to the quantization bit width.

8. A highly efficient deployment device for artificial neural networks for neuromorphic chips, characterized in that, include: The quantization module is used to uniformly quantize the trained artificial neural network and perform bias calibration based on the quantization parameters determined according to the bias term range to obtain the quantized network. The mapping module is used to replace the weights and calculation of the output activation value in the quantization network with the cumulative-spiking neuron model. In the accumulation stage, the weights and calculation of the corresponding multiply-accumulate operations in the quantization network are decomposed into the accumulation of membrane potentials in multiple time steps. In the pulse generation stage, the output activation value is decomposed into the quantization bit range of the activation value output by introducing scaling factors and mapping it to the activation value output through linear transformation. The activation value is sparsely encoded and a pulse sequence is generated. The pipeline control module is used to introduce a pipeline acceleration mechanism, enabling neurons in different layers to process data in parallel during the replacement process, reducing the average inference time per sample to the number of time steps corresponding to the quantization bit width. The deployment module is used to obtain a two-layer synaptic connection structure based on the convolution or fully connected layers in the cumulative-spiking neuron model. Each layer of the model corresponds to a group of cores of the neuromorphic chip. The module configures the synaptic connections of the cores and writes the cumulative-spiking neuron model and pipeline acceleration mechanism using the instructions of the neuromorphic chip, thereby enabling the deployment of artificial neural networks on the neuromorphic chip.

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