A board-level fan-out packaging structure and its manufacturing method

Abstract

This invention provides a board-level fan-out package structure and its manufacturing method, comprising: a protective structure, wherein a chip and a first insulating passivation layer on the chip wafer segment are packaged within the protective structure, and a through-hole is provided in the protective structure. Layers are added to the front and back sides of the protective structure and the through-hole is filled to form a double-sided interconnected redistribution layer. The double-sided interconnection of the redistribution layer achieves the interconnection of the front and back sides of the chip. Direct interconnection of the double-sided redistribution layers through the through-hole in the protective structure avoids the aspect ratio limitations of traditional blind via plating. The symmetrical distribution of the double-sided redistribution layers balances thermal stress and reduces warpage, thereby improving structural stability and reducing production costs.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, specifically to a board-level fan-out packaging structure and its manufacturing method. Background Technology

[0002] Board-level fan-out packaging, as a derivative and iteration of wafer-level fan-out packaging, has largely solved the problem of its persistently high cost. Wafer-level fan-out packaging primarily uses semiconductor-grade packaging materials, equipment, and corresponding design rules, resulting in high packaging costs, thus limiting its application to high-end integrated circuits such as CPUs, GPUs, and APEs. Due to cost constraints, mid-to-low-end integrated circuits have continued to use traditional Wire Bond and QFN packaging methods, making further performance improvements difficult. The emergence of board-level fan-out packaging technology perfectly balances cost and performance for mid-to-low-end integrated circuits: improving product performance while further reducing costs. Currently, board-level fan-out packaging technology faces challenges such as chip warpage and long die bonding times, and cannot achieve double-sided interconnect processes. In particular, the industry has yet to find effective solutions to chip warpage and double-sided interconnect issues, and there are relatively few practically implemented large-scale solutions.

[0003] Currently, the following methods are used to achieve double-sided interconnection:

[0004] 1. Laser drilling of blind holes followed by electroplating for metallization is a method that cannot achieve high aspect ratio structures due to the use of blind holes. This is because the smaller and deeper the blind holes, the more difficult it is to drill. In addition, the electroplating solution is difficult to circulate fully within high aspect ratio blind holes, making effective filling impossible. The limited fluidity of the electroplating solution within high aspect ratio blind holes leads to abnormal additive concentration gradient distribution, disrupting the super-equiangular filling mode and causing incomplete filling or even voids at the bottom of the hole. The uneven electric field distribution at the bottom of the blind hole results in asynchronous copper deposition rates, and insufficient current density at the bottom of deep holes exacerbates the risk of incomplete filling. High aspect ratio blind holes require strict control of laser energy; insufficient energy leads to resin residue at the bottom of the hole, while excessive energy causes substrate carbonization, affecting the reliability of subsequent metallization.

[0005] 2. The copper pillars for interconnection are first made by photolithography and electroplating, and then plastic encapsulation and grinding are used to expose the copper pillars. This method introduces photoresist of customized thickness and grinding process, which leads to a significant increase in production cost.

[0006] The above background information is provided only to assist in understanding the inventive concept and technical solution of this invention. It does not necessarily belong to the prior art of this patent application, nor does it necessarily provide technical teaching. In the absence of clear evidence that the above information was disclosed before the filing date of this patent application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0007] To address the technical problems of high aspect ratio blind via interconnect defects, high cost of double-sided interconnect processes, and insufficient structural stability in existing technologies, this invention proposes a board-level fan-out packaging structure and its manufacturing method. By using through-holes that penetrate the protective structure, direct interconnection of the redistribution layers on both sides is achieved, avoiding the limitation of aspect ratio interconnect defects in traditional blind via electroplating. The symmetrical distribution of the double-sided redistribution layers balances thermal stress and reduces warpage, thereby improving structural stability and reducing production costs.

[0008] To achieve the above objectives, the technical solution of the present invention is as follows:

[0009] On one hand, the present invention provides a board-level fan-out package structure, including: a protective structure, wherein a chip and a first insulating passivation layer on the wafer segment of the chip are packaged in the protective structure, the protective structure is provided with a through hole penetrating the protective structure, and the protective structure is layered on both sides and filled with the through hole to form a redistribution layer with double-sided interconnection, the double-sided interconnection of the redistribution layer to realize the double-sided interconnection of the chip.

[0010] This invention proposes a board-level fan-out packaging structure and its manufacturing method. The direct interconnection of the redistribution layers on both sides is achieved through through-holes that penetrate the protective structure, avoiding the limitation of aspect ratio interconnection defects in traditional blind hole electroplating. The symmetrical distribution of the redistribution layers on both sides balances thermal stress and reduces warpage, which not only improves the stability of the structure but also reduces production costs.

[0011] As a preferred technical solution, the protective structure also encapsulates passive devices.

[0012] As a preferred technical solution, the first insulating passivation layer is provided with a plurality of windows, the positions of which correspond to the positions of the pads on the chip to realize the connection between the pads on the chip and the redistribution layer on the reverse side.

[0013] As a preferred technical solution, a second insulating passivation layer is provided on both the front and back redistribution layers, and the second insulating passivation layer has an external connection window.

[0014] As a preferred technical solution, a first external interconnect metal layer is provided on the second insulating passivation layer on both sides, and a second external interconnect metal layer is provided on the first external interconnect metal layer. The first external interconnect metal layer is connected to the rewiring layer through an external connection window.

[0015] On the other hand, the present invention provides a method for manufacturing a board-level fan-out package structure, which manufactures the board-level fan-out package structure as described in any of the preceding claims, comprising the following manufacturing steps:

[0016] S1 forms a first insulating passivation layer on the active surface of the chip wafer segment and opens a window corresponding to the chip pad, and then thins and cuts it to form a single chip.

[0017] S2 sets a temporary bonding layer on the carrier board and attaches the first insulating passivation layer on the chip to the temporary bonding layer;

[0018] S4 encapsulates the composite structure to form a protective structure before removing the temporary bonding layer and carrier plate;

[0019] S5 forms a through-hole in the protective structure, and interconnects the front and back redistribution layers simultaneously through double-sided electroplating to achieve front and back interconnection of the chip.

[0020] As a preferred technical solution, step S5 involves simultaneously forming interconnected redistribution layers on both sides of the chip via double-sided electroplating to achieve interconnection between the front and back sides. This specifically includes the following steps:

[0021] A seed layer is formed on the upper surface of the protective structure with through holes;

[0022] A photoresist layer is formed on the seed layer, and the photoresist layer has a photoresist layer window;

[0023] A redistribution layer is formed by simultaneously filling the photoresist layer with windows and vias using a double-sided electroplating process, creating interconnects on both sides.

[0024] As a preferred technical solution, the double-sided electroplating process utilizes through holes to achieve double-sided flow and exchange of electroplating solution, simultaneously forming a redistribution layer that interconnects the front and back sides.

[0025] As a preferred technical solution, the following steps are also included:

[0026] S6 forms a second insulating passivation layer on both sides of the redistribution layer surface and opens an external connection window;

[0027] S7 repeatedly constructs a multi-layer metal interconnect structure on the second insulating passivation layer and connects to the redistribution layer through an external connection window to achieve double-sided signal output.

[0028] As a preferred technical solution, step S2 also includes the following steps: synchronously mounting passive devices and chips onto a temporary bonding layer.

[0029] The present invention provides a board-level fan-out packaging structure and its manufacturing method, which have the following beneficial effects:

[0030] 1) The present invention provides a board-level fan-out packaging structure and its manufacturing method, which realizes direct interconnection of the front and back double-sided redistribution layers through through holes in the protective structure, avoiding the limitation of the aspect ratio of traditional blind hole electroplating. The symmetrical distribution of the double-sided redistribution layers makes the thermal stress balanced and reduces the warpage, which not only improves the stability of the structure, but also reduces the production cost.

[0031] 2) The present invention provides a board-level fan-out packaging structure and its manufacturing method, which realizes direct interconnection of the front and back double-sided redistribution layers (RDL) through through-holes in the protective structure, avoiding the aspect ratio limitation problem of traditional blind hole plating. The through-hole structure allows bidirectional flow of plating solution, ensuring complete metal filling in the hole (void rate <0.1%); forming a front and back double-sided redistribution layer, reducing the interconnection resistance by more than 40%, and achieving high-reliability double-sided interconnection;

[0032] Compared to wafer-level fan-out packaging, board-level molding materials and electroplating processes are used, eliminating the need to first create the interconnect copper pillars through photolithography and electroplating, and then mold and grind to expose the copper pillars. The introduction of customized thickness photoresist and grinding processes reduces production costs.

[0033] The symmetrical distribution of double-sided redistribution layers ensures balanced thermal stress, reduces warpage to <50μm / m, and improves structural stability.

[0034] 2) The present invention provides a board-level fan-out package structure and its manufacturing method, which introduces a through-hole structure into the board-level fan-out package, and adds layers on both sides of the protective structure to form a redistribution layer for front and back double-sided interconnection, thus balancing the warpage problem caused by traditional single-sided packaging; adding layers on both sides of the protective structure to form a redistribution layer for front and back double-sided interconnection significantly reduces the chip's packaging cycle time (CT), and also realizes the function of front and back interconnection of the chip;

[0035] The pre-passivation treatment on the chip wafer segment to form a first insulating passivation layer solves the accuracy problem of interconnect openings in the subsequent redistribution layer (RDL) layer addition stage caused by the drift problem of embedded chips after plastic encapsulation. Attached Figure Description

[0036] Figure 1 A schematic diagram of a board-level fan-out packaging structure provided by the present invention;

[0037] Figure 2This is a schematic diagram of step S1 of a method for manufacturing a board-level fan-out package structure provided in Example 1;

[0038] Figure 3 This is a schematic diagram of step S2 of a method for manufacturing a board-level fan-out package structure provided in Example 1;

[0039] Figure 4 This is a schematic diagram of step S3 in the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0040] Figure 5 This is a schematic diagram of step S4 in the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0041] Figure 6 This is a schematic diagram of step S5 in the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0042] Figure 7 This is a schematic diagram of step S6 in the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0043] Figure 8 This is a schematic diagram of step S7 of the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0044] Figure 9 This is a schematic diagram of step S8 in the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0045] Figure 10 This is a schematic diagram of step S9 in the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0046] Figure 11 This is a schematic diagram of step S10 of the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0047] Figure 12 This is a schematic diagram of step S11 of the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0048] Figure 13 This is a schematic diagram of step S12 of the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0049] Figure 14 This is a schematic diagram of step S13 of the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0050] Figure 15This is a schematic diagram of step S14 of the manufacturing method of a board-level fan-out package structure provided in Example 1;

[0051] Wherein, 100-carrier board; 200-temporary bonding layer; 300-chip; 310-first insulating passivation layer; 320-window; 400-passive device; 500-protective structure; 600-through hole; 700-photoresist layer; 710-photoresist layer window; 800-redistribution layer; 900-second insulating passivation layer; 910-external connection window; 1000-first external interconnect metal layer; 1100-second external interconnect metal layer. Detailed Implementation

[0052] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0053] like Figure 1 As shown, the present invention provides a board-level fan-out package structure, including: a protective structure 500, wherein a chip 300 and a first insulating passivation layer 310 on a wafer segment of the chip 300 are packaged in the protective structure 500, and a through-hole 600 is provided on the protective structure 500. The protective structure 500 is layered on both sides and the through-hole 600 is filled to form a redistribution layer 800 with double-sided interconnection. The double-sided interconnection of the redistribution layer 800 realizes the double-sided interconnection of the chip 300.

[0054] This invention proposes a board-level fan-out packaging structure that achieves direct interconnection of the redistribution layers on both sides through through-holes in the protective structure. This avoids the limitation of aspect ratio interconnection defects in traditional blind hole plating. The symmetrical distribution of the redistribution layers on both sides balances thermal stress and reduces warpage, thereby improving structural stability and reducing production costs.

[0055] Preferably, such as Figure 1 As shown, the protective structure 500 also encapsulates a passive device 400; the passive device 400 is directly embedded inside the protective structure 500, which can eliminate the parasitic effects caused by traditional external discrete components and optimize signal transmission quality; the passive device 400 and the chip 300 are molded together synchronously to avoid the risk of interface delamination caused by traditional soldering processes.

[0056] Preferably, such as Figure 1As shown, the first insulating passivation layer 310 has a plurality of openings 320. The positions of the openings 320 correspond to the positions of the pads on the chip 300 to enable the pads on the chip 300 to connect with the redistribution layer 800 on the reverse side. The positions of the openings 320 are strictly aligned with the pads on the chip 300, so that the pads on the chip 300 form a vertical interconnect path with the reverse redistribution layer 800 (RDL) through the vias 600, extending the I / O contacts of the chip 300 to both sides of the package. Compared with the traditional single-sided solution, the interconnect resistance is significantly reduced. The openings 320 expose the metal layer of the pads, avoiding interference of the passivation insulating material with the transmission of electrical signals.

[0057] Preferably, such as Figure 1 As shown, a second insulating passivation layer 900 is provided on the redistribution layer 800 on both sides. The second insulating passivation layer 900 has an external connection window 910. Through the external connection window 910, the second insulating passivation layer 900 exposes the pad area of ​​the redistribution layer 800 (RDL) to form an interface for connection with external pins, ensuring the reliability of the signal transmission path and reducing contact resistance.

[0058] Preferably, such as Figure 1 As shown, a first external interconnect metal layer 1000 is provided on the second insulating passivation layer 900 on both sides, and a second external interconnect metal layer 1100 is provided on the first external interconnect metal layer 1000. The first external interconnect metal layer 1000 is connected to the rewiring layer 800 through an external connection window 910.

[0059] The first external interconnect metal layer 1000 directly contacts the redistribution layer 800 (RDL) through the external connection window 910, forming a low-impedance interconnect interface (contact resistance ≤0.5mΩ·cm≤), reducing signal transmission loss;

[0060] The second external interconnect metal layer 1100 increases the conductive cross-sectional area (thickness increased to 5-10μm) based on the first external interconnect metal layer 1000, and can carry a larger current density (≥5A / mm≤) to meet the requirements of power devices.

[0061] On the other hand, such as Figure 2-15 As shown, the present invention provides a method for manufacturing a board-level fan-out package structure, which, in order to obtain the board-level fan-out package structure as described in any of the preceding claims, includes the following manufacturing steps:

[0062] S1 forms a first insulating passivation layer 310 on the active surface of the wafer segment of chip 300 and opens a window corresponding to the bonding pad of chip 300, and then thins and cuts to form a single chip 300.

[0063] S2 sets a temporary bonding layer 200 on the carrier board 100 and attaches the first insulating passivation layer 310 on the chip 300 to the temporary bonding layer 200.

[0064] S4 encapsulates the composite structure to form a protective structure, then removes the temporary bonding layer 200 and the carrier plate 100.

[0065] S5 forms a through-hole 600 on the protective structure 500, and simultaneously forms an interconnected front and back redistribution layer 800 by double-sided electroplating to achieve front and back interconnection of the chip 300.

[0066] This invention proposes a method for manufacturing a board-level fan-out package structure. By using through-holes that penetrate the protective structure, the redistribution layers on both sides can be directly interconnected, avoiding the aspect ratio limitation problem of traditional blind hole electroplating. The symmetrical distribution of the redistribution layers on both sides balances thermal stress and reduces warpage, which not only improves the stability of the structure but also reduces production costs.

[0067] Preferably, in step S5, the interconnection of the front and back sides of the chip 300 is achieved by simultaneously forming a redistribution layer 800 through double-sided electroplating to realize the interconnection of the front and back sides, specifically including the following steps:

[0068] A seed layer (not shown) is formed on the upper surface of the protective structure 500 having a through hole 600;

[0069] A photoresist layer 700 is formed on a seed layer (not shown), wherein the photoresist layer has a photoresist layer opening 710;

[0070] A redistribution layer 800 with front and back interconnects is formed by simultaneously filling the photoresist layer with windows 710 and vias 600 using a double-sided electroplating process.

[0071] The double-sided electroplating process ensures the geometric symmetry of the redistribution layer 800 (RDL) on both sides by simultaneously filling the photoresist layer with windows 710 and vias 600, optimizing the consistency of the signal transmission path and reducing losses caused by impedance mismatch. The via electroplating filling of vias 600, combined with window wiring, forms an interconnect structure that supports the direct interconnection of the electrodes on both sides of the chip 300, improving the interconnect density and achieving a high-precision symmetrical interconnect architecture.

[0072] The single-pass double-sided electroplating simultaneously completes the filling of the 600-hole and the surface wiring, which reduces the number of process steps and significantly shortens the manufacturing cycle compared to the traditional single-sided layer-by-layer processing. Through the design of a uniform conductive substrate in the seed layer (not shown), the thickness uniformity of the redistribution layer 800 formed by electroplating is achieved, avoiding the risk of interface delamination caused by step processing, simplifying the process flow and improving efficiency.

[0073] Preferably, the double-sided electroplating process utilizes through-holes 600 to achieve double-sided flow and exchange of the electroplating solution, simultaneously forming a redistribution layer 800 interconnecting the front and back sides. The double-sided flow of the electroplating solution through the through-holes 600 simultaneously fills the through-holes and surface openings, forming a conductive channel penetrating both sides, realizing a three-dimensional interconnect architecture for the chip 300, thus improving interconnect density. The integrally formed redistribution layer 800 (RDL) significantly reduces interface contact resistance and optimizes high-frequency signal transmission performance. The double-sided electroplating solution exchange mechanism eliminates the concentration polarization phenomenon of traditional single-sided electroplating, reducing the thickness non-uniformity (CV value) of the redistribution layer 800 (RDL) and ensuring the conductivity consistency of the circuit. Simultaneous deposition within the through-holes 600 avoids localized bubble residue and reduces the micropore filling defect rate.

[0074] Preferably, the method further includes the following steps:

[0075] S6 forms a second insulating passivation layer 900 on the front and back sides of the redistribution layer 800 and opens an external connection window 910.

[0076] S7 repeatedly constructs a multi-layer metal interconnect structure on the second insulating passivation layer 900 and connects it to the redistribution layer 800 through the external connection window 910 to achieve double-sided signal output; the multi-layer metal interconnect structure is stacked to construct a three-dimensional conductive network, which increases the interconnect density and meets the requirements of 3D stacking packaging; the external connection window 910 is precisely aligned with the redistribution layer 800 to reduce contact resistance and support high current transmission.

[0077] Preferably, step S2 further includes the following steps: synchronously mounting the passive device 400 and the chip 300 onto the temporary bonding layer 200; directly embedding the passive device 400 inside the protective structure 500 can eliminate the parasitic effects caused by traditional external discrete components and optimize signal transmission quality; synchronously molding the passive device 400 and the chip 300 into a plastic package avoids the risk of interface delamination caused by traditional soldering processes.

[0078] Example 1

[0079] This invention provides a method for manufacturing a board-level fan-out package structure, comprising the following steps:

[0080] S1 as Figure 2As shown, the chip is first passivated and insulated. A first insulating passivation layer 310 is formed on the active surface of the chip 300 wafer, and one or more windows 320 are formed on the first insulating passivation layer 310. The three-dimensional position of the window 320 corresponds to the pad position (not shown) on the chip 300. The first insulating passivation layer 310 is formed by methods including but not limited to coating photoresist, spraying photoresist, vacuum lamination, wafer-level molding, etc. The corresponding window formation methods include but not limited to exposure development, laser drilling, etc. After the passivation and insulation and windowing treatments are completed, the chip 300 wafer is thinned and cut to a specified thickness to form a single chip 300. In addition to packaging a single chip 300, this structure can also integrate various passive devices 400.

[0081] S2 as Figure 3 As shown, a carrier plate 100 is prepared, and a temporary bonding layer 200 is formed on the top of the carrier plate 100. The type of carrier plate 100 includes, but is not limited to, stainless steel carrier plate 100, glass carrier plate 100, molding compound carrier plate 100, polymer material carrier plate 100, metal alloy carrier plate 100, ceramic carrier plate 100, and other materials that can be used to provide support. The temporary bonding layer 200 includes, but is not limited to, release film, separable double-sided tape, pyrolytic film, separable temporary bonding adhesive, and other materials.

[0082] S3 as Figure 4 As shown, the single chip 300 and the passive device 400 in step S1 are attached to the temporary bonding layer 200, wherein the active surface (i.e. the windowed surface) of the single chip 300 is in direct contact with the temporary bonding layer 200, and the active surface of the passive device 400 is also in contact with the temporary bonding layer 200.

[0083] S4 Figure 5 As shown, in Figure 4 Based on this, the combined structure is protected by plastic encapsulation to form a protective structure 500. The protective encapsulation method can be plate-level encapsulation, and the encapsulation material used includes, but is not limited to, various powders, liquids and other encapsulation materials. The protective encapsulation method can also be vacuum lamination, and the lamination preferably uses a plastic encapsulation dry film of a specified thickness or resin materials such as PP and BT.

[0084] S5 Figure 6 As shown, the temporary bonding layer 200 is removed, and then the carrier board 100 is removed;

[0085] S6: As Figure 7 As shown, through holes 600 are formed on the protective structure 500 by laser drilling or mechanical drilling. The advantage of through holes 600 over blind holes is that they do not need to stop at the bottom of the hole, which greatly reduces the technical difficulty.

[0086] S7 Figure 8 As shown, in Figure 8Based on the structure, a seed layer (not shown) is first formed. The seed layer is formed by deposition methods such as PVD, CVD, and ALD, or by chemical copper plating. Then, a photoresist layer 700 is coated on the seed layer, and the corresponding photoresist layer opening 710 is opened by exposure and development.

[0087] S8 Figure 9 As shown, 710 is filled with copper by wet electroplating to form a redistribution layer 800 (RDL). Due to the presence of via 600, the electroplating solution can flow and exchange simultaneously on both sides of the board surface through the via 600, so as to achieve double-sided electroplating to form the front and back redistribution layers 800 (RDL) at the same time, and connect the front and back redistribution layers 800 to achieve interconnection between the front and back of the redistribution layer 800.

[0088] S9 Figure 10 As shown, the seed layer of the photoresist 700 and the non-redistribution layer (RDL) region is removed to fully expose the redistribution layer (RDL) 800.

[0089] S10 Figure 11 As shown, a second insulating passivation layer 900 is formed on both sides of the redistribution layer (RDL) 800. The formation method includes: vacuum lamination combined with insulating dry film. The insulating dry film includes, but is not limited to, insulating materials such as ABF (Ajinomoto deposited film), PP (polypropylene), and BT (bismaleimide triazine resin), or coating method combined with liquid insulating photoresist.

[0090] S11 as Figure 12 As shown, a window 910 is formed on one end of the second insulating passivation layer 900. If the second insulating passivation layer 900 is not a photosensitive material, the window 910 is formed by laser drilling, mechanical drilling, or dry etching. If the second insulating passivation layer 900 is a photosensitive material, the corresponding formation method is exposure and development.

[0091] S12 as Figure 13 As shown, in Figure 12Based on the structure, a seed layer (not shown) is first formed. The seed layer is formed by deposition methods including but not limited to PVD, CVD, ALD, etc., or by chemical copper plating. Then, a photoresist layer (not shown) is coated on the seed layer. The corresponding photoresist layer openings (not shown) are opened by exposure and development. The photoresist layer openings (not shown) are filled by wet copper plating to form the first external interconnect metal layer 1000. The photoresist (not shown) and the seed layer (not shown) in the non-first external interconnect metal layer 1000 area are removed to fully expose the first external interconnect metal layer 1000 to form the first external interconnect metal layer 1000 for signal external connection. The above steps are repeated to form the second external interconnect metal layer 1100 for signal external connection. The first external interconnect metal layer 1000 is a copper layer and the second external interconnect metal layer 1100 is a tin layer for board soldering.

[0092] S13 as Figure 14 As shown, repeat steps S11 to S12, except that the passivation opening 910 is on the other end of the second insulating passivation layer 900;

[0093] S14 as Figure 15 As shown, a first external interconnect metal layer 1000 and a second external interconnect metal layer 1100 are formed on both sides of the packaging structure to meet more diverse connection requirements, resulting in a board-level fan-out packaging structure.

[0094] This invention proposes a board-level fan-out packaging structure, which is manufactured according to the board-level fan-out packaging structure manufacturing method described above.

[0095] This invention proposes a board-level fan-out packaging structure and its manufacturing method. The direct interconnection of the redistribution layers on both sides is achieved through through-holes that penetrate the protective structure, avoiding the limitation of aspect ratio interconnection defects in traditional blind hole electroplating. The symmetrical distribution of the redistribution layers on both sides balances thermal stress and reduces warpage, which not only improves the stability of the structure but also reduces production costs.

[0096] It is understood that this invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are protected by this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of this invention.

Claims

1. A method for manufacturing a board-level fan-out package structure, characterized in that, The board-level fan-out package structure includes: a protective structure, in which a chip and a first insulating passivation layer on the chip wafer segment are packaged, and a through-hole is provided on the protective structure. The protective structure is layered on both sides and the through-hole is filled to form a redistribution layer with double-sided interconnection, and the double-sided interconnection of the redistribution layer with both sides realizes the double-sided interconnection of the chip. Manufacturing the aforementioned board-level fan-out package structure includes the following manufacturing steps: S1 forms a first insulating passivation layer on the active surface of the chip wafer segment and opens a window corresponding to the chip pad, and then thins and cuts it to form a single chip. S2 sets a temporary bonding layer on the carrier board and attaches the first insulating passivation layer on the chip to the temporary bonding layer; S4 encapsulates the composite structure to form a protective structure before removing the temporary bonding layer and carrier plate; S5 forms a through-hole in the protective structure, and interconnects the front and back redistribution layers simultaneously through double-sided electroplating to achieve front and back interconnection of the chip.

2. The manufacturing method of the board-level fan-out packaging structure according to claim 1, characterized in that, Step S5 involves simultaneously forming interconnected redistribution layers on both sides of the chip via double-sided electroplating to achieve front-to-back interconnection. This specifically includes the following steps: A seed layer is formed on the upper surface of the protective structure with through holes; A photoresist layer is formed on the seed layer, and a photoresist layer window is formed on the photoresist layer; A redistribution layer is formed by simultaneously filling the photoresist layer with windows and vias using a double-sided electroplating process, creating interconnects on both sides.

3. The manufacturing method of the board-level fan-out packaging structure according to claim 2, characterized in that, The double-sided electroplating process utilizes through holes to allow for double-sided flow and exchange of the electroplating solution, simultaneously forming a redistribution layer that interconnects the front and back sides.

4. The manufacturing method of the board-level fan-out packaging structure according to claim 1, characterized in that, It also includes the following steps: S6 forms second insulating passivation layers on both sides of the redistribution layer surface and opens external connection windows; S7 repeatedly constructs a multi-layer metal interconnect structure on the second insulating passivation layer and connects to the redistribution layer through an external connection window to achieve double-sided signal output.

5. The manufacturing method of the board-level fan-out packaging structure according to claim 1, characterized in that, Step S2 also includes the following steps: synchronously mounting passive devices and chips onto a temporary bonding layer.

6. The manufacturing method of the board-level fan-out packaging structure according to claim 1, characterized in that, The protective structure also encapsulates passive components.

7. The manufacturing method of the board-level fan-out packaging structure according to claim 1, characterized in that, The first insulating passivation layer has a plurality of openings, the positions of which correspond to the positions of the pads on the chip to enable the pads on the chip to be connected to the redistribution layer on the reverse side.

8. The method for manufacturing the board-level fan-out packaging structure according to claim 1, characterized in that, A second insulating passivation layer is provided on both the front and back redistribution layers, and the second insulating passivation layer has an external connection window.

9. The method for manufacturing the board-level fan-out packaging structure according to claim 8, characterized in that, A first external interconnect metal layer is provided on the second insulating passivation layer on both sides. A second external interconnect metal layer is provided on the first external interconnect metal layer. The first external interconnect metal layer is connected to the rewiring layer through an external connection window.

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