A method and device for low-voltage switchgear overload early warning based on current harmonic identification

Abstract

This invention provides a method and device for overload early warning of low-voltage switchgear based on current harmonic identification, relating to the field of power supply technology. The method includes: real-time monitoring of the current on both sides of the low-voltage switchgear to generate an input-side current harmonic feature vector and N output branch current harmonic feature vectors; performing overload cause localization analysis and outputting a real-time overload early warning; if the overload is primarily caused by the input side, quantifying the branch overload contribution and outputting N overload risk weight factors; performing global coordinated load reduction on N output-side devices; if the overload is primarily caused by the output side, analyzing and generating an output-side load reduction strategy based on the harmonic-load coupling disturbance characteristics of the real-time cause branch device after isolation on N-1 output-side devices. This invention solves the technical problem that existing load adjustment methods, which mostly rely on manual judgment, lack dynamic adjustment and optimization of the overall load of the power supply system, leading to unbalanced load adjustment in the overall system.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, specifically to a method and device for low-voltage switchgear overload early warning based on current harmonic identification. Background Technology

[0002] In power supply systems, low-voltage switchgear, as a crucial electrical device, is responsible for distributing power to various branches and equipment. With increasing load, overload becomes a significant factor affecting the stability and safety of low-voltage switchgear and related equipment. Overload not only directly damages equipment but can also trigger cascading failures in the power system. Therefore, overload early warning is a critical link in ensuring the reliable operation of the power system. However, most current overload early warning systems rely on manual judgment and traditional load adjustment methods, lacking dynamic adjustment and optimization of the overall system load. This prevents global load coordination and load reduction, leading not only to the neglect of overload issues in certain equipment but also to unbalanced load regulation across the entire system, ultimately resulting in equipment damage or system instability. Summary of the Invention

[0003] This application provides a low-voltage switchgear overload early warning method and device based on current harmonic identification, which aims to solve the technical problem that most existing load adjustment methods rely on manual judgment and lack dynamic adjustment and optimization of the overall load of the power supply system, resulting in unbalanced load adjustment of the overall system.

[0004] The first aspect disclosed in this application provides an overload early warning method for low-voltage switchgear based on current harmonic identification. The method includes: real-time monitoring of the current on both sides of the low-voltage switchgear to generate an input-side current harmonic feature vector and N output branch current harmonic feature vectors, wherein the N output branch current harmonic feature vectors correspond to N output-side devices; performing overload main cause localization analysis based on the input-side current harmonic feature vectors and the N output branch current harmonic feature vectors, and outputting a real-time overload early warning; if the real-time overload early warning is the input-side overload main cause, then performing branch overload contribution quantification based on the N output branch current harmonic feature vectors, and outputting N overload risk weight factors; performing global coordinated load reduction of the N output-side devices according to the N overload risk weight factors; if the real-time overload early warning is the output-side overload main cause, then analyzing and generating an output-side load reduction strategy based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the output-side overload main cause after isolation on the N-1 output-side devices.

[0005] The second aspect of this application discloses a low-voltage switchgear overload early warning device based on current harmonic identification. The device is used in the aforementioned low-voltage switchgear overload early warning method based on current harmonic identification. The device includes: a real-time monitoring module for real-time monitoring of the current on both sides of the low-voltage switchgear, generating an input-side current harmonic feature vector and N output branch current harmonic feature vectors, wherein the N output branch current harmonic feature vectors correspond to N output-side devices; and a location analysis module for performing overload main cause location analysis based on the input-side current harmonic feature vector and the N output branch current harmonic feature vectors, and outputting a real-time overload early warning... The system includes: a contribution quantification module, used to quantify the overload contribution of the N output branch current harmonic feature vectors and output N overload risk weight factors if the real-time overload warning is the main cause of the input-side overload; a global collaborative load reduction module, used to perform global collaborative load reduction of the N output-side devices based on the N overload risk weight factors; and a load reduction strategy generation module, used to analyze and generate an output-side load reduction strategy based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the output-side overload main cause on the N-1 output-side devices after isolation if the real-time overload warning is the main cause of the output-side overload.

[0006] One or more technical solutions provided in this application have at least the following beneficial effects:

[0007] By performing real-time dual-side current monitoring on both the input and output branches of the low-voltage switchgear, the harmonic characteristics of the current on the input side and each output branch can be accurately captured. The generated harmonic feature vectors can reflect the frequency characteristics and harmonic distribution of the current waveform in detail, providing accurate input for subsequent overload analysis and early warning. Based on the harmonic feature vectors of the input and output branches, overload root cause localization analysis can be performed. By comparing current characteristics, it is possible to accurately determine whether the overload source comes from the input or output side. This root cause localization analysis can provide real-time overload early warning, quickly respond to system overload problems, and help to take measures in advance to avoid system damage caused by overload. When the input side overload is the main cause, the overload contribution of each branch is quantified based on the harmonic feature vectors of each output branch. By calculating the overload risk weight factor of each branch, the overload contribution of each output branch is quantified. By analyzing the impact of branch circuits on the overall system overload, we can accurately identify which branches contribute significantly to overload and prioritize overload mitigation, thereby improving the system's load management and response capabilities. Based on the overload risk weighting factor, we can perform global coordinated load reduction on N output devices, ensuring that each branch is coordinated during load reduction and avoiding excessive load reduction on one branch while other branches bear excessive load, thus achieving load balance. When output-side overload is the main cause, we analyze its impact on other branches based on the real-time overload status of the main cause branch devices, especially its harmonic-load coupling effect. Through harmonic coupling simulation, we generate output-side load reduction strategies to ensure that the load reduction operation of output devices not only reduces the load of the main cause branch but also avoids overload on other branches due to harmonic coupling, achieving more precise and scientific load regulation and improving the stability and security of the power supply system.

[0008] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0009] Figure 1 This is a schematic flowchart of a low-voltage switchgear overload early warning method based on current harmonic identification, provided in an embodiment of this application.

[0010] Figure 2 A schematic diagram of the structure of a low-voltage switchgear overload early warning device based on current harmonic identification provided in this application embodiment.

[0011] Figure labeling: Real-time monitoring module 10, Location analysis module 20, Contribution quantification module 30, Global collaborative load reduction module 40, Load reduction strategy generation module 50. Detailed Implementation

[0012] This application provides a low-voltage switchgear overload early warning method and device based on current harmonic identification, which solves the technical problem that most existing load adjustment methods rely on manual judgment and lack dynamic adjustment and optimization of the overall load of the power supply system, resulting in unbalanced load adjustment of the overall system.

[0013] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0014] Example 1, as Figure 1 As shown in the embodiment of this application, an overload early warning method for low-voltage switchgear based on current harmonic identification is provided. The method includes:

[0015] Real-time monitoring of the current on both sides of the low-voltage switchgear is performed to generate an input-side current harmonic characteristic vector and N output branch current harmonic characteristic vectors, wherein the N output branch current harmonic characteristic vectors correspond to N output-side devices.

[0016] Real-time current monitoring is performed on the input side and output branches of the low-voltage switchgear. The input side refers to the current of the main power supply of the low-voltage switchgear, and the output branches refer to the different output devices connected to the low-voltage switchgear. Hall current sensors can be installed to monitor the current, enabling real-time acquisition of current data for each branch. Hall current sensors are configured in the input busbar and each output branch of the low-voltage switchgear, capturing current waveform data at a predefined sampling rate, such as 1000 samples per second. The acquired current waveform data is then processed through grayscale mapping. The grayscale mapping process converts the amplitude changes of the waveform signal into different grayscale values, forming an image-based current waveform. Feature extraction is performed on the grayscale image, for example, using time-series spectral feature extraction methods to extract instantaneous harmonic feature vectors. These feature vectors represent the intensity, phase, and other information of each frequency component in the current waveform. The same current data acquisition, grayscale mapping, and spectral feature extraction process is performed on the input busbar and each output branch, ultimately obtaining the input side current harmonic feature vector and N output branch current harmonic feature vectors. The N output branch current harmonic characteristic vectors correspond to N output-side devices, and each output-side device corresponds to one output branch.

[0017] Based on the input current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, overload main cause localization analysis is performed, and real-time overload warning is output.

[0018] Based on the input-side current harmonic feature vector and the current harmonic feature vectors of N output branches, an overload cause localization analysis is performed. The goal is to determine the main source of the overload, which could be a current problem on the input side or a current problem in the output branch equipment. Specifically, the current harmonic feature vectors of the input and output sides are compared with historical overload current records. The historical records contain current feature data of past overloads. By comparison, the similarity between the current characteristics and historical overload characteristics can be identified. Based on the similarity, the overload risk probability vector of the input side and each output branch is calculated, i.e., the probability that an overload exists on the input side and in each output branch equipment. The current feature vector of the input side is compared with a multi-level overload feature template to calculate the overload risk probability vector of the input side. This process uses a dynamic weighting method to assess whether there is an overload risk on the input side. At the same time, a similar analysis is performed on each output branch to calculate the overload risk of each branch.

[0019] If the input current characteristics are highly similar to historical overload characteristics, and the overload risk on the input side exceeds a preset threshold, the input side is determined to be the main cause of the overload, and a real-time overload warning is output. If the current characteristics of the output branch are compared with historical overload characteristics and a high overload risk is identified, the output side is determined to be the main cause of the overload, and a real-time overload warning for the corresponding branch is output.

[0020] If the real-time overload warning is the main cause of input-side overload, then the overload contribution of the branch is quantified based on the N output branch current harmonic characteristic vectors, and N overload risk weight factors are output.

[0021] When the overload is the primary cause of the input-side overload, the overload contribution of each branch is quantified based on the harmonic feature vectors of the currents of N output branches. An overload risk weight factor is output for each branch. The aim is to quantify the contribution of each output branch to the overall overload and provide data support for subsequent load reduction decisions. Specifically, for each output branch's harmonic feature vector, it is compared with the input-side current feature vector to evaluate the overload contribution of each branch. A similarity-based metric is used to calculate the similarity between the current harmonic feature vectors of each output branch and the input-side current harmonic feature vectors. The higher the similarity, the greater the contribution of that branch to the input-side overload. The contribution of each branch is converted into an overload risk weight factor. Branches with high overload risk weight factors indicate that they account for a large proportion of the overall system overload and should be prioritized for load reduction.

[0022] Global coordinated load reduction of the N output-side devices is performed based on the N overload risk weighting factors.

[0023] Global coordinated load reduction is implemented based on N overload risk weighting factors. This involves coordinating load adjustments across multiple output branches to prevent system-wide instability caused by overload in a single branch. Specifically, based on the N overload risk weighting factors, overloaded branches are first prioritized. Branches with higher weighting factors have higher priority because they contribute more to the overload and need to be reduced first. After prioritization, load switching or disconnection is automatically implemented based on the priority and risk factor of each overloaded branch. For example, if a branch has a very high overload risk factor and is crucial to system stability, partial load disconnection or even complete disconnection of that branch is implemented to alleviate overload pressure. The load reduction operation is coordinated, meaning that load adjustments across output devices need to be balanced to avoid overloading other branches. Load reduction is not just targeted at a single branch but involves globally optimizing and adjusting the load of each branch to ultimately reduce the overall overload risk.

[0024] If the real-time overload warning is the main cause of the output-side overload, then based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the main cause of the output-side overload after isolation on N-1 output-side devices, an output-side load reduction strategy is generated.

[0025] If the real-time overload warning indicates the main cause of the output-side overload, the harmonic-load coupling disturbance characteristics of the corresponding real-time main cause branch equipment are analyzed to formulate targeted load reduction strategies. Specifically, for the real-time main cause branch equipment corresponding to the main cause of the output-side overload, the impact of the equipment after isolation is analyzed. That is, after the equipment is disconnected, the harmonic-load coupling characteristics of the remaining N-1 output-side equipment are analyzed. The harmonic-load coupling disturbance characteristic analysis can be achieved through simulation models to simulate the impact of load disturbance after branch isolation on other equipment. This analysis helps to identify which branch overload will cause the greatest interference to other branches, thus affecting the stability of the overall system. Based on the harmonic-load disturbance characteristics, an output-side load reduction strategy is generated, with the goal of reducing the load of the affected branches in the system and ensuring system stability. For example, based on the load coupling relationship between branches, priority is given to adjusting those branches most affected by the interference to ensure that the overall system recovers to the normal load state with minimal interference.

[0026] Furthermore, the method also includes:

[0027] A Hall current sensor installed on the input busbar of the low-voltage switchgear acquires raw current waveform data of the input side at a predefined sampling rate and outputs a time-series current waveform sequence. The time-series current waveform sequence is processed by grayscale mapping to output a waveform grayscale image. The waveform grayscale image is segmented into multiple segmented waveform images using a preset sliding window, wherein the overlap between adjacent time-series segmented waveform images is greater than 75%. Time-series spectral features are extracted from the multiple segmented waveform images to output multiple instantaneous harmonic feature vectors. The input-side current harmonic feature vector is output by sliding weighted fusion of the multiple instantaneous harmonic feature vectors.

[0028] A Hall current sensor is installed on the input busbar of the low-voltage switchgear to collect input current data. The Hall current sensor senses the current in real time and converts it into a voltage signal for monitoring the current waveform. To obtain sufficient current waveform information, a predefined sampling rate is set for the Hall current sensor, such as 1000 samples per second, to ensure that details of the current waveform are captured. A high sampling rate helps to accurately capture rapid changes in current, thereby improving the accuracy of subsequent data processing. The Hall current sensor collects raw current waveform data according to the predefined sampling rate, and the raw current waveform data is arranged in chronological order to form a time-series current waveform sequence.

[0029] Gray-scale mapping is the process of converting time-series current waveform data into a gray-scale image. Since current waveform data is usually a continuous numerical signal, gray-scale mapping can convert these numerical signals into image data, making it easier to capture and analyze the changes in the signal. Through gray-scale mapping, the amplitude value (or certain frequency characteristics) of the time-series current waveform is converted into gray levels, and a waveform gray-scale image is output. In the waveform gray-scale image, the changes in the current signal are represented by different gray values. The higher the gray value, the greater the amplitude of the current signal, and vice versa.

[0030] A preset sliding window is used to segment the waveform grayscale image. For example, the width of the preset sliding window is set to a time span of 200ms. This means that each window covers the current waveform data within 200ms and slides across the entire time-series image to segment different waveform segments. Each preset sliding window extracts a portion of the image, i.e., the current waveform of a 200ms time segment. Thus, the entire time-series current waveform sequence is segmented into multiple segmented waveform images, each containing the current waveform data within 200ms. In these multiple segmented waveform images, there is more than 75% overlap between adjacent time-series segmented waveform images. That is, when processing each new sliding window, the last part of the previous window will overlap with the beginning part of the current window. This overlap preserves temporal continuity, ensures the coherence of timing information, and avoids information loss.

[0031] Time-series spectral characteristics can reveal information about current waveforms at different frequencies, and are used to identify the variation patterns of current and its harmonic characteristics. Time-frequency analysis can be performed on multiple segmented waveform images. For example, the Fourier transform method can be used to convert the time-domain signal into a frequency-domain signal to obtain the frequency distribution and amplitude information, and obtain the instantaneous harmonic feature vector. The instantaneous harmonic feature vector describes the frequency characteristics of the current waveform in that time-series segment, including the amplitude, frequency and phase of the harmonics, and can reflect the harmonic nature of the current in that segment.

[0032] Since each instantaneous harmonic feature vector reflects the current waveform characteristics of the corresponding time segment, in order to obtain the comprehensive characteristics of the entire input-side current waveform, these instantaneous feature vectors need to be fused. Sliding weighted fusion is achieved by weighting multiple instantaneous harmonic feature vectors. The weights can be dynamically adjusted according to the changes in the time step to smooth and emphasize changes in a short period of time. Through sliding weighted fusion, a smooth input-side current harmonic feature vector that can represent the entire time process is obtained. This input-side current harmonic feature vector integrates the spectral information of the entire current waveform and can more comprehensively reflect the changing characteristics of the current.

[0033] Furthermore, based on the input-side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, an overload cause localization analysis is performed, and a real-time overload warning is output. The method includes:

[0034] The system locally retrieves historical overload current records and performs fault feature vector fitting based on these records, outputting a multi-level overload feature vector template. It calculates the time-varying weighted similarity between the input-side current harmonic feature vector and the multi-level overload feature vector template, outputting an input-side multi-level overload risk probability vector. A preset dynamic diagnostic threshold matrix is ​​used, and the input-side overload analysis result is obtained by comparing the dynamic diagnostic threshold matrix with the input-side multi-level overload risk probability vector. Similarly, synchronous overload cause localization analysis is performed on the N output branch current harmonic feature vectors, producing N output branch overload analysis results. The input-side overload analysis results and the N output branch overload analysis results constitute the real-time overload warning.

[0035] The system locally accesses historical overload current records, stored in a local database. These records contain current characteristic data under different overload scenarios, including the current waveform, overload occurrence time, duration, and amplitude for each overload event. This data allows for understanding the current variation patterns and characteristics under overload conditions. Fault feature vector fitting is then performed based on these historical overload current records. Specifically, by analyzing these records, typical overload characteristics are extracted, such as the characteristic frequency, amplitude variation, and nonlinear characteristics of the current waveform. Multi-level overload feature vector templates are then established based on the historical data, with each template representing a specific overload mode, such as mild, moderate, or severe overload.

[0036] The input-side current harmonic feature vector is compared with the multi-level overload feature vector template to calculate their similarity. This similarity calculation considers not only static feature comparison but also dynamic changes between real-time and historical data to ensure timely identification of the evolution of overload risk. Time-varying weighting allows for dynamic adjustment of weights when comparing the real-time current features (i.e., the input-side current harmonic feature vector) with historical overload data templates, focusing more on recent changes rather than long-term historical trends. That is, more weight is given to the similarity at the most recent moment, while historical data further away from the current moment is given less weight. For example, a weighted sliding window method can be used to assign higher weights to more recent historical data. By calculating the time-varying weighted similarity between the input-side current harmonic feature vector and the multi-level overload feature template, the input-side multi-level overload risk probability vector is obtained. This vector represents the degree of matching between the current input-side current and different overload states. Each element represents the probability that the input-side current waveform belongs to a specific overload level in the current state. For example, if the similarity between the input-side current and the severe overload template is high, the probability of severe overload risk is high.

[0037] The purpose of the dynamic diagnostic threshold matrix is ​​to provide a benchmark for the system, comparing it with the multi-level overload risk probability vector on the input side to determine whether the current state has reached the overload warning threshold. The matrix elements contain the risk probability thresholds corresponding to each overload level. These thresholds are dynamically adjusted according to the actual operating conditions of the power system. For example, during peak load periods, the overload tolerance needs to be reduced, and the thresholds will be lowered accordingly. The multi-level overload risk probability vector on the input side is compared with the preset dynamic diagnostic threshold matrix. If the risk probability of a certain overload level on the input side exceeds the corresponding threshold, then the overload risk at that level is considered valid. The comparison result forms the input side overload analysis result, indicating the current overload risk level on the input side.

[0038] For each output branch, an overload cause localization analysis is performed. By analyzing the current characteristics of each branch, the main causes of overload are identified, and corresponding overload analysis results are generated. Similar to the overload analysis on the input side, the overload analysis of the output branch also compares its current characteristics with historical overload characteristic templates to calculate the similarity with historical overload patterns. Then, by comparing with the dynamic diagnostic threshold matrix, the overload risk level of each output branch is determined. For each output branch, a corresponding overload analysis result is generated, indicating whether the branch has experienced an overload and the severity of its overload risk.

[0039] Furthermore, if the real-time overload warning is the main cause of input-side overload, then the overload contribution of the branches is quantified based on the N harmonic characteristic vectors of the output branch currents, and N overload risk weight factors are output. The method includes:

[0040] When the overload analysis results of the N output branches all indicate no overload risk, and the overload analysis results of the input side indicate an input side overload, the real-time overload warning is determined to be the main cause of the input side overload. In the risk scenario where the real-time overload warning is the main cause of the input side overload, the N output side overload risk probability distributions of the current harmonic characteristic vectors of the N output branches are called. Based on the N output side overload risk probability distributions, the branch overload contribution is quantified, and the N overload risk weight factors are output.

[0041] When the overload analysis results for all N output branches indicate no overload risk, it means that the current waveform of each output branch has not reached the overload threshold and no overload signs have been detected. Simultaneously, the input-side overload analysis results indicate an input-side overload, meaning that the input-side current waveform has exceeded the preset overload threshold, indicating an abnormal input-side current and a risk of overload. When both conditions are met simultaneously—that is, no overload in the output branches but an overload on the input side—the overload is determined to be the primary cause of the input-side overload. This determination implies that the overload problem originates from the input side, not from a specific output branch.

[0042] In risk scenarios where the input-side overload is determined to be the main cause, it is necessary to further clarify the overload risk status of each output branch. The N output-side overload risk probability distributions of the N output branch current harmonic characteristic vectors are called. The output-side overload risk probability distributions provide overload probability information for each branch. For example, some branches have a higher overload risk probability, and these branches should be given priority when reducing the load.

[0043] Based on the overload risk probability distribution on the output side, the overload contribution of each branch is quantified. The purpose is to determine the contribution of each output branch to the overall overload risk, i.e., which branches are more likely to have an impact on the overall system when overloaded. Specifically, by weighting the overload risk probability distribution of each branch, an overload risk weight factor for each branch is obtained. The overload risk weight factor reflects the magnitude of the branch's contribution to the overall system overload. For example, if a branch has a high overload risk probability, its risk weight factor will also be large, indicating that the branch contributes more to the overload event and should be prioritized for load reduction or load optimization.

[0044] Furthermore, the method for globally coordinated load reduction of the N output-side devices based on the N overload risk weighting factors includes:

[0045] In a risk scenario where the real-time overload warning is the main cause of input-side overload, the input-side overload level is extracted from the input-side overload analysis results; the overload adjustment scale is obtained by matching the input-side overload level with the dynamic load reduction coefficient mapping table; N collaborative load reduction command vectors are calculated and output based on the overload adjustment scale and N overload risk weight factors; the N collaborative load reduction command vectors are used to drive the N output-side devices, and global collaborative load reduction is performed using gradient load reduction operation.

[0046] When real-time overload warning is the main cause of input-side overload, the input-side overload level is extracted from the input-side overload analysis results. The input-side overload level indicates the severity of the input-side overload, and is usually divided into different levels such as mild, moderate and severe. This level is determined based on the similarity between the input-side current waveform and the overload feature template, the comparison with historical data, and the comparison with the threshold matrix.

[0047] The dynamic descent factor mapping table maps the relationship between different overload levels and descent adjustment scales. For example, when the input overload level is mild, the descent factor is small, requiring adjustment only for a small portion of the load; when the overload level is severe, the descent factor is large, requiring large-scale descent of multiple devices or branches. Based on the input overload level, the corresponding overload adjustment scale is looked up from the dynamic descent factor mapping table. The overload adjustment scale can be understood as a control parameter representing the system's response strength to input overload. A larger overload adjustment scale means a greater adjustment of the load is needed to alleviate the overload pressure.

[0048] Based on the product of the overload adjustment scale and N overload risk weight factors, N collaborative load reduction instruction vectors are calculated and output. Specifically, the output branches with larger overload risk weights need to receive stronger load reduction instructions to alleviate the overall system overload. The collaborative load reduction instruction vectors indicate the amount of load reduction required for each output branch. The purpose of the collaborative load reduction instructions is to enable the entire system to smoothly reduce the load and avoid system overload.

[0049] Gradient load derating is a method of gradually adjusting the load. Based on N calculated coordinated load derating command vectors, the load of each output branch is gradually adjusted, reducing the device load according to a preset gradient to smoothly achieve global load derating. Gradient load derating helps avoid system instability caused by sudden load switching, ensuring that the load of each branch is reduced as needed, avoiding excessive stress on the equipment. The calculated coordinated load derating command vectors drive each output-side device, including: reducing the current output of devices with heavy loads; and appropriately reducing the load of devices with light loads to ensure balanced load distribution. The load derating process is carried out in a gradient distribution manner, gradually alleviating overload pressure and ensuring stable system operation. Ultimately, all N output-side devices adjust their loads according to their respective load derating commands, completing global coordinated load derating. The load of the entire system is effectively controlled, overload is alleviated, and further damage to the system is avoided.

[0050] Furthermore, when the input-side overload analysis result indicates no overload risk, and the first output branch overload analysis result among the N output branch overload analysis results indicates an output-side overload, the real-time overload warning is determined to be the main cause of the output-side overload.

[0051] If the input-side overload analysis result indicates no overload risk, meaning the input-side current has not exceeded the overload threshold, then the overload analysis of the output branches continues. The overload analysis results of N output branches are examined. If the overload analysis result of the first output branch indicates an output-side overload, and the first output branch overload analysis result refers to any one output branch with the highest overload level, this indicates that the overload of the output branch is the root cause of the system overload, rather than the input-side current problem. In this case, the real-time overload warning is determined to be the main cause of the output-side overload, and the output-side overload problem is addressed centrally.

[0052] Furthermore, if the real-time overload warning is the main cause of the output-side overload, then based on the harmonic-load coupling disturbance characteristics of the corresponding real-time main cause branch equipment to N-1 output-side equipment after isolation, an output-side load reduction strategy is analyzed and generated. The method includes:

[0053] In a risk scenario where the real-time overload warning is the main cause of the output-side overload, the device corresponding to the real-time main cause branch device in the first output branch overload analysis result is located; the first output-side overload level is extracted from the first output branch overload analysis result; if the first output-side overload level is lower than the preset emergency disconnection threshold, an isolation command is output to perform electrical isolation of the real-time main cause branch device; the output-side load reduction strategy is generated by simulating the harmonic-load coupling disturbance characteristics of the N-1 output-side devices after the real-time main cause branch device is disconnected.

[0054] When the real-time overload warning is the main cause of the overload on the output side, the specific real-time main cause branch device is located based on the overload analysis results of the first output branch. If the overload analysis results of a certain output branch indicate that it is the main source of overload, that is, the current of the branch exceeds the overload threshold and has a significant impact on the overall stability of the system, then the branch is the real-time main cause branch device.

[0055] Based on the overload analysis results of the first output branch, the overload level of the first output side of the main cause branch equipment in real time is extracted. The overload level is determined based on the similarity between the current waveform and the historical data template, or by comparison with the preset overload threshold. It includes classifications such as mild, moderate, and severe, indicating the degree of overload of the branch.

[0056] The emergency disconnection threshold is preset according to specific needs. The overload level of the first output side is compared with the preset emergency disconnection threshold. If the overload level of the branch is lower than the preset threshold, it indicates that the overload is relatively minor, and there is no need to disconnect the branch immediately. In this case, an isolation command is output. The isolation command requires electrical isolation of the real-time main branch equipment to prevent the branch from continuing to affect other branches and to avoid the overload problem from spreading to the entire system. Isolation can be achieved by disconnecting the circuit, cutting off the power supply, or other similar means to ensure that the load of the main branch does not interfere with the load of other branches.

[0057] After isolating the main branch devices in real time, simulation analysis is performed on the remaining N-1 output-side devices to evaluate their operating status after the main branch is cut off. This includes analyzing the behavior of these remaining branches under harmonic-load coupling disturbances. Specifically, the simulation process simulates the load changes and current distribution after the main branch is isolated, checking whether other devices are affected or whether further adjustments are needed. Based on the simulation results, an output-side load reduction strategy for the N-1 output-side devices is generated, including: allocating load reduction tasks according to the overload risk and remaining load of the devices, adjusting the load of each output branch, reducing the burden on other parts of the system, and ensuring that the entire system returns to a safe operating state. In this process, priority is given to reducing the load of devices that are more affected by harmonic-load coupling disturbances to avoid overload and ensure system stability.

[0058] Furthermore, by simulating the harmonic-load coupling disturbance characteristics of the N-1 output-side devices after the real-time main branch device is disconnected, the output-side load reduction strategy is generated, and the method includes:

[0059] Construct a branch topology network for the N-1 output-side devices; calculate the branch harmonic transfer matrix based on the branch topology network, and mark the strongly coupled harmonic branches based on the branch harmonic transfer matrix; use the strongly coupled harmonic branches as harmonic constraints to perform load priority allocation for the N-1 output-side devices, and obtain the output-side load reduction strategy.

[0060] Branch topology networks are used to describe the electrical connections between N-1 output-side devices. By establishing a branch topology network, the interactions and influences between each branch and other branches can be clearly defined, especially the coupling relationships between harmonics and loads. By acquiring the connection information of each output-side device, such as current flow direction, connection points, and power flow, a branch topology network of N-1 output-side devices is constructed. In the branch topology network, each output-side device is represented as a node, and nodes are connected by edges. The weight of each edge represents the impedance of current transmission, harmonic coupling, or other influencing factors.

[0061] The branch harmonic transfer matrix is ​​a matrix used to describe the mutual transfer of harmonic signals between branches. It is constructed by performing harmonic analysis on each branch to calculate the harmonic influence between different branches. Specifically, it performs spectral analysis on the current waveform of each branch to extract harmonic components and calculates the propagation characteristics of these harmonic components between different branches. Based on these analyses, the branch harmonic transfer matrix is ​​constructed, where each element represents the influence of the harmonic component of one branch on another branch. In other words, the value in the matrix can represent the coupling strength of the harmonics of one branch to another branch.

[0062] Based on the calculated branch harmonic transfer matrix, identify which pairs of branches have strong harmonic coupling. In the electrical system, these branch pairs are characterized by the fact that when one branch experiences an overload or abnormality, the load or current of the other branch may also be affected. By setting a threshold, branch pairs with high harmonic coupling strength are marked, namely, strongly coupled harmonic branch pairs. These branch pairs are the focus of attention when reducing load, because their load changes may cause significant disturbances to other branches.

[0063] Based on harmonic-coupled branch pairs, a load priority is assigned to each output branch to determine which branches should be prioritized for load reduction and which branches can continue to bear a larger load during system load reduction. Specifically, if two branches have strong harmonic coupling and one branch needs to be reduced in load, the load of the other branch also needs to be adjusted accordingly. This is because harmonic coupling can cause abnormal load fluctuations, and it is necessary to ensure that these strongly coupled branches can handle overload problems together. Based on this, branches with stronger load capacity and lower overload risk are assigned lower priority, while branches with weaker load capacity and higher overload risk are assigned higher priority. Based on the load priority allocation, an output-side load reduction strategy is generated. This strategy indicates the amount of load that each output branch should reduce during load reduction and ensures system stability.

[0064] Furthermore, if the first output-side overload level is higher than the emergency cut-off threshold, the harmonic-load coupling disturbance characteristics of the N output-side devices are simulated to generate the output-side load reduction strategy.

[0065] If the overload level of the first output side is higher than the emergency cut-off threshold, i.e., the overload is severe, the harmonic-load coupling disturbance characteristics of N output-side devices are simulated. Specifically, the simulation process simulates the harmonic interaction between N output-side devices. That is, an overload in one branch may interfere with other devices through harmonics, causing their load changes and even triggering further overload problems. The simulation simulates these harmonic-load coupling effects, including: the current change in the overloaded branch may lead to changes in the harmonic frequency components. These changes are propagated to other branches through electrical connections within the system. The simulation process evaluates whether the load of other devices will be affected after the main branch is cut off or the load is reduced, and whether corresponding adjustments are needed. Based on simulation results, output-side load reduction strategies are generated. For example, based on the overload risk, load capacity, and harmonic coupling degree of each branch, a load reduction priority is assigned to each branch, prioritizing the reduction of loads on devices with strong harmonic coupling and heavy loads. Based on the harmonic-load disturbance characteristics, the amount of load reduction required for each branch is determined to ensure that the overall system can recover stability. Combining the coupling effects between branches, the load reduction operations are ensured to be coordinated and consistent, avoiding the exacerbation of load pressure on other branches by the load reduction of one branch.

[0066] In summary, the low-voltage switchgear overload early warning method based on current harmonic identification provided in this application has the following technical effects:

[0067] By performing real-time dual-side current monitoring on both the input and output branches of the low-voltage switchgear, the harmonic characteristics of the current on the input side and each output branch can be accurately captured. The generated harmonic feature vectors can reflect the frequency characteristics and harmonic distribution of the current waveform in detail, providing accurate input for subsequent overload analysis and early warning. Based on the harmonic feature vectors of the input and output branches, overload root cause localization analysis can be performed. By comparing current characteristics, it is possible to accurately determine whether the overload source comes from the input or output side. This root cause localization analysis can provide real-time overload early warning, quickly respond to system overload problems, and help to take measures in advance to avoid system damage caused by overload. When the input side overload is the main cause, the overload contribution of each branch is quantified based on the harmonic feature vectors of each output branch. By calculating the overload risk weight factor of each branch, the overload contribution of each output branch is quantified. By analyzing the impact of branch circuits on the overall system overload, we can accurately identify which branches contribute significantly to overload and prioritize overload mitigation, thereby improving the system's load management and response capabilities. Based on the overload risk weighting factor, we can perform global coordinated load reduction on N output devices, ensuring that each branch is coordinated during load reduction and avoiding excessive load reduction on one branch while other branches bear excessive load, thus achieving load balance. When output-side overload is the main cause, we analyze its impact on other branches based on the real-time overload status of the main cause branch devices, especially its harmonic-load coupling effect. Through harmonic coupling simulation, we generate output-side load reduction strategies to ensure that the load reduction operation of output devices not only reduces the load of the main cause branch but also avoids overload on other branches due to harmonic coupling, achieving more precise and scientific load regulation and improving the stability and security of the power supply system.

[0068] Example 2, based on the same inventive concept as the low-voltage switchgear overload early warning method based on current harmonic identification in the previous examples, such as... Figure 2 As shown in the figure, this application embodiment provides a low-voltage switchgear overload early warning device based on current harmonic identification, the device comprising:

[0069] The real-time monitoring module 10 is used to perform real-time monitoring of the current on both sides of the low-voltage switchgear, and generate an input-side current harmonic feature vector and N output branch current harmonic feature vectors, wherein the N output branch current harmonic feature vectors correspond to N output-side devices.

[0070] The location analysis module 20 is used to perform overload main cause location analysis based on the input side current harmonic feature vector and N output branch current harmonic feature vectors, and output real-time overload warning.

[0071] The contribution quantification module 30 is used to perform branch overload contribution quantification based on the N output branch current harmonic feature vectors if the real-time overload warning is the main cause of input-side overload, and output N overload risk weight factors.

[0072] The global collaborative load reduction module 40 is used to perform global collaborative load reduction of the N output-side devices based on the N overload risk weight factors.

[0073] The load reduction strategy generation module 50 is used to analyze and generate an output-side load reduction strategy based on the harmonic-load coupling disturbance characteristics of the real-time overload warning branch device corresponding to the output-side overload main cause after isolation of N-1 output-side devices if the real-time overload warning is the main cause of the output-side overload.

[0074] Furthermore, the real-time monitoring module 10 is used to perform the following operation steps:

[0075] A Hall current sensor installed on the input busbar of the low-voltage switchgear acquires raw current waveform data of the input side at a predefined sampling rate and outputs a time-series current waveform sequence. The time-series current waveform sequence is processed by grayscale mapping to output a waveform grayscale image. The waveform grayscale image is segmented into multiple segmented waveform images using a preset sliding window, wherein the overlap between adjacent time-series segmented waveform images is greater than 75%. Time-series spectral features are extracted from the multiple segmented waveform images to output multiple instantaneous harmonic feature vectors. The input-side current harmonic feature vector is output by sliding weighted fusion of the multiple instantaneous harmonic feature vectors.

[0076] Furthermore, the positioning analysis module 20 is used to perform the following operation steps:

[0077] The system locally retrieves historical overload current records and performs fault feature vector fitting based on these records, outputting a multi-level overload feature vector template. It calculates the time-varying weighted similarity between the input-side current harmonic feature vector and the multi-level overload feature vector template, outputting an input-side multi-level overload risk probability vector. A preset dynamic diagnostic threshold matrix is ​​used, and the input-side overload analysis result is obtained by comparing the dynamic diagnostic threshold matrix with the input-side multi-level overload risk probability vector. Similarly, synchronous overload cause localization analysis is performed on the N output branch current harmonic feature vectors, producing N output branch overload analysis results. The input-side overload analysis results and the N output branch overload analysis results constitute the real-time overload warning.

[0078] Furthermore, the contribution quantification module 30 is used to perform the following operational steps:

[0079] When the overload analysis results of the N output branches all indicate no overload risk, and the overload analysis results of the input side indicate an input side overload, the real-time overload warning is determined to be the main cause of the input side overload. In the risk scenario where the real-time overload warning is the main cause of the input side overload, the N output side overload risk probability distributions of the current harmonic characteristic vectors of the N output branches are called. Based on the N output side overload risk probability distributions, the branch overload contribution is quantified, and the N overload risk weight factors are output.

[0080] Furthermore, the global collaborative load reduction module 40 is used to perform the following operation steps:

[0081] In a risk scenario where the real-time overload warning is the main cause of input-side overload, the input-side overload level is extracted from the input-side overload analysis results; the overload adjustment scale is obtained by matching the input-side overload level with the dynamic load reduction coefficient mapping table; N collaborative load reduction command vectors are calculated and output based on the overload adjustment scale and N overload risk weight factors; the N collaborative load reduction command vectors are used to drive the N output-side devices, and global collaborative load reduction is performed using gradient load reduction operation.

[0082] Furthermore, when the input-side overload analysis result indicates no overload risk, and the first output branch overload analysis result among the N output branch overload analysis results indicates an output-side overload, the real-time overload warning is determined to be the main cause of the output-side overload.

[0083] Furthermore, the load reduction strategy generation module 50 is used to perform the following operation steps:

[0084] In a risk scenario where the real-time overload warning is the main cause of the output-side overload, the device corresponding to the real-time main cause branch device in the first output branch overload analysis result is located; the first output-side overload level is extracted from the first output branch overload analysis result; if the first output-side overload level is lower than the preset emergency disconnection threshold, an isolation command is output to perform electrical isolation of the real-time main cause branch device; the output-side load reduction strategy is generated by simulating the harmonic-load coupling disturbance characteristics of the N-1 output-side devices after the real-time main cause branch device is disconnected.

[0085] Furthermore, the load reduction strategy generation module 50 is used to perform the following operation steps:

[0086] Construct a branch topology network for the N-1 output-side devices; calculate the branch harmonic transfer matrix based on the branch topology network, and mark the strongly coupled harmonic branches based on the branch harmonic transfer matrix; use the strongly coupled harmonic branches as harmonic constraints to perform load priority allocation for the N-1 output-side devices, and obtain the output-side load reduction strategy.

[0087] Furthermore, if the first output-side overload level is higher than the emergency cut-off threshold, the harmonic-load coupling disturbance characteristics of the N output-side devices are simulated to generate the output-side load reduction strategy.

[0088] Through the foregoing detailed description of the low-voltage switchgear overload early warning method based on current harmonic identification, those skilled in the art can clearly understand the low-voltage switchgear overload early warning device based on current harmonic identification in this embodiment. Since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and relevant parts can be referred to the method section.

[0089] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-voltage cabinet overload early warning method based on current harmonic identification, characterized in that, The method includes: Real-time monitoring of the current on both sides of the low-voltage switchgear is performed to generate an input-side current harmonic characteristic vector and N output branch current harmonic characteristic vectors, wherein the N output branch current harmonic characteristic vectors correspond to N output-side devices. Based on the input current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, overload main cause localization analysis is performed, and real-time overload warning is output. If the real-time overload warning is the main cause of input-side overload, then the overload contribution of the branch is quantified based on the N harmonic feature vectors of the output branch current, and N overload risk weight factors are output. Global coordinated load reduction of the N output-side devices is performed based on the N overload risk weighting factors. If the real-time overload warning is the main cause of the output-side overload, then based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch equipment corresponding to the main cause of the output-side overload after isolation on N-1 output-side equipment, an output-side load reduction strategy is generated. If the real-time overload warning is the main cause of input-side overload, then the overload contribution of the branches is quantified based on the N output branch current harmonic characteristic vectors, and N overload risk weight factors are output, including: When the overload analysis results of N output branches all indicate no overload risk, and the overload analysis results of the input side indicate an overload on the input side, the real-time overload warning is determined to be the main cause of the overload on the input side. In the risk scenario where the real-time overload warning is the main cause of input-side overload, the N output-side overload risk probability distributions of the N output branch current harmonic characteristic vectors are invoked. The overload contribution of the branch is quantified based on the N output-side overload risk probability distributions, and the N overload risk weight factors are output. Global coordinated load reduction of the N output-side devices based on the N overload risk weighting factors includes: In a risk scenario where the real-time overload warning is the main cause of input-side overload, the input-side overload level is extracted from the input-side overload analysis results. The overload adjustment scale is obtained by matching the input-side overload level with the dynamic load reduction coefficient mapping table; Based on the overload adjustment scale and N overload risk weighting factors, calculate and output N coordinated load reduction command vectors; The N coordinated load reduction command vectors are used to drive the N output-side devices, and a gradient load reduction operation is used to perform global coordinated load reduction.

2. The current harmonic identification based low voltage cabinet overload early warning method of claim 1, wherein, The method further includes: The Hall current sensor installed on the input busbar of the low-voltage switchgear acquires the raw current waveform data of the input side at a predefined sampling rate and outputs a time-series current waveform sequence. The time-series current waveform sequence is processed by grayscale mapping to output a waveform grayscale image; The waveform grayscale image is segmented into multiple segmented waveform images using a preset sliding window, wherein the overlap between adjacent time-series segmented waveform images is greater than 75%. Temporal spectral features are extracted from the multiple segmented waveform images to output multiple instantaneous harmonic feature vectors; The input-side current harmonic feature vector is output by performing sliding weighted fusion on the multiple instantaneous harmonic feature vectors.

3. The current harmonic identification based low voltage cabinet overload early warning method of claim 2, wherein, Based on the input-side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, an overload cause localization analysis is performed, and a real-time overload warning is output. The method includes: Locally retrieve historical overload current records, and perform fault feature vector fitting based on the historical overload current records to output multi-level overload feature vector templates; Calculate the time-varying weighted similarity between the input-side current harmonic feature vector and the multi-level overload feature vector template, and output the input-side multi-level overload risk probability vector; A preset dynamic diagnostic threshold matrix is ​​used, and the input-side overload analysis results are obtained by comparing the dynamic diagnostic threshold matrix with the input-side multi-level overload risk probability vector. Similarly, synchronous overload cause localization analysis is performed on the harmonic characteristic vectors of the N output branch currents to generate N output branch overload analysis results. The input-side overload analysis results and the N output branch overload analysis results constitute the real-time overload warning.

4. The current harmonic identification based low voltage cabinet overload early warning method of claim 1, wherein, When the input-side overload analysis result indicates no overload risk, and the first output branch overload analysis result among the N output branch overload analysis results indicates an output-side overload, the real-time overload warning is determined to be the main cause of the output-side overload.

5. The current harmonic identification based low voltage cabinet overload early warning method of claim 4, wherein, If the real-time overload warning is the main cause of output-side overload, then based on the harmonic-load coupling disturbance characteristics of the corresponding real-time main cause branch equipment to N-1 output-side equipment after isolation, an output-side load reduction strategy is analyzed and generated. The method includes: In a risk scenario where the real-time overload warning is the main cause of the output-side overload, locate the real-time main cause branch device corresponding to the overload analysis result of the first output branch; Extract the overload level of the first output side from the overload analysis results of the first output branch; If the overload level of the first output side is lower than the preset emergency cut-off threshold, the output isolation command executes the electrical isolation of the real-time main branch equipment; The output-side load reduction strategy is generated by simulating the harmonic-load coupling disturbance characteristics of the N-1 output-side devices after the real-time main branch device is disconnected.

6. The current harmonic identification based low voltage cabinet overload early warning method of claim 5, wherein, By simulating the harmonic-load coupling disturbance characteristics of the N-1 output-side devices after the real-time main branch device is disconnected, the output-side load reduction strategy is generated, the method comprising: Construct the branch topology network for the N-1 output-side devices; After calculating the branch harmonic transfer matrix based on the branch topology network, the strongly coupled harmonic branch pairs are marked based on the branch harmonic transfer matrix. Using the strongly coupled harmonic branch pairs as harmonic constraints, the load priority allocation of the N-1 output-side devices is executed to obtain the output-side load reduction strategy.

7. The current harmonic identification based low voltage cabinet overload early warning method of claim 5, wherein, If the overload level of the first output side is higher than the preset emergency cut-off threshold, then the harmonic-load coupling disturbance characteristics of the N output side devices are simulated to generate the output side load reduction strategy.

8. The low-voltage cabinet overload early warning device based on current harmonic identification, characterized in that, For implementing the low-voltage switchgear overload early warning method based on current harmonic identification as described in any one of claims 1-7, the apparatus comprises: The real-time monitoring module is used to perform real-time monitoring of the current on both sides of the low-voltage switchgear, and generate the input-side current harmonic feature vector and N output branch current harmonic feature vectors, wherein the N output branch current harmonic feature vectors correspond to N output-side devices. The location analysis module is used to perform overload cause location analysis based on the input current harmonic feature vector and the N output branch current harmonic feature vectors, and output real-time overload warning. The contribution quantification module is used to perform branch overload contribution quantification based on the N output branch current harmonic feature vectors if the real-time overload warning is the main cause of input-side overload, and output N overload risk weight factors. The global collaborative load reduction module is used to perform global collaborative load reduction of the N output-side devices based on the N overload risk weight factors. The load reduction strategy generation module is used to analyze and generate an output-side load reduction strategy based on the harmonic-load coupling disturbance characteristics of the real-time overload warning branch device corresponding to the output-side overload main cause after isolation of N-1 output-side devices if the real-time overload warning is the main cause of the output-side overload.

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