Metal oxide semiconductor field effect transistor and method of making the same
By employing a three-dimensional shielding region design in silicon carbide trench gate MOSFETs, the problems of insufficient current density and difficulty in reducing cell size are solved, achieving higher current density and long-term reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHUZHOU CRRC TIMES SEMICON CO LTD
- Filing Date
- 2024-03-20
- Publication Date
- 2026-07-31
AI Technical Summary
The current density of existing silicon carbide trench gate MOSFETs is insufficient, the cell size is difficult to shrink further, and the parasitic junction field-effect transistor region resistance introduced by the electric field shielding structure leads to a decrease in current density.
The shielding area design employs a three-dimensional structure to wrap the bottom and sidewalls of the trench gate. By setting multiple spaced second trench gates and shielding areas on the substrate, the stress of the trench gate oxygen electric field is reduced, and the cell size is reduced in three dimensions to increase the current density.
It effectively reduces the gate oxide electric field stress in the trench, improves the current density and long-term reliability of the MOSFET, and at the same time reduces the resistance of the JFET region, thereby increasing the current density of the cell and the current capability of the parasitic diode.
Smart Images
Figure CN120751737B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and more specifically, to metal-oxide-semiconductor field-effect transistors and their fabrication methods. Background Technology
[0002] With the development of power semiconductor technology, silicon carbide metal oxide semiconductor field-effect transistors (MOSFETs) are becoming increasingly widely used in new energy, wind power, photovoltaics, and energy storage fields due to their material advantages.
[0003] Among them, trench-gate MOSFETs can reduce cell size and significantly increase MOSFET current density compared to planar-gate MOSFETs. However, due to the wide bandgap of silicon carbide material, the gate oxide electric field stress in the trench is extremely high. Therefore, an electric field shielding structure must be designed to protect the gate oxide in the trench to meet long-term reliability requirements. However, the electric field shielding structure introduces parasitic junction field-effect transistor (JFET) region resistance, resulting in a decrease in MOSFET current density. Currently, the current density of trench-gate silicon carbide MOSFETs with shielding structures needs to be improved, and the cell size needs to be further reduced. Summary of the Invention
[0004] The present invention aims to at least partially solve one of the technical problems in the related art.
[0005] Therefore, in one aspect of the present invention, a metal-oxide-semiconductor field-effect transistor (MOSFET) is provided. The MOSFET comprises: a substrate; an epitaxial layer disposed on the substrate; a trench gate group including a first trench gate and a plurality of second trench gates, the first trench gate extending from a surface of the epitaxial layer away from the substrate into the epitaxial layer, and the first trench gate extending along a first direction in the plane of the epitaxial layer; the plurality of second trench gates being spaced apart along the first direction; the orthographic projection of the second trench gates onto the substrate being within the orthographic projection range of the first trench gate onto the substrate; the top of the second trench gate contacting the bottom of the first trench gate; and the gate layer in the second trench gate being connected to the gate layer in the first trench gate; and a plurality of shielding regions, each shielding region encompassing the bottom and all sidewalls of the second trench gate and extending towards the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench gate, and the plurality of shielding regions being spaced apart. The shielding region has a three-dimensional structure, which can not only reduce the electric field stress of the trench gate oxide, but also reduce the cell size of the MOSFET and increase the current density of the MOSFET.
[0006] Further, in the direction in which the substrate and the epitaxial layer are stacked, the second trench gate extends into the substrate; or, a buffer layer is provided between the substrate and the epitaxial layer, and in the direction in which the substrate and the epitaxial layer are stacked, the second trench gate extends into the buffer layer or into the substrate.
[0007] Furthermore, the second trench gate includes a plurality of interconnected trench gate portions, which are arranged sequentially in the direction of the epitaxial layer toward the substrate, and their widths decrease sequentially.
[0008] Furthermore, the thickness of the shielding area covering the sidewall portion of the first trench gate is consistent with the thickness of the shielding area enclosing the sidewall portion of the second trench gate, and the thickness is 0.1-1 μm, while the thickness of the shielding area enclosing the bottom of the second trench gate is 0.5-2 μm.
[0009] Furthermore, the doping concentration of the shielding region is 1×10⁻⁶. 16 cm -3 -1×10 19 cm -3 .
[0010] Furthermore, it includes a plurality of trench gate groups, wherein the first trench gates in the plurality of trench gate groups are arranged sequentially along a second direction in the plane where the epitaxial layer is located, the second direction intersects the first direction, and in the second direction, adjacent two second trench gates are arranged in the same row or staggered.
[0011] Further, the system includes multiple trench gate groups, wherein the first trench gates in the multiple trench gate groups are arranged sequentially along a second direction in the plane of the epitaxial layer, the second direction intersecting the first direction. The N+ region and P+ region in the epitaxial layer extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer. The top of the P-well region in the epitaxial layer contacts the bottom of the N+ region and the bottom of the P+ region. The first trench gates penetrate the N+ region and the P-well region. The P+ regions are spaced apart along the first direction and located between two adjacent first trench gates, and the N+ regions are located around the P+ regions. Alternatively, the P+ regions extend along the first direction and are located between two adjacent first trench gates, and the N+ regions are located on both sides of the P+ regions.
[0012] Further, it includes: a plurality of trench gate groups, wherein the first trench gates in the plurality of trench gate groups are arranged sequentially along a second direction on the plane where the epitaxial layer is located, and the second direction intersects with the first direction; a plurality of third trench gates extending along the second direction and arranged sequentially along the first direction, wherein the third trench gates extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer, wherein the orthographic projection of the second trench gate on the substrate is located within the orthographic projection range of the intersection area of the first trench gate and the third trench gate on the substrate, and each of the shielding areas further covers the sidewall of the third trench gate, or, the orthographic projection of the second trench gate on the substrate is located between the orthographic projections of two adjacent third trench gates on the substrate, and each of the shielding areas is located between two adjacent third trench gates.
[0013] Furthermore, the N+ and P+ regions in the epitaxial layer extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer. The top of the P-well region in the epitaxial layer contacts the bottom of the N+ region and the bottom of the P+ region. The first trench gate and the third trench gate both penetrate the N+ region and the P-well region. The P+ region is located in the area enclosed by the first trench gate and the third trench gate, and the N+ region is located around the P+ region.
[0014] Furthermore, the third trench gate and the first trench gate define a plurality of cells, the shape of which includes square, hexagon, octagon or circle.
[0015] In another aspect of the present invention, a method for fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed. The method includes: forming an epitaxial layer on a substrate; forming a trench gate group and a plurality of shielding regions in the epitaxial layer. The trench gate group includes a first trench gate and a plurality of second trench gates. The first trench gate extends from a surface of the epitaxial layer away from the substrate into the epitaxial layer, and the first trench gate extends along a first direction in the plane of the epitaxial layer. The plurality of second trench gates are spaced apart along the first direction. The orthographic projection of the second trench gates onto the substrate is within the orthographic projection range of the first trench gate onto the substrate. The top of the second trench gate contacts the bottom of the first trench gate, and the gate layer in the second trench gate is connected to the gate layer in the first trench gate. Each shielding region wraps around the bottom and all sidewalls of the second trench gate and extends towards the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench gate. The plurality of shielding regions are spaced apart. The shielding regions formed by this method have a three-dimensional structure, which can not only reduce the voltage field stress of the trench gate oxide field but also reduce the cell size of the MOSFET and increase the current density of the MOSFET.
[0016] Further, forming a trench gate group and a plurality of shielding regions in the epitaxial layer includes: forming a first trench extending from a surface of the epitaxial layer away from the substrate into the epitaxial layer, and the first trench extending along a first direction; forming a plurality of second trenches in the first trench, the plurality of second trenches being spaced apart along the first direction; forming a plurality of shielding regions, each shielding region enclosing the bottom and all sidewalls of a second trench and extending toward a surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench; forming a gate oxide layer on the sidewalls and bottom of the first trench and the second trench; forming a gate layer in the first trench and the second trench, the gate layer contacting the gate oxide layer to form the first trench gate and the second trench gate, thereby forming the trench gate group. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A top view schematic diagram of a MOSFET according to an embodiment of the present invention is shown;
[0019] Figure 2 Showing MOSFET along Figure 1 Schematic diagram of the structure at section A-A';
[0020] Figure 3 Showing MOSFET along Figure 1 Schematic diagram of the structure at section B-B';
[0021] Figure 4 Showing MOSFET along Figure 1 Schematic diagram of the structure at section C-C';
[0022] Figure 5 Showing MOSFET along Figure 1 Schematic diagram of the structure at section D-D';
[0023] Figure 6 A schematic diagram of a MOSFET according to another embodiment of the present invention is shown;
[0024] Figure 7 A top view schematic diagram of a MOSFET according to another embodiment of the present invention is shown;
[0025] Figure 8A top view schematic diagram of a MOSFET according to another embodiment of the present invention is shown;
[0026] Figure 9 A top view schematic diagram of a MOSFET according to another embodiment of the present invention is shown;
[0027] Figure 10 A top view schematic diagram of a MOSFET according to another embodiment of the present invention is shown;
[0028] Figure 11 A schematic flowchart of a MOSFET fabrication method according to an embodiment of the present invention is shown;
[0029] Figure 12 A partial flowchart of a MOSFET fabrication method according to an embodiment of the present invention is shown.
[0030] Figure label:
[0031] 100: Substrate; 200: Epitaxial layer; 210: P-well region; 220: N+ region; 230: P+ region; 300: Trench gate group; 310: First trench gate; 320: Second trench gate; 321A / 321B: Trench gate portion; 10: Gate oxide layer; 20: Gate layer; 400: Shielding region; 500: Source; 600: Interlayer dielectric layer; 700: Drain; 800: Buffer layer; 900: Third trench gate; D1: First direction; D2: Second direction; D3: Third direction. Detailed Implementation
[0032] The embodiments of the present invention are described in detail below. The embodiments described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Where specific techniques or conditions are not specified in the embodiments, they shall be performed in accordance with the techniques or conditions described in the literature in the art or in accordance with the product manual.
[0033] In one aspect of the invention, a metal-oxide-semiconductor field-effect transistor is provided. In some embodiments of the invention, combined with... Figures 1-5 The metal-oxide-semiconductor field-effect transistor includes a substrate 100, an epitaxial layer 200, a trench gate group 300, and a plurality of shielding regions 400. The epitaxial layer 200 is disposed on the substrate 100, and the trench gate group 300 includes a first trench gate 310 and a plurality of second trench gates 320. The first trench gate 310 extends from a surface of the epitaxial layer 200 away from the substrate 100 into the epitaxial layer 200 (e.g., ...). Figure 2As shown), the first trench gate 310 extends along the first direction D1 in the plane where the epitaxial layer 200 is located, and a plurality of second trench gates 320 are arranged at intervals along the first direction D1. The orthographic projection of the second trench gates 320 on the substrate 100 is located within the orthographic projection range of the first trench gate 310 on the substrate 100. The top of the second trench gate 320 is in contact with the bottom of the first trench gate 310, and the gate layer 20 in the second trench gate 320 is connected to the gate layer 20 in the first trench gate 310 (as shown). Figure 2 As shown), each shielding zone 400 encloses the bottom and all sidewalls of the second trench grid 320 (as shown). Figure 2 and Figure 4 As shown), and extends towards the surface of the epitaxial layer 200 away from the substrate 100 to cover the sidewalls of the first trench gate 310 (as shown). Figure 2 As shown), and multiple shielding zones are arranged at 400 intervals.
[0034] Since the second trench gates 320 are arranged at intervals along the first direction D1, the shielding area 400 can cover the entire sidewall of the second trench gates 320, such as Figure 2 As shown, the shielding area 400 covers the sidewall of the second trench grid 320 in the second direction D2, and as... Figure 4 As shown, the shielding area 400 also covers the sidewall of the second trench gate 320 in the first direction D1, wherein the second direction D2 is the direction on the plane where the epitaxial layer 200 is located that intersects with the first direction D1, and more specifically, the second direction D2 is perpendicular to the first direction D1.
[0035] Each shielding region 400 encloses the bottom and all sidewalls of the second trench gate 320 and extends toward the surface of the epitaxial layer 200 away from the substrate 100 to cover the sidewalls of the first trench gate 310 (e.g., Figure 1 and Figure 2 (As shown). This invention obtains a shielding region with a three-dimensional structure by setting a second trench gate arranged at intervals below the first trench gate. On the one hand, this shielding region can reduce the gate oxide electric field stress in the trench gate and improve the long-term reliability of the MOSFET. On the other hand, compared with the current two-dimensional shielding structure, this invention forms a shielding region in the three-dimensional direction (i.e., the first direction D1), which can significantly reduce the size of the MOSFET cell in the two-dimensional direction, thereby increasing the current density of the MOSFET. Furthermore, the shielding region around the second trench gate is completely exhausted when the MOSFET is in the blocking state, so the doping concentration of the epitaxial layer can be significantly increased, the JFET region resistance can be reduced, and the current density of the MOSFET can be increased.
[0036] Multiple shielding zones are arranged at 400 intervals, such as Figure 1 As shown, multiple shielding areas are arranged at intervals in the first direction to ensure the conduction of the MOSFET.
[0037] It should be noted that the top of the second trench gate 320 is the end of the second trench gate 320 away from the substrate 100, the bottom of the first trench gate 310 is the end of the first trench gate 310 close to the substrate 100, and the bottom of the second trench gate 320 is the end of the second trench gate 320 close to the substrate 100.
[0038] In some embodiments of the present invention, reference is made to Figure 2 The first trench gate 310 includes a gate oxide layer 10 disposed on the inner wall and bottom of the first trench and a gate layer 20 filling the middle of the first trench and contacting the gate oxide layer 10. The second trench gate 320 includes a gate oxide layer 10 disposed on the inner wall and bottom of the second trench and a gate layer 20 filling the middle of the second trench and contacting the gate oxide layer 10, and the gate layer 20 of the second trench gate 320 is connected to the gate layer 20 of the first trench gate 310. The first trench is the trench used to form the first trench gate, and the second trench is the trench used to form the second trench gate. The gate layer material may include polysilicon, and the thickness of the gate oxide layer 10 can be [missing information].
[0039] Multiple second trench gates 320 are arranged at intervals along the first direction D1. Preferably, the distance between two adjacent second trench gates 320 is equal to improve the stability of the MOSFET. The specific distance between two adjacent second trench gates is not particularly limited, and those skilled in the art can design it according to specific circumstances. For example, if the doping concentration of the epitaxial layer is high, the distance between two adjacent second trench gates can be relatively smaller.
[0040] The second trench gates 320 are spaced apart along the first direction D1, and the orthographic projection of the second trench gates 320 onto the substrate 100 lies within the orthographic projection range of the first trench gates 310 onto the substrate 100. Therefore, in the second direction D2, the width of the second trench gates is equal to or less than the width of the first trench gates. The width of the first trench gate can be 0.3-2 μm, and the specific width of the second trench gates is not particularly limited and can be designed according to specific circumstances. The length of the second trench gates in the first direction is also not particularly limited. Preferably, the length and width of the second trench gates can be equal, that is, the orthographic projection of the second trench gates onto the substrate is a square.
[0041] In some embodiments of the present invention, the depth of the first trench gate 310 can be 0.4-2 μm. The depth of the second trench gate is not particularly limited; for example, in the direction in which the substrate 100 and the epitaxial layer 200 are stacked, i.e., in the third direction D3, the second trench gate can extend into the substrate 100 (this case is not shown in the figures). When a buffer layer 800 is provided between the substrate 100 and the epitaxial layer 200 (e.g.... Figure 2As shown in the figure, on the third-direction D3, the second trench gate can extend into the buffer layer 800, or the second trench gate can extend through the buffer layer 800 into the substrate 100 (this case is not shown in the figure). The greater the depth of the second trench gate, the smaller the JFET region resistance, which improves the MOSFET current density and parasitic diode capability. The thickness of the buffer layer 800 can be 0.5-3 μm, and the doping concentration is 1×10⁻⁶. 18 cm -3 -1×10 19 cm -3 .
[0042] In some embodiments of the invention, the widths of the various portions of the second trench gate on the third direction D3 may be equal. Alternatively, in other embodiments of the invention, reference is made to... Figure 6 The second trench gate 320 includes multiple interconnected trench gate portions (321A and 321B as shown in the figure). These trench gate portions are arranged sequentially in the direction from the epitaxial layer 200 toward the substrate 100, and their widths decrease sequentially. For example, the width of the lower trench gate portion 321B is smaller than the width of the upper trench gate portion 321A, meaning the second trench gate is composed of a multi-level trench gate. The second trench gate composed of multiple trench gate portions can extend into the buffer layer or extend through the buffer layer into the substrate. The second trench gate is composed of a gate oxide layer disposed on the inner wall and bottom of the second trench gate and a gate layer filling the middle of the second trench and contacting the gate oxide layer. Therefore, each trench gate portion is also composed of a gate oxide layer and a gate layer, and the gate layers in each trench gate portion are interconnected.
[0043] In some embodiments of the present invention, reference is made to Figure 2 The thickness d1 of the portion of the shielding region 400 covering the sidewall of the first trench gate 310 is consistent with the thickness d2 of the portion of the shielding region 400 covering the sidewall of the second trench gate 320. d1 and d2 can be 0.1-1 μm, which reduces the gate oxide electric field stress and ensures a suitable length for the conductive region while preventing the shielding region from breaking. The thickness d3 of the shielding region 400 covering the bottom of the second trench gate 320 can be 0.5-2 μm, effectively reducing the gate oxide electric field stress. The length of the shielding region in the first direction can be determined based on the length of the second trench gate and the thickness of the shielding region covering the sidewall of the second trench gate.
[0044] In some embodiments of the present invention, the doping concentration of the shielding region 400 can be 1×10⁻⁶. 16 cm -3 -1×10 19 cm -3 This shielding region can reduce the gate oxide electric field stress in three dimensions. When the MOSFET is in the blocking state, this shielding region and the epitaxial layer are completely depleted, which can increase the epitaxial layer doping concentration to 1×10⁻⁶. 16cm -3 -5×10 17 cm -3 This increases the current density of the MOSFET. The substrate can be an N-type silicon carbide substrate, and the shielding area can be a P-type shielding area.
[0045] In some embodiments of the present invention, reference is made to Figure 1 The metal-oxide-semiconductor field-effect transistor includes multiple trench gate groups 300. First trench gates 310 in the multiple trench gate groups 300 are arranged sequentially along a second direction D2. In the second direction D2, adjacent second trench gates 320 are arranged in the same row (e.g., ...). Figure 1 (as shown) or staggered arrangement (such as) Figure 7 (As shown).
[0046] In some embodiments of the present invention, reference is made to Figure 3 The N+ region 220 and P+ region 230 in the epitaxial layer 200 extend from the surface of the epitaxial layer 200 away from the substrate 100 into the epitaxial layer 200. The top of the P-well region 210 in the epitaxial layer 200 contacts the bottom of the N+ region 220 and the bottom of the P+ region 230. The first trench gate 310 penetrates the N+ region 220 and the P-well region 210. (Reference) Figure 1 and Figure 7 The P+ regions 230 are arranged at intervals along the first direction D1 and located between two adjacent first trench gates 310, and the N+ regions 220 are located around the P+ regions 230. That is, in the second direction D2, the P+ regions 230 can be arranged in the same row as the second trench gates 320 (not shown in the figure), or the second trench gates 320 can be located between two adjacent rows of P+ regions 230 (e.g., Figure 1 (as shown), or, some of the second trench gates 320 are arranged in the same row as the P+ region, and some of the second trench gates 320 are located between two adjacent rows of P+ regions (as shown). Figure 7 (As shown). Or, refer to Figure 8 The P+ region 230 extends along the first direction D1 and is located between two adjacent first trench gates 310, while the N+ region 220 is located on both sides of the P+ region 230. Because the three-dimensional shielding region reduces the size of the MOSFET cell in the two-dimensional direction, it increases the area ratio of the P+ region, thereby improving the parasitic diode current capability. The current capability of the parasitic diode can be controlled by adjusting the area ratio of the P+ and N+ regions. The junction depth of the P-well region can be 0.2-1 μm, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 -1×10 18 cm -3 The junction depth of the N+ region can be 0.1-0.4 μm, and the doping concentration is 5 × 10⁻⁶. 18 cm -3 -5×10 20 cm -3The junction depth of the P+ region can be 0.1-1.5 μm, and the doping concentration is 5 × 10⁻⁶. 18 cm -3 -5×10 20 cm -3 .
[0047] In other embodiments of the invention, reference is made to... Figure 9 and Figure 10 The metal-oxide-semiconductor field-effect transistor includes multiple trench gate groups 300 and multiple third trench gates 900. First trench gates 310 in the multiple trench gate groups 300 are arranged sequentially along a second direction D2. Multiple third trench gates 900 extend along the second direction D2 and are arranged sequentially along a first direction D1. The third trench gates 900 extend from the surface of the epitaxial layer 200 away from the substrate 100 into the epitaxial layer 200 (a cross-sectional view of the third trench gate is not shown in the figure). The third trench gates 900 intersect with the first trench gates 310. The orthographic projection of the second trench gate 320 onto the substrate can be located within the orthographic projection range of the intersection region of the first trench gate 310 and the third trench gate 900 onto the substrate. Each shielding region further covers the sidewalls of the third trench gate 900 (e.g., Figure 9 (As shown). Alternatively, the orthographic projection of the second trench gate 320 onto the substrate lies between the orthographic projections of two adjacent third trench gates 900 onto the substrate, and each shielding region 400 lies between two adjacent third trench gates 900 (as shown). Figure 10 (As shown). The third trench gate 900 and the first trench gate 310 define multiple cells, the shape of which may include squares, hexagons, octagons or circles.
[0048] In this embodiment, the N+ region 220 and P+ region 230 in the epitaxial layer extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer. The top of the P-well region 210 in the epitaxial layer contacts the bottom of the N+ region 220 and the bottom of the P+ region 230. The first trench gate 310 and the third trench gate 900 both penetrate the N+ region 220 and the P-well region 210 (a cross-sectional view of the third trench gate is not shown in the figure). The P+ region 230 is located within the area enclosed by the first trench gate 310 and the third trench gate 900, and the N+ region 220 is located around the P+ region 230 (e.g., ...). Figure 9 and Figure 10 (As shown).
[0049] refer to Figure 2The metal-oxide-semiconductor field-effect transistor further includes an interlayer dielectric layer 600, a source 500, and a drain 700. The interlayer dielectric layer 600 is located on the side of the first trench gate 310 away from the substrate, and its thickness can be 0.3-0.8 μm. The source 500 covers the interlayer dielectric layer 600 and the P+ region 230 and N+ region 220. The interlayer dielectric layer 600 has a via (not shown) connecting the source 500 and the gate layer 20. The source 500 forms an ohmic contact with the P+ region 230 and N+ region 220. The source 500 may include a nickel layer forming an ohmic contact with the P+ region 230 and N+ region 220, and an aluminum layer located on the side of the nickel layer away from the substrate. The thickness of the nickel layer can be [missing information]. The thickness of the aluminum layer can be 1-6 μm. The drain 700 is located on the side of the substrate 100 away from the epitaxial layer 200, and the drain material can include Ti, Ni, and Ag. Multiple shielding regions are connected in parallel to the source.
[0050] It should be noted that, for the purpose of clearly illustrating the positional relationship between the first trench grid, the shielding area, the P+ area, and the N+ area, Figure 1 , Figures 7-10 The interlayer dielectric layer and source electrode located above the epitaxial layer are not shown.
[0051] In another aspect, the present invention provides a method for fabricating a metal-oxide-semiconductor (MOS) field-effect transistor (FET). The MOS FET fabricated by this method can be the MOS FET described above. Therefore, the MOS FET fabricated by this method can have the same characteristics and beneficial effects as the MOS FET described above, which will not be repeated here.
[0052] In some embodiments of the present invention, reference is made to Figure 11 The method includes:
[0053] S100: An epitaxial layer is formed on the substrate.
[0054] In this step, an epitaxial layer is formed on the substrate. The substrate can be an N-type silicon carbide substrate formed by in-situ doping, with nitrogen as the dopant element, a thickness of 80-350 μm, and a doping concentration of 1×10⁻⁶. 18 cm -3 -5×10 19 cm -3 .
[0055] There are no particular restrictions on the formation method of the epitaxial layer. For example, a homoepitaxial growth process can be used to form the epitaxial layer, with nitrogen as the dopant element, a thickness of 5-120 μm, and a doping concentration of 2 × 10⁻⁶. 14 cm -3 -3×10 16cm -3 .
[0056] In this step, a buffer layer can also be pre-formed on the substrate before forming the epitaxial layer. There are no particular restrictions on the formation method of the buffer layer; for example, an in-situ doping process can be used to form the buffer layer, with nitrogen as the dopant element, a thickness of 0.5-3 μm, and a doping concentration of 1 × 10⁻⁶. 18 cm -3 -1×10 19 cm -3 .
[0057] S200: Trench gate arrays and multiple shielding areas are formed in the epitaxial layer.
[0058] In this step, a trench gate group and multiple shielding regions are formed in the epitaxial layer. The trench gate group includes a first trench gate and multiple second trench gates. The first trench gate extends from the surface of the epitaxial layer away from the substrate into the epitaxial layer, and extends along a first direction in the plane of the epitaxial layer. The multiple second trench gates are spaced apart along the first direction. The orthographic projection of the second trench gates onto the substrate is within the orthographic projection range of the first trench gates onto the substrate. The top of the second trench gate contacts the bottom of the first trench gate, and the gate layer in the second trench gate is connected to the gate layer in the first trench gate. Each shielding region wraps around the bottom and all sidewalls of the second trench gate and extends towards the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench gate. The multiple shielding regions are spaced apart. Thus, the resulting shielding region has a three-dimensional structure. On the one hand, this shielding region can reduce the gate oxide electric field stress in the trench gate and improve the long-term reliability of the MOSFET. On the other hand, compared with the current two-dimensional shielding structure, the three-dimensional shielding region of the present invention can significantly reduce the size of the MOSFET cell in the two-dimensional direction, thereby increasing the current density of the MOSFET. Furthermore, the shielding region around the second trench gate is completely exhausted when the MOSFET is in the blocking state, thus significantly increasing the doping concentration of the epitaxial layer, reducing the resistance of the JFET region, and thereby increasing the current density of the MOSFET.
[0059] Before forming the trench gate assembly and multiple shielding regions in the epitaxial layer, this step also includes:
[0060] A P-well region is formed in the epitaxial layer. The specific process for forming the P-well region is not particularly limited; for example, a P-well region can be formed using a 500°C high-temperature ion implantation process, with a junction depth of 0.2-1 μm and a doping concentration of 1 × 10⁻⁶. 17 cm -3 -1×10 18 cm -3 The doping element is aluminum to form the channel region;
[0061] An N+ region is formed in the epitaxial layer, located on the side of the P-well region away from the substrate, with the bottom of the N+ region contacting the top of the P-well region. The specific process for forming the N+ region is not particularly limited; for example, it can be formed using a 500°C high-temperature ion implantation process, with a junction depth of 0.1-0.4 μm and a doping concentration of 5 × 10⁻⁶. 18 cm -3 -5×10 20 cm -3 The doping element is nitrogen;
[0062] A P+ region is formed in the epitaxial layer, located on the side of the P-well region away from the substrate, with the bottom of the P+ region contacting the top of the P-well region. The P+ regions are spaced apart from the N+ regions in a first direction, or the P+ regions extend along the first direction, with N+ regions located on either side of the P+ regions. The specific process for forming the P+ regions is not particularly limited; for example, the P+ regions can be formed using a 500°C high-temperature ion implantation process, with a junction depth of 0.1-1.5 μm and a doping concentration of 5 × 10⁻⁶. 18 cm -3 -5×10 20 cm -3 The doping element is aluminum. During the formation of the N+ and P+ regions, photolithography can be used to selectively cover a portion of the epitaxial layer surface with photoresist to form the N+ and P+ regions via ion implantation.
[0063] In this step, refer to Figure 12 The formation of trench grids and multiple shielding regions in the epitaxial layer includes:
[0064] S210: Formation of the first trench.
[0065] In this step, a first trench is formed. The first trench extends from the surface of the epitaxial layer away from the substrate into the epitaxial layer, penetrating both the N+ region and the P-well region, and extending along a first direction. The specific process for forming the first trench is not particularly limited; for example, the first trench can be formed in the epitaxial layer by plasma etching. The width of the first trench can be 0.3-2 μm, and the depth of the first trench can be 0.4-2 μm.
[0066] This step can form multiple first trenches extending along a first direction and arranged sequentially along a second direction in the epitaxial layer, so as to subsequently form multiple trench gate groups. The second direction is the direction on the plane where the epitaxial layer is located that intersects with the first direction; specifically, the second direction can be perpendicular to the first direction.
[0067] This step may also include forming multiple third trenches extending along the second direction and arranged sequentially along the first direction during the formation of the first trench, so as to subsequently form a third trench gate, wherein the third trench gate and the first trench gate define multiple cells. The width and depth of the third trench can be the same as the width and depth of the first trench, respectively. The specific process for forming the third trench is not particularly limited; for example, the third trench can be formed in the epitaxial layer by plasma etching.
[0068] S220: Multiple second trenches are formed in the first trench.
[0069] In this step, a plurality of second trenches are formed in the first trench, and the plurality of second trenches are spaced apart along a first direction. The width of the second trenches can be equal to or less than the width of the first trench, and the depth of the second trenches is not particularly limited. For example, the second trenches can extend into the substrate, or, when a buffer layer is provided between the substrate and the epitaxial layer, the second trenches can extend into the buffer layer or extend through the buffer layer into the substrate. This is beneficial for further reducing the JFET region resistance and increasing the current density of the MOSFET.
[0070] The width of each portion of the second trench in the third direction (i.e., the direction in which the substrate and the epitaxial layer are stacked) can be the same. Alternatively, the second trench can include multiple interconnected trench portions, which are sequentially connected in the direction from the epitaxial layer toward the substrate, and their widths decrease sequentially, thus forming a multi-level trench. The second trench formed by multiple trench portions can extend into the buffer layer or extend through the buffer layer into the substrate.
[0071] The specific process for forming the second trench is not particularly limited; for example, multiple second trenches can be formed in the first trench by plasma etching.
[0072] In other embodiments of the present invention, a plurality of third trenches are formed in the epitaxial layer. In this case, the second trench may be located below the intersection region of the first trench and the third trench, or the second trench may be located between two adjacent third trenches.
[0073] S230: Forms multiple shielding zones.
[0074] In this step, multiple shielding regions are formed. Each shielding region covers the bottom and all sidewalls of the second trench and extends toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench. Since the second trenches are spaced apart along the first direction, the shielding regions can cover the sidewalls of the second trenches along the second direction as well as the sidewalls along the first direction to form a three-dimensional shielding region.
[0075] There are no particular restrictions on the specific process for forming the shielding region. For example, the shielding region can be formed by a 500°C high-temperature ion implantation process with a doping concentration of 1×10⁻⁶. 16 cm -3-1×10 19 cm -3 The doping element is aluminum. This reduces the electric field stress of the gate oxide layer in three dimensions. When the MOSFET is in the off state, this shielding region and the epitaxial layer are completely depleted, allowing the epitaxial layer doping concentration to be increased to 1×10⁻⁶. 16 cm -3 -5×10 17 cm -3 This increases the current density of the MOSFET.
[0076] Since each shielding region covers the bottom and all sidewalls of the second trench and extends toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench, the region where the epitaxial layer is ion implanted covers the second trench, and the width of this region is greater than the width of the first trench.
[0077] In this step, high-temperature annealing at 1600℃-1900℃ can be performed to activate the doped impurities in the P-well region, P+ region, N+ region, and shielding region and repair the lattice.
[0078] In some other embodiments of the present invention, a plurality of third trenches are formed in the epitaxial layer, and the second trench may be located below the area where the first trench and the third trench intersect. In this case, each shielding area further covers the sidewall of the third trench. Alternatively, the second trench may be located between two adjacent third trenches. In this case, each shielding area may be located between two adjacent third trenches.
[0079] S240: A gate oxide layer is formed on the sidewalls and bottom of the first and second trenches.
[0080] In this step, a gate oxide layer is formed on the sidewalls and bottom of the first and second trenches. The specific formation process of the gate oxide layer is not particularly limited; for example, it can be formed in the first and second trenches using thermal oxidation. Thick gate oxide layer.
[0081] This step may also include forming a gate oxide layer on the sidewalls and bottom of the third trench to facilitate the subsequent formation of the third trench gate.
[0082] S250: A gate layer is formed in the first trench and the second trench.
[0083] In this step, a gate layer is formed in the first trench and the second trench, and the gate layer contacts the gate oxide layer to form a first trench gate and a second trench gate, thereby forming a trench gate group. The specific process for forming the gate layer is not particularly limited; for example, polysilicon can be deposited on the gate oxide layer using low-pressure chemical vapor deposition to form a polysilicon gate.
[0084] This step may also include forming a gate layer in the third trench to form a third trench gate.
[0085] The method also includes depositing a 0.3-0.8 μm thick oxide layer on a polysilicon gate using plasma chemical vapor deposition to form an interlayer dielectric layer, and forming gate source contact holes in the interlayer dielectric layer through patterning.
[0086] Sputtering on interlayer dielectric layer and epitaxial layer A thick nickel layer is annealed at 900-1100℃ to form an ohmic contact between the nickel layer and the P+ and N+ regions. A 1-6μm thick aluminum layer is deposited on the nickel layer to form the source electrode.
[0087] Metals Ti, Ni, and Ag are sputtered sequentially on the side of the substrate away from the epitaxial layer to form a drain.
[0088] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0089] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0090] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A metal oxide semiconductor field effect transistor, characterized by, include: Substrate; An epitaxial layer, wherein the epitaxial layer is disposed on the substrate; A trench gate array, comprising a first trench gate and a plurality of second trench gates, wherein the first trench gate extends from a surface of the epitaxial layer away from the substrate into the epitaxial layer, and the first trench gate extends along a first direction in the plane of the epitaxial layer; the plurality of second trench gates are spaced apart along the first direction; the orthographic projection of the second trench gates on the substrate is located within the orthographic projection range of the first trench gates on the substrate; the top of the second trench gates contacts the bottom of the first trench gates; and the gate layer in the second trench gates is connected to the gate layer in the first trench gates. Multiple shielding regions, each shielding region enclosing the bottom and all sidewalls of the second trench gate and extending toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench gate, and the multiple shielding regions are arranged at intervals.
2. The metal oxide semiconductor field effect transistor of claim 1, wherein, In the direction in which the substrate and the epitaxial layer are stacked, the second trench gate extends into the substrate; or, A buffer layer is disposed between the substrate and the epitaxial layer, and the second trench gate extends into the buffer layer or into the substrate in the direction in which the substrate and the epitaxial layer are stacked.
3. The metal-oxide-semiconductor field-effect transistor according to claim 1 or 2, characterized in that, The second trench gate includes a plurality of interconnected trench gate portions, which are arranged sequentially in the direction of the epitaxial layer toward the substrate, and their widths decrease sequentially.
4. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The thickness of the shielding area covering the sidewall portion of the first trench gate is the same as the thickness of the shielding area enclosing the sidewall portion of the second trench gate, and the thickness is 0.1-1 μm. The thickness of the shielding area enclosing the bottom of the second trench gate is 0.5-2 μm.
5. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The doping concentration of the shielding region is 1×10⁻⁶. 16 cm -3 -1×10 19 cm -3 .
6. The MOSFET of claim 1, wherein: It includes multiple trench gate groups, wherein the first trench gates in the multiple trench gate groups are arranged sequentially along a second direction in the plane where the epitaxial layer is located, the second direction intersects with the first direction, and in the second direction, two adjacent second trench gates are arranged in the same row or staggered.
7. The MOSFET of claim 1, wherein: The system includes multiple trench gate groups, wherein the first trench gates in the multiple trench gate groups are arranged sequentially along a second direction in the plane of the epitaxial layer, and the second direction intersects the first direction. The N+ and P+ regions in the epitaxial layer extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer. The top of the P-well region in the epitaxial layer contacts the bottom of the N+ region and the bottom of the P+ region. The first trench gate penetrates the N+ region and the P-well region. The P+ regions are spaced apart along the first direction and located between two adjacent first trench gates, and the N+ regions are located around the P+ regions. Alternatively, the P+ regions extend along the first direction and are located between two adjacent first trench gates, and the N+ regions are located on both sides of the P+ regions.
8. The MOSFET of claim 1, wherein: include: The plurality of trench gate groups, wherein the first trench gate in the plurality of trench gate groups is arranged sequentially along a second direction in the plane where the epitaxial layer is located, and the second direction intersects the first direction; A plurality of third trench gates extending along the second direction and arranged sequentially along the first direction, the third trench gates extending from the surface of the epitaxial layer away from the substrate into the epitaxial layer, the orthographic projection of the second trench gate on the substrate being located within the orthographic projection range of the intersection region of the first trench gate and the third trench gate on the substrate, and each of the shielding regions further covering the sidewall of the third trench gate. Alternatively, the orthographic projection of the second trench gate on the substrate is located between the orthographic projections of two adjacent third trench gates on the substrate, and each shielding region is located between two adjacent third trench gates.
9. The MOSFET of claim 8, wherein, The N+ and P+ regions in the epitaxial layer extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer. The top of the P-well region in the epitaxial layer contacts the bottom of the N+ region and the bottom of the P+ region. The first trench gate and the third trench gate both penetrate the N+ region and the P-well region. The P+ region is located in the area enclosed by the first trench gate and the third trench gate, and the N+ region is located around the P+ region.
10. The MOSFET of claim 8, wherein: The third trench grid and the first trench grid define a plurality of cells, the shape of which includes square, hexagonal, octagonal or circular.
11. A method of fabricating a metal oxide semiconductor field effect transistor, characterized by, include: An epitaxial layer is formed on the substrate; A trench gate group and a plurality of shielding regions are formed in the epitaxial layer. The trench gate group includes a first trench gate and a plurality of second trench gates. The first trench gate extends from the surface of the epitaxial layer away from the substrate into the epitaxial layer and extends along a first direction in the plane of the epitaxial layer. The plurality of second trench gates are spaced apart along the first direction. The orthographic projection of the second trench gate on the substrate is within the orthographic projection range of the first trench gate on the substrate. The top of the second trench gate contacts the bottom of the first trench gate, and the gate layer in the second trench gate is connected to the gate layer in the first trench gate. Each shielding region wraps the bottom and all sidewalls of the second trench gate and extends to the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench gate. The plurality of shielding regions are spaced apart.
12. The method of claim 11, wherein, The formation of trench gates and multiple shielding regions in the epitaxial layer includes: A first trench is formed, the first trench extending from the surface of the epitaxial layer away from the substrate into the epitaxial layer, and the first trench extending along the first direction; A plurality of second trenches are formed in the first trench, and the plurality of second trenches are spaced apart along the first direction; Multiple shielding areas are formed, each shielding area enveloping the bottom and all sidewalls of the second trench and extending toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench; A gate oxide layer is formed on the sidewalls and bottom of the first trench and the second trench; A gate layer is formed in the first trench and the second trench, the gate layer being in contact with the gate oxide layer to form the first trench gate and the second trench gate, thereby forming the trench gate group.