Data processing method and device, electronic equipment and storage medium

Abstract

Embodiments of the present disclosure provide a data processing method and device, electronic equipment and storage medium, comprising: obtaining a hardware supported unit vector operation width; obtaining a source address to be aligned and a number of object data to be operated; in response to the width of the object data being greater than or equal to a first threshold, calculating a remainder of the source address to be aligned after aligning the unit vector operation width to obtain a data width of the object data that is not address-aligned, wherein the width of the object data is equal to the product of the unit data width of the object data and the number of the object data, and the width of the address misaligned data is equal to the difference between the unit vector operation width and the remainder; determining the number of the address misaligned data according to the unit data width of the object data and the width of the address misaligned data, determining first mask information based on the number of the address misaligned data and the unit vector operation width; and loading and processing the address misaligned data according to the first mask information, which improves the data processing performance.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a data processing method, apparatus, electronic device, and storage medium. Background Technology

[0002] Modern processor architectures for floating-point computing include scalar computation units and vector computation units. The scalar computation unit can only perform one floating-point calculation at any given time, while the vector computation unit can perform multiple floating-point calculations at any given time. Single Instruction Multiple Data (SIMD) is a technique that uses a single controller to control multiple processors, simultaneously executing the same operation on each data item in a set, thus achieving spatial parallelism. Simply put, one instruction can process multiple data items concurrently. Commonly used SIMD techniques for floating-point computing include instruction sets such as SSE, AVX, AVX2, and AVX512.

[0003] SIMD address alignment means that the starting address of a contiguous memory space accessed by a SIMD instruction must be an integer multiple of the SIMD vector width. SSE, AVX, AVX2, and AVX512 instruction sets support unaligned address access in hardware, but the performance difference between aligned and unaligned address access is significant. Furthermore, in many practical engineering applications, arrays within loops may be unaligned, which can severely impact SIMD performance. Summary of the Invention

[0004] This disclosure provides a data processing method, comprising: obtaining a source address to be aligned and the number of object data to be operated on; in response to the width of the object data being greater than or equal to a first threshold, calculating the remainder after aligning the source address to be aligned with the width of a unit vector operation to obtain the width of the address-misaligned data in the object data, wherein the width of the object data is equal to the product of the unit data width of the object data and the number of object data, and the width of the address-misaligned data is equal to the difference between the unit vector operation width and the remainder; determining the number of address-misaligned data based on the unit data width of the object data and the width of the address-misaligned data; determining first mask information based on the number of address-misaligned data and the unit vector operation width; and loading and processing the address-misaligned data according to the first mask information.

[0005] For example, in at least one embodiment of the present disclosure, after loading and processing address-misaligned data, the method further includes: offsetting the source address by the width of the address-misaligned data to obtain an offset first address; and processing the remaining data in the object data other than the address-misaligned data based on the offset first address.

[0006] For example, at least one embodiment of the present disclosure provides a data processing method in which the remaining data includes address-aligned data, and the remaining data in the object data, excluding address-misaligned data, is processed based on the offset first address, including: processing address-aligned data based on the offset first address.

[0007] For example, at least one embodiment of the present disclosure provides a data processing method in which address-aligned data is processed based on the offset first address, including: calculating the width of the remaining data based on the width of the object data and the width of the address-misaligned data, and determining the number of loop operations for the address-aligned data according to the width of the remaining data and the width of the unit vector operation, wherein the following steps are performed in each loop operation cycle: sequentially loading and processing the address-aligned data according to the width of the unit vector operation.

[0008] For example, in at least one embodiment of the present disclosure, a data processing method is provided, wherein the remaining data further includes tail data. After sequentially loading and processing address-aligned data according to the unit vector operation width, the method further includes: calculating the width of the address-aligned data, wherein the width of the address-aligned data is equal to the product of the number of loop operations and the unit vector operation width; offsetting the width of the address-aligned data by the first address to obtain the offset second address; and processing the tail data based on the offset second address.

[0009] For example, at least one embodiment of this disclosure provides a data processing method in which tail data is processed based on an offset second address, including: calculating the width of the tail data, wherein the width of the tail data is equal to the difference between the width of the remaining data and the width of the data aligned to the address; determining the number of tail data based on the unit data width of the object data and the width of the tail data; determining second mask information based on the number of tail data and the unit vector operation width; and loading and processing the tail data based on the second mask information.

[0010] For example, at least one embodiment of the present disclosure provides a data processing method in which the unit vector operation width includes any one of 16 bytes, 32 bytes, and 64 bytes.

[0011] For example, at least one embodiment of the present disclosure provides a data processing method in which a first threshold is equal to twice the product of the unit vector operation width and the processing coefficient, wherein the processing coefficient includes any one of 2, 3 and 4.

[0012] For example, at least one embodiment of the present disclosure provides a data processing method in which the object data includes any one of integer, single-precision floating-point, and double-precision floating-point types.

[0013] For example, at least one embodiment of the present disclosure provides a data processing method in which the first mask information and the second mask information are binary sequences.

[0014] For example, at least one embodiment of the present disclosure provides a data processing method in which, in response to the first mask information being a binary sequence, the binary sequence includes valid bits and invalid bits, wherein the total number of valid bits is equal to the number of data that are not address-aligned, and the total number of invalid bits is equal to the length of the binary sequence minus the remaining number of valid bits, wherein the length of the binary sequence is obtained by the quotient of the unit vector operation width and the unit data width of the object data.

[0015] For example, at least one embodiment of the present disclosure provides a data processing method in which, in response to the second mask information being a binary sequence, the binary sequence includes valid bits and invalid bits, wherein the total number of valid bits is equal to the number of tail data, and the total number of invalid bits is equal to the length of the binary sequence minus the remaining number of valid bits, wherein the length of the binary sequence is obtained based on the quotient of the unit vector operation width and the unit data width of the object data.

[0016] For example, in at least one embodiment of the present disclosure, a data processing method is provided in which the valid bits are consecutive low bits in a binary sequence and the invalid bits are consecutive high bits in a binary sequence.

[0017] For example, at least one embodiment of the present disclosure provides a data processing method in which valid bits are consecutive high bits in a binary sequence and invalid bits are consecutive low bits in a binary sequence.

[0018] For example, at least one embodiment of this disclosure provides a data processing method in which the remainder is obtained by performing a logical AND gate operation between the source address to be aligned and the width of the unit vector operation.

[0019] For example, at least one embodiment of the present disclosure provides a data processing method, wherein processing at least one of address-misaligned data, address-aligned data, and tail data includes: processing using functions in a database, wherein the database includes any one of a basic linear algebra library, a kernel, and an acceleration library.

[0020] For example, at least one embodiment of this disclosure provides a data processing method in which the function includes a first-level function from a basic linear algebra library.

[0021] Embodiments of this disclosure also provide a data processing apparatus, comprising: a first acquisition module configured to acquire a hardware-supported unit vector operation width; a second acquisition module configured to acquire a source address to be aligned and the number of object data to be operated on; a first calculation module configured to, in response to the width of the object data being greater than or equal to a first threshold, calculate the remainder after aligning the source address to be aligned with the unit vector operation width to obtain the width of the address-misaligned data in the object data, wherein the width of the object data is equal to the product of the unit data width of the object data and the number of object data, and the width of the address-misaligned data is equal to the difference between the unit vector operation width and the remainder; a second calculation module configured to determine the number of address-misaligned data based on the unit data width of the object data and the width of the address-misaligned data, and determine first mask information based on the number of address-misaligned data and the unit vector operation width; and a loading and processing module configured to load and process the address-misaligned data according to the first mask information.

[0022] Embodiments of this disclosure also provide an electronic device, including: a processor; and a memory including one or more computer program instructions; wherein the one or more computer program instructions are executed by the processor to perform the data processing method of any of the above embodiments.

[0023] Embodiments of this disclosure also provide a computer-readable storage medium for non-transitory storage of computer-readable instructions, wherein the data processing methods of any of the above embodiments are implemented when the computer-readable instructions are executed by a processor. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0025] Figure 1 A flowchart illustrating an address misalignment data processing method provided in at least one embodiment of this disclosure;

[0026] Figure 2 For at least one embodiment of this disclosure Figure 1 The flowchart of the remaining data processing method provided based on the above;

[0027] Figure 3 Processing provided for at least one embodiment of this disclosure Figure 2 Flowchart of the method for aligning address data in the remaining data;

[0028] Figure 4 and Figure 5 For at least one embodiment of this disclosure Figure 3 The flowchart of the tail data processing method provided based on the above;

[0029] Figure 6 This is an example of data processing for scal functions provided in at least one embodiment of the present disclosure;

[0030] Figure 7 This is an example of data processing for the iamax function provided in at least one embodiment of the present disclosure;

[0031] Figure 8 A schematic diagram of a data processing apparatus provided in at least one embodiment of this disclosure;

[0032] Figure 9 A schematic diagram of an electronic device provided for at least one embodiment of this disclosure;

[0033] Figure 10 A schematic diagram of a storage medium provided for at least one embodiment of this disclosure; and

[0034] Figure 11 This is a schematic diagram of another electronic device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0036] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0037] Single Instruction Multiple Data (SIMD) is a parallel computing technique that allows multiple data points to be processed simultaneously under a single instruction. This technique is widely used in multimedia, scientific computing, and other applications requiring large amounts of numerical processing. For SIMD to be used effectively, the storage and access methods for data must meet certain conditions, one of which is address alignment.

[0038] SIMD address alignment refers to the requirement that data storage locations in memory must conform to certain rules to enable SIMD instruction sets to efficiently read and process this data. Specifically, address alignment requires that the starting address of the data be a multiple of a certain value, which depends on the hardware platform and the type of SIMD instruction set used. For example, in some implementations, a 128-bit wide SIMD operation might require data to start from a 16-byte boundary, meaning the data's memory address should be a multiple of 16. This can be illustrated by the formula: address = k * w, where address is the starting address of a contiguous memory space, k is an integer, and w is the SIMD vector width (e.g., for the SSE instruction set, which is 128-bit, the vector width w is 128 / 8 = 16 bytes; for the AVX instruction set, which is 256-bit, the vector width w is 256 / 8 = 32 bytes).

[0039] Proper address alignment ensures that data loaded into registers does not cross cache lines or page boundaries, thus avoiding additional performance overhead such as multiple memory accesses or data rearrangement. Incorrect data alignment can lead to performance degradation and even errors on some platforms. For example, while x86's SSE, AVX, AVX2, and AVX512 instruction sets support unaligned address access in hardware, the performance difference between aligned and unaligned address access is significant. Furthermore, in many practical engineering applications, arrays within loops may be unaligned, severely impacting SIMD performance.

[0040] Modern compilers have achieved remarkable advancements in parallel vectorization, automatically replacing C / C++ code with SIMD instructions. In C / C++, the `__attribute__` keyword sets the `aligned` and `packed` attributes. `__attribute__` is a compiler extension that allows developers to specify special attributes for functions, variables, types, etc. The `aligned` attribute specifies the alignment of variables or types, while the `packed` attribute reduces padding between structure members, making the structure as compact as possible. Specifying the alignment of a variable or type tells the compiler to allocate memory for the variable according to the specified address alignment, requiring developers to specify specific compiler attributes. However, in general code vectorization, compilers rarely optimize alignment and seldom perform targeted alignment operations based on SIMD instruction set support.

[0041] The Basic Linear Algebra Subprograms (BLAS) library is a collection of core subprograms for linear algebra, primarily covering vector and matrix operations. It is one of the most fundamental and important mathematical libraries, widely used in scientific and engineering computing. In higher-level languages ​​and libraries, even if the BLAS interface is not used directly, BLAS will still be invoked for implementation.

[0042] Specifically, BLAS is designed with three layers:

[0043] (1) Level 1 BLAS: handles operations between vectors, such as vector addition, scalar multiplication and dot product.

[0044] (2) Level 2 BLAS: Involves matrix and vector operations, including matrix-vector multiplication, solving trigonometric linear equations, etc.

[0045] (3) Level 3 BLAS: handles matrix-matrix operations, such as matrix-matrix multiplication, which is one of the most frequently used operations in many high-performance applications.

[0046] Most functions in Level 1 BLAS (hereinafter referred to as "Level 1 functions") are one-dimensional operations, such as scal, copy, and iamax. Level 1 functions directly manipulate memory data, therefore, memory access speed has a significant impact on performance. However, current methods for handling unaligned SIMD address data only include addition operations for specific SIMD arrays, which suffers from several drawbacks, including limited versatility, inapplicability to other functions (such as scal and iamax functions in Level 1), and narrow coverage.

[0047] To address the technical problems existing in the above-mentioned related technologies, embodiments of this disclosure provide a data processing method, including: obtaining a hardware-supported unit vector operation width; obtaining a source address to be aligned and the number of object data to be operated on; in response to the width of the object data being greater than or equal to a first threshold, calculating the remainder after aligning the source address to be aligned with the unit vector operation width to obtain the width of the address-misaligned data in the object data, wherein the width of the object data is equal to the product of the unit data width of the object data and the number of object data, and the width of the address-misaligned data is equal to the difference between the unit vector operation width and the remainder; determining the number of address-misaligned data based on the unit data width of the object data and the width of the address-misaligned data; determining first mask information based on the number of address-misaligned data and the unit vector operation width; and loading and processing the address-misaligned data according to the first mask information.

[0048] Embodiments of this disclosure also provide a data processing apparatus, electronic device, and storage medium for the above-described data processing method.

[0049] The data processing method provided in this disclosure is applicable to, for example, Level 1 functions in the BLAS library, with wide coverage and strong versatility. Furthermore, by combining with a compiler, address alignment is achieved, memory bandwidth is optimized, and thus processing performance is improved.

[0050] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0051] Figure 1 This is a flowchart illustrating a method for processing address-misaligned data, provided in at least one embodiment of this disclosure. Figure 1 As shown, the data processing method includes the following steps S100 to S140.

[0052] Step S100: Obtain the width of the unit vector operation supported by the hardware.

[0053] Step S110: Obtain the source address to be aligned and the number of object data to be operated on.

[0054] Step S120: In response to the width of the object data being greater than or equal to the first threshold, calculate the remainder after the width of the source address alignment unit vector operation to obtain the width of the address misaligned data in the object data, wherein the width of the object data is equal to the product of the unit data width of the object data and the number of object data, and the width of the address misaligned data is equal to the difference between the unit vector operation width and the remainder.

[0055] Step S130: Determine the number of misaligned data based on the unit data width of the object data and the width of the misaligned data, and determine the first mask information based on the number of misaligned data and the unit vector operation width.

[0056] Step S140: Load and process the address-misaligned data according to the first mask information.

[0057] For step S100, for example, in one possible implementation, the unit vector operation width (byte) is determined based on the processor's performance. Commonly used SIMD technologies for floating-point calculations include instruction sets such as SSE, AVX, AVX2, and AVX512. For example, the maximum supported instruction set can be obtained by reading the processor's identifier (ID). Specifically, for a 128-bit SSE instruction set, the unit vector operation width is 16 bytes; for a 256-bit AVX instruction set, it is 32 bytes; and for a 512-bit AVX instruction set, it is 64 bytes. That is, the unit vector operation width can include any of 16 bytes, 32 bytes, and 64 bytes. However, it should be noted that this unit vector operation width is merely exemplary, and this disclosure does not impose any limitations on it.

[0058] For step S110, for example, in one possible implementation, the source address (Source, src) to be aligned is passed in by the user through programming on the host computer. In addition, the user also passes in the destination address (Destination, dst). For example, the source address src can be 0x6F, and the destination address dst can be 0xFA; this disclosure does not impose any restrictions on this. Besides passing in the source and destination addresses, the user also passes in a certain amount of data (i.e., the object data to be transmitted). For example, the object data to be transmitted passed in by the user includes any one of integer (int), single-precision floating-point (float), and double-precision floating-point (double) types, and the size of the object data to be transmitted is the number of any one of the integer, single-precision floating-point, or double-precision floating-point types passed in by the user (e.g., 1000 double-type data). It should be noted that the object data passed in by the user is of the same type, for example, all int types, or any other type of data; this disclosure does not impose any restrictions on this.

[0059] For step S120, the first threshold is equal to twice the product of the unit vector operation width and the processing coefficient (alpha). The value of alpha is platform-dependent; for example, alpha can be any of 2, 3, or 4, and a suitable alpha value needs to be selected through testing. The width of the object data is equal to the product of the unit data width of the object data and the number of object data items. The unit data width of the object data is the byte length occupied by a single object data item. For example, the unit data width of an int type object data is 4 bytes, the unit data width of a float type object data is 4 bytes, and the unit data width of a double type object data is 8 bytes. It should be noted that when the width of the object data is greater than or equal to this first threshold, it indicates that the amount of data to be processed is large, and the address alignment of the object data has a significant impact on performance; therefore, the data processing method of this disclosure needs to be executed. For example, if the width of a unit vector operation is w=32 bytes and alpha=2, then the first threshold is 128 bytes. If the user inputs 100 double-type data, then the width of the object data is 100*8=800 bytes > 128 bytes. At this time, whether the addresses of the 100 double-type object data are aligned will have a significant impact on the data processing performance, thus requiring the execution of the data processing method disclosed herein.

[0060] Furthermore, it is necessary to calculate the remainder after aligning the source address to be aligned with the unit vector operation width to obtain the width of the misaligned data in the object data. For example, the user-input source address to be aligned is src=0x7FFF0008 (i.e., the starting address of the current object data). The maximum instruction set supported by the hardware is AVX256, which means the unit vector operation width is w=32 bytes. w=32 bytes indicates that the starting address of the object data must be an integer multiple of 32 to be aligned. However, the starting address is not an integer multiple of 32 bytes, so the object data is in an unaligned state. In this case, for example, the remainder rem can be obtained by performing a logical AND operation between the source address to be aligned (0x7FFF0008) and the unit vector operation width (32 bytes). For example, rem=src & (w-1), and the remainder rem=0x8 is calculated. Then, the width of the misaligned data in the object data (i.e., 32-8=24 bytes) can be obtained by calculating the difference between the unit vector operation width (32 bytes) and the remainder (8). Specifically, when the source address src of the object data is 0x7FFF0008, the object data is only aligned when the address is 0x7FFF0020. Therefore, the first 24 bytes of the object data are the width of the misaligned data.

[0061] For step S130, referring to the example in step S120 above, the number of misaligned data is determined based on the unit data width (8 bytes) of the object data (double type) and the width of the misaligned data (24 bytes). That is, the number of misaligned data is 24 / 8 = 3 double type data. Since the unit vector operation width is 32 bytes, meaning the processor loads 32 bytes of data from the data storage address at once in each operation cycle, to successfully load the 24 bytes of misaligned data within one operation cycle without affecting the aligned data after address 0x7FFF0020, the first mask information needs to be determined based on the number of misaligned data and the unit vector operation width. Specifically, the first mask information can be a binary sequence. Since the source address of the object data is 0x7FFF0008, meaning there is no data between addresses 0x7FFF0000 and 0x7FFF0007, the 8 bytes of empty data corresponding to these 8 empty addresses can be combined with the 24 bytes of misaligned data to form the 32 bytes that the processor needs to process within one cycle. Specifically, this binary sequence is calculated as "0111".

[0062] For example, the binary sequence described above includes valid bits and invalid bits. The total number of valid bits is equal to the number of misaligned data bits. The total number of invalid bits is equal to the length of the binary sequence minus the total number of valid bits. The length of the binary sequence is obtained by dividing the width of the unit vector operation by the width of the object data. That is, in "0111", "0" represents an invalid bit and "1" represents a valid bit. The length of the binary sequence is 32 / 8 = 4, the total number of valid bits is 3, and the total number of invalid bits is 4 - 3 = 1.

[0063] For example, in one possible implementation, the valid bits in the above binary sequence are consecutive low-order bits, and the invalid bits are consecutive high-order bits. It should be noted that each address stores one byte of data, and the corresponding data is stored sequentially in ascending order of address. Addresses 0x7FFF0000-0x7FFF0007 store 8 bytes of empty data, and addresses 0x7FFF0008-0x7FFF0019 store 24 bytes of unaligned data. Considering the address order (i.e., increasing from left to right), the corresponding mask binary sequence "0111" is also ordered, meaning the valid bits are consecutive low-order bits, and the invalid bits are consecutive high-order bits.

[0064] For step S140, referring to the example of step S130 above, according to the valid and invalid bit information indicated by the first mask information (i.e., the binary sequence "0111"), the data with misaligned address indicated by the valid bit "1" is loaded into the vector register to prevent data from going out of bounds, and then the misaligned data is processed by, for example, level 1 functions scal and iamax in the BLAS library.

[0065] The data processing method provided in this disclosure can efficiently handle address misalignment in object data and is applicable to any Level 1 function in the BLAS library, for example. It has a wide coverage and strong versatility, optimizes memory bandwidth, and thus improves data processing performance.

[0066] Figure 2 For at least one embodiment of this disclosure Figure 1 The flowchart provides the remaining data processing method based on this. For example... Figure 2 As shown, in Figure 1 After step S140 is shown, Figure 2 It also includes the following steps S150-S160.

[0067] Step S150: Adjust the width of the data that is not aligned with the source address offset address to obtain the first offset address.

[0068] Step S160: Process the remaining data in the object data, excluding the data with misaligned addresses, based on the first address after offset.

[0069] For step S150, referring to the example of step S130 above, after loading and processing the misaligned data, since the object data consists of 100 double-type data and only 3 double-type data are misaligned, there are still 97 double-type data to be processed. Therefore, it is necessary to obtain the first offset address 0x7FFF0020 from the width (24 bytes) of the misaligned data offset from the source address 0x7FFF0008. This first offset address is the starting address of the remaining data.

[0070] For step S160, based on the first address 0x7FFF0020 after the offset, process the remaining 97 double-type data in the object data, excluding the 3 double-type data with misaligned addresses. That is, process the address-aligned data based on the first address after the offset.

[0071] The data processing method provided in at least one embodiment of this disclosure ensures the continuity of data processing by offsetting the source address to process the remaining data after processing the misaligned data.

[0072] Figure 3Processing provided for at least one embodiment of this disclosure Figure 2 A flowchart illustrating the method for aligning address data in the remaining data. (For example...) Figure 3 As shown, after step S160, Figure 3 It also includes the following step S170.

[0073] Step S170: Calculate the width of the remaining data based on the width of the object data and the width of the misaligned data. Determine the number of loop operations for the address-aligned data based on the width of the remaining data and the width of the unit vector operation. In each loop operation cycle, the following steps are performed: Load and process the address-aligned data sequentially according to the width of the unit vector operation.

[0074] For example, in one possible implementation, the remaining data includes address-aligned data. As mentioned above, starting from address 0x7FFF0020, the data stored therein is the address-aligned part of the object data. Therefore, after processing the address-misaligned data, the address-aligned data needs to be processed based on the first offset address (i.e., address 0x7FFF0020).

[0075] For step S170, referring to the example of step S130 above, the width of the remaining data is first calculated based on the width of the object data and the width of the misaligned data. That is, the width of the remaining data is equal to 100*8-3*8=776 bytes. Then, the number of loop operations for the address-aligned data is determined based on the width of the remaining data (776 bytes) and the unit vector operation width (32 bytes). That is, the number of loop operations is equal to 776 / 32=24. This means that for 776 bytes of address-aligned data, it can be processed 24 times continuously according to the unit vector operation width of 32 bytes. In each loop operation cycle, the address-aligned data is loaded and processed sequentially according to the unit vector operation width (32 bytes).

[0076] For example, in one possible implementation, address-aligned data is loaded and processed sequentially in unit vector operation width (32 bytes) within each loop operation cycle, specifically including:

[0077] In the first loop cycle, the data at address 0x7FFF0020-0x7FFF003F (i.e., the first 32 bytes of aligned data) is loaded into the vector register for processing. For example, this data can be processed using the level 1 function scal in the BLAS library. Then, the current address 0x7FFF0020 is offset by 32 bytes to obtain the starting address 0x7FFF0040 of the data corresponding to the next loop cycle. In the second loop cycle, the data at address 0x7FFF0040-0x7FFF005F (i.e., the second 32 bytes of aligned data) is loaded into the vector register for processing. For example, this data can still be processed using the level 1 function scal in the BLAS library, and so on, until the data at address 0x7FFF0300-0x7FFF031F (i.e., the twenty-fourth 32 bytes of aligned data) is loaded and processed in the twenty-fourth loop cycle, thus ending the processing flow of the address-aligned part of the object data.

[0078] Figure 4 and Figure 5 For at least one embodiment of this disclosure Figure 3 The flowchart for the tail data processing method provided is based on this. For example... Figure 4 As shown, in Figure 3 After step S170 shown, Figure 4 It also includes the following step S180.

[0079] Step S180: Calculate the width of the address-aligned data, where the width of the address-aligned data is equal to the product of the number of loop operations and the width of the unit vector operation; offset the first address by the width of the address-aligned data to obtain the offset second address; process the tail data based on the offset second address.

[0080] For example, referring to the example above, the width of the address-aligned data is equal to the product of the number of loop operations 24 and the width of the unit vector operation 32 bytes, which is 768 bytes. Then, the first address 0x7FFF0020 is offset by 768 bytes to obtain the offset second address 0x7FFF0320. After that, the tail data is processed based on the second address 0x7FFF0320.

[0081] like Figure 5 As shown, in Figure 4 After step S180 shown, Figure 5 It also includes the following step S190.

[0082] Step S190: Calculate the width of the tail data, where the width of the tail data is equal to the difference between the width of the remaining data and the width of the address-aligned data; determine the number of tail data based on the unit data width of the object data and the width of the tail data; determine the second mask information based on the number of tail data and the unit vector operation width; load and process the tail data based on the second mask information.

[0083] For example, as in the example above, the width of the tail data is equal to the difference of 8 bytes between the remaining data width of 776 bytes and the address-aligned data width of 768 bytes. The number of tail data is determined based on the unit data width (8 bytes) of the object data (double type) and the width of the tail data (8 bytes), that is, the number of tail data is 8 / 8 = 1 double type data. Since the unit vector operation width is 32 bytes, meaning the processor loads 32 bytes of data from the data storage address at once in each operation cycle, to successfully load the last 8 bytes in one operation cycle, a second mask information needs to be determined based on the number of last data bytes and the unit vector operation width. Specifically, the second mask information can be a binary sequence. Since the starting address of the last data bytes (i.e., the second address after the offset mentioned above) is 0x7FFF0320 and the ending address is 0x7FFF0327, and there is no data at addresses 0x7FFF0328-0x7FFF033F, the 24 bytes of empty data corresponding to these last 24 addresses can be combined with the 8 bytes of last data to form the 32 bytes that the processor needs to process in one cycle. Specifically, this binary sequence is calculated as "1000".

[0084] For example, the binary sequence above includes valid bits and invalid bits. The total number of valid bits is equal to the number of tail data. The total number of invalid bits is equal to the length of the binary sequence minus the total number of valid bits. The length of the binary sequence is obtained by the quotient of the unit vector operation width and the unit data width of the object data. That is, in "1000", "0" is an invalid bit and "1" is a valid bit. The length of the binary sequence is 32 / 8=4, the total number of valid bits is 1, and the total number of invalid bits is 4-1=3.

[0085] For example, in one possible implementation, the valid bits in the above binary sequence are consecutive high-order bits, and the invalid bits are consecutive low-order bits. It should be noted that each address stores one byte of data, and the corresponding data is stored sequentially in ascending order of address. Addresses 0x7FFF0320-0x7FFF0327 store 8 bytes of tail data, and addresses 0x7FFF0328-0x7FFF033F store 24 bytes of empty data. Considering the address order (i.e., increasing from left to right), the corresponding mask binary sequence "1000" is also ordered, meaning the valid bits are consecutive high-order bits, and the invalid bits are consecutive low-order bits.

[0086] Finally, based on the valid and invalid bit information indicated by the second mask information (i.e., the binary sequence "1000"), the tail data indicated by the valid bit "1" is loaded into the vector register to prevent data from going out of bounds. Then, the tail data is processed by functions such as scal and iamax in the BLAS library.

[0087] At least one embodiment of this disclosure loads and processes the unaligned portion, the aligned portion, and the tail portion of the object data separately. This is applicable to any Level 1 function in the BLAS library, with broad coverage and high versatility, thereby improving the processor's data processing performance.

[0088] For example, in one possible implementation, if alpha=2, the unit vector operation width w=32, and the number of object data is 12 double-type data (unit data width is 8 bytes), then the width of the object data is equal to 12*8=96 bytes, and the first threshold is equal to 2*2*32=128 bytes. In this case, when the width of the object data is less than the first threshold, it indicates that the alignment of the data source address has little impact on performance. Therefore, it is unnecessary to consider whether the user-input source address is aligned, and the process directly jumps to the address-aligned data processing flow. That is, in this case, the 96 bytes of data are loaded and processed sequentially according to the unit vector operation width of 32 bytes (i.e., loop count = 3). It should be noted that if the number of object data is 13 double-type data, then the width of the object data is equal to 13*8=104 bytes < 128 bytes. After processing the address-aligned data in 3 loops, there are still 8 bytes of tail data remaining. The processing method for these 8 bytes still refers to the above tail data processing method, that is, using the mask binary sequence "1000" to load and process the remaining 8 bytes of data.

[0089] For example, in one possible implementation, processing at least one of the aforementioned address-misaligned data, address-aligned data, and tail data includes: processing using functions from a database, wherein the database includes any one of a basic linear algebra library, a kernel, and an acceleration library. For example, the functions include first-level functions from the basic linear algebra library such as scal, copy, dot, axpy, and iamax, etc., which are not limited in this disclosure.

[0090] Figure 6 This provides an example of data processing for scal functions, as shown in at least one embodiment of this disclosure. Figure 6 As shown, the main process of this data processing includes processing the unaligned part of the address, the aligned part of the address, and the mantissa part.

[0091] Specifically, the user needs to input data (e.g., the number of object data items, source address, and destination address). Then, the processor information (e.g., processor ID) and the user-input data are obtained. Next, the relationship between the object data width and a first threshold is determined. If the object data width is large (i.e., greater than or equal to the first threshold), the unaligned portion of the address is processed. Then, the aligned portion and the mantissa portion are processed in sequence, and finally, the relevant data is output. If the object data width is small (i.e., less than the first threshold), there is no need to consider whether the data source address is aligned. The operation of processing the aligned portion is performed directly. If there is remaining data, the mantissa portion is processed, and finally, the relevant data is output.

[0092] The following discussion focuses only on the case where the width of the object data is greater than or equal to the first threshold.

[0093] First, for the portion of the address that is not aligned, obtain the remainder of the address alignment vector width (i.e., the width of the unit vector operation mentioned above), then obtain the amount of data to be pre-processed (i.e., the width of the address-inaligned data mentioned above), then obtain the length of the corresponding data type (i.e., the number of address-inaligned data items), and then obtain the mask corresponding to this length. This mask is the first mask information mentioned above (e.g., a binary sequence). Then, load the data from this address according to the mask and process the data. During the data processing, a scal operation is performed, multiplying the loaded data by a constant to obtain new data. The new data is then rewritten to this address according to the mask to end the processing operation. Finally, the address offset ends the non-alignment operation. The specific steps of this non-alignment operation are described above and will not be repeated here.

[0094] Secondly, after processing the unaligned portion, the address alignment operation begins. First, the remaining data width (the difference between the object data width and the unaligned data width) is obtained. Then, the loop count is obtained (derived by dividing the remaining data width by the unit vector operation width). Next, the mantissa is obtained. Then, in each loop cycle, data is sequentially loaded into the vector register and processed using the `scal` function. The specific processing includes multiplying the vector register by a constant to obtain new data, rewriting this new data to the aligned address, offsetting the address, checking if the loop has ended, and finally ending the alignment operation. The specific steps of this alignment operation are detailed above and will not be repeated here.

[0095] Finally, after processing the address alignment, if a mantissa exists, a mantissa operation is required. This involves obtaining the mantissa length (i.e., the number of data items at the end), then obtaining the mask corresponding to that length. This mask is the second mask information mentioned above (e.g., a binary sequence). Data is then loaded from the address based on the mask and processed. During data processing, a scal operation is performed, multiplying the loaded data by a constant to obtain new data. This new data is then rewritten to the address based on the mask to end the processing. Finally, the address is offset to terminate the mantissa operation. The specific steps of this mantissa operation are detailed above and will not be repeated here.

[0096] At least one embodiment of this disclosure is applicable to the first-level function scal in the BLAS library. Tests have shown that, with a step size of 1, the performance is improved by 40% compared to the unoptimized large-scale object data (i.e., the number of object data is greater than 10,000).

[0097] Figure 7 This provides a data processing example for the iamax function, which is one embodiment of this disclosure. Figure 7 As shown, the main process of this data processing includes processing the unaligned part of the address, the aligned part of the address, and the mantissa part.

[0098] Specifically, the user needs to input data (e.g., the number of object data items, source address, and destination address). Then, the processor information (e.g., processor ID) and the user-input data information are obtained. Next, the relationship between the object data width and the first threshold is determined. If the object data width is large (i.e., greater than or equal to the first threshold), the unaligned part of the address is processed. Then, the aligned part and the mantissa part are processed in sequence, and the relevant data is output. Then, the iamax output operation is performed. The maximum value and index of the unaligned, aligned, and mantissa parts are compared, and the index of the maximum value is selected. Finally, the index is returned. If the object data width is small (i.e., less than the first threshold), it is not necessary to consider whether the data source address is aligned. The operation of processing the aligned part is performed directly. If there is remaining data, the mantissa part is processed. Finally, the index of the maximum value is selected according to the above steps.

[0099] The following discussion will only cover the case where the width of the object data is greater than or equal to the first threshold.

[0100] First, for the portion with unaligned addresses, obtain the remainder of the address alignment vector width (i.e., the width of the unit vector operation mentioned above), then obtain the amount of data to be pre-processed (i.e., the width of the unaligned data mentioned above), then obtain the length of the corresponding data type (i.e., the number of unaligned data items), and then obtain the mask corresponding to this length. This mask is the first mask information mentioned above (e.g., a binary sequence). Then, load the data from this address according to the mask and process the data. During the data processing, perform an iamax operation to find the maximum value in the unaligned data and return the maximum value and its index to end the processing operation. Then, offset the address to end the unalignment operation. The specific steps of this unalignment operation are described above and will not be repeated here.

[0101] Secondly, after processing the unaligned portion, the address alignment operation begins. First, the remaining data width (the difference between the object data width and the unaligned data width) is obtained. Then, the loop count is obtained (derived by dividing the remaining data width by the unit vector operation width). Next, the mantissa is obtained. Then, in each loop cycle, data is sequentially loaded into the vector register and processed using the `iamax` function. The specific processing includes looping through the data, comparing the vector containing the maximum value and returning the maximum value and its index, offsetting the address, determining if the loop has ended, and finally ending the alignment operation. The specific steps of this alignment operation are detailed above and will not be repeated here.

[0102] Finally, after processing the address alignment, if a mantissa exists, a mantissa operation is required. This involves obtaining the mantissa length (i.e., the number of data items at the end), then obtaining the mask corresponding to that length. This mask is the second mask information mentioned above (e.g., a binary sequence). Data is then loaded from the address based on the mask and processed. During data processing, an iamax operation is performed to find the maximum value among the unaligned data and return the maximum value and its index to end the processing. The address is then offset to terminate the mantissa operation. The specific steps of this mantissa operation are detailed above and will not be repeated here.

[0103] At least one embodiment of this disclosure is applicable to the first-level function iamax in the BLAS library. Tests have shown that, with an iamax step size of 1, the performance is improved by 12% compared to the unoptimized large-scale object data (i.e., the number of object data is greater than 10,000).

[0104] It should be noted that, in the embodiments of this disclosure, the flow of the data processing method provided in the above embodiments may include more or fewer operations, which may be executed sequentially or in parallel. Although the flow of the data processing method described above includes multiple operations appearing in a specific order, it should be clearly understood that the order of the multiple operations is not limited. The data processing method described above may be executed once or multiple times according to predetermined conditions.

[0105] Embodiments of this disclosure also provide a data processing apparatus for the above-described data processing method. Figure 8 This is a schematic diagram of a data processing apparatus provided for at least one embodiment of the present disclosure.

[0106] like Figure 8 As shown, the data processing device 200 includes a first acquisition module 210, a second acquisition module 220, a first calculation module 230, a second calculation module 240, and a loading and processing module 250. These units can be implemented, for example, through hardware (e.g., circuit) modules or software modules. For instance, these units can be implemented using a central processing unit (CPU), a graphics processing unit (GPU), a tensor processor (TPU), a field-programmable gate array (FPGA), or other forms of processing units with data processing and / or instruction execution capabilities, along with corresponding computer instructions.

[0107] The first acquisition module 210 is configured to acquire the width of the unit vector operation supported by the hardware. For example, the first acquisition module 210 can implement step S100, and its specific implementation method can be found in the relevant description of step S100, which will not be repeated here.

[0108] The second acquisition module 220 is configured to acquire the source address to be aligned and the number of object data to be operated on. For example, the second acquisition module 220 can implement step S110, and its specific implementation method can be found in the relevant description of step S110, which will not be repeated here.

[0109] The first calculation module 230 is configured to, in response to the width of the object data being greater than or equal to a first threshold, calculate the remainder after the width of the source address alignment unit vector operation to be aligned, in order to obtain the width of the address-misaligned data in the object data. Here, the width of the object data is equal to the product of the unit data width of the object data and the number of object data items, and the width of the address-misaligned data is equal to the difference between the unit vector operation width and the remainder. For example, the first calculation module 230 can implement step S120; its specific implementation method can be found in the relevant description of step S120, which will not be repeated here.

[0110] The second calculation module 240 is configured to determine the number of misaligned data points based on the unit data width of the object data and the width of the misaligned data points, and to determine the first mask information based on the number of misaligned data points and the unit vector operation width. For example, the second calculation module 240 can implement step S130, and its specific implementation method can be found in the relevant description of step S130, which will not be repeated here.

[0111] The loading and processing module 250 is configured to load and process address-misaligned data based on the first mask information. For example, the loading and processing module 250 can implement step S140, and its specific implementation method can be found in the relevant description of step S140, which will not be repeated here.

[0112] The data processing apparatus provided in this disclosure is applicable to, for example, Level 1 functions in the BLAS library, has a wide coverage and strong versatility, and achieves address alignment by combining with a compiler, thereby optimizing memory bandwidth and improving processing performance.

[0113] It should be noted that, for clarity and brevity, the embodiments of this disclosure do not show all the constituent units of the data processing device 200. To achieve the necessary functions of the data processing device 200, those skilled in the art can provide and set other constituent units (not shown) according to specific needs, and the embodiments of this disclosure do not impose any limitations on this.

[0114] Embodiments of this disclosure also provide an electronic device. Figure 9 This is a schematic diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0115] For example, such as Figure 9As shown, the electronic device 300 includes a processor 310 and a memory 320. The memory 320 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 310 is used to execute the computer program instructions, which, when executed by the processor 310, perform the data processing method provided in any embodiment of this disclosure. The memory 320 and the processor 310 can be interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0116] Processor 310 can be a central processing unit (CPU), tensor processor (TPU), network processor (NP), or graphics processing unit (GPU) with data processing and / or program execution capabilities. It can also be a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. For example, the central processing unit (CPU) can be based on x86 or ARM architectures. Processor 310 can be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 300 to perform desired functions.

[0117] For example, memory 320 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 310 may run one or more computer program modules to implement various functions of electronic device 300. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0118] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the electronic device 300 can be referred to the description of the data processing method above, and will not be repeated here.

[0119] Embodiments of this disclosure also provide a storage medium. Figure 10 This is a schematic diagram of a storage medium provided for at least one embodiment of the present disclosure. For example, such as... Figure 10As shown, the storage medium 400 non-temporarily stores computer-executable instructions 410, which can execute the data processing method of any embodiment of this disclosure when executed by a computer (including a processor).

[0120] For example, one or more computer instructions may be stored on the storage medium 400. Some of the computer instructions stored on the storage medium 400 may be, for example, instructions for implementing one or more steps in the data processing method described above.

[0121] For example, the storage medium may include the storage component of a tablet computer, the hard disk of a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media. For example, storage medium 400 may include memory 320 in the aforementioned electronic device 300.

[0122] The technical effects of the storage medium provided in the embodiments of this disclosure can be found in the corresponding descriptions of the data processing methods in the above embodiments, and will not be repeated here.

[0123] Figure 11 This is a schematic diagram of another electronic device provided for at least one embodiment of the present disclosure. Figure 11 The illustrated electronic device 500 is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0124] like Figure 11 As shown, in some examples, electronic device 500 includes a processing unit (e.g., central processing unit, graphics processor, etc.) 501, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 502 or a program loaded from storage device 508 into random access memory (RAM) 503. The RAM 503 also stores various programs and data required for the operation of the computer system. The processing unit 501, ROM 502, and RAM 503 are connected via bus 504. An input / output (I / O) interface 505 is also connected to bus 504.

[0125] For example, the following components can be connected to I / O interface 505: input devices 506 including, for example, touch screens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 508 including, for example, magnetic tapes, hard disks, etc.; and communication devices 509, such as network interface cards like LAN cards and modems, etc. Communication device 509 allows electronic device 500 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 510 is also connected to I / O interface 505 as needed. Removable media 511, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 510 as needed so that computer programs read from them can be installed into storage device 508 as needed.

[0126] Although Figure 11 An electronic device 500 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0127] For example, the electronic device 500 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 509 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0128] For example, the electronic device 500 may include any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or any combination of data processing device and hardware. The embodiments disclosed herein do not limit this.

[0129] The following points need to be clarified regarding this disclosure:

[0130] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0131] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0132] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A data processing method, comprising: Get the width of the unit vector operation supported by the hardware; Obtain the source address to be aligned and the number of object data to be operated on; In response to the width of the object data being greater than or equal to a first threshold, the remainder after aligning the source address to be aligned with the width of the unit vector operation is calculated to obtain the width of the address-misaligned data in the object data, wherein the width of the object data is equal to the product of the unit data width of the object data and the number of object data, and the width of the address-misaligned data is equal to the difference between the unit vector operation width and the remainder; The number of misaligned data points is determined based on the unit data width of the object data and the width of the misaligned data points. First mask information is determined based on the number of misaligned data points and the unit vector operation width, wherein the total number of valid bits in the first mask information is equal to the number of misaligned data points. Based on the first mask information, the data whose address is misaligned as indicated by the valid bit is loaded and processed using functions of the database, wherein the database includes any one of the basic linear algebra library, kernel, and acceleration library; Offset the source address by the width of the misaligned data to obtain the offset first address; The remaining data in the object data, excluding the data with misaligned addresses, is processed based on the first address after the offset.

2. The method according to claim 1, wherein, The remaining data includes address-aligned data. The process of processing the remaining data in the object data, excluding the data with misaligned addresses, based on the first address after the offset includes: The address-aligned data is processed based on the first address after the offset.

3. The method according to claim 2, wherein, The process of processing the address-aligned data based on the offset first address includes: The width of the remaining data is calculated based on the width of the object data and the width of the address-misaligned data. The number of loop operations for the address-aligned data is determined based on the width of the remaining data and the width of the unit vector operation. The following steps are performed in each loop operation cycle: The address-aligned data is loaded and processed sequentially according to the unit vector operation width.

4. The method according to claim 3, wherein, The remaining data also includes tail data. After loading and processing the address-aligned data sequentially according to the unit vector operation width, the method further includes: Calculate the width of the address-aligned data, wherein the width of the address-aligned data is equal to the product of the number of loop operations and the width of the unit vector operation; The first address is offset by the width of the data aligned to that address to obtain the offset second address; The tail data is processed based on the second address after the offset.

5. The method according to claim 4, wherein, The process of processing the tail data based on the offset second address includes: Calculate the width of the tail data, wherein the width of the tail data is equal to the difference between the width of the remaining data and the width of the address-aligned data; The number of tail data is determined based on the unit data width of the object data and the width of the tail data, and the second mask information is determined based on the number of tail data and the unit vector operation width; The tail data is loaded and processed based on the second mask information.

6. The method according to any one of claims 1-5, wherein, The unit vector operation width includes any one of 16 bytes, 32 bytes, and 64 bytes.

7. The method according to any one of claims 1-5, wherein, The first threshold is equal to twice the product of the unit vector operation width and the processing coefficient, wherein the processing coefficient includes any one of 2, 3 and 4.

8. The method according to any one of claims 1-5, wherein, The object data includes any one of integer, single-precision floating-point, and double-precision floating-point types.

9. The method according to claim 5, wherein, The first mask information and the second mask information are binary sequences.

10. The method according to claim 9, wherein, In response to the first mask information being the binary sequence, the binary sequence including valid bits and invalid bits, wherein, The total number of valid bits is equal to the number of data that are misaligned at the address, and the total number of invalid bits is equal to the length of the binary sequence minus the remaining number of valid bits. The length of the binary sequence is obtained by the quotient of the unit vector operation width and the unit data width of the object data.

11. The method according to claim 9, wherein, In response to the second mask information being the binary sequence, the binary sequence including valid bits and invalid bits, wherein, The total number of valid bits is equal to the number of tail data, and the total number of invalid bits is equal to the length of the binary sequence minus the remaining number of valid bits. The length of the binary sequence is obtained by the quotient of the unit vector operation width and the unit data width of the object data.

12. The method according to claim 10, wherein, The valid bits are consecutive low-order bits in the binary sequence, and the invalid bits are consecutive high-order bits in the binary sequence.

13. The method according to claim 11, wherein, The valid bits are consecutive high-order bits in the binary sequence, and the invalid bits are consecutive low-order bits in the binary sequence.

14. The method according to claim 1, wherein, The remainder is obtained by performing a logical AND operation between the source address to be aligned and the width of the unit vector operation.

15. The method according to claim 1, wherein, The functions include first-level functions from the basic linear algebra library.

16. A data processing apparatus, comprising: The first acquisition module is configured to acquire the width of the unit vector operation supported by the hardware; The second acquisition module is configured to acquire the source address to be aligned and the number of object data to be operated on; A first calculation module is configured to, in response to the width of the object data being greater than or equal to a first threshold, calculate the remainder after aligning the source address to be aligned with the width of the unit vector operation to obtain the width of the address-misaligned data in the object data, wherein the width of the object data is equal to the product of the unit data width of the object data and the number of object data, and the width of the address-misaligned data is equal to the difference between the unit vector operation width and the remainder; The second calculation module is configured to determine the number of address-misaligned data based on the unit data width of the object data and the width of the address-misaligned data, and to determine first mask information based on the number of address-misaligned data and the unit vector operation width, wherein the total number of valid bits in the first mask information is equal to the number of address-misaligned data; The loading and processing module is configured to load the address-misaligned data indicated by the valid bits according to the first mask information and process it using functions of the database, wherein the database includes any one of the basic linear algebra library, kernel, and acceleration library. The third calculation module is configured to offset the source address by the width of the misaligned data to obtain the offset first address; and to process the remaining data in the object data excluding the misaligned data based on the offset first address.

17. An electronic device comprising: processor; as well as Memory, which includes one or more computer program instructions; The one or more computer program instructions are executed by the processor during runtime as described in any one of claims 1-15.

18. A non-transitory computer-readable storage medium having stored thereon computer-readable instructions, wherein, The data processing method according to any one of claims 1-15 is implemented when the computer-readable instructions are executed by a processor.

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