Control method for pull-down circuit of vertical shift register and related product

Abstract

The application discloses a control method of a pull-down circuit of a vertical shift register and a related product. The method comprises controlling each group of driving power sources connected with each group of pull-down circuits to operate according to a power supply timing sequence meeting a preset condition, so that each group of pull-down circuits is switched into a working state in time, and there is an overlapping interval of the working states of adjacent pull-down circuits when switching. The adjacent pull-down circuits refer to the pull-down circuits switched into the working state continuously in time sequence. The driving capability of the switching gap of the pull-down circuit is enhanced by the control method, stable pull-down of a target node is realized, and the occurrence of picture abnormal phenomena such as screen flashing is avoided.

Description

Technical Field

[0001] This application generally relates to the field of display technology. More specifically, this application relates to a control method and related products for a pull-down circuit of a vertical shift register. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT LCDs) are widely used in various terminal devices due to their high image quality, low power consumption, and cost advantages. Their structure can be as follows: Figure 1 As shown, it includes an AA (Active Area) region with multiple pixel electrodes and a VSR (Vertical Shift) for switching control of the TFTs connected to each pixel electrode in the AA region. The vertical shift register (VFD) is usually located on one or both sides of the AA area.

[0003] The VSR circuit functions similarly to a shift register, consisting of multiple cascaded single-stage shift register units. Each unit corresponds to a row of pixels on the panel and is specifically responsible for generating and controlling the Gate signal for that row. The units transmit the drive signal row by row through cascading signal transmission, ensuring that the Gate signal takes effect sequentially in row order, and works with the column drive circuit to complete the display of one frame of the image.

[0004] Single-stage shift register unit such as Figure 2 As shown, it includes a thin-film field-effect transistor (TFT) that directly drives the pixel at this level, and two sets of pull-down circuits connected to the target node Q in the TFT (corresponding to...). Figure 2 The pull-down circuits 1 and 2 in the thin-film field-effect transistor (TFT) directly determine whether the pixel at this level is selected, while the target node Q controls the Gate (corresponding to...). Figure 2 The key node for the Gn signal state. One end of each of the two pull-down circuits is connected to the target node Q, while the other end is connected to the corresponding drive power supply (corresponding to...). Figure 2 The VDD1 and VDD2 connections are used to pull down the target node Q using power supplied by the drive power supply at specific timings, changing its potential state and thus the Gate signal state. When the target node Q is at a high potential, it causes the Gate signal to output an effective level, at which point the thin-film transistor (TFT) is turned on, and the pixel at this level is selected; when the target node Q is at a low potential, the Gate signal becomes ineffective, the TFT is turned off, and the pixel at this level is not selected.

[0005] The two sets of pull-down circuits are independently driven by their corresponding electrically connected power supplies and operate in an alternating manner: when one set of pull-down circuits is running, the other set is off; and when the running set is off, the previously off set starts running simultaneously. Through this alternating operation mode, the pull-down of the target node Q point is achieved in a time-division manner, thereby controlling the state of the Gate signal.

[0006] However, in actual operation, when the pull-down circuit is switched (pull-down circuit 1 switches to pull-down circuit 2, or pull-down circuit 1 switches to pull-down circuit 2), due to insufficient driving capability of the pull-down circuit, the pull-down circuit may not pull down the Q point enough in the initial stage of switching, resulting in abnormal Gate signal output, which in turn leads to screen flickering and other abnormal screen phenomena, affecting the user's viewing experience.

[0007] In view of this, there is an urgent need to provide a control method and related products for the pull-down circuit of the vertical shift register, so as to solve the problem of abnormal display screen due to insufficient driving capability in the initial switching of the pull-down circuit of the vertical shift register, and improve the user viewing experience. Summary of the Invention

[0008] In order to at least solve one or more of the technical problems mentioned above, this application proposes a control method and related products for a pull-down circuit of a vertical shift register in several aspects.

[0009] In a first aspect, this application provides a control method for pull-down circuits of a vertical shift register, comprising: controlling each group of drive power supplies connected to each group of pull-down circuits to operate according to a power supply sequence that meets preset conditions, so that each group of pull-down circuits switches into a working state in a time-division manner, and the working states of adjacent pull-down circuits overlap during the switching; wherein the adjacent pull-down circuits refer to pull-down circuits that switch into a working state consecutively in time sequence.

[0010] In some embodiments, the preset conditions include: the power supply duty cycle of adjacent drive power supplies is greater than 50%, and the power supply time interval of one group of drive power supplies is [0, The power supply time interval of the other set of drive power supplies is [( [,T], where D represents the power supply duty cycle of the drive power supply and T represents the time period.

[0011] In some embodiments, the preset conditions include: the power supply duty cycle of adjacent drive power supplies satisfies: the power supply duty cycle of one set of drive power supplies is greater than 50%, the power supply duty cycle of the other set of drive power supplies is less than 50%, and the sum of the power supply duty cycles of the two sets of drive power supplies is greater than 100%; the power supply time interval of adjacent drive power supplies satisfies: the power supply time interval of one set of drive power supplies is [0, The power supply time interval of the other set of drive power supplies is [( [,T], where D represents the power supply duty cycle of the drive power supply and T represents the time period.

[0012] In some embodiments, the method further includes: controlling each group of drive power supplies connected to each group of pull-down circuits to switch operation according to a power supply timing sequence that meets a first preset condition and a power supply timing sequence that meets a second preset condition, so that each group of pull-down circuits switches into the working state in a time-division manner, and the working states of adjacent pull-down circuits overlap during the switching; wherein the adjacent pull-down circuits refer to pull-down circuits that switch into the working state consecutively in the timing sequence.

[0013] In some embodiments, the first preset condition includes: among the power supply duty cycles of adjacent driving power supplies, the power supply duty cycle of the first group of driving power supplies is greater than 50%, the power supply duty cycle of the second group of driving power supplies is less than 50%, and the sum of the power supply duty cycles of the first group of driving power supplies and the power supply duty cycles of the second group of driving power supplies is greater than 100%; The power supply time intervals of adjacent drive power supplies satisfy the following condition: the power supply time interval of one set of drive power supplies is [0, ..., ... The power supply time interval of the other set of drive power supplies is [( [,T], where D represents the power supply duty cycle of the drive power supply and T represents the time period.

[0014] In some embodiments, the second preset condition includes: among the power supply duty cycles of adjacent driving power supplies, the power supply duty cycle of the first group of driving power supplies is less than 50%, the power supply duty cycle of the second group of driving power supplies is greater than 50%, and the sum of the power supply duty cycles of the first group of driving power supplies and the second group of driving power supplies is greater than 100%; The power supply time intervals of adjacent drive power supplies satisfy the following condition: the power supply time interval of one set of drive power supplies is [0, ..., ... The power supply time interval of the other set of drive power supplies is [( [,T], where D represents the power supply duty cycle of the drive power supply and T represents the time period.

[0015] In a second aspect, this application proposes a vertical shift register, comprising: a plurality of cascaded single-stage shift register units; and a controller connected to a drive power supply in each of the single-stage shift register units, for use in the methods described in the first aspect and any of its embodiments; wherein, each single-stage shift register unit comprises: a thin-film field-effect transistor; at least two sets of pull-down circuits, wherein one end of each set of pull-down circuits is connected to a target node in the thin-film field-effect transistor, the target node being a node that controls the gate signal in the thin-film field-effect transistor to be turned off; and a drive power supply corresponding to the number of pull-down circuit sets, wherein each set of drive power supplies is connected to the other end of a set of pull-down circuits for independently powering the pull-down circuits connected thereto; wherein when the drive power supply is powered, the pull-down circuits connected thereto enter a working state, realizing pull-down control of the target node and turning off the gate signal in the thin-film field-effect transistor.

[0016] In a third aspect, this application proposes a thin-film field-effect transistor liquid crystal display panel, comprising: an effective display area region for image display; and a vertical shift register as described in the second aspect, used to drive the effective display area region to achieve image display.

[0017] The control method for the pull-down circuit of the vertical shift register provided above controls the power supply connected to it to operate according to the power supply sequence that meets the preset conditions. This allows each group of pull-down circuits to switch into working state in a time-division manner, and the working states of adjacent pull-down circuits overlap in time during the switching. This enhances the overall driving capability of the pull-down circuit, ensures a stable pull-down effect on the target node, and avoids problems such as abnormal gate signal output and screen flickering caused by insufficient driving of a single pull-down circuit, thus ensuring the stability of the display panel and the user experience. Attached Figure Description

[0018] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein: Figure 1 An exemplary schematic diagram of a thin-film field-effect transistor liquid crystal display panel according to some embodiments of this application is shown; Figure 2 An exemplary schematic diagram of a single-stage shift register unit according to some embodiments of this application is shown; Figure 3 An exemplary flowchart illustrating a control method for a pull-down circuit of a vertical shift register according to some embodiments of this application is shown. Figure 4An exemplary flowchart illustrating a control method for a pull-down circuit of a vertical shift register according to other embodiments of this application is shown. Figure 5 An exemplary schematic diagram showing the power supply timing of the drive power supply in some embodiments of this application is provided. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] It should be understood that the terms "comprising" and "including" used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0021] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0022] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0023] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0024] Exemplary application scenarios With its significant advantages in high image quality, low power consumption, and cost control, thin-film transistor liquid crystal display panels have been deeply integrated into various scenarios and have become an indispensable core display component for many devices.

[0025] From smartphones and tablets to laptops, most screens use this panel to clearly display text, images, and videos, comprehensively meeting users' diverse needs for communication, entertainment, and office work. The high-definition output of smart TVs, the information interaction functions of refrigerator displays, and the command feedback mechanism of washing machine control panels all rely on this panel, providing users with an intuitive and convenient operating experience and a wealth of diverse information access methods. Smartwatches, fitness trackers, and other products also widely use this panel to display key information such as time, activity data, and message notifications in real time, helping users efficiently manage their daily lives.

[0026] However, the vertical shift register built into this type of panel may have insufficient driving capability when switching, resulting in poor pull-down effect on the Q point in the initial stage of switching. This can lead to abnormal Gate signal output, causing screen flickering and other image problems, which can affect the user's viewing experience.

[0027] In view of this, this application proposes a control method for the pull-down circuit of a vertical shift register. This method achieves pull-down control of the target node by controlling at least two sets of pull-down circuits to switch into working states in a time-division manner, ensuring that the working states of adjacent pull-down circuits overlap in time during the switching process. This enhances the overall driving capability through the synergistic effect of two consecutively switching sets of pull-down circuits during the switching phase, ensuring a stable pull-down effect on the target node and avoiding problems such as abnormal gate signal output and screen flickering caused by insufficient driving from a single pull-down circuit during switching. This guarantees the stability of the display panel and the user experience.

[0028] Exemplary application scheme This application proposes a vertical shift register, including multiple cascaded single-stage shift register units and a controller. The controller is communicatively connected to each group of drive power supplies in the single-stage shift register units to control each group of drive power supplies to operate according to a preset power supply sequence, thereby supplying power to the pull-down circuits connected to each group of drive power supplies so that they enter the working state.

[0029] In some embodiments, such as Figure 2 The single-stage shift register unit shown includes a thin-film field-effect transistor, at least two sets of pull-down circuits, and a drive power supply corresponding to the number of pull-down circuit sets.

[0030] Furthermore, one end of each pull-down circuit is connected to the target node in the thin-film field-effect transistor circuit. This target node is the gate (corresponding to) in the thin-film field-effect transistor. Figure 2 The node in the Gn signal state. In other words, the target node is... Figure 2The node Q is shown. Each set of drive power supplies is connected to the other end of a set of pull-down circuits to independently power the pull-down circuits connected to them. When the drive power supply is powered, the pull-down circuit connected to it enters the working state, realizing the pull-down of the target node.

[0031] Furthermore, the controller is communicatively connected to each group of drive power supplies in the single-stage shift register unit. This allows the pull-down circuits to switch into their operating states in a time-division multiplexing manner by executing a control method for the pull-down circuits of the vertical shift register. During switching, the operating states of adjacent pull-down circuits overlap in time, thereby enhancing the driving capability of the pull-down circuits and preventing gate signal jitter. The aforementioned control method for the pull-down circuits of the vertical shift register will be described in detail below and will not be elaborated upon here.

[0032] This application also proposes a thin-film field-effect transistor liquid crystal display panel, including an effective display area region for image display, and a vertical shift register of any of the above embodiments for driving the effective display area region to achieve image display.

[0033] The vertical shift register is composed of multiple cascaded single-stage shift register units, each of which controls a row of pixels on the display panel. Specifically, the gate signal output of the thin-film field-effect transistor in the single-stage shift register unit is connected to the scan line of the driving pixel, and the scan line is in turn connected to the gate of the thin-film field-effect transistor in each pixel unit in the corresponding row.

[0034] When the single-stage shift register unit outputs a valid Gate signal (e.g., high level), the signal is synchronously transmitted through the scan lines to the gates of the thin-film field-effect transistors (TFTs) of all pixels in that row, triggering these TFTs to conduct simultaneously. At this time, the image data signal (e.g., grayscale voltage) on the column data lines can be written into the storage capacitors of each pixel through the conducting TFTs, completing the charging and data loading of the pixels in that row. When the Gate signal turns to an invalid level (e.g., low level), the signal transmitted through the scan lines causes the TFTs of all pixels in that row to turn off, and the storage capacitors maintain the voltage already written, ensuring that the pixels maintain their current display state until the next refresh. This achieves image display within the effective display area.

[0035] Figure 3 This application illustrates a control method 100 for a pull-down circuit of a vertical shift register, which can be executed by the controller described above. Figure 3 As shown, method 100 includes step S101.

[0036] It should be noted that the control method 100 in this embodiment controls the independent drive power supplies (which are connected to pull-down circuits) within each single-stage shift register unit of the vertical shift register. Therefore, the controller communicates directly with each set of drive power supplies within each unit.

[0037] It should be noted that the control method 100 executed by the controller in this embodiment controls the sets of drive power supplies (used to power the pull-down circuits, enabling them to enter the working state and pull down the target node) within each single-stage shift register unit of the vertical shift register. Therefore, the controller needs to communicate with each set of drive power supplies within the single-stage shift register unit.

[0038] In step S101, the driving power supply connected to each group of pull-down circuits is controlled to operate according to the power supply sequence that meets the preset conditions, so that each group of pull-down circuits switches into the working state in a time-sharing manner, and the working states of adjacent pull-down circuits overlap during the switching; wherein the adjacent pull-down circuits refer to pull-down circuits that switch into the working state consecutively in the timing sequence.

[0039] As described above, the output voltage of the drive power supply connected to the pull-down circuit is sufficient to put the pull-down circuit into operation, thereby achieving pull-down control of the target node. Therefore, the management of the operating states of each group of pull-down circuits needs to be achieved through the power supply timing settings of the drive power supplies connected to them.

[0040] In this embodiment, by controlling the driving power supply connected to the pull-down circuit to operate according to the power supply sequence that meets the preset conditions, each group of pull-down circuits switches into working state in a time-sharing manner, and the working states of adjacent pull-down circuits overlap in time during the switching. This enhances the overall driving capability of the pull-down circuit, ensures a stable pull-down effect on the target node, avoids problems such as abnormal gate signal output and screen flickering caused by insufficient driving of a single pull-down circuit, and ensures the stability of the display panel and user experience.

[0041] This embodiment does not limit the specific implementation form of the power supply timing (such as the power supply duty cycle and the specific value of the power supply time interval), as long as it can meet the requirements of the time-division switching of the pull-down circuit and the overlapping of the working state during the switching.

[0042] For the adjacent pull-down circuits in this embodiment, an exemplary description is provided. For example, there are pull-down circuits 1 to 4, each independently connected to drive power supplies 1 to 4. If the timing of the pull-down circuits entering the working state is pull-down circuits 1, 2, 3, 4, then pull-down circuits 1 and 2 are adjacent pull-down circuits, pull-down circuits 2 and 3 are adjacent pull-down circuits, and pull-down circuits 3 and 4 are adjacent pull-down circuits. If the timing of the pull-down circuits entering the working state is: first, [pull-down circuit 1, pull-down circuit 2] is executed cyclically n times, and then switched to executing [pull-down circuit 3, pull-down circuit 4] cyclically, then in this mode, within the initial n cycles, the working sequence is fixed as 1→2→1→2....... During this stage, pull-down circuits 1 and 2 constitute a pair of "adjacent pull-down circuits" because they are always adjacent to each other in the sequence and switch back and forth. At the instant of switching to the new mode after the nth cycle, the working sequence is 2 (nth cycle)→3→......(n+1th cycle). At this moment, pull-down circuits 2 and 3 temporarily form a pair of "adjacent pull-down circuits" due to their direct timing succession. Starting from the (n+1)th time, after entering a new stable phase, the working sequence becomes fixed: →3→4→3→4... In this phase, pull-down circuits 3 and 4 form a new pair of "adjacent pull-down circuits." Therefore, the "adjacent" relationship of the adjacent pull-down circuits described in this embodiment does not refer to physical proximity or consecutive numbering, but rather to pull-down circuits that sequentially switch into their working state in timing.

[0043] The specific implementation of step S101 above will be explained below, but this does not limit the scope of protection of this application.

[0044] In some embodiments, for the pull-down circuit to have time-division switching and overlapping working states during switching, the power supply timing of the drive power supply must meet the following preset conditions: the power supply duty cycle of adjacent drive power supplies is greater than 50%, and the power supply time interval of one set of drive power supplies is [0, The power supply time interval of the other set of drive power supplies is []. [,T], where D represents the power supply duty cycle of the drive power supply, T represents the time period, and adjacent drive circuits refer to drive power supplies that switch power supply sequentially in time.

[0045] In this embodiment, by defining the power supply duty cycle and the power supply time interval within a time period for the power supply timing of the driving power supply, it is possible to ensure that each group of driving power supplies switches power supply in a time-sharing manner, and that adjacent driving power supplies can maintain an overlap in power supply time during the switching. This allows each group of pull-down circuits to switch into working state in a time-sharing manner, and the adjacent pull-down circuits have an overlap in working state time during the switching, thereby enhancing the overall driving capability of the pull-down circuit, ensuring a stable pull-down effect on the target node, avoiding problems such as abnormal gate signal output and screen flickering caused by insufficient driving of a single pull-down circuit, and ensuring the stability of the display panel and user experience.

[0046] For example, there exists a pull-down circuit 1 and its connected drive power supply 1, and a pull-down circuit 2 and its connected drive power supply 2. The duty cycles of both drive power supply 1 and drive power supply 2 are greater than 50%, and they are adjacent drive power supplies. Therefore, their power supply time intervals must satisfy the condition that the power supply time interval of one of the drive power supplies is [0, ...]. The power supply time interval of the other set of drive power supplies is [( [, T], where D represents the duty cycle of the drive power supply, and T represents the time period. For example... Figure 5 (a) shows the power supply timing diagrams for drive power supply 1 and drive power supply 2, where VDD1 corresponds to the power supply timing of drive power supply 1 and VDD2 corresponds to the power supply timing of drive power supply 2. These two power supply timings satisfy the aforementioned preset conditions. It can be seen that the high-level intervals of VDD1 and VDD2 significantly overlap on the time axis. When the high level of VDD1 is about to end, VDD2 is still at a high level; while when the high level of VDD2 is about to end, VDD1 has already entered a high-level state. This timing relationship ensures that the working states of pull-down circuit 1 and pull-down circuit 2 remain connected, achieving both time-sharing alternation of the two sets of pull-down circuits and avoiding drive interruption through the overlap of high-level intervals, thus forming a continuous and stable pull-down drive effect, effectively enhancing the overall drive capability and ensuring reliable pull-down of the target node.

[0047] In a specific example, the time period T is 50μs, the duty cycle of drive power supply 1 is 60% (D1=0.6), and its power supply time interval is [ ]μs, i.e. [20, 50]μs. The duty cycle of the drive power supply 2 is 70% (D2=0.7), and its power supply time interval is [ The time period is [20, 50] μs, i.e., [0, 35] μs. Therefore, within a 50μs time period, drive power supply 1 outputs a high-level power supply within [20, 50] μs, while drive power supply 2 outputs a high-level power supply within [0, 35] μs. Thus, when drive power supply 1 switches from low to high at 20μs, drive power supply 2 remains in a high-level power supply state. The high-level power supply periods of both overlap within the [20, 35] μs interval, thus jointly providing energy to the pull-down circuit, enhancing the pull-down driving capability, and achieving stable pull-down of the target node.

[0048] While the power supply duty cycle and power supply time interval settings of the aforementioned drive power supply can ensure driving continuity by ensuring overlapping operating states of adjacent pull-down circuits during switching, they also extend the effective operating time of each group of pull-down circuits. Since the pull-down circuits are in a continuous operating state, excessively long operating times may accelerate the wear and tear of their internal components, thereby shortening their overall service life.

[0049] To address the aforementioned deficiencies, in some embodiments, the power supply timing of the drive power supply can be set to meet the following preset conditions: the power supply duty cycle of adjacent drive power supplies satisfies: the power supply duty cycle of one set of drive power supplies is greater than 50%, the power supply duty cycle of the other set of drive power supplies is less than 50%, and the sum of the power supply duty cycles of the two sets of drive power supplies is greater than 100%; the power supply time interval of adjacent drive power supplies satisfies: the power supply time interval of one set of drive power supplies is [0, The power supply time interval of the other set of drive power supplies is [( [,T], where D represents the power supply duty cycle of the drive power supply and T represents the time period.

[0050] In this embodiment, by limiting the power supply duty cycle and power supply time interval of the power supply sequence of the drive power supply, it can not only ensure that each group of pull-down circuits can achieve time-sharing switching and form an overlapping interval of working states during the switching interval, but also reduce the wear rate of the pull-down circuit and extend its service life.

[0051] For example, there exists a pull-down circuit 1 and its connected drive power supply 1, and a pull-down circuit 2 and its connected drive power supply 2. The power supply duty cycle of drive power supply 1 is greater than 50%, and the power supply duty cycle of drive power supply 2 is less than 50%. Since they are adjacent drive power supplies, their power supply time intervals must satisfy the condition that the power supply time interval of one of the drive power supplies is [0, ...]. The power supply time interval of the other set of drive power supplies is []. [, T], where D represents the duty cycle of the drive power supply, and T represents the time period. For example... Figure 5(b) shows the power supply timing diagram of drive power supply 1 and drive power supply 2, where VDD1 corresponds to the power supply timing of drive power supply 1 and VDD2 corresponds to the power supply timing of drive power supply 2. These two power supply timings satisfy the aforementioned preset conditions. It can be seen that the high-level intervals of VDD1 and VDD2 overlap significantly on the time axis. When the high level of VDD1 is about to end, VDD2 is still at a high level; while when the high level of VDD2 is about to end, VDD1 has already entered a high-level state. This timing relationship ensures that the working states of pull-down circuit 1 and pull-down circuit 2 remain connected, achieving both time-division switching of the two sets of pull-down circuits and avoiding drive interruption through the overlap of high-level intervals, thus forming a continuous and stable pull-down drive effect, effectively enhancing the overall drive capability and ensuring reliable pull-down of the target node. Meanwhile, by adopting a configuration of "one group with a power supply duty cycle greater than 50% and one group with a duty cycle less than 50%", compared with a scheme where both groups have a duty cycle greater than 50%, the continuous working time of a single pull-down circuit can be reduced. In particular, the effective working time of pull-down circuit 2 with a power supply duty cycle less than 50% is shorter, which can significantly reduce the component loss rate. Pull-down circuit 1 with a power supply duty cycle greater than 50% also avoids the pressure of long-term independent operation through time-sharing switching with pull-down circuit 2.

[0052] In a specific example, the time period T is 50μs, the duty cycle of drive power supply 1 is 60% (D1=0.6), and its power supply time interval is [( [20, 50]μs, i.e. [20, 50]μs, the power supply duty cycle of drive power supply 2 is 45% (D2=0.45), and its power supply time interval is [0, 50]μs. The time interval is [0, 22.5] μs. Therefore, within a 50μs time period, drive power supply 1 outputs a high-level power supply within the range [20, 50] μs, while drive power supply 2 outputs a high-level power supply within the range [0, 22.5] μs. Thus, when drive power supply 1 switches from low to high at 20μs, drive power supply 2 remains in a high-level power supply state. The high-level power supply periods of both overlap within the range [20, 22.5] μs, thus jointly providing energy to the pull-down circuit, enhancing the pull-down driving capability, and achieving stable pull-down of the target node.

[0053] The above combination Figure 3This application provides a detailed description of a control method for a pull-down circuit of a vertical shift register according to some embodiments. This method controls the connected drive power supply to operate according to a power supply sequence that meets preset conditions. This allows each group of pull-down circuits to switch into working states in a time-division manner, with overlapping time intervals between the working states of adjacent pull-down circuits during the switching process. This enhances the overall driving capability of the pull-down circuit, ensuring a stable pull-down effect on the target node. It also avoids problems such as abnormal gate signal output and screen flickering caused by insufficient driving of a single pull-down circuit, thus ensuring the stability of the display panel and the user experience.

[0054] Figure 4 This application illustrates a control method 200 for a pull-down circuit of a vertical shift register, which can be executed by the controller described above. Figure 4 As shown, method 200 includes step S201.

[0055] In step S201, the driving power supply connected to each group of pull-down circuits is controlled to switch operation according to the power supply timing sequence that meets the first preset condition and the power supply timing sequence that meets the second preset condition, so that each group of pull-down circuits switches into the working state in a time-division manner, and the working states of adjacent pull-down circuits overlap during the switching; wherein the adjacent pull-down circuits refer to pull-down circuits that switch into the working state consecutively in the timing sequence.

[0056] In this embodiment, the control drive power supply switches between power supply timing sequences that meet the first and second preset conditions. It is important to clarify that at any given time, all drive power supplies can only uniformly adopt one of these power supply timing sequences; that is, they must either all follow the power supply timing sequence under the first preset condition or all follow the power supply timing sequence under the second preset condition. There is no situation where some drive power supplies use the power supply timing sequence that meets the first preset condition while others use the power supply timing sequence that meets the second preset condition. Therefore, not only can the pull-down circuits switch into their working states in a time-sharing manner, but the working states of adjacent pull-down circuits also overlap during switching. This also balances the workload and loss rate among the pull-down circuits, further extending the service life of all pull-down circuits and improving the overall reliability of the pull-down circuits.

[0057] There are no specific restrictions on how to switch between the first and second preset conditions; those skilled in the art can choose flexibly according to the actual application scenario.

[0058] In some embodiments, the drive power supply may first run continuously n times according to a power supply timing sequence that meets a first preset condition, and then switch to running continuously m times according to a power supply timing sequence that meets a second preset condition, and repeat this process as one cycle. Here, n and m may be the same or different, and this embodiment does not specifically limit this.

[0059] In some embodiments, the first preset condition includes: among the power supply duty cycles of adjacent driving power supplies, the power supply duty cycle of the first group of driving power supplies is greater than 50%, the power supply duty cycle of the second group of driving power supplies is less than 50%, and the sum of the power supply duty cycles of the first group of driving power supplies and the second group of driving power supplies is greater than 100%. Furthermore, the power supply time intervals of adjacent driving power supplies satisfy: the power supply time interval of one group of driving power supplies is [0, ... The power supply time interval of the other set of drive power supplies is [( [,T], where D represents the power supply duty cycle of the drive power supply and T represents the time period.

[0060] In some embodiments, the second preset condition includes: among the power supply duty cycles of adjacent driving power supplies, the power supply duty cycle of the first group of driving power supplies is less than 50%, the power supply duty cycle of the second group of driving power supplies is greater than 50%, and the sum of the power supply duty cycles of the first group of driving power supplies and the second group of driving power supplies is greater than 100%. Furthermore, the power supply time intervals of adjacent driving power supplies satisfy: the power supply time interval of one group of driving power supplies is [0, ... The power supply time interval of the other set of drive power supplies is [( [,T], where D represents the power supply duty cycle of the drive power supply and T represents the time period.

[0061] In summary, the first and second preset conditions are a set of symmetrical and complementary timing rules. The former stipulates that the first group of driving power supplies has a high duty cycle and the second group of driving power supplies has a low duty cycle, while the latter stipulates that the first group of driving power supplies has a low duty cycle and the second group of driving power supplies has a high duty cycle. By cyclically switching between the two, it is possible to ensure that adjacent pull-down circuits always maintain a stable driving effect with time-sharing switching and overlapping working states, and to dynamically balance the workload of each group of pull-down circuits, avoiding long-term high-load operation of a single pull-down circuit. Thus, while ensuring driving reliability, it balances the loss rate, extends the overall service life, and improves the reliability of the pull-down circuit.

[0062] For example, there exists a pull-down circuit 1 and its connected drive power supply 1, and a pull-down circuit 2 and its connected drive power supply 2. Figure 5 As shown in (c), VDD1 corresponds to the power supply timing of drive power supply 1, and VDD2 corresponds to the power supply timing of drive power supply 2. Drive power supply 1 and drive power supply 2 first operate with a power supply timing that meets the first preset condition. After cycling 3 times, drive power supply 1 and drive power supply 2 switch to a power supply timing that meets the second preset condition. Thus, by switching between different preset conditions, the high power supply duty cycles of drive power supply 1 and drive power supply 2 are alternately exchanged, achieving dynamic balancing of the workload.

[0063] The above combination Figure 4The control method for the pull-down circuit of the vertical shift register in some embodiments of this application is described in detail. It controls the driving power supply to switch between power supply timings that meet the first preset condition and the second preset condition. This not only allows each group of pull-down circuits to switch into working state in a time-division manner, but also ensures that the working states of adjacent pull-down circuits overlap during the switching process. Furthermore, it balances the workload and loss rate between each group of pull-down circuits, thereby extending the service life of all pull-down circuits and improving the overall reliability of the pull-down circuit.

[0064] While numerous embodiments of this application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise for those skilled in the art without departing from the spirit and intent of this application. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A control method for a pull-down circuit of a vertical shift register, characterized in that, include: The control system operates the power supply of each group of pull-down circuits according to the power supply sequence that meets the preset conditions, so that each group of pull-down circuits switches into the working state in a time-sharing manner, and the working states of adjacent pull-down circuits overlap during the switching. The adjacent pull-down circuits mentioned above refer to pull-down circuits that switch sequentially into the working state in a single-stage shift register unit. The preset conditions include: The duty cycles of adjacent drive power supplies are both greater than 50%, and the power supply time interval of one set of drive power supplies is [0, D×T], while the power supply time interval of the other set of drive power supplies is [(1-D)×T, T], where D represents the duty cycle of the drive power supply and T represents the time period; or The duty cycle of adjacent drive power supplies meets the following conditions: the duty cycle of one set of drive power supplies is greater than 50%, the duty cycle of the other set of drive power supplies is less than 50%, and the sum of the duty cycles of the two sets of drive power supplies is greater than 100%. The power supply time intervals of adjacent drive power supplies satisfy the following: the power supply time interval of one set of drive power supplies is [0, D×T], and the power supply time interval of the other set of drive power supplies is [(1-D)×T, T], where D represents the power supply duty cycle of the drive power supply and T represents the time period.

2. The method according to claim 1, characterized in that, The method further includes: The control system switches the power supply of each group of pull-down circuits according to the power supply timing sequence that meets the first preset condition and the power supply timing sequence that meets the second preset condition, so that each group of pull-down circuits switches into the working state in a time-division manner, and the working states of adjacent pull-down circuits overlap during the switching; wherein the adjacent pull-down circuits refer to the pull-down circuits that switch into the working state consecutively in the timing sequence.

3. The method according to claim 2, characterized in that, The first preset conditions include: In the adjacent drive power supplies, the first group of drive power supplies has a power supply duty cycle greater than 50%, the second group of drive power supplies has a power supply duty cycle less than 50%, and the sum of the power supply duty cycles of the first group of drive power supplies and the second group of drive power supplies is greater than 100%. The power supply time intervals of adjacent drive power supplies satisfy the following: the power supply time interval of one set of drive power supplies is [0, D×T], and the power supply time interval of the other set of drive power supplies is [(1-D)×T, T], where D represents the power supply duty cycle of the drive power supply and T represents the time period.

4. The method according to claim 3, characterized in that, The second preset condition includes: In the adjacent drive power supplies, the power supply duty cycle of the first group of drive power supplies is less than 50%, the power supply duty cycle of the second group of drive power supplies is greater than 50%, and the sum of the power supply duty cycles of the first group of drive power supplies and the second group of drive power supplies is greater than 100%. The power supply time intervals of adjacent drive power supplies satisfy the following: the power supply time interval of one set of drive power supplies is [0, D×T], and the power supply time interval of the other set of drive power supplies is [(1-D)×T, T], where D represents the power supply duty cycle of the drive power supply and T represents the time period.

5. A vertical shift register, characterized in that, include: Multiple cascaded single-stage shift register units; as well as A controller, connected to the drive power supply in the single-stage shift register unit, is used to execute the method according to any one of claims 1 to 4; The single-stage shift register unit includes: Thin-film field-effect transistors; At least two sets of pull-down circuits, wherein one end of each set of pull-down circuits is connected to a target node in the thin-film field-effect transistor, and the target node is the node that controls the gate signal in the thin-film field-effect transistor to be turned off; A drive power supply corresponding to the number of pull-down circuit groups, wherein each drive power supply is connected to the other end of a pull-down circuit group and is used to independently power the pull-down circuit connected to it. When the driving power supply is powered, the pull-down circuit connected to it enters the working state to realize the pull-down control of the target node and shut down the Gate signal in the thin film field-effect transistor.

6. A thin-film field-effect transistor liquid crystal display panel, characterized in that, include: Effective display area, used for image display; The vertical shift register as described in claim 5 is used to drive the effective display area to achieve image display.

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