Method of handling failure of memory, memory controller and memory system

Abstract

Embodiments of the present disclosure provide a method for processing memory failure, a memory controller and a memory system. The method for processing memory failure comprises: in response to a target row address existing in the memory, performing a repair operation on the target row address, wherein the target row address comprises a first target row address, a first count value of the first target row address is greater than a first threshold value or a second count value of the first target row address is greater than a second threshold value; after performing the repair operation on the target row address, determining whether the target row address is successfully repaired; and adjusting the first threshold value and the second threshold value based on a result of whether the target row address is successfully repaired. The method for processing memory failure can avoid unnecessary repair operation on a row address without failure, and more accurately and timely detect and repair a failed row address, thereby reducing the probability of UE.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a method for handling memory failures, a memory controller, and a memory system. Background Technology

[0002] As memory (e.g., Dynamic Random Access Memory (DRAM)) sizes decrease and storage capacities increase, the probability of memory failures also rises. To enhance the reliability, availability, and serviceability (RAS) of storage systems and minimize the probability of errors, memory repair functions have been introduced. For example, the JEDEC memory specification for DDR5 introduces Post-Package Repair (PPR). When the memory system detects a logical row address failure, it can use the DRAM's PPR function to perform a repair operation on the failed row address, thereby effectively reducing the error rate, improving system stability, and ultimately ensuring the normal operation of the memory system. Summary of the Invention

[0003] This disclosure provides at least one embodiment of a method for handling memory faults. The method includes: in response to the presence of a target row address in the memory, performing a repair operation on the target row address, wherein the target row address includes a first target row address, a first count value of the first target row address is greater than a first threshold, or a second count value of the first target row address is greater than a second threshold, the first count value characterizing the number of times that correctable errors exist in data read from the corresponding row address and the correctable errors meet the characteristics of a bounded fault, and the second count value characterizing the number of times that correctable errors exist in data read from the corresponding row address and the correctable errors do not meet the characteristics of a bounded fault; after performing the repair operation on the target row address, determining whether the target row address has been successfully repaired; and adjusting the first threshold and the second threshold based on the result of whether the target row address has been successfully repaired.

[0004] For example, the method provided in at least one embodiment of this disclosure further includes: in response to reaching a time threshold and the existence of a second target row address in the memory, triggering a repair operation on the second target row address, wherein the data read from the second target row address contains correctable errors.

[0005] For example, at least one embodiment of this disclosure provides a method that further includes: counting the number of times the target row address is not successfully repaired to obtain a third count value; and counting the number of times the target row address is successfully repaired to obtain a fourth count value, wherein adjusting the first threshold and the second threshold based on whether the target row address is successfully repaired includes: decreasing the first threshold and the second threshold in response to the third count value being equal to 0 and the fourth count value being greater than 0 within a preset time period; keeping the first threshold and the second threshold unchanged in response to the ratio of the third count value to the fourth count value being greater than 0 and less than the first value; or increasing the first threshold and the second threshold in response to the ratio of the third count value to the fourth count value being greater than the first value and less than the second value.

[0006] For example, in a method provided in at least one embodiment of this disclosure, in response to a third count value being equal to 0 and a fourth count value being greater than 0 within a preset time period, decreasing a first threshold and a second threshold includes: multiplying the first threshold and the second threshold by 0.95 respectively in response to a third count value being equal to 0 and a fourth count value being greater than 0 within a preset time period; keeping the first threshold and the second threshold unchanged in response to a ratio of the third count value to the fourth count value being greater than 0 and less than a first value includes: keeping the first threshold and the second threshold unchanged in response to a ratio of the third count value to the fourth count value being greater than 0 and less than 0.2; increasing the first threshold and the second threshold in response to a ratio of the third count value to the fourth count value being greater than a first value and less than a second value includes: multiplying the first threshold and the second threshold by 1.05 respectively in response to a ratio of the third count value to the fourth count value being greater than or equal to 0.2 and less than 1; multiplying the first threshold and the second threshold by 1.2 respectively in response to a ratio of the third count value to the fourth count value being greater than or equal to 10; and multiplying the first threshold and the second threshold by 1.5 respectively in response to a ratio of the third count value to the fourth count value being greater than or equal to 10.

[0007] For example, in the method provided in at least one embodiment of this disclosure, after each adjustment of the first threshold and the second threshold, the third count value and the fourth count value are cleared to zero.

[0008] For example, in the method provided in at least one embodiment of this disclosure, adjusting the first threshold and the second threshold is performed periodically.

[0009] For example, in at least one embodiment of the method provided in this disclosure, determining whether the target row address has been successfully repaired includes: using repair verification data to perform read and write operations on the repaired target row address to determine whether the target row address has been successfully repaired.

[0010] For example, in at least one embodiment of the method provided in this disclosure, the repair verification data includes first repair verification data and second repair verification data, which are opposites of each other. The repair verification data is used to perform read and write operations on the repaired target row address to determine whether the target row address has been successfully repaired. This includes: traversing all column addresses corresponding to the repaired target row address and writing the first repair verification data into the repaired target row address; traversing all column addresses corresponding to the repaired target row address and reading the first repair verification data written into the repaired target row address; in response to the first repair verification data read from the repaired target row address being correct, traversing all column addresses corresponding to the repaired target row address and writing the second repair verification data into the repaired target row address; traversing all column addresses corresponding to the repaired target row address and reading the second repair verification data written into the repaired target row address; and in response to the second repair verification data read from the repaired target row address being correct, determining that the target row address has been successfully repaired.

[0011] For example, the method provided in at least one embodiment of this disclosure further includes: determining that the target row address has not been successfully repaired in response to the first repair verification data read from the repaired target row address being incorrect, or in response to the second repair verification data read from the repaired target row address being incorrect.

[0012] For example, at least one embodiment of the method provided in this disclosure further includes: in response to the target row address not being successfully repaired, performing a repair undo operation on the repaired target row address.

[0013] For example, in the method provided in at least one embodiment of this disclosure, performing a repair undo operation on the repaired target line address includes: generating and executing a command sequence corresponding to the repair undo operation based on the repaired target line address to undo the repair operation, and releasing the resources used by the repair operation.

[0014] For example, at least one embodiment of the method provided in this disclosure further includes: performing an intermittent error detection operation on the target row address before performing a repair operation on the target row address to determine whether the error of the target row address is an intermittent error; stopping the repair operation on the target row address in response to the error of the target row address being an intermittent error, and performing an intermittent error detection operation on the next target row address of the target row address; and performing a repair operation on the target row address in response to the error of the target row address not being an intermittent error.

[0015] For example, in a method provided in at least one embodiment of this disclosure, an intermittent error detection operation is performed on a target row address, including: writing first detection data to the target row address, traversing all column addresses corresponding to the target row address to read corresponding first detection column data from each column address; writing second detection data to the target row address, traversing all column addresses corresponding to the target row address to read corresponding second detection column data from each column address, wherein the second detection data and the first detection data are opposite to each other; determining erroneous column data in the first and second detection column data, and counting the erroneous column data to obtain a fifth count value, wherein the erroneous column data corresponds to at least one erroneous data pin of the memory, and the number of error bursts corresponding to at least one erroneous data pin is greater than 2, and the initial value of the fifth count is 0; in response to the fifth count value being greater than 0, determining that the error of the target row address is not an intermittent error; and in response to the fifth count value being equal to 0, determining that the error of the target row address is an intermittent error.

[0016] For example, the method provided in at least one embodiment of this disclosure further includes: backing up the data read from the target row address before writing the first detection data to the target row address; and writing the backed-up data back to the repaired target row address after determining whether the target row address has been successfully repaired.

[0017] At least one embodiment of this disclosure also provides a memory controller. The memory controller is used to control a memory and includes: a repair module, a repair verification module, and a threshold adjustment module. The repair module is configured to perform a repair operation on a target row address in response to the presence of a target row address in the memory. The target row address includes a first target row address, a first count value of the first target row address being greater than a first threshold, or a second count value of the first target row address being greater than a second threshold. The first count value represents the number of times that correctable errors exist in data read from the corresponding row address and the correctable errors meet the characteristics of bounded faults. The second count value represents the number of times that correctable errors exist in data read from the corresponding row address and the correctable errors do not meet the characteristics of bounded faults. The repair verification module is configured to determine whether the target row address has been successfully repaired. The threshold adjustment module is configured to adjust a first threshold and a second threshold based on the result of whether the target row address has been successfully repaired.

[0018] For example, at least one embodiment of the memory controller provided in this disclosure further includes a timing module. The timing module is configured to trigger a repair module to perform a repair operation on the second target row address in response to reaching a time threshold and the presence of a second target row address in the memory, wherein the data read from the second target row address contains correctable errors.

[0019] For example, the memory controller provided in at least one embodiment of this disclosure further includes a first counter and a second counter. The first counter is configured to count the number of times the target row address is not successfully repaired, obtaining a third count value. The second counter is configured to count the number of times the target row address is successfully repaired, obtaining a fourth count value. The threshold adjustment module is further configured to: decrease the first threshold and the second threshold in response to the third count value being equal to 0 and the fourth count value being greater than 0 within a preset time period; keep the first threshold and the second threshold unchanged in response to the ratio of the third count value to the fourth count value being greater than 0 and less than the first value; or increase the first threshold and the second threshold in response to the ratio of the third count value to the fourth count value being greater than the first value and less than the second value.

[0020] For example, the memory controller provided in at least one embodiment of this disclosure further includes an intermittent error detection module. Before the repair module performs a repair operation on the target row address, the intermittent error detection module is configured to perform an intermittent error detection operation on the target row address to determine whether the error at the target row address is an intermittent error; in response to the error at the target row address being an intermittent error, the repair module is configured to stop performing the repair operation on the target row address, and the intermittent error detection module is configured to perform an intermittent error detection operation on the next target row address; and in response to the error at the target row address not being an intermittent error, the repair module is configured to perform a repair operation on the target row address.

[0021] At least one embodiment of this disclosure also provides a memory system, which includes a processor and a memory controller provided in any embodiment of this disclosure. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0023] Figure 1 A schematic diagram illustrating an exemplary DRAM repair method based on the PPR mechanism is shown.

[0024] Figure 2A A schematic diagram of an exemplary DRAM memory cell array is shown;

[0025] Figure 2B A schematic diagram illustrating an exemplary memory controller accessing memory is shown;

[0026] Figure 3A A schematic diagram of an exemplary memory controller accessing memory is shown;

[0027] Figure 3B It shows Figure 3AThe diagram shows the structure of the register array in the memory controller.

[0028] Figure 4 A flowchart of a method for handling memory failures according to at least one embodiment of the present disclosure is shown;

[0029] Figure 5 A flowchart illustrating the repair line address according to at least one embodiment of the present disclosure is shown;

[0030] Figure 6 A flowchart illustrating the adaptive adjustment of a first threshold and a second threshold according to at least one embodiment of the present disclosure is shown;

[0031] Figure 7 A flowchart of occasional error detection according to at least one embodiment of the present disclosure is shown;

[0032] Figure 8 A flowchart illustrating the periodic triggering of row address repair according to at least one embodiment of the present disclosure is shown;

[0033] Figure 9 A flowchart illustrating the detection and repair of faulty line addresses according to at least one embodiment of the present disclosure is shown;

[0034] Figure 10 A schematic diagram of a memory controller according to at least one embodiment of the present disclosure is shown;

[0035] Figure 11 A schematic diagram of a memory controller accessing memory according to at least one embodiment of the present disclosure is shown;

[0036] Figure 12 A schematic diagram of a memory system provided in at least one embodiment of the present disclosure is shown;

[0037] Figure 13 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown; and

[0038] Figure 14 A schematic diagram of a non-transiently readable storage medium according to at least one embodiment of the present disclosure is shown. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0040] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0041] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0042] First, the abbreviations and related terms involved in this application are defined and explained.

[0043] Dynamic Random Access Memory (DRAM): A type of semiconductor memory capable of temporarily storing data in a computer system. DRAM consists of multiple memory cells, each representing binary data by storing electrical charge in a capacitor. Data is maintained and prevented from being lost by periodically refreshing the capacitor's state.

[0044] Double Data Rate (DDR) refers to a memory technology that can transfer twice the amount of data per clock cycle. For example, DDR5 generally refers to fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory, a high-speed computer memory based on DRAM technology.

[0045] Post-Package Repair (PPR): A technique defined in the JEDEC memory specification for DDR5 that repairs memory row faults using a fixed instruction process after DRAM packaging. PPR technology includes hard Post-Package Repair (hPPR) and soft Post-Package Repair (sPPR).

[0046] Hard Post-Package Repair (hPPR): A technique that permanently repairs faulty memory cells after DRAM packaging, and the repaired information remains effective even after power is lost.

[0047] Soft Post-Package Repair (sPPR): A technique that repairs faulty memory cells by configuring the internal logic of the DRAM after it has been packaged, and the repair information is invalid after power is turned off.

[0048] Error checking and correcting (ECC) is a technology used to detect and correct errors during data transmission or storage. ECC detects errors by adding extra parity bits to the raw data and then performing calculations on the parity bits and data bits using a specific algorithm when reading or receiving data. If an error is detected, its location can be determined based on the parity information, and it can be automatically corrected.

[0049] UE (Uncorrectable Error): An error that cannot be corrected.

[0050] CE (Correctable Error): An error that can be corrected.

[0051] Soft errors are data errors caused by external interference or transient abnormal conditions, without permanent damage to the hardware itself. Soft errors are usually temporary and do not have a permanent impact on the physical structure of the system.

[0052] A hard error is an error caused by physical damage or defect in the hardware itself. Hard errors are usually permanent and require hardware-level repair or replacement.

[0053] Bounded fault: A data error mode defined in the JEDEC memory specification for DDR5. For example, if a memory cell in a storage system fails, and the resulting data queuing (DQ) errors are limited to a finite number of DQs, then the fault is called a "bounded fault".

[0054] Data Quadrature (DQ): Also known as "Data Pin" or DQ interface, it is a set of parallel data lines for data transmission between DRAM and external devices.

[0055] Nibble: One nibble consists of 4 bits of data, and one byte consists of 2 nibs.

[0056] Data Device: A storage device that stores data, such as in DDR memory, also known as a data memory chip.

[0057] ECC Device: A storage chip that stores parity bits, such as in DDR memory, also known as a parity memory chip.

[0058] Storage chips: Data storage chips and parity storage chips are collectively referred to as storage chips. For example, in DDR memory, storage chips are also called memory chips, and can be used as a general term for both data memory chips and parity memory chips.

[0059] It is understood that the terms defined above are merely exemplary definitions for a specific application scenario, in order to better understand this application. For example, the exemplary definitions for a specific type of memory described above can be extended to other types of memory.

[0060] Figure 1 A schematic diagram illustrating an exemplary DRAM repair method based on the PPR mechanism is shown. Because... Figure 1 The diagram shown illustrates application scenarios for DRAM memory. (See attached diagram.) Figure 1 The described storage unit can also correspond to a memory unit, and the memory controller can also correspond to a memory controller.

[0061] like Figure 1 As shown, DRAM 100 includes multiple memory cells, for example... Figure 1 Storage units 102, 103, and 105. Multiple storage units are divided into primary storage units and redundant storage units. For example... Figure 1As shown, the storage units to the left of the dashed line (such as storage units 102 and 105) are primary storage units, while the storage units to the right of the dashed line (such as storage unit 103) are redundant storage units. There is a one-to-one mapping between primary storage units and logical row addresses, allowing for precise location of the corresponding primary storage unit through the logical row address, thus enabling efficient read and write operations. There is no mapping between redundant storage units and logical row addresses, and under normal circumstances, redundant storage units do not directly participate in regular data storage and access processes, but rather serve as backup resources for primary storage units.

[0062] For example, when the row address Address_102 corresponding to storage cell 102 fails, the repair module 111 in the memory controller 110 performs a repair operation (such as a PPR operation) on the row address Address_102. That is, the repair module 111 remaps the row address Address_102 corresponding to storage cell 102 to a redundant storage cell (such as storage cell 103) so that the memory controller 110 can still access the row address Address_102 normally for read and write operations without reading or writing errors.

[0063] For example, PPR operations can include sPPR mode and hPPR mode. In sPPR mode, DRAM 100 retains the data in the memory array (i.e., multiple memory cells). After completing the sPPR operation, the memory controller 110 can perform normal read and write operations on DRAM 100, and the time required for the sPPR operation is the same as the time required to access the row address normally. After a power outage or restart of the memory system, the repair information corresponding to the sPPR operation (e.g., the mapping relationship between row address Address_102 and memory cell 103) will be lost. In hPPR mode, DRAM 100 cannot retain the data in the memory array; that is, the data in the memory array will disappear after the hPPR operation is performed, and the time required for the hPPR operation is much longer than the time required for the sPPR operation. After a power outage or restart of the memory system, the repair information corresponding to the hPPR operation (e.g., the mapping relationship between row address Address_102 and memory cell 103) remains valid.

[0064] For example, Figure 2A A schematic diagram of an exemplary DRAM memory cell array is shown.

[0065] like Figure 2AAs shown, the DRAM includes multiple memory cells 220_0~220_15, a main word line driver 200, and multiple sub word line drivers 210_0~210_14. The main word line driver 200 and the sub word line drivers 210_0~210_14 are coupled via a global word line. The multiple sub word line drivers 210_0~210_14 and the multiple memory cells 220_0~220_15 are connected via local word lines and according to... Figure 2A The coupling is as shown.

[0066] When the memory controller accesses a row address, the corresponding main word line driver 200 drives multiple sub-word line drivers 210_0~210_14. These sub-word line drivers 210_0~210_14 drive their respective coupled memory cells, allowing the capacitance sensing circuits (LSA) 230_0~230_15 to read data from their respective coupled memory cells and send the read data to the serial-to-parallel converters (SERDES) 240_0~240_15. The SERDES converts the parallel data into serial data, which is then transmitted via the DQ interface (or data pins). When the main word line driver 200 fails, all data pins (i.e., DQ0~DQ7) will experience read / write errors. When a sub-word line driver fails, some data pins will experience read / write errors. For example, when... Figure 2A When the sub-word line driver 210_13 in the middle fails, read / write errors occur on the data pins DQ6 and DQ7 coupled to the sub-word line driver 210_13.

[0067] Errors caused by failures in the main word line driver or sub-word line driver are permanent errors. Although the memory controller's ECC module can correct erroneous data (i.e., data transmitted on the data pin where the read / write error occurred) using the ECC algorithm, this weakens the ECC module's ability to correct other intermittent errors, thus increasing the probability of UE (User Error Detection) in the memory system. The following section combines... Figure 2B This will be described exemplarily.

[0068] 2B shows a schematic diagram of an exemplary memory controller accessing memory.

[0069] like Figure 2B As shown, the memory includes four data storage chips 220-223 and one parity storage chip 224. The structure of the data storage chip 220 can be referred to... Figure 2A“X8” indicates that the data bus width of this memory chip is 8 bits and includes 8 data pins (or 8 DQ interfaces). “BL=16” indicates that the burst length of this memory chip is 16. The data storage chip 220 transmits 8 bits of data through data pins DQ0~DQ7 in one read operation. Among them, the data transmitted by data pins DQ0~DQ3 (i.e., DQ[3:0]) belongs to the same half byte (e.g., Nibble A), and the data transmitted by data pins DQ4~DQ7 (i.e., DQ[7:4]) belongs to another half byte (e.g., Nibble B). The data storage chip 220 transmits a total of 16 Burst * 8 bits = 128 bits of data in one read operation.

[0070] The memory controller 210 includes a data verification module 211, a data correction unit 212, a data receiver 213, and an ECC data receiver 214. The data receiver 213 is coupled to the data storage particles 220-223 to receive data transmitted through data pins DQ0-DQ31 (i.e., DQ[31:0]), and the ECC data receiver 214 is coupled to the verification memory particle 224 to receive verification data transmitted through data pins DQ_ECC0-DQ_ECC7 (i.e., DQ_ECC[7:0]).

[0071] For example, when Figure 2A When the sub-word line driver 210_13 in the memory fails, read / write errors occur on data pins DQ6 and DQ7. The data verification module 211 detects errors in the data transmitted on data pins DQ6 and DQ7, and the data correction unit 212 corrects the erroneous data. In this situation, if other memory chips (e.g., data storage chip 223) experience errors (e.g., intermittent or fixed errors) exceeding the error correction capability of the data correction module 212, the probability of a UE (User Error Detection) in the memory system increases. Furthermore, the data verification module 211 and the data correction module 212 can be integrated into the ECC (Extended Computation and Correction) module, in which case the ECC module is used to detect data errors and correct them.

[0072] However, the repair capabilities of the ECC module in a storage system (such as a memory system) are limited. After a faulty row address occurs, the probability of a UE (Uncorrectable Error) in the storage system increases. In the first exemplary method, the storage system typically interrupts normal operation upon detecting an uncorrectable error (UE), monitors the faulty row address through a memory self-test mode, and then repairs the faulty row address by performing a PPR (Proof-of-Repair) operation. However, this method requires the detection and repair of the faulty row address to be initiated based on the reporting of the UE error; that is, the detection and repair of the faulty row address only begins after a UE occurs. Therefore, this method cannot detect and repair the faulty row address in a timely manner after it has failed.

[0073] A second exemplary method is to record the row address where a correctable error (CE) occurs and perform a repair operation (PPR) on the corresponding row address when the CE count exceeds a threshold. However, CEs in a storage system can also be caused by random errors within the DRAM or column address faults. Therefore, based on the CE threshold, it is impossible to accurately determine whether a row address fault has occurred within the DRAM. For example, when a column address fault occurs in the DRAM, the CE count may also exceed the threshold, triggering a repair operation (e.g., a PPR operation). However, the PPR operation cannot repair column address faults and will also perform unnecessary repair operations on fault-free row addresses, resulting in a waste of PPR resources.

[0074] To more accurately determine whether a row address fault has occurred inside the DRAM and to repair the detected faulty row address in a timely manner, the second exemplary method above introduces a process to detect whether the CE corresponding to the row address meets the bounded fault characteristics. Based on the number of times the CE at that row address meets the bounded fault characteristics or the number of times the CE at that row address does not meet the bounded fault characteristics, the row address that needs to perform PPR operation is determined.

[0075] For example, Figure 3A A schematic diagram of an exemplary memory controller accessing memory is shown. Figure 3B It shows Figure 3A The diagram shows the structure of the register array in the memory controller.

[0076] like Figure 3A As shown, the memory controller 310 includes an ECC module 311, a CE detection module 312, a bounded fault detection module 313, an address queue 314, a register array 315, an address selection module 316, and a repair module 317.

[0077] like Figure 3A As shown, address queue 314 is configured to store address information for each read operation. Figure 3BAs shown, register array 315 includes one or more entries (e.g., Entry0~Entry2), and register array 315 is configured to store address information, a first count value, and a second count value of the row address (e.g., Address_302) in response to a correctable error in data read for a row address (e.g., Address_302) of memory 300. The first field (also called the "bounded fault field") of each entry records the first count value for the corresponding row address, and the second field (also called the "correctable error field") records the second count value for the corresponding row address. For example, the address information of the row address may include information such as the DRAM Device ID, bank group, bank address, row address, and DQ group information.

[0078] ECC module 311 is configured to detect whether there are errors in the data read from a row address (e.g., Address_302) of memory 300. If the data is erroneous, ECC module 311 corrects the erroneous data based on the ECC algorithm, and CE detection module 312 is configured to detect the error type of the data. If CE detection module 312 determines that the error type of the data is CE, it sends a first signal to address queue 314, causing address queue 314 to send the address information of the row address (e.g., Address_302) to register array 315. After the CE detection module 312 determines that the error belongs to a CE, the bounded fault detection module 313 further detects whether the CE meets the characteristics of a bounded fault. If the CE meets the characteristics of a bounded fault, the bounded fault detection module 313 can send a high-level second signal to the address queue 314 so that when the address information of the row address (e.g., Address_302) is written into the table entry (e.g., Entry0) of the register array 315, the first count value of the row address (e.g., Address_302) is incremented by 1 (e.g., the value of the first field of Entry0 is incremented by 1). If the CE does not meet the characteristics of a bounded fault, the bounded fault detection module 313 can send a low-level second signal to the address queue 314 so that when the address information of the row address (e.g., Address_302) is written into the table entry (e.g., Entry0) of the register array 315, the second count value of the row address (e.g., Address_302) is incremented by 1 (e.g., the value of the second field of Entry0 is incremented by 1).

[0079] When a target entry exists in register array 315, register array 315 can send a third signal to address selection module 316 to initiate a repair operation. Address selection module 316 is configured to select a target entry from register array 315 upon receiving the third signal, and use the row address corresponding to the selected target entry as the row address to be repaired by repair module 317. Repair module 317 performs a repair operation (e.g., PPR operation) on the selected row address. Here, "target entry" refers to the entry occupied by the row address with a high probability of triggering the UE, such as an entry with a first count value greater than a first threshold or a second count value greater than a second threshold.

[0080] The inventors of this disclosure note that, in the above combination Figure 3A and Figure 3B In the described method, the threshold conditions used to initiate the repair operation (i.e., the first threshold and the second threshold) are generally set based on empirical values ​​from post-silicon testing. Therefore, the threshold conditions are easily affected by the number and type of test samples and are difficult to set accurately. Moreover, the setting of the threshold conditions affects the reliability of the repair operation; that is, too small a threshold may lead to a waste of repair resources, while too large a threshold may affect the accuracy and timeliness of detecting faulty row addresses.

[0081] On the other hand, a column address fault or a DQ path fault in the memory may also cause the CE count to exceed the second threshold, thus triggering a repair operation (e.g., a PPR operation). However, the PPR operation cannot repair column address faults and DQ path faults. In this case, the repair operation triggered will perform unnecessary repair operations on the non-faulty row addresses, resulting in a waste of repair resources.

[0082] This disclosure provides one or more embodiments of a method, memory controller, and memory system for handling memory faults. After performing a repair operation on a row address, by determining whether the row address was successfully repaired, unnecessary repair operations on non-faulty row addresses due to column address faults or DQ path faults can be avoided. Based on the result of whether the row address was successfully repaired, the threshold for triggering the repair operation can be adaptively adjusted, making the set threshold more accurate.

[0083] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0084] Figure 4A flowchart of a method for handling memory failures according to at least one embodiment of the present disclosure is shown, the method including steps S410, S420 and S430.

[0085] Step S410: In response to the presence of a target row address in the memory, a repair operation is performed on the target row address. The target row address includes a first target row address, wherein a first count value of the first target row address is greater than a first threshold, or a second count value of the first target row address is greater than a second threshold.

[0086] Step S420: After performing the repair operation on the target row address, determine whether the target row address has been successfully repaired.

[0087] Step S430: Adjust the first threshold and the second threshold based on whether the target row address has been successfully repaired.

[0088] In step S410, the first count value represents the number of times that the data read from the corresponding row address contains a correctable error and that the correctable error meets the characteristics of a bounded fault. The second count value represents the number of times that the data read from the corresponding row address contains a correctable error and that the correctable error does not meet the characteristics of a bounded fault. For example, for data read from a certain row address, it can be determined whether there is a correctable error through an error correction process. If there is a correctable error, it can be determined whether it meets the characteristics of a bounded fault. If it does, a first counting operation can be performed to obtain a first count value. If it does not meet the characteristics, a second counting operation can be performed to obtain a second count value.

[0089] Correctable errors (CE) are errors within the error correction capabilities of the ECC algorithm, while uncorrectable errors (UE) are errors exceeding the error correction capabilities of the ECC algorithm. Bounded faults are a data error mode defined in the JEDEC memory specification for DDR5; the specific definition will not be elaborated here.

[0090] In some embodiments of this disclosure, a correctable error can be determined to conform to the characteristics of a bounded fault when any of the following conditions are met.

[0091] Condition 1: The number of error data pins corresponding to the data is 1, and the number of error bursts corresponding to the error data pins is greater than the error burst threshold.

[0092] Condition 2: The number of error data pins corresponding to the data is 2, the data read from the 2 error data pins belongs to the same half byte, and the total number of error bursts corresponding to the 2 error data pins is greater than the error burst threshold.

[0093] Condition 3: The number of erroneous data pins corresponding to the data is greater than half the number of data pins of the memory chip, and all erroneous data pins belong to the same memory chip in the memory.

[0094] For example, the "error data pin" in the above conditions is the same as the "error DQ," meaning that the data transmitted by the error DQ contains an error. Within a burst, if the data transmitted by the data pin contains an error, then that burst is the "error burst" in the above conditions.

[0095] For example, the error burst threshold can be 4, or it can be set according to actual needs, or a suitable value can be obtained based on model training or based on experience. This disclosure does not impose any restrictions on this.

[0096] For example, such as Figure 2B As shown, when the error DQ corresponding to the data is DQ6, and the number of error bursts corresponding to DQ6 is greater than the error burst threshold, the correctable errors in the data meet the above condition 1. Therefore, the correctable errors in the data meet the characteristics of bounded faults.

[0097] For example, such as Figure 2A As shown, when the sub-word line driver 210_13 malfunctions, read / write errors occur on data pins DQ6 and DQ7. In this case, the number of error DQ pins corresponding to the data is 2. Figure 2B As shown, the data read from the two error data pins DQ6 and DQ7 belongs to the same half-byte. If the total number of error bursts corresponding to DQ6 and DQ7 is greater than the error burst threshold, then the correctable errors in this data meet condition 2 above. Therefore, the correctable errors in this data meet the characteristics of a bounded fault.

[0098] For example, such as Figure 2B As shown, each memory chip has 8 data pins. When the number of error DQs corresponding to the data is greater than 4 (for example, error DQs are DQ0, DQ1, DQ3, DQ6 and DQ7), since DQ0, DQ1, DQ3, DQ6 and DQ7 all belong to memory chips 220 in the memory, the correctable errors in the data meet the above condition 3. Therefore, the correctable errors in the data meet the characteristics of bounded faults.

[0099] In some embodiments of this disclosure, the repair operation performed on the target row address in step S410 may include: generating a sequence of encapsulated repair operations based on the target row address to repair the target row address, wherein the generated command sequence can establish a new mapping relationship for the target row address. For example, Figure 3AAs shown, the target row address Address_302 is remapped from the main storage unit 302 to a new storage unit (e.g., redundant storage unit 303), thereby achieving the repair of the target row address.

[0100] It should be noted that the repair operation in the embodiments of this disclosure includes post-package repair (PPR) operation, which can be sPPR operation or hPPR operation, and this disclosure does not limit it.

[0101] For step S420, after performing the repair operation on the target row address, it is also necessary to perform a verification operation on the repaired target row address to determine whether the target row address has been successfully repaired.

[0102] For example, if the target row address is successfully repaired, the repair operation is valid. Conversely, if the target row address is not successfully repaired, it indicates that the target row address may not have experienced a row address fault, or the correctable errors in the data read from the target row address are caused by faults other than row address faults. For example, a column address fault or a DQ path fault corresponding to the target row address could cause correctable errors in the data. In this case, the repair operation cannot repair these faults, the repair operation is invalid, and an unnecessary repair operation was performed on a perfectly good target row address.

[0103] In some embodiments of this disclosure, repair verification data (e.g., clock signal data, 01010101) can be used to perform read and write operations on the repaired target row address to determine whether the target row address has been successfully repaired. For example, step S420 may include: writing repair verification data to the repaired target row address; determining that the target row address has been successfully repaired in response to the repair verification data read from the repaired target row address being correct; and determining that the target row address has not been successfully repaired in response to the repair verification data read from the repaired target row address being incorrect.

[0104] For example, the repair verification data may include first repair verification data and second repair verification data, and the first repair verification data and the second repair verification data are opposites of each other. For example, the first repair verification data may be 0x00 (i.e., 00000000) and the second repair verification data may be 0xFF (i.e., 11111111). The first repair verification data and the second repair verification data can be set according to the actual situation, and this disclosure does not limit them. For example, the first repair verification data and the second repair verification data may include any combination of high level (i.e., 1) and low level (i.e., 0).

[0105] The embodiments of this disclosure can effectively eliminate interference from occasional errors introduced by signal integrity by using, for example, all 0s (i.e., 00000000), all 1s (i.e., 11111111) or clock signal data to verify whether the row address has been successfully repaired.

[0106] Examples of using repair verification data to perform read and write operations on the repaired target row address to determine whether the target row address has been successfully repaired are not limited to this.

[0107] In some embodiments, repair verification data may be written to the repaired target row address; in response to the repair verification data read from the repaired target row address being correct, it is determined that the target row address has been successfully repaired; and in response to the repair verification data read from the repaired target row address being incorrect, it is determined that the target row address has not been successfully repaired.

[0108] In some embodiments, the verification data can be a single data point or multiple data points.

[0109] In some embodiments, two repair verification data that are opposite to each other can be used to perform read and write operations on the repaired target row address to determine whether the target row address has been successfully repaired.

[0110] When verifying the validity of the repair operation using the first repair verification data and the second repair verification data, step S420 may include steps S4201, S4202, S4203, S4204 and S4205.

[0111] Step S4201: Traverse all column addresses corresponding to the repaired target row address and write the first repair verification data into the repaired target row address.

[0112] Step S4202: Traverse all column addresses corresponding to the repaired target row address, and read the first repair verification data written into the repaired target row address.

[0113] Step S4203: In response to the first repair verification data read from the repaired target row address being correct (i.e., the first repair verification data read from the repaired target row address is consistent with the first repair verification data written to the repaired target row address), traverse all column addresses corresponding to the repaired target row address and write the second repair verification data to the repaired target row address.

[0114] Step S4204: Traverse all column addresses corresponding to the repaired target row address, and read the second repair verification data written into the repaired target row address.

[0115] Step S4205: In response to the second repair verification data read from the repaired target row address being correct (i.e., the second repair verification data read from the repaired target row address is consistent with the second repair verification data written to the repaired target row address), it is determined that the target row address has been successfully repaired.

[0116] If both the first repair verification data and the second re-verification data read from the repaired target row address are correct, the target row address is successfully repaired, and the repair operation is valid.

[0117] For example, step S420 above may also include step S4204, in response to the first repair verification data read from the repaired target row address being incorrect, or in response to the second repair verification data read from the repaired target row address being incorrect, determining that the target row address has not been successfully repaired.

[0118] For step S4204, if the first repair verification data read from the repaired target row address (e.g., 00000010) is inconsistent with the first repair verification data written to the repaired target row address (e.g., 00000000), or if the second repair verification data read from the repaired target row address (e.g., 11111101) is inconsistent with the second repair verification data written to the repaired target row address (e.g., 11111111), then it is determined that the target row address has not been successfully repaired, and the repair operation is invalid.

[0119] In some embodiments of this disclosure, by traversing all column addresses corresponding to the target row address, the storage unit of a row is filled with data. Since some faults may cause the storage unit to only be able to read data 0 or only be able to read data 1, the effectiveness of the repair operation is verified by using a pair of opposite data (i.e., the first repair verification data and the second repair verification data). Both data 0 and data 1 can be checked to ensure that there are no errors in the storage unit (i.e., the row address has been successfully repaired). It can also check whether the storage unit corresponding to each address and the address decoding path are working properly, so as not to miss some potential faults of specific addresses.

[0120] Although the above embodiments describe writing the second repair verification data to the repaired target row address after traversing all column addresses corresponding to the repaired target row address in response to the confirmation that the first repair verification data read from the repaired target row address is correct, i.e., the second repair verification data needs to be written to the repaired target row address only after confirming that the first repair verification data read from the repaired target row address is correct, the embodiments of this disclosure are not limited to this. For example, both the first and second repair verification data can be written to the repaired target row address, and then it can be determined whether the first and second repair verification data read from the repaired target row address are correct.

[0121] In some embodiments of this disclosure, in response to the target row address not being successfully repaired (i.e., the repair operation being invalid), a repair undo operation can be performed on the repaired target row address.

[0122] For example, if it is determined that the target row address has not been successfully repaired (i.e., the repair operation is invalid), the repair operation previously performed on the target row address can be undone to avoid performing unnecessary repair operations on the target row address that has not failed, thereby avoiding the waste of repair resources.

[0123] For example, performing a repair undo operation on the repaired target row address may include: generating and executing a command sequence corresponding to the repair undo operation based on the repaired target row address to undo the repair operation performed on the target row address and releasing the resources used by the repair operation.

[0124] Here, the command sequence corresponding to the repair / undo operation meets the JEDEC standard. The resources used by the repair operation can be... Figure 3A The row address used to replace the faulty row address in the redundant storage unit 303.

[0125] For example, Figure 5 A flowchart illustrating the repair line address according to at least one embodiment of the present disclosure is shown.

[0126] The following example uses the sPPR operation to repair the row address, combined with... Figure 5 Describe it.

[0127] Step S500: Start the row address repair process.

[0128] Step S501: Select a row address Row0 that meets the conditions.

[0129] It should be noted that when step S500 is triggered because there is a row address in the memory with a first count greater than the first threshold or a second count greater than the second count value, the "row address that meets the conditions" in step S501 is the row address with the first count greater than the first threshold or the second count greater than the second count value.

[0130] It should be noted that when step S500 is due to Figure 3A When the storage space of the register array 315 shown is full and the process is triggered to determine the target entry for writing new row address information, the "matching row address Row0" in step S501 is the row address corresponding to the target entry. The target entry is the entry in register array 315 with the largest first count value (i.e., the value of the first field is the largest). If there are multiple entries with the largest first count value, then an entry with the largest second count value (i.e., the value of the second field is the largest) is selected from these multiple entries as the target entry.

[0131] It's important to note that the term "maximum" here is somewhat ambiguous. Specifically, only the high-order bits (e.g., the high 3 bits or 4 bits) of the first and second fields of each entry can be compared, while the low-order bits (e.g., ignoring the low 2 bits when comparing sizes, thus blurring 0-3 error differences) can be considered. For example, the entry in register array 315 with the largest value in the high-order bits of the first field can be selected as the target entry. If multiple entries have the largest values ​​in the high-order bits of their first field, then the entry with the largest value in the high-order bits of its second field can be selected as the target entry.

[0132] Step S502: Perform intermittent error detection on row address Row0 (corresponding to steps S400 and S502 described below). Figure 7 ).

[0133] Step S503: If row address Row0 passes the intermittent error detection, then based on row address Row0, generate an sPPR command sequence and execute the sPPR command sequence to complete the repair operation on row address Row0.

[0134] Step S504: Periodically send refresh commands to the memory.

[0135] It should be noted that step S504 is used to keep the data in the memory unchanged, thereby preventing data loss. If it is not necessary to keep the data in the memory unchanged, step S504 can be skipped.

[0136] Step S505: Initiate the verification process for the sPPR operation.

[0137] The following steps S506~S511 are used to determine whether row address Row0 has been successfully repaired, that is, to verify whether the sPPR operation performed on row address Row0 is effective.

[0138] Step S506: Traverse all column addresses corresponding to the repaired row address Row0, and write data D0 (i.e., "first repair verification data") to the repaired row address Row0.

[0139] Step S507: Traverse all column addresses corresponding to the repaired row address Row0, and read data D0 from the repaired row address Row0.

[0140] Step S508: Determine whether the read data D0 is correct.

[0141] For example, if the data D0 read from the repaired row address Row0 is consistent with the data D0 written from the repaired row address Row0, then the read data D0 is determined to be correct, and step S509 is executed.

[0142] For example, if the data D0 read from the repaired row address Row0 is inconsistent with the data D0 written from the repaired row address Row0, then it is determined that the read data D0 is incorrect, and step S513 is executed.

[0143] Step S509: Traverse all column addresses corresponding to the repaired row address Row0, and write data ~D0 (i.e., "second repair verification data") to the repaired row address Row0. Data ~D0 and data D0 are the opposite of each other.

[0144] Step S510: Traverse all column addresses corresponding to the repaired row address Row0, and read data ~D0 from the repaired row address Row0.

[0145] Step S511: Determine if the read data ~D0 is correct.

[0146] For example, if the data ~D0 read from the repaired row address Row0 is consistent with the data ~D0 written from the repaired row address Row0, then it is determined that the read data ~D0 is correct, and the sPPR operation is valid (step S509), and the row address Row0 is successfully repaired.

[0147] For example, if the data ~D0 read from the repaired row address Row0 is inconsistent with the data ~D0 written from the repaired row address Row0, then it is determined that the read data ~D0 is incorrect, and step S513 is executed.

[0148] Step S513: Perform an sPPR-undo operation (i.e., "repair undo operation") on the repaired row address Row0 to undo the sPPR operation performed on row address Row0 in step S503 and release the sPPR resources used by the sPPR operation.

[0149] If the data corresponding to row address Row0 was backed up before executing step S502, then after executing step S512 or step S513, regardless of whether row address Row0 was successfully repaired, the backed-up data needs to be written back to the repaired row address Row0 (step S514). If the data corresponding to row address Row0 was not backed up before executing step S502, step S514 can be skipped.

[0150] Step S515: Select the next matching row address Row1.

[0151] It is important to note that when the "qualified row address Row0" in step S501 is a row address whose first count is greater than the first threshold or whose second count is greater than the second count (e.g., Row0), regardless of whether the sPPR operation successfully repairs row address Row0, it is necessary to traverse all "qualified row addresses" to perform intermittent error detection, sPPR operation, and sPPR operation verification processes on all "qualified row addresses" (i.e., steps S502 to S515). In this case, the "next qualified row address Row1" in step S515 is another row address other than row address Row0 whose first count is greater than the first threshold or whose second count is greater than the second count.

[0152] It should be noted that when the "qualified row address Row0" in step S501 is the row address corresponding to the target entry (e.g., entry Entry0) in the register array, if the sPPR operation successfully repairs row address Row0 (i.e., step S512 determines that the sPPR operation performed on row address Row0 is valid), then after step S514 (if any), Figure 5 The row address repair process shown ends. If the sPPR operation fails to repair row address Row0, after executing steps S513 and S514 (if any), step S515 needs to be executed to select the next eligible row address Row1 (for example, the row address corresponding to another target table entry in the register array other than table entry Entry0).

[0153] For step S430 above, based on the result of whether the target row address has been successfully repaired (also known as the "historical repair success rate"), the first threshold and the second threshold are adjusted so that the adjusted first threshold and the second threshold are more accurate and more applicable to the actual repair process, thereby improving the reliability of the repair operation and enabling more timely detection and repair of faulty row addresses.

[0154] In some embodiments of this disclosure, the number of times the target row address is not successfully repaired (or the number of invalid repair operations) can be counted to obtain a third count value; and the number of times the target row address is successfully repaired (or the number of valid repair operations) can be counted to obtain a fourth count value. Then, based on the ratio of the third count value and the fourth count value, the first threshold and the second threshold are adjusted.

[0155] For example, step S430 may include steps S4301 to S4303.

[0156] Step S4301: In response to the third count value being equal to 0 and the fourth count value being greater than 0 within a preset time period, decrease the first threshold and the second threshold;

[0157] Step S4302: In response to the ratio of the third count value to the fourth count value being greater than 0 and less than the first value, keep the first threshold and the second threshold unchanged; or

[0158] Step S4303: In response to the ratio of the third count value to the fourth count value being greater than the first value and less than the second value, increase the first threshold and the second threshold.

[0159] Here, "preset time period" can be understood as the execution cycle of step S430, such as 24 hours or other time. The definition of "first value" and "second value", and the increase or decrease ratio of the first threshold and the second threshold can be set by the user according to actual needs or based on the experience of the operator. This disclosure does not impose any restrictions on this.

[0160] For example, step S4301 may include: in response to a third count value being equal to 0 and a fourth count value being greater than 0 within a preset time period, multiplying the first threshold and the second threshold by 0.95 respectively.

[0161] For example, step S4302 may include: in response to the ratio of the third count value to the fourth count value being greater than 0 and less than 0.2, keeping the first threshold and the second threshold unchanged.

[0162] For example, step S4303 may include: in response to the ratio of the third count value to the fourth count value being greater than or equal to 0.2, multiplying the first threshold and the second threshold by 1.05 respectively.

[0163] For example, the case of "increasing the first threshold and the second threshold" can be further divided into multiple levels to more accurately adjust the first threshold and the second threshold. For example, step S4303 may include: in response to the ratio of the third count value to the fourth count value being greater than or equal to 0.2 and less than 1, multiplying the first threshold and the second threshold by 1.05 respectively; in response to the ratio of the third count value to the fourth count value being greater than or equal to 1 and less than 10, multiplying the first threshold and the second threshold by 1.2 respectively; in response to the ratio of the third count value to the fourth count value being greater than or equal to 10, multiplying the first threshold and the second threshold by 1.5 respectively.

[0164] It should be noted that the adjustment ratios of the first and second thresholds in the above examples (e.g., multiplying by 0.95, 1.05, 1.2 or 1.5, etc.) and the comparison ranges of the ratios (e.g., 0, 0~0.2, 0.2~1, 1~10, etc.) are merely illustrative and this disclosure does not impose any limitations on them.

[0165] For example, in some embodiments of this disclosure, the first threshold and the second threshold may be adjusted periodically. For example, step S430 may be performed once every 24 hours.

[0166] For example, after each adjustment of the first and second thresholds, the third and fourth count values ​​are reset to zero, and invalid and valid repair operations within the next preset time period (e.g., 24 hours) are recounted to obtain new third and fourth count values. Based on the new third and fourth count values, the first and second thresholds are adjusted according to the method described above.

[0167] For example, Figure 6 A flowchart illustrating adaptive adjustment of a first threshold and a second threshold according to at least one embodiment of the present disclosure is shown.

[0168] like Figure 6 As shown, the example is performing an sPPR operation on a row address. Figure 6 In this context, "sPPR_undo" (the third value) represents the number of times the repair undo operation was performed, that is, the number of times the row address was not successfully repaired by the sPPR operation, or the number of times an invalid sPPR operation was performed; "sPPR_ok" (the fourth value) represents the number of times the row address was successfully repaired by the sPPR operation, or the number of times a valid sPPR operation was performed. The "threshold" in steps S607, S609, S611, S613, and S615 actually represents the first threshold and the second threshold.

[0169] like Figure 6 As shown, step S600: Set the period threshold. That is, set the above-mentioned "preset time period", for example, it can be set to 24 hours.

[0170] Step S601: Set the values ​​of sPPR_undo and sPPR_ok to 0.

[0171] Step S602: Count sPPR_undo and sPPR_ok based on whether an sPPR_undo operation (i.e., the above "repair undo operation") is performed on the row address.

[0172] For example, if the current sPPR operation is triggered by the target row address (where the first count of the target row address is greater than the first threshold or the second count is greater than the second count value), and the current sPPR operation fails to repair the target row address, then the sPPR_undo operation will be executed, thereby incrementing the value of sPPR_undo by 1; if the current sPPR operation successfully repairs the target row address, then the sPPR_undo operation will not be executed, thereby incrementing the value of sPPR_ok by 1.

[0173] Step S604: When the set periodic threshold is reached, a periodic check operation on the threshold is triggered. For example, every 24 hours, based on the current values ​​of sPPR_undo and sPPR_ok, it is checked whether the first and second thresholds need to be adjusted.

[0174] Step S606: Determine whether the ratio of sPPR_undo to sPPR_ok is greater than or equal to 10.

[0175] If the ratio of sPPR_undo to sPPR_ok is greater than or equal to 10, it indicates that many invalid sPPR operations have been performed in the past 24 hours. In this case, it is necessary to increase the first threshold and the second threshold to reduce invalid sPPR operations, thereby reducing the waste of sPPR resources. Therefore, step S607 can be executed, multiplying both thresholds (i.e., the first threshold and the second threshold) by 1.5.

[0176] Step S608: Determine whether the ratio of sPPR_undo to sPPR_ok is greater than or equal to 1 and less than 10.

[0177] If the ratio of sPPR_undo to sPPR_ok is greater than or equal to 1 and less than 10, it indicates that a large number of invalid sPPR operations have been performed, for example, in the past 24 hours, and the first and second thresholds need to be slightly increased. Therefore, step S609 can be performed to multiply both thresholds (i.e., the first and second thresholds) by 1.2.

[0178] Step S610: Determine whether the ratio of sPPR_undo to sPPR_ok is greater than or equal to 0.2 and less than 1. In response to the ratio of sPPR_undo to sPPR_ok being greater than or equal to 0.2 and less than 1, proceed to step S611, multiplying both thresholds (i.e., the first threshold and the second threshold) by 1.05.

[0179] Step S612: Determine whether the ratio of sPPR_undo to sPPR_ok is greater than 0 and less than 0.2.

[0180] If the ratio of sPPR_undo to sPPR_ok is greater than 0 and less than 0.2, it indicates that there were few invalid sPPR operations performed in the past 24 hours, which is within an acceptable range. Therefore, step S613 can be performed to keep the thresholds (i.e., the first threshold and the second threshold) unchanged.

[0181] Step S614: Determine whether the value of sPPR_undo is equal to 0 and whether the value of sPPR_ok is greater than 0.

[0182] If the value of sPPR_undo is equal to 0 and the value of sPPR_ok is greater than 0, it indicates that the sPPR operations performed in the past 24 hours have been valid, and there may be a large number of faulty row addresses in the memory. Therefore, the first and second thresholds need to be reduced to repair the faulty row addresses more promptly. Thus, step S615 can be executed, multiplying the thresholds (i.e., the first and second thresholds) by 0.95.

[0183] Therefore, the method provided in at least one embodiment of this disclosure can adaptively adjust the first threshold and the second threshold for triggering the repair operation based on whether the row address has been successfully repaired, so as to make the set first threshold and the second threshold more accurate and thereby improve the timeliness of repairing faulty row addresses.

[0184] In some embodiments of this disclosure, the method for handling memory faults may further include step S400 before performing step S410 ("perform repair operation on target row address") described above.

[0185] Step S400: Perform an intermittent error detection operation on the target row address to determine whether the error in the target row address is an intermittent error; in response that the error in the target row address is an intermittent error, stop performing the repair operation on the target row address and perform an intermittent error detection operation on the next target row address; and in response that the error in the target row address is not an intermittent error, perform the repair operation on the target row address.

[0186] For example, occasional errors are temporary and can be fixed by rereading the data.

[0187] For example, if the error at the target row address is an intermittent error (i.e., the target row address fails the intermittent error detection), it means that the data error at that target row address was caused by an intermittent error. If the repair operation is continued to be performed on the target row address, it will lead to the incorrect repair of intact row addresses, resulting in a waste of repair resources. Therefore, it is necessary to stop performing the repair operation on the target row address and perform the intermittent error detection operation on the next target row address.

[0188] For example, if the error at the target row address is not an intermittent error (i.e., the target row address passes the intermittent error detection), it means that the data error at that target row address is not caused by an intermittent error, and a repair operation can be performed on that target row address. After performing the repair operation, step S420 can be performed on the repaired target row address to verify whether the repair operation is effective, thereby further determining whether the data error at the target row address is caused by a fault in the target row address or by a fault in the column address corresponding to the target row address, etc.

[0189] For example, the specific steps of performing an intermittent error detection operation on a target row address may include: writing first detection data to the target row address, traversing all column addresses corresponding to the target row address to read the corresponding first detection column data from each column address; writing second detection data to the target row address, traversing all column addresses corresponding to the target row address to read the corresponding second detection column data from each column address, wherein the second detection data and the first detection data are opposite to each other; determining the erroneous column data in the first and second detection column data, and counting the erroneous column data to obtain a fifth count value, wherein the erroneous column data corresponds to at least one erroneous data pin of the memory, and the number of error bursts corresponding to at least one erroneous data pin is greater than 2, and the initial value of the fifth count is 0; in response to the fifth count value being greater than 0, determining that the error at the target row address is not an intermittent error; and in response to the fifth count value being equal to 0, determining that the error at the target row address is an intermittent error.

[0190] In some embodiments of this disclosure, after the target row address is repaired, the data originally stored in the target row address may continue to be used. Therefore, the data can be backed up in advance.

[0191] For example, before writing the first detection data to the target row address, the data read from the target row address is backed up; and after determining whether the target row address has been successfully repaired, the backed-up data is written back to the repaired target row address.

[0192] Figure 7 A flowchart of occasional error detection according to at least one embodiment of the present disclosure is shown, corresponding to Figure 5 Step S502 in [the document / section]. This is understandable; see [reference needed]. Figure 7 The described sporadic error detection is merely exemplary and can be implemented using other methods. Figure 5 Step S502 in the process.

[0193] The following is combined with Figure 7 This section describes the process of performing occasional error detection on a target row address (e.g., row address Row0).

[0194] Step S700: Start the intermittent error detection process.

[0195] Step S701: Select the row address Row0 that meets the criteria.

[0196] It should be noted that the row address selected in step S701, Row0, is the same as the one mentioned above. Figure 5 In step S501, the selected row address is Row0.

[0197] Step S702: Read back the data in row address Row0 and back up the data.

[0198] For example, data read back from row address Row0 can be backed up to redundant storage units or non-volatile memory, and this disclosure does not limit this.

[0199] Step S703: Write data D0 (i.e., "first detection data") to row address Row0 and reset the value of the counter to 0.

[0200] Step S704: Send a read instruction to a column address (e.g., column0) corresponding to row address Row0.

[0201] For example, if there is an error in the column data read from column address 0 corresponding to row address Row0, and the erroneous column data corresponds to at least one error DQ, and the number of error bursts corresponding to the error DQ is greater than 2 (step S705), then step S706 is executed to increment the value of the counter by 1.

[0202] For example, if the column data read back from the column address column0 corresponding to row address Row0 is correct, skip step S706 and proceed directly to step S707.

[0203] Step S707: Determine whether the read instruction has been completed for all column addresses corresponding to row address Row0.

[0204] For example, if it is determined that the read instructions for all column addresses corresponding to row address Row0 have not yet been completed, then step S708 is executed to increment the current column address by 1, that is, to determine the next column address (e.g., column1) of the current column address (e.g., column0), and then send a read instruction to column address column1 corresponding to row address Row0.

[0205] For example, loop steps S704~S708 traverse all column addresses corresponding to row address Row0, thereby completing the read instruction for all column addresses of row address Row0.

[0206] Step S709: Write data ~D0 (i.e., "second detection data") to row address Row0. Data ~D0 is the opposite of data D0 in step S703 above.

[0207] The subsequent steps S710~S714 are similar to the steps S704~S708 described above, and will not be repeated here.

[0208] It should be noted that the counter used in steps S706 and S712 is the same counter, and the value of the counter is not cleared before step S712 is executed.

[0209] After reading and writing all column addresses of row address Row0 using the first and second detection data, step S715 is executed.

[0210] Step S715: Determine if the value of the counter is greater than 0.

[0211] Step S715 above is used to determine whether the error at row address Row0, which is used for intermittent error detection, is an intermittent error (soft error).

[0212] For example, if Counter is greater than 0, it is determined that the error at row address Row0 is not a soft error, and a repair operation needs to be performed on row address Row0 (step S719) to repair the fault (e.g., a hard error) present at row address Row0. For detailed procedures, please refer to [link to relevant documentation]. Figure 5 Steps S503 to S514 will not be repeated here.

[0213] For example, if Counter equals 0, then it is determined that the error at row address Row0 is a soft error (step S716), and then step S717 is executed.

[0214] Step S717: Write the backed-up data back to row address Row0.

[0215] When it is determined that the error at row address Row0 is a soft error, it means that the data backed up in step S702 is correct. Therefore, there is no need to perform subsequent repair operations on row address Row0. Instead, the backed-up data is directly written back to row address Row0.

[0216] Step S718: Delete the register array (e.g.) Figure 3A The table entry occupied by row address Row0 in the register array 315 shown continues to perform occasional error detection for the next matching row address.

[0217] According to at least one embodiment of the present disclosure, the method for handling memory faults can avoid unnecessary repair operations on row addresses that have not experienced faults due to occasional errors by performing an intermittent error detection operation on the row addresses before performing repair operations. This allows the detection of row addresses that have actually experienced faults and avoids the waste of repair resources.

[0218] In some embodiments of this disclosure, a time threshold can be set for the repair operation in this disclosure so that the repair operation is performed periodically on all row addresses in the memory where CE occurs (i.e., "second target row addresses"), thereby repairing faulty row addresses more promptly and reducing the possibility of UE occurrence.

[0219] For example, a method for handling memory failures may further include step S440: in response to reaching a time threshold and the presence of a second target row address in the memory, triggering a repair operation on the second target row address, wherein data read from the second target row address contains a correctable error.

[0220] For example, address information, first count, and second count of all second target row addresses in memory can be stored in a register array.

[0221] Figure 8 A flowchart illustrating the periodic triggering of row address repair according to at least one embodiment of the present disclosure is shown.

[0222] like Figure 8 As shown, the first time threshold (i.e., the "time threshold" in step S440) can be 48 hours. For example, every 48 hours (step S800), the repair process for the second target row address can be automatically triggered (or started) (step S800). This "repair process" includes an occasional error detection operation, a repair operation, and an operation to determine whether the row address has been successfully repaired (also known as a "repair verification operation"). The occasional error detection operation in step S803 can be referenced... Figure 7 The repair operations in steps S702~S719 and step S806 can be referred to Figure 5The repair and verification operations for steps S503-S504 and step S807 can be referred to Figure 5 Steps S505 to S514 will not be repeated here.

[0223] When the first time threshold is reached (step S800), regardless of whether there is a first target row address in the memory with a first count value greater than the first threshold or a second count value greater than the second threshold, the second target row address in the memory is traversed to perform an occasional error detection operation, a repair operation, and a repair verification operation.

[0224] For example, there may be multiple second target row addresses in the memory. After the repair process is started, step S802 is executed to select a second target row address (e.g., Row0) from the memory (or register array) to perform subsequent operations. For example, the intermittent error detection operation can be performed starting from the second target row address corresponding to the end of the previous repair process, or a second target row address can be randomly selected to start the intermittent error detection operation; this disclosure does not limit this.

[0225] If the second target row address Row0 fails the intermittent error detection (i.e., the error at the second target row address Row0 is a soft error), then step S805 is executed to select the next second target row address (e.g., Row1) from the memory (or register array) to continue the intermittent error detection operation.

[0226] If the second target row address Row0 passes the intermittent error detection (i.e., the error in the second target row address Row0 is a hard error), then steps S806 and S807 are executed to perform a repair operation and a repair verification operation on the second target row address Row0.

[0227] If the second target row address Row0 is successfully repaired, the repair process triggered by the arrival time threshold ends (step S809). If the second target row address Row0 is not successfully repaired, step S805 is executed to select the next second target row address (e.g., Row1) from the memory (or register array) to continue the intermittent error detection operation.

[0228] For example, to reduce the impact on memory access bandwidth, the memory controller cannot continuously perform repair operations. Therefore, a second time threshold can be set for the repair process (e.g., 20 microseconds, 30 microseconds, etc.), and the second time threshold is less than the first time threshold. When the second time threshold is reached, the repair process automatically ends.

[0229] Therefore, in the method for handling memory failures provided in at least one embodiment of this disclosure, by performing an intermittent error detection operation before the repair operation and a repair verification operation after the repair operation, the dependence of detecting and repairing faulty row addresses on accurately setting a threshold can be reduced. For example, a smaller threshold can be used to initiate the repair operation, thereby enabling more timely detection and repair of faulty row addresses.

[0230] Figure 9 A flowchart illustrating the detection and repair of faulty line addresses according to at least one embodiment of this disclosure is shown. It can be understood that... Figure 9 This description is merely an exemplary description in a scenario where memory is used as the storage medium, and this disclosure is not limited thereto. See also: Figure 9 The flowchart described can be applied to other memory systems with or without modification.

[0231] like Figure 9 As shown, step S901: Power on the memory system to start up and perform related initialization operations.

[0232] Step S902: The memory system enters normal operating mode.

[0233] Step S903: Determine whether the data being read or written is correct.

[0234] If the data read and written is correct, return to step S902 and continue to execute the normal working mode.

[0235] If the data to be read or written is incorrect, proceed to step S904.

[0236] Step S904: Determine whether the error in the currently read / written data is a correctable error (CE).

[0237] If the error in the data is not a CE (Error Correction) but an Uncorrectable Error (UE), then proceed to step S905 (i.e., restart the memory system).

[0238] If the error in the data belongs to CE, then both steps S906 and S907 are executed simultaneously.

[0239] Step S906: Correct the current data.

[0240] Step S907: Generate a fault flag and record the address information of the row address corresponding to the current data. The fault flag is used to indicate whether the current data's CE (Criterion Detection) meets the characteristics of a bounded fault. The steps for determining whether a CE meets the characteristics of a bounded fault can refer to conditions 1-3 of the above embodiments, and will not be repeated here.

[0241] Step S908: Determine whether a first entry exists in the register array. The address information recorded in the first entry is consistent with the address information of the row address corresponding to the current data.

[0242] If the first entry exists in the register array, proceed to step S909; otherwise, proceed to step S912.

[0243] Step S909: Determine the count value that needs to be updated based on the fault flag.

[0244] If the fault flag indicates that CE meets the characteristics of a bounded fault, then step S910 is executed to increment the first count value in the first entry by 1.

[0245] If the fault flag indicates that CE does not meet the characteristics of a bounded fault, then step S911 is executed to increment the second count value in the first entry by 1.

[0246] Step S912: If the register array does not have a first entry, determine whether the register array has a second entry. The second entry is any idle entry in the register array.

[0247] If a second entry exists in the register array, then step S913 is executed, storing the address information of the row address of the current data into the second entry, and adjusting the value of the corresponding field in the second entry according to the fault flag (for example, see...). Figure 3B The value of the first or second field in the description is set to 1.

[0248] If the register array does not contain a second entry, then proceed to step S914.

[0249] Step S914: Check if there is an entry to be replaced in the register array. The entry to be replaced is the entry in the register array whose first count value is 0 and whose second count value is the smallest.

[0250] If there is an entry to be replaced in the register array, then proceed to step S915.

[0251] Step S915: Delete the information stored in the table entry to be replaced, store the address information of the row address of the current data into the table entry to be replaced, and set the value of the corresponding field in the table entry to be replaced to 1 according to the fault flag.

[0252] After performing steps S910, S911, S913 or S915, perform step S916.

[0253] Step S916: Determine whether there exists a first target row address in the register array whose first field value is greater than the first threshold or whose second field value is greater than the second threshold.

[0254] If the first target row address exists in the register array, then step S918 is executed to initiate the repair process for the first target row address. The specific steps of the repair process can be found in [reference needed]. Figure 8 This will not be elaborated upon here.

[0255] If there is no entry to be replaced in the register array, proceed to step S917.

[0256] Step S917: Determine the target entry in the register array and perform a repair operation on the row address occupying the target entry. The specific steps for determining the target entry can be referred to the above embodiment, and will not be repeated here.

[0257] After executing step S917, step S918 is executed to initiate the repair process for the row address occupying the target table entry. The specific steps of the repair process can be found in [reference needed]. Figure 8 This will not be elaborated upon here.

[0258] When the time threshold is reached (step S919), step S918 is executed to start the repair process for all second target row addresses where CE exists.

[0259] Figure 10 A schematic diagram of a memory controller 1000 according to at least one embodiment of the present disclosure is shown.

[0260] See Figure 10 The memory controller 1000 includes a repair module 1010, a repair verification module 1020, and a threshold adjustment module 1030.

[0261] Repair module 1010 is configured to perform a repair operation on a target row address in response to the presence of a target row address in the memory. The target row address includes a first target row address, a first count value of the first target row address being greater than a first threshold, or a second count value of the first target row address being greater than a second threshold. The first count value represents the number of times that correctable errors exist in the data read from the corresponding row address and that the correctable errors meet the characteristics of a bounded fault. The second count value represents the number of times that correctable errors exist in the data read from the corresponding row address and that the correctable errors do not meet the characteristics of a bounded fault.

[0262] The repair verification module 1020 is configured to determine whether the target row address has been successfully repaired.

[0263] The threshold adjustment module 1030 is configured to adjust the first threshold and the second threshold based on whether the target row address has been successfully repaired.

[0264] Thus, the memory controller according to at least one embodiment of the present disclosure can avoid unnecessary repair operations on row addresses that have not failed, and can detect and repair faulty row addresses more accurately and in a more timely manner, thereby reducing the probability of UE occurrence.

[0265] Figure 11 A schematic diagram of a memory controller accessing memory according to at least one embodiment of the present disclosure is shown.

[0266] like Figure 11 As shown, the repair module 1117, repair verification module 1118, and threshold adjustment module 1119 in the memory controller 1110 can be found in [reference needed]. Figure 10 The repair module 1010, the repair verification module 1020, and the threshold adjustment module 1030 are described.

[0267] For example, when the repair operation of the repair module 1117 includes a post-encapsulation repair operation, the repair module 1117 is configured to generate a command sequence of post-encapsulation repair operations based on the target row address to repair the target row address.

[0268] For example, the memory controller 1110 may also optionally include a refresh module 1124. The refresh module 1124 is configured to periodically send refresh commands to the memory 1100 to keep the data in the memory 1100 unchanged, thereby preventing data loss in the memory 1100.

[0269] For example, memory controller 1110 may also include time module 1123. Time module 1123 is configured to trigger repair module 1117 to perform a repair operation on the second target row address in response to reaching a time threshold and the presence of a second target row address in memory 1100, wherein the data read from the second target row address contains a correctable error.

[0270] For example, the memory controller 1110 may also include a first counter and a second counter ( Figure 11 (Not shown in the image). The first counter is configured to count the number of times the target row address is not successfully repaired, obtaining a third count value. The second counter is configured to count the number of times the target row address is successfully repaired, obtaining a fourth count value. The threshold adjustment module 1119 is also configured to: decrease the first threshold and the second threshold in response to the third count value being equal to 0 and the fourth count value being greater than 0 within a preset time period; keep the first threshold and the second threshold unchanged in response to the ratio of the third count value to the fourth count value being greater than 0 and less than the first value; or increase the first threshold and the second threshold in response to the ratio of the third count value to the fourth count value being greater than the first value and less than the second value.

[0271] For example, the threshold adjustment module 1119 can also be configured to: multiply the first threshold and the second threshold by 0.95 respectively in response to the third count value being equal to 0 and the fourth count value being greater than 0 within a preset time period; keep the first threshold and the second threshold unchanged in response to the ratio of the third count value to the fourth count value being greater than 0 and less than 0.2; multiply the first threshold and the second threshold by 1.05 respectively in response to the ratio of the third count value to the fourth count value being greater than or equal to 0.2 and less than 1; multiply the first threshold and the second threshold by 1.2 respectively in response to the ratio of the third count value to the fourth count value being greater than or equal to 1 and less than 10; and multiply the first threshold and the second threshold by 1.5 respectively in response to the ratio of the third count value to the fourth count value being greater than or equal to 10.

[0272] For example, after the threshold adjustment module 1119 adjusts the first threshold and the second threshold, the values ​​of the first counter and the second counter are cleared to zero (that is, the third counter value and the fourth counter value are cleared to zero).

[0273] For example, the threshold adjustment module 1119 can periodically adjust the first threshold and the second threshold.

[0274] For example, the repair verification module 1118 can be configured to use repair verification data to perform read and write operations on the repaired target row address to determine whether the target row address has been successfully repaired.

[0275] For example, the repair verification data includes first repair verification data and second repair verification data, which are opposites of each other. The repair verification module 1118 can also be configured to: traverse all column addresses corresponding to the repaired target row address and write the first repair verification data into the repaired target row address; traverse all column addresses corresponding to the repaired target row address and read the first repair verification data written into the repaired target row address; in response to the first repair verification data read from the repaired target row address being correct, traverse all column addresses corresponding to the repaired target row address and write the second repair verification data into the repaired target row address; traverse all column addresses corresponding to the repaired target row address and read the second repair verification data written into the repaired target row address; and in response to the second repair verification data read from the repaired target row address being correct, determine that the target row address has been successfully repaired.

[0276] For example, the repair verification module 1118 can also be configured to: determine that the target row address has not been successfully repaired in response to the first repair verification data read from the repaired target row address being incorrect, or in response to the second repair verification data read from the repaired target row address being incorrect.

[0277] For example, the memory controller 1110 may also include a repair undo module 1120. The repair undo module 1120 is configured to perform a repair undo operation on the repaired target row address in response to the target row address not being successfully repaired.

[0278] For example, the repair undo module 1120 can be configured to generate and execute a sequence of commands corresponding to the repair undo operation based on the repaired target row address to undo the repair operation and release the resources used by the repair operation.

[0279] For example, the memory controller 1110 may also include an intermittent error detection module 1121. Before the repair module 1117 performs a repair operation on the target row address, the intermittent error detection module 1121 is configured to perform an intermittent error detection operation on the target row address to determine whether the error at the target row address is an intermittent error. In response to the error at the target row address being an intermittent error, the repair module 1117 is configured to stop performing the repair operation on the target row address, and the intermittent error detection module 1121 is configured to perform an intermittent error detection operation on the next target row address. In response to the error at the target row address not being an intermittent error, the repair module 1117 is configured to perform a repair operation on the target row address.

[0280] For example, the intermittent error detection module 1121 can be configured to: write first detection data to a target row address, traverse all column addresses corresponding to the target row address to read corresponding first detection column data from each column address; write second detection data to the target row address, traverse all column addresses corresponding to the target row address to read corresponding second detection column data from each column address, wherein the second detection data and the first detection data are opposite to each other; determine the erroneous column data in the first and second detection column data, and count the erroneous column data to obtain a fifth count value, wherein the erroneous column data corresponds to at least one erroneous data pin of the memory, and the number of error bursts corresponding to at least one erroneous data pin is greater than 2, and the initial value of the fifth count is 0; in response to the fifth count value being greater than 0, determine that the error at the target row address is not an intermittent error; and in response to the fifth count value being equal to 0, determine that the error at the target row address is an intermittent error.

[0281] For example, the memory controller 1110 may also include a backup module 1122. Before the intermittent error detection module 1121 writes the first detection data to the target row address, the backup module 1122 is configured to back up the data read from the target row address. After the repair verification module 1118 determines whether the target row address has been successfully repaired, the backup module 1122 is configured to write the backed-up data back to the repaired target row address.

[0282] For example, the memory controller 1110 may also include a bounded fault detection module 1113, a register array 1115, and an address selection module 1116. Its functions and principles can be found in [reference needed]. Figure 3A The bounded fault detection module 313, register array 315 and address selection module 316 shown are not described in detail here.

[0283] For example, the memory controller 1110 may also include an ECC module 1111, a CE detection module 1112, and an address queue 1114. The address queue 1114 is configured to store address information for each read operation. The ECC module 1111 is configured to detect whether there is an error in the data read for a row address (e.g., Address_1102) of the memory 1100. If the data is erroneous, the ECC module 1111 corrects the erroneous data based on the ECC algorithm, and the CE detection module 1112 is configured to detect the error type of the erroneous data. If the CE detection module 1112 determines that the error belongs to CE, it sends a first signal CE_hit to the address queue 1114, causing the address queue 1114 to send the address information of the row address (e.g., Address_1102) to the register array 1115. After the CE detection module 1112 determines that the error belongs to a CE, the bounded fault detection module 1113 will further detect whether the CE meets the characteristics of a bounded fault. If the CE meets the characteristics of a bounded fault, the bounded fault detection module 1113 can send a high-level second signal Bounded_hit to the address queue 1114 to increment the first count value of the row address (e.g., Address_1102). If the CE does not meet the characteristics of a bounded fault, the bounded fault detection module 1113 can send a low-level second signal Bounded_hit to the address queue 1114 to increment the second count value of the row address (e.g., Address_1102).

[0284] For example, Figure 11 The structure of register array 1115 in the middle can be referred to Figure 3B The structure of register array 315 is shown. When there is an entry in register array 1115 where the first count value (i.e., the value of the first field) is greater than the first threshold or the second count value (i.e., the value of the second field) is greater than the second threshold, or when the storage space of register array 1115 is full and new row address information needs to be written, register array 1115 sends a third signal Loop_start to address selection module 1116. Alternatively, when a time threshold is reached, time module 1123 sends a time signal Timeout to register array 1115, causing register array 1115 to send the third signal Loop_start to address selection module 1116.

[0285] When the address selection module 1116 receives the third signal Loop_start, it initiates the row address repair process. The address selection module 1116 selects a matching row address from the register array 1115 and sends the selected row address to the occasional error detection module 1121 to perform occasional error detection, thereby determining whether the error in the selected row address is an occasional error. If the error in the selected row address passes the occasional error detection (i.e., the error in the selected row address is not an occasional error), the occasional error detection module 1121 sends the row address to the repair module 1117 for repair.

[0286] For example, the address selection module 1116 can also send the selected row address directly to the repair module 1117 for repair operation, and this disclosure does not limit this.

[0287] For example, after the repair module 1117 performs a repair operation on the row address, it sends the repaired row address to the repair verification module 1118 to determine whether the row address has been successfully repaired. If the repair verification module 1118 determines that the row address has not been successfully repaired, it sends the repaired row address to the repair cancellation module 1120 to cancel the repair operation performed by the repair module 1117 on the row address. Regardless of whether the row address has been successfully repaired, the repair verification module 1118 sends the determination result to the threshold adjustment module 1119 so that the threshold adjustment module 1119 updates the third and fourth count values, thereby adjusting the first and second thresholds.

[0288] As described above, the memory controller according to at least one embodiment of this disclosure, after repairing a row address, can avoid unnecessary repair operations on row addresses that have not experienced faults due to column address faults or DQ path faults by determining whether the row address has been successfully repaired, thereby avoiding waste of repair resources. Based on the result of whether the row address has been successfully repaired, the threshold for triggering the repair operation can be adaptively adjusted to make the set threshold more accurate.

[0289] The additional aspects of the memory controller according to at least one embodiment of the present disclosure can correspond to the additional aspects of the method for handling memory failures according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the method for handling memory failures according to at least one embodiment of the present disclosure can also be mapped to the additional aspects of the memory controller according to at least one embodiment of the present disclosure, which will not be repeated here.

[0290] Figure 12 A schematic diagram of a memory system provided in at least one embodiment of the present disclosure is shown.

[0291] At least one embodiment of this disclosure also provides a memory system 1200, which includes a memory 1201 (e.g., may include...). Figure 1 The DRAM memory 100 shown Figure 3A The memory 300 shown or Figure 11 The memory 1100 shown) and the memory controller 1202 provided in any embodiment of this disclosure (e.g., may include memory controller 1202) Figure 10 The memory controller 1000 shown or Figure 11 The memory controller 1110 shown is shown.

[0292] For example, memory 1201 can be any memory that memory controller 1202 can control.

[0293] The technical effects of the memory system in the above embodiments of this disclosure are the same as those of the method for handling memory faults described above, and therefore will not be repeated here.

[0294] Figure 13 A schematic diagram of an electronic device 1300 according to at least one embodiment of the present disclosure is shown.

[0295] like Figure 13 As shown, the electronic device 1300 includes a processor 1310 and a memory 1320. The memory 1320 includes one or more computer program modules 1321. The one or more computer program modules 1321 are stored in the memory 1320 and configured to be executed by the processor 1310. These computer program modules 1321 include instructions for performing a method for handling memory failures according to at least one embodiment of the present disclosure. When executed by the processor 1310, they can perform one or more steps of the method for handling memory failures according to at least one embodiment of the present disclosure and its additional aspects. The memory 1320 and the processor 1310 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown). For example, the bus may be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc.

[0296] For example, processor 1310 may be a central processing unit (CPU), a digital signal processor (DSP), or other form of processor with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) may be an x86 or ARM architecture, a RISC-V architecture, etc. Processor 1310 may be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 1300 to perform desired functions.

[0297] For example, memory 1320 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules 1321 may be stored on the computer-readable storage medium, and processor 1310 may run one or more computer program modules 1321 to implement various functions of electronic device 1300. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0298] For example, electronic device 1300 may also include input devices such as touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, and gyroscopes; output devices such as liquid crystal displays, speakers, and vibrators; storage devices such as magnetic tapes and hard disks (HDDs or SDDs); and communication devices such as network interface cards such as LAN cards and modems. The communication devices allow electronic device 1300 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. A drive is connected to the I / O interface as needed. Removable storage media, such as disks, optical disks, magneto-optical disks, and semiconductor memories, are installed on the drive as needed so that computer programs read from them can be installed into the storage device as required.

[0299] For example, the electronic device 1300 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0300] The electronic device 1300 may be, for example, a system-on-a-chip (SOC) or a device including the SOC. For instance, it can be any device such as a mobile phone, tablet computer, laptop computer, e-reader, game console, television, digital photo frame, navigator, home appliance, communication base station, industrial controller, server, etc. It can also be any combination of operating devices and hardware for a memory controller; the embodiments of this disclosure do not limit this. The specific functions and technical effects of the electronic device 1300 can be found in the above description of the method for handling memory faults and its additional aspects according to at least one embodiment of this disclosure, and will not be repeated here.

[0301] At least one embodiment of this disclosure also provides a computer-readable storage medium storing computer-readable instructions thereon. When a processor executes the computer-readable instructions, the processor performs the method for handling memory failures provided in any of the above embodiments.

[0302] Figure 14 A schematic diagram of a non-transiently readable storage medium 1400 according to at least one embodiment of the present disclosure is shown.

[0303] like Figure 14 As shown, a non-transiently readable storage medium 1400 stores computer instructions 1410, which, when executed by a processor, perform one or more steps of the method for handling memory failures as described above and its additional aspects.

[0304] For example, the non-transiently readable storage medium 1400 may be any combination of one or more computer-readable storage media.

[0305] For example, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium, performing one or more steps of a method for handling memory failures and its additional aspects, as described in at least one embodiment of this disclosure.

[0306] For example, the non-transitory readable storage medium may include a memory card for a smartphone, a storage component for a tablet computer, a hard disk for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, and other non-transitory readable storage media or any combination thereof.

[0307] In addition to the illustrative examples described above, the following points also need to be noted:

[0308] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0309] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0310] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A method for handling memory faults, comprising: In response to the presence of a target row address in the memory, a repair operation is performed on the target row address, wherein the target row address includes a first target row address, a first count value of the first target row address is greater than a first threshold or a second count value of the first target row address is greater than a second threshold, the first count value represents the number of times that the data read from the corresponding row address contains a correctable error and the correctable error conforms to the characteristics of a bounded fault, and the second count value represents the number of times that the data read from the corresponding row address contains the correctable error and the correctable error does not conform to the characteristics of the bounded fault; After performing the repair operation on the target row address, determine whether the target row address has been successfully repaired; and Based on whether the target row address has been successfully repaired, the first threshold and the second threshold are adjusted.

2. The method according to claim 1, further comprising: In response to reaching a time threshold and the presence of a second target row address in the memory, the repair operation is triggered on the second target row address, wherein the data read from the second target row address contains the correctable error.

3. The method according to claim 1, further comprising: The number of times the target row address was not successfully repaired is counted to obtain a third count value; as well as The number of times the target row address was successfully repaired was counted to obtain a fourth count value. The step of adjusting the first threshold and the second threshold based on whether the target row address has been successfully repaired includes: In response to the third count value being equal to 0 and the fourth count value being greater than 0 within a preset time period, the first threshold and the second threshold are reduced; In response to the ratio of the third count value to the fourth count value being greater than 0 and less than the first value, the first threshold and the second threshold remain unchanged; or In response to the ratio of the third count value to the fourth count value being greater than the first value and less than the second value, the first threshold and the second threshold are increased.

4. The method according to claim 3, wherein, The response to the third count value being equal to 0 and the fourth count value being greater than 0 within a preset time period, decreasing the first threshold and the second threshold, includes: In response to the third count value being equal to 0 and the fourth count value being greater than 0 within a preset time period, the first threshold and the second threshold are multiplied by 0.95 respectively; The step of keeping the first threshold and the second threshold unchanged in response to the ratio of the third count value to the fourth count value being greater than 0 and less than the first value includes: In response to the ratio of the third count value to the fourth count value being greater than 0 and less than 0.2, the first threshold and the second threshold remain unchanged; The step of increasing the first threshold and the second threshold in response to the ratio of the third count value to the fourth count value being greater than the first value and less than the second value includes: In response to the ratio of the third count value to the fourth count value being greater than or equal to 0.2 and less than 1, the first threshold and the second threshold are each multiplied by 1.

05. In response to the ratio of the third count value to the fourth count value being greater than or equal to 1 and less than 10, the first threshold and the second threshold are multiplied by 1.2 respectively. In response to the ratio of the third count value to the fourth count value being greater than or equal to 10, the first threshold and the second threshold are multiplied by 1.5 respectively.

5. The method according to claim 3 or 4, wherein, After each adjustment of the first threshold and the second threshold, the third count value and the fourth count value are reset to zero.

6. The method according to any one of claims 1-4, wherein, The adjustment of the first threshold and the second threshold is performed periodically.

7. The method according to claim 1, wherein, Determining whether the target row address has been successfully repaired includes: The repair verification data is used to perform read and write operations on the repaired target row address to determine whether the target row address has been successfully repaired.

8. The method according to claim 7, wherein, The repair verification data includes first repair verification data and second repair verification data, wherein the first repair verification data and the second repair verification data are opposites of each other. The step of using repair verification data to perform read and write operations on the repaired target row address to determine whether the target row address has been successfully repaired includes: Traverse all column addresses corresponding to the repaired target row address and write the first repair verification data into the repaired target row address; Traverse all column addresses corresponding to the repaired target row address, and read the first repair verification data written into the repaired target row address; In response to the confirmation that the first repair verification data read from the repaired target row address is correct, all column addresses corresponding to the repaired target row address are traversed, and the second repair verification data is written to the repaired target row address; Iterate through all column addresses corresponding to the repaired target row address, and read the second repair verification data written into the repaired target row address; and In response to the confirmation that the second repair verification data read from the repaired target row address is correct, it is determined that the target row address has been successfully repaired.

9. The method according to claim 8, further comprising: If the first repair verification data read from the repaired target row address is incorrect, or if the second repair verification data read from the repaired target row address is incorrect, it is determined that the target row address has not been successfully repaired.

10. The method according to claim 1, further comprising: In response to the failure to successfully repair the target row address, a repair undo operation is performed on the repaired target row address.

11. The method according to claim 10, wherein, The step of performing a repair undo operation on the repaired target row address includes: Based on the repaired target row address, generate and execute the command sequence corresponding to the repair undo operation to undo the repair operation and release the resources used by the repair operation.

12. The method according to claim 1, further comprising: Before performing the repair operation on the target row address, perform an intermittent error detection operation on the target row address to determine whether the error in the target row address is an intermittent error; In response to the fact that the error at the target row address is an intermittent error, the repair operation for the target row address is stopped, and the intermittent error detection operation is performed on the next target row address of the target row address. as well as In response that the error at the target row address is not an occasional error, the repair operation is performed on the target row address.

13. The method according to claim 12, wherein, The operation of performing intermittent error detection on the target row address includes: Write the first detection data to the target row address, and traverse all column addresses corresponding to the target row address to read the corresponding first detection column data from each column address; The second detection data is written to the target row address, and all column addresses corresponding to the target row address are traversed to read the corresponding second detection column data from each column address, wherein the second detection data is the opposite of the first detection data; The erroneous column data in the first detection column data and the second detection column data are determined, and the erroneous column data is counted to obtain a fifth count value, wherein the erroneous column data corresponds to at least one erroneous data pin of the memory, and the number of erroneous bursts corresponding to the at least one erroneous data pin is greater than 2, and the initial value of the fifth count is 0; In response to the fifth count value being greater than 0, it is determined that the error at the target row address does not belong to the occasional error; and In response to the fifth count value being equal to 0, it is determined that the error in the target row address belongs to the occasional error.

14. The method of claim 13, further comprising: Before writing the first detection data to the target row address, the data read from the target row address is backed up; as well as After determining whether the target row address has been successfully repaired, the backed-up data is written back to the repaired target row address.

15. A memory controller for controlling a memory, comprising: A repair module is configured to perform a repair operation on a target row address in response to the presence of a target row address in the memory. The target row address includes a first target row address, wherein a first count value of the first target row address is greater than a first threshold or a second count value of the first target row address is greater than a second threshold. The first count value represents the number of times that correctable errors exist in the data read from the corresponding row address and the correctable errors meet the characteristics of a bounded fault. The second count value represents the number of times that correctable errors exist in the data read from the corresponding row address and the correctable errors do not meet the characteristics of a bounded fault. The repair verification module is configured to determine whether the target row address has been successfully repaired; and The threshold adjustment module is configured to adjust the first threshold and the second threshold based on whether the target row address has been successfully repaired.

16. The memory controller of claim 15, further comprising: A time module is configured to trigger the repair module to perform the repair operation on the second target row address in response to reaching a time threshold and the presence of a second target row address in the memory, wherein the data read from the second target row address contains the correctable error.

17. The memory controller of claim 15, further comprising: First counter and second counter, The first counter is configured to count the number of times the target row address is not successfully repaired, and obtain a third count value. The second counter is configured to count the number of times the target row address is successfully repaired, to obtain a fourth count value; The threshold adjustment module is further configured to: In response to the third count value being equal to 0 and the fourth count value being greater than 0 within a preset time period, the first threshold and the second threshold are decreased. In response to the ratio of the third count value to the fourth count value being greater than 0 and less than the first value, the first threshold and the second threshold remain unchanged, or In response to the ratio of the third count value to the fourth count value being greater than the first value and less than the second value, the first threshold and the second threshold are increased.

18. The memory controller of claim 15, further comprising: Intermittent error detection module, Specifically, before the repair module performs the repair operation on the target row address, the intermittent error detection module is configured to perform an intermittent error detection operation on the target row address to determine whether the error in the target row address is an intermittent error; In response to the error at the target row address being an intermittent error, the repair module is configured to stop performing the repair operation on the target row address, and the intermittent error detection module is configured to perform the intermittent error detection operation on the next target row address of the target row address; and In response to the fact that the error at the target row address does not belong to the occasional error, the repair module is configured to perform the repair operation on the target row address.

19. A memory comprising: Memory; as well as The memory controller as described in any one of claims 15-18.

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